JP4973858B2 - IO unit - Google Patents

Description

  The present invention relates to an IO unit, and more specifically, to a failure detection technique in which a plurality of boards are provided and board board IO data is communicated by serial communication.

  In a network system in FA (Factory Automation), one or a plurality of PLCs (programmable controllers) that control production facilities and devices whose operations are controlled by the PLCs are connected to a control system network. These PLCs and devices communicate with each other cyclically via the network of the control system, thereby transmitting / receiving IO data and controlling production facilities.

  The PLC connects a CPU unit that executes calculations based on a control program, an input device such as a sensor or a switch and inputs an on / off signal as an input signal, and an output device such as an actuator or a relay. Output units that send output signals to them, communication units that send and receive data to and from other devices connected to the network, master units for master-slave communication, power supply units that supply power to each unit, etc. It is configured by combining a plurality of units.

  The master unit is connected to a field network, and performs master-slave communication with a digital IO unit (remote IO unit) connected to the field network. The digital IO unit is connected to an IO device such as an input device or an output device, and transmits / receives IO data of the IO device to / from the master unit (PLC) via the network.

  The input unit, the output unit, and the digital IO unit transmit / receive IO data to / from an IO device connected to the built-in MPU. These units are configured by housing a circuit board for performing the above-described processing in a case. The circuit board is usually composed of one board, but may be divided into a plurality of boards. In such a case, the boards are connected to each other by a connector / cable.

  FIG. 1 shows a state where the first substrate 1 on the transmission side and the second substrate 2 on the reception side are connected by the interface unit 3. The interface unit 3 may be a type in which connectors provided at predetermined positions on both the boards 1 and 2 are directly connected to each other, or a type using a flexible cable.

  Transmission / reception of IO data in such a circuit board is performed as follows. When the power is turned on, the oscillator 1d of the first substrate 1 starts oscillating, and the output of the oscillator 1d is given to the clock unit 1c composed of a 4-bit binary counter. Then, the clock unit 1c starts operation and outputs a clock signal. Along with this, the MPU 1a also starts operation, and outputs IO data (output data) for the IO device (output device) connected to the unit at a predetermined timing. That is, the MPU 1a validates the Enable signal and sets IO data in the 8-bit shift register 1b which is a standard logic IC.

  The IO data set in the 8-bit shift register 1b is transferred to the 8-bit shift register 2a, which is a standard logic IC mounted on the second substrate 2, via the interface unit 3, and is output to the corresponding IO device. The

  When data transfer between the 8-bit shift registers 1b and 2a provided on the first and second substrates 1 and 2 is performed by serial communication, the following problems occur. In the configuration illustrated in FIG. 1, since the second substrate 2 is configured only by the standard logic IC, a failure of the system cannot be detected in advance. Therefore, the MPU 1a performs data transmission regardless of whether or not a failure has occurred. Then, if data is transmitted from the first board 1 to the second board 2 without noticing that there is a failure, the data of the serial signal may not be correctly received on the second board 2 side. In this case, there is a risk that a device that operates based on the parallel signal output from the 8-shift bit shift register 2a does not perform an appropriate operation.

  The present invention provides an IO unit capable of detecting the presence / absence of a failure / abnormality in advance in an IO unit having a function of transferring IO data using serial communication.

  Other objects and operational effects of the present invention will be easily understood by those skilled in the art by referring to the following description of the specification.

  In order to achieve the above object, an IO unit according to the present invention is (1) an IO unit that outputs IO data to a connected IO device, the first board on the transmission side, and the second on the reception side. A board and an interface unit for connecting the boards. The first board receives the MPU that outputs IO data composed of parallel signals, and the IO data output from the MPU, converts it into a serial signal, and sends it to the second board via the interface unit. A first logic IC. The second board includes a second logic IC that receives IO data including a serial signal sent via the interface unit, converts the IO data into a parallel signal, and outputs the parallel signal. Then, one of the output terminals of the second logic IC is branched and input to the abnormality check input terminal of the MPU of the first substrate, and the MPU is connected to the abnormality check input terminal. The state of one output terminal of the second logic IC acquired from the above is acquired, and it is configured to check whether there is an abnormality by determining whether the check data output by the MPU is correctly transmitted or not .

  (2) The abnormality check processing function in the MPU is an “H” signal for the first logic IC as check data for one output terminal of the second logic IC fed back to the abnormality check input terminal. "L" signal is sent to determine whether or not each check data has been sent correctly from the state of the abnormality check input terminal. The IO device linked to the output terminal of the second logic IC to which the check data is sent may be provided with a control unit that controls so as not to operate.

  (3) The control unit connects one output terminal of the second logic IC fed back to the abnormality check input terminal to one input terminal of the logical sum IC provided on the second substrate, and the MPU. The output of the abnormality check output terminal is connected to the other input terminal of the logical sum IC, and at the time of abnormality check, the output of the abnormality check output terminal is the output of the logical sum IC. The IO device can be controlled to be inactive. Of course, the inactive configuration is not limited to this, and a part of the system to the IO device may be cut off so that the output is not simply performed, or the power supply to the IO device is not performed. In addition, the IO device itself may not be operated.

  (4) On the condition that the MPU determines that there is no abnormality, it is preferable to output regular IO data to the connected IO device.

  According to the present invention, the parallel signal is converted into a serial signal using the MPU and the first logic IC (corresponding to the “8-bit shift register 12” in the embodiment), and the second logic IC (in the embodiment “ By utilizing the 8-bit shift register 21 ″) and converting the serial signal into a parallel signal again, one-way wiring saving from the first substrate to the second substrate can be realized. In a system that realizes such wire-saving, a part of the parallel signal is fed back to the MPU (the state of the abnormality check input terminal is confirmed), so that a failure of the entire wire-saving system can be detected in advance. In this way, since a system failure can be detected in advance, for example, before sending IO data from the first board, the user is notified that an abnormality or failure has occurred by an alarm alarm or the like. Or prevent the system operation from starting. Thereby, it is possible to prevent the occurrence of an accident in a device that operates by the parallel signal of the second substrate.

  At the time of abnormality check, the output state of the output terminal of the second logic IC may cause the connected IO device to be active (operation) based on the check data output from the MPU. Therefore, it is preferable to provide a control unit that prevents the IO device from operating as in (2). When configured as in the invention of (3), the control unit can be realized with a simple configuration using a standard logic IC. Therefore, it is preferable.

  The present invention can detect the presence / absence of a failure / abnormality in advance in an IO unit having a function of transferring wire-saving IO data by wire-saving using serial communication. Therefore, malfunction of IO apparatus can be suppressed as much as possible.

  FIG. 2 shows an example of a circuit mounted on the IO unit according to the present invention. In this example, the first substrate 10 on the transmission side and the second substrate 20 on the reception side are connected by an interface 30 that performs serial communication. This IO unit is, for example, one of the units constituting the PLC, or a digital IO unit (also referred to as a remote IO unit) connected to the PLC via a network.

  On the first substrate 10, an MPU 11, an 8-bit shift register 12 that is a standard logic IC, a clock unit 13 that is a 4-bit binary counter that is a standard logic IC, an oscillator 14 having an oscillation frequency of 1 MHz, and the like are mounted. Yes.

  The clock unit 13 counts the signal supplied from the oscillator 14 and generates a reference clock signal. Based on the reference clock signal, each element (IC or the like) on the circuit board operates.

  The MPU 11 executes various set processes, and in relation to the present invention, the MPU 11 outputs IO data output to an IO device connected at an appropriate timing as a parallel signal. It is set in the 8-bit shift register 12.

  The 8-bit shift register 12 outputs the 8-bit data set by the MPU 11 one by one in order from the top. Thus, the parallel signal is converted into a serial signal. This serial signal is given to the 8-bit shift register 21 of the second substrate 20 through the first signal line L1 of the interface unit 30. The 8-bit shift register 21 has a latch function, and 8-bit signals sent as serial signals from the 8-bit shift register 12 are output from the output terminals QA to QH. Thereby, the serial signal can be converted into the parallel signal again. Therefore, wiring saving in the interface unit 30 is realized.

  The Enable signal output from the MPU 11 is transmitted to the 8-bit shift register 21 of the second substrate 20 via the second signal line L2.

  In the present embodiment, the third signal line L3 and the fourth signal line L4 are provided as the interface unit 30. Further, the output of one output terminal (here, “QA”) of the 8-bit shift register 21 of the second substrate 20 is connected to one input terminal of the OR element 22 which is a standard logic IC. The output of the OR element 22 is given to the IO device as the QA output.

  One end of the third signal line L3 is connected to the other input terminal of the OR element 22. The other end of the third signal line L3 is connected to the abnormality check output terminal PA of the MPU 11. The abnormality check output terminal PA outputs a stop signal for preventing the IO device from malfunctioning during the presence / absence check. Specifically, in this embodiment, since the output of the 8-bit shift register 21 is L active, the stop signal is set to output “H”. Therefore, when the output of PA is the stop signal “H”, the stop signal is input to the OR element 22 via the third signal line L3, so that the QA state (L / H) of the 8-bit shift register 21 is reached. ), The output of the OR element 22 becomes “H”, and the operation of the input device connected thereto is stopped.

  The fourth signal line L4 has one end connected to the abnormality check input terminal PB of the MPU 11 and the other end connected to the output terminal (QA) of the 8-bit shift register 21 connected to the OR element 22. As a result, the state (H / L) of the output terminal (QA) of the 8-bit shift register 21 is given to the MPU 11 via the fourth signal line L4.

  In this embodiment, since the output unit is an 8-unit IO unit, the 8-bit shift registers 12 and 21 are used. However, the number of output points is appropriately changed according to the number of output points. The IO unit is specifically an IO unit constituting the PLC (sometimes called an output unit) or a digital IO unit connected to the PLC over a network (sometimes called a remote IO unit). ), And can be applied not only to a type in which only output devices are connected, but also to a mixed type in which input devices and output devices are connected.

  Next, the operation of the IO unit configured as described above will be described based on the flowchart shown in FIG. First, the power is turned on (S1). Then, when the clock unit 13 starts operating and the reference clock signal starts to be output, the MPU 11 also starts operating (S11). The MPU 11 first enables the Enable signal and outputs the abnormality check output terminal PA to H (S4). Accordingly, the output of the OR element 22 is held at “H”.

  The MPU 11 outputs L to P0 and H to P1 to P7 (S5), and waits for a time for a serial signal based thereon to reach the 8-bit shift register 21 of the second substrate 20 (S6). As described above, the output from P0 to P7 is converted into a serial signal by outputting the 8-bit shift register 12, which is sent to the 8-bit shift register 21 of the second substrate 20 and reconverted into a parallel signal. Is done. The output (L) of P0 is output from the QA of the 8-bit shift register 21. Similarly, the outputs of P1 to P7 are output from QB to QH of the 8-bit shift register 21.

  The MPU 12 reads the abnormality check input terminal PB and determines whether or not it is “L” (S7). If it is H, it is recognized as an error (S8). That is, since P0 is “L”, if the signal transmission system, the 8-bit shift register, etc. are normal, QA is also “L”. Therefore, in this state, if PB is “L”, it is normal, and if it is “H”, it can be said that there is a possibility that an abnormality has occurred.

  In addition, since P0 is set to L for abnormality check, if normal, QA also becomes L, and the IO device operates as it is. Therefore, in this embodiment, PA is set to H, and the output of the OR element 22 is kept at “H” regardless of the output of QA, so that the output device is prevented from operating erroneously.

  If it is determined to be normal by the above-described processing from S5 to S7 (Yes in S7), the MPU 11 next outputs H to P0 and H to P1 to P7 (S9), and the serial signal based on it outputs the second signal. It waits for the time to reach the 8-bit shift register 21 of the substrate 20 (S10). Next, the MPU 12 reads the abnormality check input terminal PB and determines whether or not it is “H” (S NW). If “L”, it is recognized as an error (S11). That is, since P0 is “H”, if the signal transmission system, the 8-bit shift register, and the like are normal, QA also becomes “H”. Therefore, in this state, if PB is “H”, it is normal, and if it is “L”, it can be said that there is a possibility that an abnormality has occurred.

  In this way, if the two branch determinations are both YES, it is determined to be normal, and PA is output L (S13). Thus, thereafter, the output of QA becomes dependent on the output of the OR element. Thereafter, the original data is output to P0 to P7, and the data is transmitted from the first substrate 10 (8-bit shift register 11) to the second substrate 20 (8-bit shift register 21) (S14).

  If an error is recognized in steps S6 and S12, the MPU 11 performs predetermined error processing, for example, various alarms (lamp lighting, alarm sound generation, etc.).

  FIG. 4 shows an example of a specific substrate block configuration to which the present invention is applied. Of course, the present invention is not limited to such a configuration. The IO unit is configured by mounting a predetermined board in a casing. Here, the board to be mounted is divided into three boards, that is, a communication control unit board 31, an IO circuit unit board 32, and a base unit board 33. ing.

  The communication control unit substrate 31 is a substrate on which a circuit for realizing a function as a communication unit is formed, and the communication interface 31a and the like are also mounted on the communication control unit substrate 21. Further, the communication control unit board 31 includes a power supply terminal 31b, a power supply circuit 31d, a clock oscillator 31e, a reset circuit 31f, an EEPROM 31g, an address setting switch 31h, a communication LED 31i, and main components 31j such as an ASIC and an MPU. It is. The communication LED 31i is also referred to as an operation LED, and blinks or lights in a predetermined color when communication is executed. The power supply terminal 31b is a terminal for connecting an external power supply, for example, and a voltage supplied from the external power supply is converted into a desired voltage by the power supply circuit 31d and supplied to the IO device.

  The IO circuit unit board 32 electrically connects the IO data to and from the IO connector, the status 32b such as the input / output power supply monitor, the circuit on the communication control unit board 31 side, and the IO device. An insulating photocoupler 32c and the like are included.

  The base portion substrate 33 includes an IO connector (terminal block) 33a for connecting an IO device, an IO LED 33b indicating an operation state of the IO device, and the like. The IO LED 33b may be installed on the side of the IO circuit board 32 in terms of function. However, by arranging the IO LED 33b near the IO connector 33a, the operation of each IO device connected to the IO connector 33a is possible. In this example, it is installed on the base portion substrate 33 side because there is an advantage that the situation can be understood immediately.

  In terms of the relationship with the substrate shown in FIG. 4, the communication control unit substrate 31 corresponds to the first substrate 10, and the IO circuit unit substrate 32 corresponds to the second substrate 20. The MPU 11, the 8-bit shift register 12 and the like correspond to the main component 31j, and the 8-bit shift register 21 corresponds to the input / output unit 32a. For example, in the case of an IO unit constituting the PLC, the communication interface 31a is an interface connected to the PLC internal bus, and performs IO data transmission and reception with the CPU unit via the internal bus. In the case of a digital IO unit (remote IO unit) connected to the PLC via a network, the interface corresponds to the communication protocol of the network to be connected.

  In FIG. 2, although not specifically shown, various circuit components as shown in FIG. 4 are mounted. In FIG. 4, the substrate is separated into three substrates. However, for example, the IO circuit unit substrate 32 and the base unit substrate 33 may be configured by a single substrate, or may be divided at other positions.

It is a figure for demonstrating an example of the circuit board which comprises the IO unit which transfers IO data by serial communication between the internal boards | substrates used as the premise of this invention. It is a figure which shows one Embodiment of the circuit board which comprises the IO unit which concerns on this invention. It is a flowchart explaining operation | movement of IO unit. It is a figure which shows the block configuration of the specific circuit board of IO unit.

Explanation of symbols

10 First substrate 11 MPU
12 8-bit shift register (first logic IC)
20 Second substrate 21 8-bit shift register (second logic IC)
22 OR element (logical OR IC)
30 interface unit L1 first signal line (wiring for transmitting IO data and check data)
L2 Second signal line (wiring for transmitting an Enable signal)
L3 Third signal line (wiring for transmitting a stop signal)
L4 Fourth signal line (wiring for transmitting a feedback signal)
PA Abnormality check output terminal PB Abnormality check input terminal

Claims (4)

An IO unit that outputs IO data to a connected IO device,
A first board on the transmission side, a second board on the reception side, and an interface unit for connecting both boards,
The first board receives the MPU that outputs IO data composed of parallel signals, and the IO data output from the MPU, converts it into a serial signal, and sends it to the second board via the interface unit. A first logic IC;
The second board includes a second logic IC that receives IO data composed of a serial signal sent via the interface unit, converts the IO data into a parallel signal, and outputs the parallel signal.
One of the output terminals of the second logic IC is branched and input to the abnormality check input terminal of the MPU of the first board,
The MPU acquires the state of one output terminal of the second logic IC acquired from the abnormality check input terminal, and determines whether or not the check data output from the MPU is correctly transmitted. An IO unit configured to check whether there is an abnormality. The abnormality check processing function in the MPU is a check signal for one output terminal of the second logic IC that is fed back to the abnormality check input terminal. Each of the signals, from the state of the abnormality check input terminal, to determine whether each check data has been sent correctly,
When performing the abnormality check, a control unit is provided for controlling the IO device linked to the output terminal of the second logic IC to which the check data is sent so as not to operate. Item 10. The IO unit according to Item 1. The controller is
One output terminal of the second logic IC fed back to the abnormality check input terminal is connected to one input terminal of the logical sum IC provided on the second substrate, and the abnormality check output terminal provided on the MPU. Is configured to be connected to the other input terminal of the logical sum IC,
3. The IO unit according to claim 2, wherein at the time of abnormality check, the output of the abnormality check output terminal is controlled so that the output of the logical sum IC becomes inactive of the IO device.   4. The regular IO data is output to a connected IO device on condition that the MPU determines that there is no abnormality. IO unit.

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