JP4973363B2 - Output voltage detection circuit for power converter - Google Patents

Description

  The present invention relates to an output voltage detection circuit for detecting an output voltage of various power converters such as a PWM inverter that drives an electric motor.

  FIG. 6 is a main circuit configuration diagram of a PWM inverter INV which is an example of a power conversion device, in which 300 is a DC power supply, and 301 to 306 are power semiconductor switching elements such as IGBTs having freewheeling diodes connected in antiparallel. . Since the operating principle of the PWM inverter is well known, the description of the operating principle is omitted here.

  In general, in a PWM inverter, an error voltage is generated in an actual output voltage with respect to an output voltage command due to an on-voltage drop of a switching element constituting the device, a delay in switching timing, or the like. For this reason, in order to achieve high-speed and high-precision control of an electric motor or the like with a PWM inverter, it is necessary to perform feedback control using the output voltage of the inverter. An A / D conversion circuit that detects and converts the analog detection value into a digital quantity is required.

Here, FIG. 7 is a block diagram of an output voltage detection circuit of the three-phase voltage source PWM inverter described in Non-Patent Document 1, and FIG. 8 is an operation waveform diagram thereof.
In FIG. 7, the circuit configuration of the PWM inverter INV is partially omitted and only one output phase is shown, and the potential (ground potential) serving as the reference of the voltage detection circuit is the negative side potential of the DC power supply 300 of the inverter INV. Are the same.

In FIG. 7, 101 is a voltage dividing circuit connected to both ends of the switching element 302, SW ₀ and SW ₁ are switches (a state connected to the ground side is turned off), 102 is a subtracting circuit, and 103 is an integrating circuit. Circuit 104, zero cross comparator, 105 on / off detection comparator, 106 voltage detection control circuit, 106a and 107b counters.

The operation of this prior art will be described below with reference to FIG.
First, the voltage detection circuit in FIG. 7 sets the apex of the triangular wave carrier of the PWM inverter INV as the start time of one cycle T (t = 0 in FIG. 8), and the output voltage of the inverter INV in the carrier cycle (inverter INV in FIG. 7). The average value of the voltage between the output terminal U and the ground) is detected as a digital quantity.

The specific contents of the detection operation are as follows.
(1) Operation 1
Voltage detection control circuit 106 recognizes the vertices of the triangular wave carrier by carrier synchronization signal input from the control circuit (not shown), a divided voltage v _i by the voltage dividing circuit 101 by turning on the switch SW ₀ of the period T In the meantime, it is possible to input to the + side of the subtraction circuit 102. At the same time, the counter 106a for measuring the rise of the divided voltage v _i starts counting the clock signal. At this time, the switch SW ₁ is turned off, is connected to the ground side.

(2) Operation 2
The counter 106a is the output of the on-off detection comparator 105 the divided voltage v _i is input, counts the time t _{1 (see} FIG. 8) to the rising of the divided voltage v _i, to stop the operation.

(3) Operation 3
After a time 2t _{1 that} is twice t ₁ obtained by the operation 2 has elapsed, the switch SW ₁ is turned on to input the reference voltage V _REF to the minus side of the subtraction circuit 102. At the same time, the counter 106b that measures the time when the reference voltage _VREF is input starts to count the clock signal.
Note that the accumulation circuit 103 are inputted divided voltage v _i from the time of lapse of time t _1, after the elapse of time 2t ₁ is the difference between the divided voltage v _i and the reference voltage V _REF Since a voltage is input, the output voltage of the integrating circuit 103 has a value as shown in FIG.

(4) Operation 4
After the divided voltage v _i falls at time (T−t ₁ ), the input to the integration circuit 103 is only −V _REF, and the output voltage of the integration circuit 103 decreases as shown in FIG.

(5) Operation 5
When the time (2t ₁ + t ₂ ) elapses and the output voltage of the integration circuit 103 becomes 0V, the zero cross detection signal output from the zero cross comparator 104 is input to the voltage detection control circuit 106. Voltage detection control circuit 106, along with turns off the switch SW ₁ to stop input of the reference voltage V _REF to the subtracting circuit 102, it stops the operation of the reference voltage input time measuring counter 106b. Prior to the off switch SW _1, switch SW ₀ at the time of the lapse of time T is off.

With the above operation, _(although the formulas described below are denoted by the "¯" to the top of the V _i, omitted on body) divided voltage v _i mean V _i of the carrier 1 cycle reference voltage V _REF to The average value of the output voltage for one phase of the inverter can be detected by multiplying the average value V _i by the voltage dividing ratio of the voltage dividing circuit 101.

Next, the above-described operation will be described below using mathematical expressions.
The output voltage of the integrating circuit 103 with respect to the divided voltage v _i can be expressed by Equation 1. Where RC is an integration time constant.

Further, the output voltage of the integration circuit 103 related to the reference voltage V _REF can be expressed by Equation 2.

Since the sum of Formula 1 and Formula 2 when time (2t ₁ + t ₂ ) has elapsed is 0, Formula 3 is satisfied.

Therefore, the average value V _i of the divided voltage v _i in one carrier cycle can be expressed by Equation 4. That is, since T and V _REF are known, the average value V _i can be obtained by measuring the input time t ₂ of the reference voltage V _REF by the switch SW ₁ .

Here, the detection accuracy of the output voltage will be considered.
An output voltage detection circuit described above, when the detected maximum 1.5T (= 1.5 carrier cycle) was designed to end, up to 1.5T to the input time of the reference voltage _{V REF t 2} also ideal It is possible to take.
At this time, based on Equation 4, the maximum detected voltage V _imax of the average value V _i is expressed by Equation 5.

On the other hand, since the minimum detection voltage V _imin of the average value V _i becomes one clock cycle T _c of the counter 106b, Expression 6 is obtained based on Expression 4.

Therefore, based on Equations 4 and 6, the relationship between the minimum detection voltage V _imin and the maximum detection voltage V _imax of the average value V _i is expressed as Equation 7.

Hidehiko Sugimoto, Nobuyuki Tanaka, “Development of output voltage detection circuit for three-phase voltage type PWM inverter”, 2005 Annual Conference of the Institute of Electrical Engineers of Japan, I-415 to I-418

In the above-described prior art, in order to improve the detection accuracy, that is, the resolution, as is clear from Equation 7, the clock cycle _Tc may be reduced, that is, the clock frequency may be increased.
However, in reality, the clock frequency has an upper limit from the viewpoint of the characteristics and performance of the electronic components used in the voltage detection circuit, and it is difficult to increase the voltage detection accuracy.
For this reason, even if it is desired to feed back the output voltage of the PWM inverter to control the motor at high speed and with high accuracy, there is a problem that desired control performance cannot be obtained as a result.

  SUMMARY OF THE INVENTION An object of the present invention is to provide an output voltage detection circuit for a power converter that can improve the voltage detection accuracy regardless of a method such as increasing the clock frequency.

In order to solve the above problems, an invention according to claim 1 is directed to an output voltage detection circuit of a power converter having a power semiconductor switching element.
An integrating means for selecting a detected voltage, or an addition / subtraction result of the detected voltage and the first reference voltage or the second reference voltage and integrating with a predetermined time constant;
First comparing means for comparing the output of the integrating means with a third reference voltage;
Second comparing means for comparing the output of the integrating means with a fourth reference voltage;
First latch means for latching the output of the first comparison means in synchronization with the clock signal;
Second latch means for latching the output of the second comparison means in synchronization with the clock signal;
A voltage detection control means for inputting the outputs of the first and second latch means, the clock signal, and a synchronization signal synchronized with the switching period of the power converter, and enabling the integration means to be reset;
In the first period synchronized with the switching cycle of the power converter,
In accordance with the output of the first latch means, the addition or subtraction value of the detected voltage or the detected voltage and the first reference voltage is integrated by the integrating means,
In a second period that is synchronized with the switching period of the power converter and that is continuous with the first period,
In response to the output of the second latch means, the output of the integrating means at the end of the first period is set as an initial value, the second reference voltage is integrated by the integrating means, and then the integrating means is reset,
In the first period, the number of the clock signals in the period in which the addition / subtraction results of the detected voltage and the first reference voltage are integrated, or the number of the clock signals in the period in which the detected voltage is integrated is set as the first count value. And
In the second period, the number of the clock signals in the period obtained by integrating the second reference voltage is set as the second count value,
The detected voltage is measured using the first count value and the second count value.

The invention according to claim 2 is an output voltage detection circuit of a power converter having a power semiconductor switching element.
An integration means for selecting the detected voltage or the addition / subtraction result of the detected voltage and the first reference voltage and integrating with the first or second integration time constant;
First comparing means for comparing the output of the integrating means with a third reference voltage;
Second comparing means for comparing the output of the integrating means with a fourth reference voltage;
First latch means for latching the output of the first comparison means in synchronization with the clock signal;
Second latch means for latching the output of the second comparison means in synchronization with the clock signal;
A voltage detection control means for inputting the outputs of the first and second latch means, the clock signal, and a synchronization signal synchronized with the switching period of the power converter, and enabling the integration means to be reset;
In the first period synchronized with the switching cycle of the power converter,
In accordance with the output of the first latch means, the detected voltage or the addition / subtraction value of the detected voltage and the first reference voltage is integrated by the integrating means with a first integration time constant,
In a second period that is synchronized with the switching period of the power converter and that is continuous with the first period,
In response to the output of the second latch means, the output of the integrating means at the end of the first period is set as an initial value, the first reference voltage is integrated by the integrating means with the second integration time constant, and then Reset the integration means to
In the first period, the number of the clock signals in the period in which the addition / subtraction results of the detected voltage and the first reference voltage are integrated, or the number of the clock signals in the period in which the detected voltage is integrated is set as the first count value. And
In the second period, the number of the clock signals in the period obtained by integrating the first reference voltage is set as the second count value,
The detected voltage is measured using the first count value and the second count value.

The invention according to claim 3 is the output voltage detection circuit of the power conversion device according to claim 1 or 2,
The frequency of the clock signal is an integral multiple of the switching frequency of the power converter.

  The invention according to claim 4 is the output voltage detection circuit of the power conversion device according to any one of claims 1 to 3, wherein the output of the first latch means in the first period and the second voltage in the second period. A logical sum signal with the output of the latch means is transmitted to the voltage detection control means via the insulation means.

  The invention according to claim 5 is the output voltage detection circuit of the power conversion device according to any one of claims 1 to 4, wherein the detected voltage is obtained by dividing the output voltage of the inverter as the power conversion device. It is a voltage.

  According to the present invention, it is possible to improve the voltage detection accuracy regardless of the method of increasing the clock frequency, and it is possible to improve the control performance when the electric motor is driven by the power converter.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention according to claim 1.
In FIG. 1, as in FIG. 7, the PWM inverter INV partially omits its circuit configuration and shows only one phase of output, and the potential (ground potential) serving as a reference for the voltage detection circuit is the inverter INV. This is the same as the negative side potential of the DC power supply 300. Further, in each component of the voltage detection circuit, the same components as those in FIG. 7 are denoted by the same symbols.

In Figure 1, SW ₀ is turned on and off by the carrier sync signal _{V CAR,} switch for switching and outputting the divided voltage _{v i} and the ground _potential, SW _1, SW ₂ by the output of the latch circuit 208, 210 to be described later This switch is turned on / off, and switches and outputs preset first reference voltage V _REF1 , second reference voltage V _REF2 and ground potential. Here, the state in which the switches SW ₀ , SW ₁ , SW ₂ are connected to the ground side is turned off.
Reference numeral 202 denotes a subtraction circuit that performs an operation by inputting the output voltages of the switches SW ₀ , SW ₁ , and SW ₂ with the reference numerals shown in the figure, and 203 denotes an integration circuit connected to the output side of the subtraction circuit 202.

207 The first comparator for comparing the output voltage _{v s} and the third reference voltage _{V REF3} of the integration circuit 203, 208 is a carrier sync signal _{V CAR} and the clock signal _{V CLK} is input, based on the carrier synchronization signal _{V CAR} , the first latch circuit, 209 second comparator for comparing the output voltage _{v s} of the integrating circuit 203 and a fourth reference voltage _{V REF4} for latching the output of the comparator 207 during the first carrier period T, 210 Is a second latch circuit that receives the carrier synchronization signal V _CAR and the clock signal V _CLK via the NOT circuit 215 and latches the output of the comparator 209 during the next carrier period based on the carrier synchronization signal V _CAR. .
The outputs of the latch circuits 208 and 210 are input to the switches SW ₁ and SW ₂ and the voltage detection control circuit 206, respectively.

Incidentally, in the voltage detection control circuit 206, 206a is a counter for counting the number _{n 1on} the clock signal _{V CLK,} 206 b is a counter for counting the number _{n 2on} the clock signal _{V CLK.}
Further, the reset signal V _RST output from the voltage detection control circuit 206 is input to the integration circuit 203.

Next, the output voltage detection operation in this embodiment will be described below with reference to FIG.
(1) Operation 1
Voltage detection control circuit 206 recognizes the vertices of the triangular wave carrier by the carrier sync signal _{V CAR,} turns on the switch SW _0, while the divided voltage _{v i} by the voltage dividing circuit 101 of the carrier period T, the subtracting circuit 202 + It is possible to input to the side.
At this time, the switch SW1 is off, and _one minus side of the subtraction circuit 202 is kept at the ground potential. The switch SW ₂ is between the carrier period T are turned off continuously, the subtracting circuit 202 the other - is kept side to ground potential.
As a result, the integration circuit 203 integrates the divided voltage v _i , so that the output of the integration circuit 203 increases as shown in FIG. 2 after the time when the divided voltage v _i (PWM pulse) rises.

(2) Operation 2
When the output voltage of the integrating circuit 203 becomes larger than the third reference voltage V _REF3 , the output of the comparator 207 becomes a high level, and the output is latched by the latch circuit 208 in synchronization with the clock signal V _CLK .

(3) Operation 3
When the output of the latch circuit 208 becomes the High level, the switch SW ₁ is turned on by the subtraction circuit 202 - since entering the first reference voltage _{V REF1} to the side, the integration circuit 203, and the divided voltage _{v i} first The difference voltage (v _i −V _REF1 ) from the reference voltage V _{REF1 of} 1 is input, and the integration circuit 203 integrates the difference voltage (v _i −V _REF1 ). At this time, as shown in FIG. 2, if the differential voltage (v _i −V _REF1 ) is designed to be negative, the output voltage of the integrating circuit 203 decreases during the period when the switch SW ₁ is on. To do.

(4) Operation 4
When the output voltage of the integration circuit 203 becomes smaller than the third reference voltage V _REF3 by the operation 3, the output of the comparator 207 becomes a low level, and the output is latched by the latch circuit 208 in synchronization with the clock signal V _CLK. Is done.

(5) Operation 5
When the output of the latch circuit 208 becomes the Low level, the switch SW ₁ is turned off, only the divided voltage v _i is the integrator circuit 203 is input, the output voltage of the integrating circuit 203 as shown in FIG. 2 is increased again Begin to.

(6) Operation 6
When the voltage detection control circuit 206 recognizes the apex of the next triangular wave carrier, it turns off the switch SW ₀ during the next carrier period T and sets the + side of the subtraction circuit 202 to the ground potential. The latch circuit 208 is so not operate on the basis of the carrier sync signal V _CAR, one of the subtraction circuit 202 turns off the switch SW ₁ - to ground side potential. On the other hand, the latch circuit 210 is so operated on the basis of a carrier synchronization signal _{V CAR,} by turning on the switch SW ₂ of the subtracting circuit 202 the other - to enter the second reference voltage _{V REF2} to the side. As a result, the input of the integrating circuit 203 becomes −V _REF2 , and the output voltage starts to decrease.

(7) Operation 7
Due to the operation 6, the output voltage of the integrating circuit 203 is lower than the fourth reference voltage V _REF4 (this reference voltage V _REF4 needs to be designed to be lower than the third reference voltage V _REF3 and is set to 0 V in this embodiment). Then, the output of the comparator 209 becomes low level, and the output is latched by the latch circuit 210 in synchronization with the clock signal _VCLK .

(8) Operation 8
When the operation 7 is completed, the switches SW ₀ , SW ₁ , and SW ₂ are all turned off by the operation of the voltage detection control circuit 206 so that the + side and − side of the subtraction circuit 202 are all set to the ground potential and the reset signal V _The integration circuit 203 is reset by _RST and further waits until the top of the next triangular wave carrier is recognized.

By the above operation, the average value _{V i} of the divided voltage _{v i} first, can be expressed as a function of the second reference voltage _{V REF1, V REF2,} minute voltage dividing circuit 101 to the average value _{V i} By multiplying the pressure ratio, the average value of the output voltage for one phase of the inverter can be detected.
Hereinafter, the calculation principle of the average value V _i will be described using mathematical expressions.

In the first carrier cycle (referred to as a first period), all the time _{t 1on} the switch SW ₁ in synchronism with the clock signal _{V CLK} is turned on, all the time off the _{t 1Off,} also first When the average value of the divided voltage v _i in the carrier cycle is V _i , the output voltage v _S1 of the integration circuit 203 at the end of the first carrier can be expressed by Equation 8. Where CR is an integration time constant.

On the other hand, if the time from the start of the second carrier cycle to the time when the output v _S of the integrating circuit 203 becomes 0 V is t _{2on in} the second carrier cycle (referred to as the second period), Equation 9 is established.

Here, the relationship of Formula 10 is established between the carrier cycle T and the on / off times t _1on and t _1off of the switch SW _{1 in} the _first carrier cycle. Therefore, Expression 9 becomes Expression 11.

Also, in the first carrier cycle, the number of clock signals V _CLK when the switch SW ₁ is turned on in synchronization with the clock signal V _CLK is n _1on , and the output of the integrating circuit 203 is 0 V from the start of the second carrier cycle. _Assuming that the number of clock signals V _CLK until n ₂ is n _2on , the relations of Expressions 12 and 13 are established. However, _Tc is a clock cycle.

Further, when the first reference voltage _{V REF1} a relationship between the second reference voltage _{V REF2} is set as Equation 14, the average value _{V i} of the divided voltage _{v i} in the carrier period of the first expressed by Equation 15 be able to. In Equation 14, n is a natural number.

In Expression 15, since the carrier period T, the clock period T _c , and the ratio 2 ⁿ of the first reference voltage V _REF1 and the second reference voltage V _REF2 are known, the divided voltage v in the first carrier period _It can be seen that the average value V _i of _i can be measured by Equation 15 if n _1on and n _2on are counted. The calculation of Formula 15 may be executed by a calculation means such as a CPU provided inside or outside the voltage detection control circuit 206.

Here, the detection accuracy of the output voltage will be examined below.
From what has been described in the above operation 3, the maximum detectable value of the average value _{V i} and (maximum detection voltage _{V imax} average value _{V i)} is between the first reference voltage _{V REF1,} the relationship of Equation 16 Holds.

On the other hand, from Equation 15, the minimum detection voltage V _imin of the average value V _i is Equation 17.

Therefore, from Equations 16 and 17, the relationship between the minimum detection voltage V _imin of the average value V _i and the maximum detection voltage V _imax is expressed by Equation 18.

From the above, as is clear from a comparison between Formula 7 representing the minimum detection voltage V _imin in the conventional technique and Formula 18 representing the minimum detection voltage V _imin in the present embodiment, in the present embodiment, the first reference voltage is By adjusting the ratio 2 ⁿ between V _REF1 and the second reference voltage V _REF2 , it is possible to improve the detection accuracy, that is, the resolution as compared with the prior art.

Next, FIG. 3 is a block diagram showing a second embodiment of the present invention according to claim 2.
The difference from the first embodiment will be described. In the first embodiment, the integration time constant of the integration circuit 203 in the first carrier cycle and the second carrier cycle is made the same, and two different reference voltages V _{REF1 are used.} , V _REF2 is used to detect the voltage, but in the second embodiment, the switch SW ₃ is switched between the first carrier cycle and the second carrier cycle by the carrier synchronization signal V _CAR , and the integration circuit 203 The integration time constant is changed and the same reference voltage _VREF1 is used. Other operations are the same as those in the first embodiment. Note that the outputs of the latch circuits 208 and 210 are applied to the switch SW ₁ via the OR circuit 216.
In this case, when the integration time constant in the _first carrier cycle is CR ₁ and the integration time constant in the second carrier cycle is CR ₂ , Equation 19 is established.

  Here, the ratio of the integration time constants in the first and second carrier periods is set as in Expression 20.

In the first carrier cycle, the number of clock signals V _CLK when the switch SW ₁ is turned on in synchronization with the clock signal V _CLK is n _1on , and the output of the integration circuit 203 is 0 V from the start of the second carrier cycle. _Assuming that the number of clock signals V _CLK until n ₂ is n _2on , the average value V _i of the _divided voltage v _i in the first carrier cycle can be expressed by Equation 21 as in Equation 15 in the first embodiment. It can be _measured by counting n _1on and n _2on and calculating Formula 21.
Since the operation waveform of this embodiment is substantially the same as that of the first embodiment, a description thereof will be omitted.

Although the first and second embodiments have been described on the assumption that the divided voltage v _i is not negative, the divided voltage of one carrier cycle is actually decreased due to an on-voltage drop or the like of the power semiconductor switching element. In some cases, the average value becomes negative, and the method of the first and second embodiments cannot detect a negative voltage.
In order to solve this problem, the offset voltage is added in advance to the voltage obtained by dividing the output voltage of the inverter so that a negative voltage is not input to the subtraction circuit. It is also possible to measure the true divided voltage by subtracting the offset voltage by such processing.

  In each embodiment, the average value of the divided voltage is measured by increasing / decreasing the output voltage of the integration circuit 203 in the first carrier cycle and decreasing the output voltage of the integration circuit 203 in the second carrier cycle. An example is described. However, a divided voltage is generated by an operation that increases or decreases the output voltage of the integration circuit 203 in a period synchronized with the carrier, for example, up to the second carrier cycle and decreases the output voltage of the integration circuit 203 in the third carrier cycle. The average value of can also be measured. Therefore, in this case, the average value of the divided voltage in two carrier cycles is measured.

As described above, according to the first embodiment and the second embodiment, the equation 15 or equation 21, the average value _{V i} of the divided voltage _{v i} in the carrier period of the first _time, n _1on, counts _{n 2on} It is possible to measure.
However, when the frequency of the clock signal V _CLK is not an integral multiple of the switching frequency (carrier frequency) of the power converter, the number of clock signals V _CLK within one carrier period differs for each carrier period, resulting in an error in measurement values. Produce.

Therefore, in the third embodiment of the present invention, as described in claim 3, by setting the frequency of the clock signal V _CLK to an integer multiple of the switching frequency of the power converter, the clock signal V _CLK in each carrier period is set. _The voltage can be detected with high accuracy by using the same number of _CLKs .

  Now, in general, when detecting the voltage of the main circuit unit of the power converter, the voltage to be detected is much higher than the voltage of the control circuit, and the power handled by the main circuit unit is also higher than the power handled by the control circuit. Therefore, the control circuit unit and the main circuit unit are electrically insulated for the purpose of reducing the influence of noise generated in the main circuit unit on the control circuit.

Here, in the first embodiment of FIG. 1, when the main circuit unit is electrically insulated from the control circuit unit together with the voltage detection circuit unit, for example, the circuit configuration is as shown in FIG.
4 shows only one phase of the output of the power converter, 310 is a main circuit unit, and 220 is a voltage detection circuit unit (corresponding to a part excluding the voltage detection control circuit 206 from the configuration of FIG. 1). ), 230 is a power converter main control unit that generates a gate signal for the switching element of the main circuit unit 310, 240 is a power converter control circuit unit including the main control unit 230 and the voltage detection control circuit 206, and PC1 to PC5. Is an insulating circuit composed of a photocoupler or the like.

In the configuration shown in FIG. 4, data is sent from the main control unit 230 in the power conversion device control circuit unit 240 to the voltage detection control circuit 206, and based on this data, the carrier synchronization signal V _CAR synchronized with the switching cycle, The reset signal V _RST and the clock signal V _{CLK of the} integration circuit 203 are sent to the voltage detection circuit unit 220 via the insulation circuits PC1, PC2, PC3, respectively.
On the other hand, the output signals V _CNT1 and V _CNT2 of the latch circuits 208 and 210 corresponding to the voltage detection values are sent to the counters 206a and 206b of the voltage detection control circuit 206 via the insulation circuits PC4 and PC5, respectively, and the count values are output. Transmit to the main control unit 230. The main control unit 230 calculates a divided voltage using the count value, and generates a gate signal for on / off control of the switching element of the main circuit unit 310 based on the detected voltage value.

However, in the case of the configuration shown in FIG. 4, an increase in the number of parts accompanying insulation of the insulation circuits PC1 to PC5 and the like hinders cost reduction. In addition, this type of insulation component is generally large, and for the sake of insulation, the mounting of the component is also restricted, which greatly hinders downsizing.
In FIG. 4, only the output for one phase is described for the purpose of simplifying the drawing. For example, in the case of a three-phase output power converter, the carrier synchronization signal V for the voltage detection circuit unit 220 is described. _{Since the CAR} , the reset signal V _RST, and the clock signal V _CLK can be shared by three phases, only three insulation circuits (insulation circuits PC1 to PC3) are required to control the voltage detection circuit unit 220. However, in order to insulate the outputs of the latch circuits 208 and 210 and send them to the voltage detection control circuit 206, two insulation circuits PC4 and PC5 are required for one phase. The number of circuits is six in total for three phases.
Therefore, if the three insulation circuits PC1 to PC3 necessary for controlling the voltage detection circuit unit 220 are included, a total of nine insulation circuits are required for the entire three-phase output power conversion device, thereby reducing costs. It becomes the cause which obstructs miniaturization.

A fourth embodiment of the present invention according to claim 4 is for solving the above-mentioned problems, and FIG. 5 is a block diagram thereof. FIG. 5 differs from FIG. 4 in that the voltage detection circuit unit 221 _obtains a logical sum signal V _CNT of the output signal V _CNT1 of the latch circuit 208 and the output signal V _CNT2 of the latch circuit 210 by the OR circuit 217. The logical sum signal _VCNT is transmitted to the counters 206a and 206b in the voltage detection control circuit 206 through the insulation circuit PC4.

As described above, in order to detect the divided voltage, the respective output signals V _CNT1 and V _CNT2 of the latch circuits 208 and 210 are required. Therefore, in this embodiment, the logical sum is generated in the voltage detection control circuit 206. It is necessary to separate the signal _VCNT into _VCNT1 and _VCNT2 .
Here, as described above, the output signal V _CNT1 of the latch circuit 208 is output only within the first carrier cycle of the power converter, and the output signal V _CNT2 of the latch circuit 210 is within the second carrier cycle of the power converter. Is output only. Thus, by using the carrier sync signal _{V CAR,} it is easy to separate the logical sum signal _{V CNT} to the signal _{V CNT1, V CNT2} in the voltage detection control circuit 206, the signal _{V CNT1} as shown in FIG. 4, V _{The divided} voltage can be calculated without separately insulating the _{CNTs 2} and transmitting them to the control circuit unit 240.

According to the present embodiment, for example, in the case of a three-phase output power conversion device, the total number of insulation circuits necessary for performing voltage detection for three phases is six, which is lower than the example of FIG. Cost and size can be reduced.
This embodiment can also be applied to the case where the main circuit section is electrically insulated from the control circuit section together with the voltage detection circuit section in the second embodiment of the present invention shown in FIG. .

It is a block diagram which shows the structure of 1st Embodiment of this invention. FIG. 2 is an operation waveform diagram of FIG. 1. It is a block diagram which shows the structure of 2nd Embodiment of this invention. In 1st Embodiment of this invention, it is a block diagram at the time of insulating between the main circuit part and a voltage detection circuit part, and a power converter device control circuit part. It is a block diagram which shows the structure of 4th Embodiment of this invention. It is a main circuit block diagram of a PWM inverter. It is a block diagram which shows the structure of a prior art. FIG. 8 is an operation waveform diagram of FIG. 7.

Explanation of symbols

101: Voltage dividing circuit 202: Subtraction circuit 203: Integration circuit 206: Voltage detection control circuit 206a, 206b: Counter 207, 209: Comparator 208, 210: Latch circuit 215: NOT circuit 216, 217: OR circuit 220, 221: Voltage Detection circuit unit 230: Power conversion device main control unit 240: Power conversion device control circuit unit 300: DC power supply 301, 302: Semiconductor switching element 310: Main circuit unit INV: PWM inverter U: Output terminals SW ₀ , SW ₁ , SW ₂ , SW ₃ : Switch PC1, PC2, PC3, PC4, PC5: Insulation circuit

Claims (5)

In an output voltage detection circuit of a power converter having a power semiconductor switching element,
An integrating means for selecting a detected voltage, or an addition / subtraction result of the detected voltage and the first reference voltage or the second reference voltage and integrating with a predetermined time constant;
First comparing means for comparing the output of the integrating means with a third reference voltage;
Second comparing means for comparing the output of the integrating means with a fourth reference voltage;
First latch means for latching the output of the first comparison means in synchronization with the clock signal;
Second latch means for latching the output of the second comparison means in synchronization with the clock signal;
Voltage detection control means for inputting the outputs of the first and second latch means, the clock signal, and a synchronization signal synchronized with the switching cycle of the power converter, and enabling the integration means to be reset;
With
In the first period synchronized with the switching cycle of the power converter,
In accordance with the output of the first latch means, the addition or subtraction value of the detected voltage or the detected voltage and the first reference voltage is integrated by the integrating means,
In a second period that is synchronized with the switching period of the power converter and that is continuous with the first period,
In response to the output of the second latch means, the output of the integrating means at the end of the first period is set as an initial value, the second reference voltage is integrated by the integrating means, and then the integrating means is reset,
In the first period, the number of the clock signals in the period in which the addition / subtraction results of the detected voltage and the first reference voltage are integrated, or the number of the clock signals in the period in which the detected voltage is integrated is set as the first count value. And
In the second period, the number of the clock signals in the period obtained by integrating the second reference voltage is set as the second count value,
An output voltage detection circuit for a power converter, wherein a detected voltage is measured using the first count value and the second count value. In an output voltage detection circuit of a power converter having a power semiconductor switching element,
An integration means for selecting the detected voltage or the addition / subtraction result of the detected voltage and the first reference voltage and integrating with the first or second integration time constant;
First comparing means for comparing the output of the integrating means with a third reference voltage;
Second comparing means for comparing the output of the integrating means with a fourth reference voltage;
First latch means for latching the output of the first comparison means in synchronization with the clock signal;
Second latch means for latching the output of the second comparison means in synchronization with the clock signal;
Voltage detection control means for inputting the outputs of the first and second latch means, the clock signal, and a synchronization signal synchronized with the switching cycle of the power converter, and enabling the integration means to be reset;
With
In the first period synchronized with the switching cycle of the power converter,
In accordance with the output of the first latch means, the detected voltage or the addition / subtraction value of the detected voltage and the first reference voltage is integrated by the integrating means with a first integration time constant,
In a second period that is synchronized with the switching period of the power converter and that is continuous with the first period,
In response to the output of the second latch means, the output of the integrating means at the end of the first period is set as an initial value, the first reference voltage is integrated by the integrating means with the second integration time constant, and then Reset the integration means to
In the first period, the number of the clock signals in the period in which the addition / subtraction results of the detected voltage and the first reference voltage are integrated, or the number of the clock signals in the period in which the detected voltage is integrated is set as the first count value. And
In the second period, the number of the clock signals in the period obtained by integrating the first reference voltage is set as the second count value,
An output voltage detection circuit for a power converter, wherein a detected voltage is measured using the first count value and the second count value. In the output voltage detection circuit of the power converter according to any one of claims 1 and 2,
The output voltage detection circuit of a power converter, wherein the frequency of the clock signal is an integral multiple of the switching frequency of the power converter. In the output voltage detection circuit of the power converter device according to any one of claims 1 to 3,
A power conversion characterized by transmitting a logical sum signal of the output of the first latch means in the first period and the output of the second latch means in the second period to the voltage detection control means through an insulating means. Device output voltage detection circuit. In the output voltage detection circuit of the power converter device according to any one of claims 1 to 4,
The output voltage detection circuit for a power converter, wherein the detected voltage is a voltage obtained by dividing an output voltage of an inverter as a power converter.

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