JPH0614560A - Output voltage detecting circuit for power converter - Google Patents

Abstract

PURPOSE:To realize accurate detection of the output voltage from a power converter including the intermediate voltage thereof and to facilitate configulation of error compensation circuit. CONSTITUTION:Normalized voltage signal of quantized error is integrated, as feedback signal, by means of an integrator 20 for a normalized voltage signal Vd of output voltage on the main circuit 11 side. The integrated signal is then converted through upper and lower limit detectors 21, 22 into a digital value which is subsequently transmitted to the control circuit 12 side. Flip-flops 23, 24 latches the digital value according to a clock on the control circuit 12 side to produce a quantized error signal, which is subsequently employed in the detection of output voltage.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output voltage detecting circuit for detecting an output voltage of a power converter such as a PWM inverter as a quantized pulse.

[0002]

2. Description of the Related Art A PWM inverter has a bridge circuit of semiconductor switching elements (transistors, IGBTs, GTOs, etc.) as shown in the main circuit of a voltage type inverter in FIG. By performing on / off control, AC power such as a sine wave approximation is supplied to the load.

In the on / off control of the switching element according to the PWM waveform, there are factors such as switching delay of the element itself, addition of dead time for preventing the upper and lower arm elements from turning on at the same time, and time delay of the drive circuit. These exist and these time delays fluctuate due to load current, element temperature, and secular change. Therefore, there is a problem in that the output voltage of the PWM inverter does not have the output voltage according to the PWM waveform that is the PWM command.

For the output voltage error compensation for this purpose, an error voltage feedback system has been conventionally proposed in which an error voltage during PWM switching is measured and the PWM waveform is corrected by feedback. This conventional method is roughly classified into the following two types.

(1) Method of correcting every half-synchronization (1 amplifier method) In this method, as shown in FIG. 6, the switch timing of the PWM waveform of the main circuit 1 is detected by the hysteresis comparator 2, and this detection signal V _o is isolated by the photocoupler 3 and taken into the control circuit, and the PWM waveform signal V _{s is taken} on the control circuit 4 side.
The phase difference between the switch elements T _u and T is used as an error voltage by the analog integrator 5 to perform delay compensation and advance compensation, and the PWM waveform shaped by the hysteresis comparator 6 through the dead time circuit (including the drive circuit) 7. Control the output width of _x .

FIG. 7 shows the same one-amplifier system which is digitally constructed. The gate logic 8 detects the phase difference between the signal V _s and the detection signal V _o, and the phase difference up / down counter 9 issues an up-count command. And a down count command to obtain a delay corresponding to the error voltage in the counter 9,
The carry signal C and borrow signal B compensate for the set and reset timings of the latch circuit 10,
To obtain a PWM waveform with output error compensation.

In the above-described one-amplifier system, the compensating amplifier is one of the integrator 5 or the counter 9 and the output voltage error can be compensated, but the switching delay time of the switch element with respect to the PWM command cannot be controlled. That is, P
The delay time between the switching time of the WM command and the switching time actually output becomes uncertain.

(2) Method for correcting every one cycle (two-amplifier method) This method eliminates uncertainties of switching time in the one-amplifier method. Therefore, for example, as proposed in JP-A-2-189467, a PWM waveform is proposed. A first controller that detects a switching delay at the time of rising and corrects the next rising timing, and a second controller that detects a switching delay at the time of falling and corrects the next falling timing are provided.

According to this method, the switching delay time of the PWM waveform can be made constant along with the error compensation of the output voltage.

FIG. 8 shows a circuit diagram of a two-amplifier system, in which a counter 9A counts as an integral value of a rising error and a counter 9B counts as an integral value of a falling error.

[0011]

In the conventional error voltage feedback system, a comparator is used to quantize the output voltage into two values, a high level and a low level. For this reason, the output voltage is set to either the high level or the low level during the period when the output voltage is at the intermediate potential, and an error occurs in the amplitude component of the voltage detection.

For example, in a PWM inverter using an induction motor as a load, if the output current becomes zero during the dead time,
As the inverter output terminal voltage, a DC power supply voltage V _dc or a load induced voltage other than zero (reference potential) appears. Since this intermediate voltage is not converted into a digital value in the conventional method, the output voltage error cannot be completely eliminated, resulting in the generation of current ripple and unstable operation of the induction motor.

In order to solve the above-mentioned problem, it is possible to use an analog amplifier so as to feed back the detection of the output voltage without converting it into a digital amount. However, the main circuit and the control circuit are insulated from the problem such as noise. Therefore, an analog isolation amplifier is required, which makes the amplifier expensive and makes it difficult to obtain response in a wide band up to the PWM frequency component.

An object of the present invention is to provide a detection circuit which accurately detects an output voltage including an intermediate voltage and facilitates the construction of an error compensation circuit.

[0015]

In order to solve the above problems, the present invention has a main circuit in which switching elements are bridge-connected, and the main circuit is controlled by the on / off control of the switching elements from the control circuit side. In the power converter for controlling the output voltage, the main circuit includes a voltage converter for converting the output voltage into a normalized voltage signal, and an integrator for integrating a difference between the converted output and the normalized voltage signal of the quantization error signal. And a comparator that converts the output of the integrator into a 1-bit digital value as an error voltage detection signal. The control circuit detects the ON / OFF output of the comparator in units of a reference clock for quantization and And a latch circuit for obtaining a quantization error signal.

[0016]

With the normalized output voltage of the main circuit, the normalized voltage signal of the quantized error signal is used as a feedback signal for integration by an integrator, and this output is converted into a 1-bit digital value and is taken out to the control circuit side for control. The detection signal is quantized on the circuit side, and this signal is used as the quantization error signal to the integrator side to obtain the detected value of the quantized output voltage.

[0017]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. For the insulation coupling between the main circuit 11 and the control circuit 12, only digital signals are transmitted and received by the photocouplers 13 to 16.

The output voltage of the main circuit 11 is the transistor T
The voltage at the connection point of _u and T _x is converted by the normalized voltage converter 17 into an analog voltage signal V _d corresponding to the main circuit current voltage V _dc . This voltage conversion is converted into voltages V _dc and O according to ON / OFF of the transistors T _u and T _x according to the PWM signal, and the intermediate voltage is also converted to V _dc / 2. This conversion is realized by, for example, a resistance voltage dividing circuit.

Similarly, the normalized voltage converters 18 and 19 convert on / off of the quantization error signals Q _A and Q _B given from the control circuit 12 side through the photo couplers 13 and 14 into voltages V _dc and O, respectively. . Among these, the output ΔV _A of the voltage converter 18 is obtained by setting “1” of the signal Q _A to −V _dc and “0” to zero voltage. The output ΔV _B of the voltage converter 19 is “1” of the signal Q _B.
As + V _dc and "0" as zero voltage. This conversion is
For example, it is realized by a configuration in which one of two series switches to which the voltage V _dc is applied is turned on according to the signals "1" and "0".

The analog integrator 20 has a main circuit output voltage V _d.
The feedback signal for the signal is input as the signal ΔV _A or ΔV _B , and the error integration is performed. The upper limit detection circuit 21 obtains a digital value "1" in the signal S _A when the output Δφ of the integrator 20 is higher than the set upper limit value (positive polarity), and "0" in the signal S _A when it is lower than that. Obtain the digital quantity of. Conversely, the lower limit detection circuit 22 obtains a digital value of "1" in the signal S _B when the output Δφ of the integrator 20 becomes lower than the set lower limit value (negative polarity), and when the output Δφ becomes higher than that, the signal S _{To B} "
Obtain a digital quantity of 0 ".

The signals S _A and S _B are taken into the control circuit 12 side through the photocouplers 15 and 16 and are input as data to the D-type flip-flops 23 and 24, respectively, and the reference clock CLK is given to the clocks thereof, Flip flop 2
3 and 24 are taken out as the quantized error signals Q _A and Q _B.

The up / down counter 25 uses the signal Q _A as an up enable signal and the signal Q _B as a down enable signal, and adds or subtracts the clock CLK to obtain a count value corresponding to the integrated value of the error voltage.

In this embodiment, the main circuit output voltage V _d is detected by inputting a signal ΔV _A (negative) or ΔV _B (positive) to the input of the integrator 20 so that the output Δφ of the integrator 20 becomes zero. ) Is added to perform feedback control.

For example, when the output of the integrator 20 exceeds the upper limit set value of the upper limit detection circuit 21, a signal S _A = "1" is obtained, and this signal S _A is detected at the timing of the clock CLK and the signal Q _A = It becomes "1", and the output of the voltage converter 18 becomes -V _dc by this signal Q _A , and the output of the integrator 20 is controlled to be lowered.

On the contrary, when the output of the integrator 20 becomes lower than the lower limit set value, the signal S _B = “1” is obtained, and the signal S _B causes the signal Q _{B to} become “1”, and the voltage converter 19 Output is V _dc
Thus, the output of the integrator 20 is controlled to increase.

Here, the signals Q _A and Q _B are signals having a time width in which one clock width of the clock CLK is one unit, and the voltages of the signals ΔV _A and ΔV _B are V _dc and −V _dc , respectively. The feedback gain is adjusted by these time width and voltage.

From the above, in this embodiment, the output voltage V
The detection of _d is detected as a quantization error digital signal with the signals Q _A and Q _B. Further, by obtaining the integrated value of both signals by the counter 25, the detected value can be obtained at the output N thereof.
This output N can be taken out as a value corresponding to the intermediate voltage even when the voltage V _d is at the intermediate voltage.

Further, the detection signals Q _A and Q _B of the voltage V _d are set to PW.
Application as an output voltage error compensation circuit of the M inverter is realized by a configuration for correcting the command V _s of the PWM waveform with the signals Q _A and Q _B and generation of a PWM waveform using the output N of the counter 25.

FIG. 2 is a circuit diagram of essential parts showing another embodiment of the present invention. This figure is a simplified version of the configuration of FIG. 1, in which the upper and lower limit detection of the output Δφ of the integrator 20 is detected by one hysteresis comparator 26, and this one detection signal S _{x is set} to 1
One photocoupler 27 transmits it to the control circuit side, and on the control circuit side, one flip-flop 28 takes out the set and reset as signals Q _A and Q _B. The inverting gate 29 is for polarity matching of the signal Q _B.

FIG. 3 is a circuit diagram of essential parts showing another embodiment of the present invention. This figure is a simplified version of the configuration of FIG.
The output of the flip-flop 28 is input to the photocoupler 14 through the inverting gate 29, and the feedback from the voltage converter 18 side is omitted.

The reason why this embodiment is established will be described. Figure 2
In the above, since the output voltage V _d can take only values of 0 to V _dc , the output Δφ is changed only in the negative direction with respect to the integrator 20. Therefore, the feedback voltage is also + V _dc
Feedback control is established by the output V _dc and 0 as only the feedback component of, and the feedback from the voltage converter 18 side can be omitted.

In the present embodiment, the output Q _B of the flip-flop 28 is a quantized pulse which changes in the width unit of one cycle of the clock CLK, so that this signal Q _B is used as shown in FIG.
The compensation circuit used as the feedback pulse V _{o in} FIG. 7 can be constructed.

FIG. 4 is a circuit diagram showing another embodiment of the present invention. The command V _s of the PWM waveform is directly used as the control signal of the main circuit, and the error between the command V _s and the output voltage V _d is obtained by using the structure of FIG. Flip-flop 2 in the figure
The output of 8 is the enable signal of the up counter 30,
By setting the count input of the counter 30 to the clock CLK, the count value corresponding to the integrated value of the error is obtained.

The output of this counter 30 overflows
Latches to register 31 before and counter 30 immediately after
A rear CPU 32 and a control gate 33 are provided. Regis
Error data latched in the data 31 by the CPU 32
Command V generated digitally _sNext pulse correction amount
By this, the dead time can be compensated.

[0035]

As described above, according to the present invention, the difference between the normalized voltage of the output voltage and the normalized voltage signal of the quantization error is integrated by the integrator provided on the main circuit side, and this is integrated into a 1-bit digital signal. The value is converted into a value and the control circuit extracts it as a quantized error signal and uses it as a feedback signal to the integrator to detect the output voltage. Therefore, even if the output voltage includes an intermediate voltage, the accurate detection is possible. You can Also,
Digital values are exchanged between the main circuit side and the control circuit side, and there is an effect that the analog insulation amplifier and the like are not required since they are only coupled by the photocoupler and malfunction due to noise or the like can be surely prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a main part of another embodiment.

FIG. 3 is a circuit diagram of a main part of another embodiment.

FIG. 4 is a circuit diagram of another embodiment.

FIG. 5 is a main circuit diagram of a PWM inverter.

FIG. 6 is a circuit diagram of a conventional 1-amplifier system.

FIG. 7 is a circuit diagram of a conventional 1-amplifier system.

FIG. 8 is a circuit diagram of a conventional 2-amplifier system.

[Explanation of symbols]

 11 ... Main circuit 12 ... Control circuit 13, 16 ... Photo coupler 20 ... Integrator 21 ... Upper limit detector 22 ... Lower limit detector 23, 24 ... Flip-flop 25 ... Up-down counter 26 ... Hysteresis comparator

Claims (2)

[Claims] 1. A power converter having a main circuit in which switching elements are bridge-connected, and controlling the output voltage of the main circuit by on / off control of the switching elements from a control circuit side, wherein the main circuit has an output voltage. To a normalized voltage signal, an integrator that integrates the difference between the converted output and the normalized voltage signal of the quantized error signal, and an output of this integrator as an error voltage detection signal. And a latch circuit for obtaining the quantized error signal by detecting the ON / OFF output of the comparator for each quantization reference clock unit. Output voltage detection circuit for power converter. 2. The output voltage detection circuit of a power converter, wherein the control circuit includes a counter that counts the quantization error signal to obtain a detection value of the output voltage.