JPH0614559A - Error compensation circuit for power converter - Google Patents

Abstract

PURPOSE:To achieve positive operation without complicating the circuitry while detecting an error voltage accurately including the intermediate voltage of the output voltage from a power converter. CONSTITUTION:An integrator 23 integrates the difference between an ON/OFF control signal Vs and an ON/OFF output voltage Vg on the main circuit 11 side. Output from the integrator 23 is detected as a 1 bit digital error through upper and lower limit detectors 24, 25 and the error detection signals are quantized through flip-flops 26, 27 on the control circuit 12 side thus producing an error compensation feedback signal to the integrator 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output voltage error compensation circuit for a power converter such as a PWM inverter.

[0002]

2. Description of the Related Art A PWM inverter has a bridge circuit of semiconductor switching elements (transistors, IGBTs, GTOs, etc.) as shown in the main circuit of a voltage type inverter in FIG.・ By controlling OFF, AC power such as sine wave approximation is supplied to the load.

Factors such as switching delay of the element itself, addition of dead time for preventing the elements of the upper and lower arms from being turned on at the same time, and time delay of the drive circuit in the on / off control of the switching element according to the PWM waveform. Exist, and these time delays vary depending on the load current, element temperature, and aging. Therefore, there is a problem in that the output voltage of the PWM inverter does not have the output voltage according to the PWM waveform that is the PWM command.

For the output voltage error compensation for this purpose, an error voltage feedback system has been conventionally proposed in which an error voltage during PWM switching is measured and the PWM waveform is corrected by feedback. This conventional method is roughly classified into the following two types.

(1) Method of correcting every half cycle (1 amplifier method) In this method, as shown in FIG. 13, the switch timing of the PWM waveform of the main circuit 1 is compared with the hysteresis comparator 2.
And the detection signal V _o is insulated by the photocoupler 3 and taken into the control circuit, and the PWM waveform signal V is obtained on the control circuit 4 side.
The phase difference from _s is used as an error voltage to delay and advance compensation in the analog integrator 5, and the PWM waveform waveform-shaped in the hysteresis comparator 6 is used to switch the switching element T _u via the dead time circuit (including the drive circuit) 7. Control the output width of T _x .

In FIG. 14, the same one-amplifier system is digitally constructed. The gate logic 8 detects the phase difference between the signal V _s and the detection signal V _o, and the up-down counter 9 counts up the phase difference. By issuing a command and a down-count command, a delay corresponding to the error voltage is obtained in the counter 9, and the latch signal 1 is generated by the carry signal C and borrow signal B.
A PWM waveform is obtained by compensating the set and reset timings of 0 and the output error of the output of the latch circuit 10.

In the above-described one-amplifier system, the compensating amplifier is one of the integrator 5 or the counter 9 and the output voltage error can be compensated, but the switching delay time of the switch element with respect to the PWM command cannot be controlled. That is, P
The delay time between the switching time of the WM command and the switching time actually output becomes uncertain.

(2) Method of compensating every one cycle (two-amplifier method) This method eliminates uncertainties of switching time in the one-amplifier method. Therefore, for example, as proposed in JP-A-2-189467, a PWM waveform is proposed. A first controller that detects a switching delay at the time of rising and corrects the next rising timing, and a second controller that detects a switching delay at the time of falling and corrects the next falling timing are provided.

In this method, the output voltage error is compensated and P
The switching delay time of the WM waveform can be made constant.

[0010]

In the conventional error voltage feedback system, a comparator is used to quantize the output voltage into two values, a high level and a low level. For this reason, the output voltage is set to either the high level or the low level during the period when the output voltage is at the intermediate potential, and an error occurs in the amplitude component of the voltage detection.

For example, in a PWM inverter using an induction motor as a load, if the output current becomes zero during the dead time,
The induced voltage of the load other than the DC power supply voltage V _dc or zero (reference potential) appears as the inverter output terminal voltage. Since this intermediate voltage is not converted into a digital value in the conventional method, the output voltage error cannot be completely eliminated, resulting in the generation of current ripple and unstable operation of the induction motor.

In order to solve the above problem, it is conceivable to use an analog amplifier so as to feed back the detection of the output voltage without converting it into a digital quantity.
Since it is necessary to insulate between the main circuit and the control circuit from the problem of noise and the like, an analog isolation amplifier is required, which becomes an expensive amplifier and makes it difficult to obtain responsiveness in a wide band up to the PWM frequency component.

It is an object of the present invention to provide an error compensating circuit which can detect the error voltage including the intermediate voltage of the output accurately and obtain a reliable operation without complicating the circuit.

[0014]

In order to solve the above problems, the present invention has a main circuit in which switching elements are bridge-connected, and the main circuit is controlled by the on / off control of the switching elements from the control circuit side. In the power converter for controlling the output voltage, the main circuit includes a voltage converter for converting the level of the on / off control signal of the switching element into a normalized voltage signal, the converted output and the on / off output of the main circuit. And a comparator that converts the output of the integrator into a 1-bit digital value as an error voltage detection signal, and the control circuit turns on / off the comparator. A latch circuit for detecting the output in units of a reference clock for quantization, and an error compensation feedback circuit from the latch output and the on / off control signal to the integrator. Characterized in that a error compensation signal generating means for obtaining a signal as an on-off signal.

[0015]

Operation: The main circuit side detects an error between the on / off control signal of the main circuit and the on / off output voltage, converts this detection signal into a 1-bit digital value, and outputs it to the control circuit side. The detection signal is quantized by and the error feedback signal from the on / off control signal of the main circuit to the integrator is obtained as the on / off signal.

[0016]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. The main circuit 11 and the control circuit 12 are insulated and coupled so that only digital signals are transmitted and received by the photocouplers 13 to 18, and the error voltage is detected by analog operation on the main circuit 11 side, and feedback including the intermediate voltage is performed. Allow control.

The voltage command V _s of the PWM waveform is insulated by the photocoupler 14 and taken into the main circuit 11 side, and converted into an analog voltage signal by the normalized voltage converter 19 on the main circuit 11 side. This voltage conversion is based on the PWM signal “1”,
“0” is taken out as a signal corresponding to the main circuit current voltage V _dc , O. For example, a multiplier is used for the voltage converter 19 and the analog signal of the voltage V _dc is used as the multiplicand. Further, by turning on one of the two series switches for applying the voltage V _{dc according} to the inputs “1” and “0”, it is possible to obtain the signals V _dc and O at the switch connection point.

The output voltage of the main circuit 11 is the transistor T
The voltage at the connection point of _u and T _x is taken out by the normalized voltage converter 20 as an analog signal corresponding to the voltage V _dc . Since the analog signal also includes the intermediate voltage as described above, the intermediate voltage is also detected. The converter 20 is realized by, for example, a resistance voltage dividing circuit or a voltage-current conversion circuit using a series resistor.

The voltages V _s and V _d detected by the voltage converters 19 and 20 are taken out as a difference voltage ΔV by the comparator 21, input to the integrator 23 through the adder 22 for balanced feedback, and then the integrator 23. At, the analog integration of the error voltage is done. The structure of this portion is, for example, the structure shown in FIG.

The output Δφ of the integrator 23 is input to the upper limit detector 24 and the lower limit detector 25. The upper limit detector 24 outputs the signal S when the signal Δφ becomes higher than the set upper limit value (positive polarity).
_A digital quantity of "1" is obtained for _A, and a digital quantity of "0" is obtained for the signal S _A when the digital quantity is lower than that. On the contrary, the lower limit detector 25 obtains a digital amount of "1" in the signal S _B when the signal Δφ becomes lower than the lower limit set value (negative polarity), and "0" in the signal S _B when the signal Δφ is higher than that. Obtain the digital quantity of.

The signals S _A and S _B are taken into the control circuit 12 side through the photocouplers 17 and 18 and are input to the balanced type error voltage detection circuit. This detection circuit inputs a signal ΔV _A to the input of the integrator 23 so that the output Δφ of the integrator 23 becomes zero.
(Negative) or ΔV _B (positive) is added, and when the signal S _A or S _B becomes “1”, it is assumed that Δφ is a value apart from zero and the feedback voltage by the signals ΔV _A and ΔV _B To occur.

Here, the feedback gain is adjusted by appropriately selecting the amplitude and time width of the feedback voltage. Therefore, the signals S _A and S _B are transmitted to the photocoupler 1
By inputting the data to the D-type flip-flops 26 and 27 through 7 and 18, and applying the clock from the reference clock CLK, the time width with one clock width as one unit is obtained as the signals Q _A and Q _B. Further, the signals Q _A and Q _B are passed through the photocouplers 15 and 16 to the voltage converters 28 and 29 on the main circuit side.
The inputs "1" and "0" are taken out by the voltage converters 28 and 29 in association with the voltages ΔV _A , O or ΔV _B , O, and the amplitude of the feedback voltage is set as the voltage conversion coefficient. . In this embodiment, the voltage amplitude is ΔV _A = −V
_dc and ΔV _B = V _dc are set.

The up / down counter 30 uses the signal Q _A as an up enable signal, the signal Q _B as a down enable signal, and adds or subtracts the clock CLK to obtain a count value corresponding to the integrated value of the error voltage. The carry signal C when the count value reaches the maximum value and the borrow signal B when the count value reaches the minimum value are used as the set and reset signals of the RS flip-flop 31, and the PWM waveform is output to the flip-flop 31. Of the dead time circuit 3 of the main circuit 11 through the photo coupler 13
2 to the PWM control signal.

The operation of this embodiment will be described in detail with reference to FIG.

When the output voltage V _{d of the} inverter is in the state shown in the figure with respect to the command signal V _{s of the} PWM waveform and an intermediate voltage exists in the voltage V _d , both inputs V _{s of the} comparator 21 until time t _1. , V _d are both at a level corresponding to V _dc , the initial value of the output Δφ = 0 of the integrator 23 is within the upper and lower limits, and the feedback voltages ΔV _A and ΔV _B are both zero.

At time t ₁ , the voltage V _d becomes the intermediate voltage V _dc / 2, the output of the comparator 21 becomes ΔV = V _dc / 2, and the output Δφ of the integrator 23 starts to increase to the positive side. And △ φ
Reaches the upper limit value at time t ₂ , the signal S _A becomes “1”, and the output Q _A of the flip-flop 26 changes to “1” at the next rising edge t ₂ ′ of the clock CLK. Hold until the next clock rise time t ₃ ′.

The signal Q _A = at this time t ₂ ′ -t ₃ ′
Due to "1", the adder 22 outputs a signal ΔV _A (= -V _dc ).
Is added. As a result, the input signal of the integrator 23 is ΔV
And the combined value of ΔV _A and −V _dc / 2 are input, and the output Δφ decreases. When the time t ₃ ′ is reached, the output Δφ is lower than the upper limit value, so that the signal Q _A =
It has become “0”, and the signal ΔV _A returns to zero. From this time t ₃ ′, the output Δφ of the integrator 23 starts increasing again,
When the upper limit value is reached at time t ₄ , a signal Δ is generated at the next clock t ₄ ′.
V _A becomes −V _dc .

As a result of such repetition, the signal Q _A becomes 1
Repeats "1" and "0" for each clock,
Only increments the count value when Q _A is "1" and counts up once every two clocks. From this, the signal Q _A is “1” every other clock during the intermediate voltage period (t ₁ −t ₅ ).
And "0" are repeated to operate the output of the integrator 23 within the upper limit, and the count value of the counter 30 is counted up every two clocks. Therefore, the intermediate voltage period counter 30 rises with a slope of 1/2 as compared with the case of integrating the clock as it is, and obtains an integral value proportional to the error voltage ΔV (= V _s −V _d ).

Next, at time t ₅ , the detection voltage signal V _d becomes zero and the error voltage ΔV = V _dc . As a result, time t ₅
After that, the slope of integration doubles, and the signal Q _A becomes “1” in synchronization with the clock at the signal S _A = “1” when the output of the integrator 23 reaches the upper limit value.

At this time, ΔV = V _dc , ΔV _A = −V
_dc , the input signal to the integrator 23 becomes just zero, and the output Δφ of the integrator 23 is held at a constant value exceeding the upper limit. The signals S _A and Q _A are “1” until ΔV ≠ V _dc.
, And the counter 30 counts up every clock.

And V_sWhen = “0” and ΔV = 0
Tick t₆Then signal Q_ADue to ΔV_A= -V _dcOnly integrated
Therefore, Δφ starts decreasing from the upper limit value toward zero.

Similarly, time t ₇ when the voltage error ΔV becomes negative.
After that, the output Δφ of the integrator 23 reaches the lower limit level, the signal Q _B repeats “1” and “0” every other clock in the intermediate voltage period, the counter 30 counts +1 in 2 clocks, and the time t ₈ After that, +1 is counted every clock.

As is apparent from the above operation, the signals Q _A and Q _B output the same number of pulses as the value obtained by time-integrating the amplitude of the error voltage ΔV, and at the intermediate voltage of V _dc / 2, the pulses are output. Since the number is also thinned to 1/2, an accurate error voltage including the intermediate potential can be quantized into a digital quantity. The unit of quantization at this time is the amplitude V _dc and the time width is one clock.

The signals Q _A and Q _B can be counted up and down by the counter 30 to obtain the integrated value of the error voltage and obtain the PWM waveform of the main circuit in the flip-flop 31. This circuit portion corresponds to the counter 9 and the flip-flop 10 in FIG. 14, but in the present embodiment, the detection including the intermediate voltage in the error voltage detection enables accurate dead time compensation.

Further, in this embodiment, the flip-flop 2
6 and 27 can be installed on the control circuit 12 side, and malfunctions due to noise can be prevented compared to the case where they are installed on the main circuit 11 side.

Further, in this embodiment, since the PWM command on the control side is transferred to the main circuit side by the photocoupler and the error voltage is detected on the main circuit side, the expensive analog isolation amplifier is not required and the coupling is performed only by the photocoupler. Can be configured to.

FIG. 3 is a circuit diagram of essential parts showing another embodiment of the present invention. 1 is different from FIG. 1 in that a logic circuit 33 is provided in place of the flip-flops 26 and 27. The logic circuit 33 limits the data input in order to obtain the signals Q _A and Q _{B due} to the relationship with the command signal V _s, and further prevents malfunction.

In FIG. 3, the D-type flip-flop 3
Reference numerals 4 and 35 correspond to the flip-flops 26 and 27 shown in FIG. 1, and the data input D has "1" and "0" of the signal V _s.
Is provided with AND gates 36 and 37 and an inverting gate 38 so as to give the signal S _A or S _B to only one data input, and a D-type flip-flop 39 for synchronizing the signals Q _A and Q _B with the signal V _s. Is provided.

The operation of this embodiment will be described. First, in the configuration of FIG. 1, the command V _s is given as a binary value of “1” or “0”, and the detection voltage V _d is changed from zero by the diodes D _u and D _x antiparallel to the transistors T _u and T _x. It is clamped in the range of voltage V _dc .

Therefore, the value of the differential voltage ΔV output from the comparator 21 is as follows when V _s = “0”.

[0041]

## EQU1 ## When V _d = 0, ΔV = V _s −V _d = 0

[0042]

## EQU2 ## When V _d = V _dc , ΔV = V _s −V _d = −V _{dc, that} is, ΔV can take only a negative value from −V _{dc to} 0. Change only in the negative direction.

On the other hand, when V _s = “1”,

[0044]

(3) When V _d = 0 ΔV = V _dc

[0045]

Equation 4] when _{V d = V dc △ V =} 0 That is, △ V from the inability to take only positive values of 0 to V _dc, varying only in the positive direction with respect to the integrator 23.

Therefore, when V _s = “0”, the negative feedback signal Q _A for balancing cannot be generated, and V _s =
At "1", the positive feedback signal Q _B cannot be generated, and the signals Q _A and Q _B are gated by the AND gates 36 and 37 by the "1" and "0" of the signal V _s , and the flip-flop It prevents the 34 and 35 from malfunctioning. For this purpose, the relationship with the signal V _s is a condition, so that the flip-flop 39 synchronizes with the clock CLK.

FIG. 4 is a circuit diagram of essential parts showing another embodiment of the present invention. 3 is different from FIG. 3 in that a hysteresis comparator 40 is used for detecting the upper and lower limits of the integrator 23.

In the present embodiment, the output S _x of the hysteresis comparator 40 has the upper limit detection signal S _A in the same phase, but has the opposite phase to the lower limit detection signal S _B , so the signal S to the gate logic circuit 37 is generated. The inverted input of the signal S _x is applied as the input of _B.

In this embodiment, by using one hysteresis comparator for detecting the upper and lower limits, one photocoupler 41 can replace the two photocouplers 17 and 18.

The time chart of this embodiment is shown in FIG.
In the figure, the error voltage ΔV up to time t ₁ and the error voltage ΔV from time t ₁ to t ₂ are quantized for 15 clocks, but the error count value of the counter 30 is 16 counts. It has two comparators 24, 25
This is because Δφ is set to move in one clock to move the hysteresis width when one hysteresis comparator is used instead of. It is possible. It should be noted that since the positive error and the negative error are inversely counted, no error occurs in the integrated value of the counter 30.

FIG. 6 is a circuit diagram of essential parts showing another embodiment of the present invention. 4 is different from FIG. 4 in that the adder 22 is moved to the preceding stage of the comparator 21, and the normalized voltage conversion is performed by the addition result of the adder 22.

Therefore, the photocouplers 14, 15, 16
The voltage converters 19, 28, 29 provided for the respective outputs can be simplified to one voltage converter 42 and the inverting gate 43.

FIG. 7 shows an embodiment in which the embodiment of FIG. 6 is further simplified. Since the input circuit configuration including the adder 22 is all logical signals in FIG. 6, the truth table of the addition result for the signals V _s and S _x is as follows.

[0054]

[Table 1]

However, Q _A , Q _B and ΔV 'are values after the flip-flops 34 and 35 are latched.

[0056] From the above table, the addition output △ V ', the signal V _s by the exclusive OR circuit (E _x -OR) 43 shown in FIG. 7
And the input of S _x , and the output of the flip-flop 44
It is sufficient to latch with the clock CLK and to take in this latched output to the main circuit side with one photocoupler 45.

In this embodiment, since the signal V _s is synchronized with the clock CLK, an error occurs in the synchronization. This error can be eliminated by using the clock as the clock CLK as a digitizing circuit when the signal V _s is generated. Further, the error can be made extremely small by setting the clock CLK to a sufficiently high frequency.

FIG. 8 shows a case where the balanced type error voltage quantization circuit shown in FIG. 7 is applied to the one-amplifier system shown in FIG.

FIG. 9 shows an embodiment in which the up / down counter 9 of FIG. 8 is replaced with a counter 46 of up / down switching input and count enable input type.

Further, FIG. 10 shows a case where the balanced type error voltage quantization circuit shown in FIG. 7 is applied to the two-amplifier system. In the figure, the up counters 47 and 48 count up by the enable input "1" and hold by the enable input "0", and the flip-flop 10 is set and reset by the key output of the respective counters 47 and 48.

Embodiments up to the above (FIGS. 8, 9 and 10)
Constitutes a feedback control for automatically correcting an error in the output voltage due to a dead time or the like, but the present invention is not limited to this and can be used as a means for detecting an error voltage.

FIG. 11 shows an embodiment in which the error voltage detecting means is used. The command V _s of the PWM waveform is used as it is as a control signal of the main circuit, and an error between the command V _s and the detection voltage V _d is obtained. In the figure, a counter 51 performs a counting operation according to an error voltage, and a CPU 51 and a control gate 52 are provided which latch the output of the counter 49 in a register 50 before overflow and clear the counter 49 immediately after. By using this error data as the correction amount of the next pulse of the command V _s digitally generated by the CPU 51, dead time compensation becomes possible.

[0063]

As described above, according to the present invention, the error voltage is detected as a 1-bit digital value on the main circuit side,
The control circuit side quantizes this signal, and the error feedback signal to the integrator from this signal and the on / off control signal of the main circuit is obtained as an on / off signal. While accurately detecting the error voltage, only the digital signals need to be coupled by the photocoupler to exchange signals between the main circuit and the control circuit, and the latch circuit or the like is provided on the control circuit side to ensure the prevention of malfunction.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a time chart of FIG.

FIG. 3 is a circuit diagram of a main part of another embodiment.

FIG. 4 is a circuit diagram of a main part of another embodiment.

5 is a time chart of FIG.

FIG. 6 is a circuit diagram of a main part of another embodiment.

FIG. 7 is a circuit diagram of a main part of another embodiment.

FIG. 8 is a circuit diagram of another embodiment.

FIG. 9 is a circuit diagram of another embodiment.

FIG. 10 is a circuit diagram of another embodiment.

FIG. 11 is a circuit diagram of another embodiment.

FIG. 12 is a main circuit diagram of a PWM inverter.

FIG. 13 is a circuit diagram of a conventional 1-amplifier system.

FIG. 14 is a circuit diagram of a conventional 1-amplifier system.

FIG. 15 is a partial configuration diagram of an error detection circuit in the embodiment.

[Explanation of symbols]

 11 ... Main circuit 12 ... Control circuit 13,18 ... Photo coupler 23 ... Integrator 24 ... Upper limit detector 25 ... Lower limit detector 26,27 ... Flip-flop 30 ... Up-down counter 40 ... Hysteresis comparator

Claims (1)

[Claims] 1. A power converter that has a main circuit in which switching elements are bridge-connected, and controls the output voltage of the main circuit by on / off control of the switching elements from a control circuit side, wherein the main circuit comprises: A voltage converter that converts the level of the on / off control signal of the switching element into a normalized voltage signal, an integrator that integrates the difference between this converted output and the normalized voltage signal of the on / off output of the main circuit, and A comparator for converting the output of the integrator into a 1-bit digital value as an error voltage detection signal; and the control circuit for detecting an on / off output of the comparator in units of a reference clock for quantization; An error compensation signal generator for obtaining an error compensation feedback signal from the latch output and the on / off control signal to the integrator as an on / off signal. Error compensation circuit for a power converter characterized by comprising and.