GB1573724A - Analogue-to-digital converter - Google Patents

Description

(54) ANALOGUE-TO-DIGITAL CONVERTER (71) We, PHILLIPS ELECTRONIC AND ASSOCIATED INDUSTRIES LI MITED of Abacus House, 33 Gutter Lane, London, EC2V 8AH a British Company, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement: This invention relates to analogue-todigital converter circuit arrangements (hereinafter referred to as "A-to-D convertors") which are used for converting an analogue signal into a representative digital number.

Various different forms of A-to-D convertors are already known, examples being given in the catalogue-type publication "Non-linear Systems Inc., 1970/1"; and in "Electronic A-to-D Conversions" by H.

Schmid, published by Van Nostrand/ Reinhold, 1970, New York, U.S.A. A common practice in known A-to-D convertors is to generate a ramp voltage of constant slope, compare the progressively changing instantaneous amplitude of the ramp voltage with the amplitude of an input analogue signal voltage, and count the pulses of a clock pulse train during the period from the start of the ramp voltage to the detection of equality between the amplitude of the ramp voltage and that of the input analogue signal voltage. The latter is then represented by the digital number provided by the resultant count. This digital number may be a binary number which is produced by a binary counter in response to the clock pulses. Also, such a binary number may be converted into a binary coded number prior to utilisation.By way of further explanation of this prior art, Figure 1 of the accompanying drawings illustrates a basic circuit diagram of a known ramp voltage generator, Figure 2 illustrates diagrammatically a known A-to-D convertor, and Figure 3 shows idealised waveform diagrams for the operation of the A-to-D convertor of Figure 2.

Referring to Figure 1, the known ramp voltage generator there shown comprises a transistor 1 which functions as a constant current source for charging a capacitor 2.

The emitter-collector path of the transistor 1, the capacitor 2 and a resistor 3 are connected in series between positive and negative supply lines +ve and -ve. The junction of resistor 3 and the emitter of transistor 1 is connected to a first input 4 of a comparator amplifier 5. A second input 6 of this comparator amplifier 5 is connected to receive a reference voltage Vre from a reference voltage source 7. The output 8 of the comparator amplifier 5 is connected to the base of the transistor 1. In operation, the capacitor 2 is charged by the current flow through the transistor 1 at the collector of which is produced an output ramp voltage Vra the slope of which depends upon the rate of charging of the capacitor 2.If the voltage at the emitter of transistor 1 changes, the voltage at its base is changed by the signal output from the comparator amplifier 8 to maintain the conduction of transistor 1 substantially constant. The ramp voltage generator also includes a second transistor 9 which has its emitter-collector path connected across the capacitor 2. This transistor 9 is periodically rendered conductive by a reset pulse Vrs applied to its base to discharge the capacitor 2 and thereby reset the ramp voltage generator.

In the A-to-D convertor shown in Figure 2, the ramp voltage generator of Figure 1 is represented by the block 10. This A-to-D convertor further comprises a comparator amplifier 11, an AND-gate 12, a counter 13, a latch 14, a multi-vibrator 15, and a clock pulse source 16. The output ramp voltage Vra from the ramp voltage generator 10 is applied to a first input 17 of the comparator amplifier 11. An input analogue signal voltage Vx for conversion into a digital number is applied to a second input 18 of the comparator amplifier 11. The output 19 of the comparator amplfier 11 is connected to a first input 20 of the AND-gate 12. A second input 21 of the AND-gate 12 is connected to receive clock pulses Vc1 from the clock pulse source 16.The counter 13 is connected to receive the clock pulses Vc1 from the AND-gate 12 when the latter is open, and the latch 14 is connected to receive the resultant count of the counter 13 over a multi-lead input connection 22, the latch 14 being rendered operable in response to a "latch-open" signal So applied to an input 23 thereof from the output 19 of the comparator amplifier 11. A multi-lead output connection 24 from the latch 14 provides the resultant count as a digital number.

Consider now the operation of the A-to D convertor shown in Figure 2, an operating sequence is started in response to each reset pulse Vrs produced by the multi-vibrator 15.

These reset pulses Vrs from the multivibrator 15 are represented by waveform diagram (a) of Figure 3 and reset the ramp voltage generator 10 and the counter 13. At the termination of a reset pulse Vrs the ramp voltage generator 10 starts to produce the ramp voltage Cra which is represented by the waveform diagram (b) of Figure 3.

Waveform diagram (c) of Figure 3 represents the signal output So from the comparator amplifier 11. During the period tO-tl when the amplitude of the ramp voltage Vra is less than that of the input analogue signal voltage Vx, the comparator amplifier signal output So is "high" and opens AND-gate 12, so that clock pulses Vc1, as represented by waveform diagram (d) of Figure 3, are applied through the AND-gate 12 to the counter 13 during this period tO-tl.At time tl, when equality between the amplitudes of the voltages Vx and Vra is reached, the comparator amplifier signal output So goes "low" and remains "low" for the period tl-t2. During this period t1-t2 AND-gate 12 is closed so that no further clock pulses Vc1 are fed to the counter 13, and the resultant count is "latched" into the latch 14 by the signal output So during the period tl-t2. At time t2 the leading edge of the reset pulse V4s occurs to reset the ramp generator 10 and the counter 13. The reset pulse persists for the period t2-t0', and at time to' the next operating sequence is started.The digital number representing the input analogue signal voltage Vx is held on the multi-lead output connection 24 during the period tl-tl, being then modified in accordance with any change in the voltage Vx and then held for the next such period, and so on.

The foregoing description of prior art has been given in order to emphasise that hitherto the accuracy of operation of an A-to-D convertor of a type in which a ramp voltage is used and clock pulses are counted during a period of ramp voltage generation relies inter alia upon the accuracy with which the slope (dVra/dt) of the ramp voltage Vra and the accuracy with which the frequency of the clock pulse Vc1 can be produced. Of these accuracy requirements, the more difficult to achieve is that of the ramp voltage because it relies for its accuracy on a reference voltage (Vre), a resistor (3) and a capacitor (2) - see Figure 1 - which therefore require close tolerances if a high degree of accuracy is to be achieved. Also, the required degree of accuracy for the clock pulse frequency may necessitate the use of a crystal-controlled oscillator.

The present invention enables the provision of an A-to-D convertor of the above type which obviates the need for relying on the accuracy of a capacitor and a resistor to produce a highly accurate ramp voltage, so that a resistor and capacitor of lower tolerance then hitherto can be used in the generation of the ramp voltage. The present invention also obviates the need for having a highly accurate clock pulse frequency.

According to the present invention there is provided, particularly but not exclusively in or for use in an A-to-D convertor for converting an analogue signal into a representative digital number, a ramp voltage generator arrangement comprising, a variable slope ramp voltage generator for generating a ramp voltage, a clock pulse source for generating clock pulses, a counter for counting the number of clock pulses occurring in recurrent periods of ramp voltage generation, each such period corresponding notionally to n clock pulse periods and said counter being operable to produce a first output signal having one or the other of two values according as the number of clock pulses actually occurring in such a period is less or greater than n, a comparator for comparing during each said period the amplitude of a reference voltage with the progressively changing instantaneous amplitude of said ramp voltage and being responsive to produce a second output signal having one or the other of two values according as the amplitude of said ramp voltage is less or greater than that of said reference voltage, a logic circuit which is responsive to said first and second output signals to provide an increment signal or a decrement signal when the number of clock pulses occurring in a said period is greater or less than n before the ramp voltage amplitude exceeds the reference voltage amplitude, and a feedback control circuit which is operable to apply the variable slope ramp voltage generator a feedback control signal for determining the slope of the ramp voltage, said feedback control circuit being an analogue voltage store which is adapted to store the feedback voltage control signal which is increased and decreased, respectively, in amplitude by a fixed amount in response to each increment signal and each decrement signal received whereby to vary the ramp voltage slope towards a rate appropriate for achieving equality of amplitude of said ramp and reference voltages in a period of ramp voltage generation corresponding to n clock pulse periods.

The invention thus provides a ramp voltage generator arrangement for producing a ramp voltage which is stabilised, using an analogue voltage store, by feedback derived from comparing the ramp voltage with a reference voltage.

In carrying out the invention the analogue voltage store may comprise a storage capacitor which is incrementally charged and discharged by two diode pump circuits which are responsive, respectively, to the increment signals and to the decrement signals.

In order to mitigate the tendency for the slope of the ramp voltage to oscillate about its notional correct slope, the value of said fixed amount can be made such that correction of the slope of the ramp voltage is made over a number of periods of ramp voltage generation. Thus, each increment/decrement signal can occur at the clock pulse frequency.

The counter of the ramp voltage gener ator arrangement may be a binary counter a selected bit output of which charges from a '0' to a '1' after the n clock pulses applied to the counter.

A ramp voltage generator arrangement according to the invention can be embodied in an A-to-D convertor arrangement which comprises one or more effective A-to-D convertors, the or each A-to-D convertor being connected to use the clock pulses and the ramp voltage of the ramp voltage generator arrangement to produce a digital number which corresponds to a clock pulse count in a period taken for the ramp voltage amplitude to reach equality (or other given relationship) with an input analogue signal voltage amplitude.The or each such A-to-D convertor may comprise a comparator for comparing an input analogue signal voltage with said ramp voltage, and a counter for counting the number of clock pulses occurring in a period from the start of the ramp voltage to the detection of equality (or other given relationship) between the amplitude of the ramp voltage and that of the input analogue signal voltage, the or each A-to-D convertor further comprising a gate through which the clock pulses are applied to the counter and which is closed by the comparator signal output upon said detection, and a latch which is responsive to said comparator signal output to store the count of the counter as a digital number which is representative of the input analogue signal voltage applied to the A-to-D convertor.

In order that the invention may be more fully understood reference will now be made by way of example to the remaining Figures of the accompanying drawings. In the drawings: Figure 1 illustrates, as aforesaid, a basic circuit diagram of a known ramp voltage generator; Figure 2 illustrates diagrammatically, as aforesaid, a known A-to-D convertor; Figure 3 shows, as aforesaid, idealised waveform diagrams for the operation of the A-to-D convertor of Figure 2; Figure 4 illustrates diagrammatically a ramp voltage generator arrangement according to the invention; Figure 5 illustrates diagrammatically an A-to-D convertor arrangement embodying the ramp voltage generator arrangement of Figure 4; Figure 6 shows a circuit diagram of the A-to-D convertor arrangement of Figures 4 and 5; and Figure 7 shows idealised waveform diagrams for the operation of the ramp voltage generator arrangement of Figure 4 and the A-to-D convertor of Figure 5.

The ramp voltage generator arrangement shown in Figure 4 comprises a clock pulse source 25 which is connected to apply clock pulses Vc1 to an 8-bit binary counter 26 and to a 'C' input of a logic circuit 27. This logic circuit 27 has an 'X' input connected to the 'bit 8' output of the counter 26 and a 'Y' input connected to the output 28 of a comparator amplifier 29. The logic circuit 27 also has a first output 30 connected to an increment" input 31 and a second output 32 connected to a "decrement" input 33 of an analogue voltage store 34. The store 34 has an output 35 connected to a 'control' input 36 of a variable slope ramp voltage generator 37.The comparator amplifier 29 has a first input 38 connected to receive the output ramp voltage Vra from the ramp voltage generator 37 and a second input 39 connected to receive a reference voltage Vre from a reference voltage source 40. The ramp voltage generator arrangement of Figure 4 also includes a divide-by-256 circuit 41 which is connected to receive the clock pulses Vc1 and supplies a reset pulse Vrs to the counter 26 and the ramp voltage generator every 256th clock pulse. Equivalently, the circuit 41 may be a suitably-timed free-running multi-vibrator, such as the multi-vibrator 15 in the A-to-D convertor of Figure 2. Also, the circuit 41 may comprise a 'bit 9' output of the counter 26, which latter would then be self-resetting.

Consider now the operation of the ramp voltage generator arrangement, which will be described also with reference to the waveform diagrams shown in Figure 7. A reset pulse Vrs from the circuit 41 occurring in the period ta-tb resets the ramp voltage generator 37 and the counter 26, the reset pulses Vrs being represented by the waveform diagram (a) of Figure 7. The counter 26 is now responsive to the clock pulses Vc1 applied to it from the clock pulse source to start its binary count cycle of 256 jut after the time ta.On the basis of the convention that the first bit of an eight-bit counter is bit 20, so that the eighth bit is bit 27, (i.e. 20=1, 2l=2, 22=4, 23=8, 24=16, 25=32, 26=64 and 27=128), the 'bit 8' output will become a '1' after 128 clock Pulses Vc1 and thereafter remain at a '1' (or high) level until the counter 26 is reset by the next reset pulse Vrs. The next reset pulse Vrs has to occur no later than the 256th clock pulse Vc1 to avoid erroneous values in the counter 26 due to the counter completing a cycle. This is achieved by using the divider circuit 41 to produce a reset pulse Vrs every 256th clock pulse. Waveform diagrams (d) and (e) of Figure 7 represent two occurrences of the 'bit 8' output becoming '1' at respective different times tc and te.The ramp voltage generator 37 is responsive at time tb after being reset to generate a ramp voltage Vra in the period tb - ta', following which it is reset by the next reset pulse Vrs in period ta' - tb', and so on. At time td during the period tb - ta' of ramp voltage generation, the amplitude of the ramp voltage Vra reaches equality with the amplitude of a reference voltage Vre. This equality is detected by the comparator amplifier 29 which as a result changes its signal output So' from a "high" level to a "low" level, waveform diagram (c) of Figure 7 representing the comparator amplifier signal output So'.

If the slope of the ramp votage Vra is correct, the time td will coincide with the time when 128 clock pulses Vc1 have been counted by counter 26, so that the 'bit 8' output of the counter will change to a '1' synchronously with the change of the signal output So' from a "high" level to a "low" level. However, if the slope of the ramp voltage Vra is not steep enough, then the signal output So' will still be at a "high" level when the 'bit 8' output changes to a '1' (e.g. at time te as shown in waveform diagram (d)). As a result, the 'X' and 'Y' inputs of the logic circuit 27 are both at a "high" level at the same time, so that on the occurrence of the next clock pulse Vc1 when the 'C' input is also at a "high" level, an increment signal (X.Y.C) is applied to the increment" input 31 of the store 34.

Conversely, if the slope of the ramp voltage Vra is too steep, then the signal output So' will have changed to a "low" level before the 'bit 8' output changes to a '1' (e.g. at time te as shown in waveform diagram (d)).

As a result, the 'X' and 'Y' inputs of the logic circuit 27 are both at a "low" level at the same time, so that on the occurrence of the next clock pulse Vc1, a decrement signal (X.Y.C) is applied to the "decrement" input 33 of the store 34.

The store 34 functions as a feedback control circuit and provides at its output 35 a feedback control signal which is applied to the 'control' input 36 of the ramp voltage generator 37 and serves to determine the slope of the ramp voltage Vra in accordance with its value. In response to the increment signal, the store 34 adjusts the value of the feedback control signal in a sense which causes an increase in the slope of the ramp voltage Vra, and in response to the decrement signal, the store 34 adjusts the value of the feedback control signal in a sense which causes a decrease in the slope of the ramp voltage Vra.

In the periods such as te - td and td - te during which errors in the ramp voltage slope exist, the number of clock pulses Vc1 that occur in these periods gives a direct measurement of the error, each clock pulse representing 100/128% error in the present embodiment. If each clock pulse were used to increment or decrement the valve of the feedback control signal by 0.8%, the error would be eliminated by the end of the current period of ramp voltage generation.

However, as this would tend to lead to oscillation of the ramp voltage slope about the notional correct slope, it was found in practice that a correction of only 0.16% per period of ramp voltage generation was more acceptable, correcting the error in five periods of ramp voltage generation. A clock pulse rate of 300 kHz was found to be acceptable, but higher rates are obviously possible.

The ramp voltage generator arrangement of Figure 4 can thus be realised using a relatively inaccurate ramp voltage generator which is stabilised by feedback. The reliance of the accuracy of the values of a capacitor and a resistor which would essentially comprise the ramp voltage generator is obviated. Therefore, as these are two of the very few discrete components which would be necessary to produce the arrangement as far as possible using integrated circuit techniques, the saving in cost is significant as compared with producing the arrangement wholly using discrete components. Also since the actual clock pulse frequency is not critical in the determination of the ramp voltage slope, the use of a relatively cheap clock pulse generator which is not crystalcontrolled is envisaged, thereby saving the cost of a crystal.

Having produced an accurate ramp voltage by means of the arrangement of Figure 4, this arrangement can be embodied in an A-to-D convertor arrangement which comprises one or more individual A-to-D convertors. Such an A-to-D convertor arrangement is shown in Figure 5 and comprises a first A-to-D convertor which is shown in full lines, and a second A-to-D convertor which is shown in dotted lines and is representative of other convertors which are similar to the first. The first A-to-D convertor is used for converting a first input analogue signal voltage Vx into a representative digital number, and other input analogue signal voltages such as Vx' are converted into respective representative digital numbers by respective ones of the other A-to-D convertors.Each of the A-to-D convertors has the clock pulses Vc1, the ramp voltage Vra and the reset pulses Vrs applied to it from the arrangement of Figure 4. As shown for the first A-to-D convertor, each of the convertors in the arrangement of Figure 5 comprises a comparator amplifier 42, an AND-gate 43, a counter 44 and a latch 45. The ramp voltage Vra is applied to a first input 46, and the input analogue signal voltage Vx is applied to a second input 47, of the comparator amplifier 42. The output 48 of the comparator amplifier 42 is connected to a first input 49, and the clock pulses Vc1 are connected to a second input 50, of the AND-gate 43.The counter 44 is connected to receive the clock pulses Vc1 from the gate 43 when the latter is open, and the latch 45 is connected to receive the resultant count of the counter 44 over a multi-lead input connection 51, the latch 45 being rendered operable in response to a "latch-open" signal So" applied to an input 52 thereof from the output 48 of the comparator amplifier 42. A multi-lead output connection 53 from the latch 45 provides the resultant count as a digital number. This A-to-D convertor operates in similar fashion to the known A-to-D convertor shown in Figure 2. The relevant waveform diagrams are included in Figure 7, the only additional one being waveform diagram (f) which represents the comparator signal output So". The input analogue signal voltage Vx is shown on waveform diagram (b).

During the period tb - tf when the amplitude of the ramp voltage Vra is less than that of the voltage Vx, the clock pulses Vc1 are counted into the counter 44 because the comparator signal output So" is "high" to hold gate 43 open. When the comparator signal output So" goes "low" at time tf, the gate 43 is closed to terminate the count and the latch 45 is rendered operative to store the resultant count in the counter 44. The next reset pulse Vrs then causes the operating sequence to be repeated.

The circuit diagram shown in Figure 6 of the A-to-D convertor arrangement comprises a ramp voltage generator arrangement 54 and a single A-to-D convertor 55. The arrangement 54 comprises a combination of discrete and modular components and the converter 55 is composed entirely of modular components. On this basis, large scale integration (L.S.I.) of the entire circuit diagram is envisaged. The circuit arrangement 54 comprises a Reset Pulse Generator 56, a Ramp Voltage Generator 57, a Reference Voltage Generator 58, a Comparator Amplifier 59, a Binary Counter 60, a Logic Circuit 61, and an Analogue Voltage Store 62. The A-to-D convertor 55 comprises a Comparator Amplifier 63, an AND-gate 64, a Binary Counter 65 and a Latch 66.

The Reset Pulse Generator 56 is a freerunning oscillator comprising two transistors 67 and 68 and associated components of which a capacitor 69 and a resistor 70 essentially determine the rate of oscillation.

The rest pulse output of the Generator 56 is taken from the collector of a transistor 71.

The Ramp Voltage Generator 57 comprises a capacitor 72 which is charged through a resistor 73 at a variable rate which is determined by the extent of conduction of a transistor 74. A transistor 75 which has its emitter-collector path connected in series with a resistor 76 across the capacitor 72 is responsive to the reset pulse output of the Generator 56 to reset the ramp voltage of the Generator 57. The ramp voltage across the capacitor 72 is applied to one input of the Comparator Amplifier 59. The Reference Voltage Generator 58 comprises a resistor 77 and a Zener diode 78 connected in series across the positive and negative supply lines +ve, -ve of the arrangement, the junction of these two components being held at a reference voltage which is applied to a second input of the Comparator Amplifier 59.The counter 60 has a 'clock input' 79 connected to receive clock pulses Vc1, a 'reset input' 80 connected to receive the reset pulse output of the Generator 56, and a 'bit-8 output' 81 which is connected into the Logic Circuit 61. In the Logic Circuit 61, the output 81 is connected directly to a first input of a NAND-gate 82 and via an inverter 83 to a first input of a NAND-gate 84. The output of the Comparator Amplifier 59 is connected directly to a second input of the gate 82 and via an inverter 85 to a second input of the gate 84. The clock pulses Vc1 are applied to a third input of each of the gates 82 and 84. These direct and inverted connections provide the X.Y.C.

and X.Y.G logic functions already described. The Analogue Voltage Store 62 includes a first diode pump comprising a transistor 86, a capacitor 87 and a diode 88, which is responsive to the signal output from the gate 82 to tend to charge a storage capacitor 89; and a second diode pump, comprising a transistor 90, a capacitor 91 and a diode 92, which is responsive to the signal output from the gate 84 to tend to discharge the capacitor 89. The resultant charge on the capacitor 89 provides a feedback control voltage which is applied via an emitter-follower transistor 93 to the base of transistor 74 in the Ramp Voltage Generator 57 to control the extent of conduction of that transistor.

The A-to-D convertor 55, being entirely of modular form, is essentially as already described with reference to Figure 5.

However, by way of modification, the Latch 66 is shown as being composed of two separate latches 94 and 95 for providing an output digital number in binary coded decimal on two sets of output leads 96 and 97.

WHAT WE CLAIM IS: 1. A ramp voltage generator arrangement comprising, a variable slope ramp voltage generator for generating a ramp voltage, a clock pulse source for generating clock pulses, a counter for counting the number of clock pulses occurring in recurrent periods of ramp voltage generation, each such period corresponding notionally to n clock pulse periods and said counter being operable to produce a first output signal having one or the other of two values according as the number of clock pulses actually occurring in such a period is less or greater than n, a comparator for comparing during each such period the amplitude of a reference voltage with the progressively changing instantaneous amplitude of said ramp voltage and being responsive to produce a second output signal having one or the other of two values according as the amplitude of said ramp voltage is less or greater than that of said reference voltage, a logic circuit which is responsive to said first and second output signals to provide an increment signal or a decrement signal when the number of clock pulses occurring in said period is greater or less than n before the ramp voltage amplitude exceeds the reference voltage amplitude, and a feedback control circuit which is operable to apply the variable slope ramp voltage generator a feedback control signal for determining the slope of the ramp voltage, said feedback control circuit being an analogue voltage store which is adapted to store the feedback voltage control signal which is increased and decresed, respectively, in amplitude by a fixed amount in response to each increment signal and each decrement signal whereby to vary the ramp voltage slope towards a rate appropriate for achieving equality of amplitude of said ramp and reference voltages in a period of ramp voltage generation corresponding to n clock pulse periods.

2. A ramp voltage generator arrangement as claimed in Claim 1, wherein said analogue voltage store comprises a storage capacitor which in incrementally charged and discharged by two diode pump circuits which are responsive, respectively, to the increment signals and to the decrement signals.

3. A ramp voltage generator arrangement as claimed in Claim 1 or Claim 2, wherein said fixed amount is made such that correction of the slope of the ramp voltage towards its notional correct slope is made over a number of periods of ramp voltage generation.

4. A ramp voltage generator arrangement as claimed in Claim 3, wherein each increment/decrement signal occurs at the clock pulse frequency.

5. A ramp voltage generator arrangement as claimed in any preceding Claim, wherein said counter is a binary counter a selected bit output of which changes from a '0' to a '1' after the n clock pulses applied to the counter.

6. A ramp voltage generator arrangement as claimed in any preceding Claim, embodied in an A-to-D convertor arrangement which comprises one or more effective A-to-D convertors, the or each A-to-D convertor being connected to use the clock pulses and the ramp voltage of the ramp voltage generator arrangement to produce a digital number which corresponds to a clock pulse count in a period taken for the ramp voltage amplitude to reach equality (or other given relationship) with an input analogue signal voltage amplitude.

7. An A-to-D convertor arrangement as claimed in Claim 6, wherein the or each A-to-D convertor comprises a comparator for comparing an input analogue signal voltage with said ramp voltage, and a counter for counting the number of clock pulses occurring in a period from the start of the ramp voltage to the detection of equality (or other given relationship) between the amplitude of the ramp voltage and that of the input analogue signal voltage, the or each A-to-D convertor further comprising a gate through which the clock pulses are applied to the counter and which is closed by the comparator signal output upon said detection, and a latch which is responsive to said comparator signal output to store the count of the counter as a digital number which is representative of the input analogue signal voltage applied to the A-to-D convertor.

8. A ramp voltage generator arrangement substantially as hereinbefore described with reference to Figures 4, 6 and 7 of the accompanying drawings.

9. An A-to-D convertor arrangement

**WARNING** end of DESC field may overlap start of CLMS **.

Claims (9)

**WARNING** start of CLMS field may overlap end of DESC **. which is responsive to the signal output from the gate 82 to tend to charge a storage capacitor 89; and a second diode pump, comprising a transistor 90, a capacitor 91 and a diode 92, which is responsive to the signal output from the gate 84 to tend to discharge the capacitor 89. The resultant charge on the capacitor 89 provides a feedback control voltage which is applied via an emitter-follower transistor 93 to the base of transistor 74 in the Ramp Voltage Generator 57 to control the extent of conduction of that transistor. The A-to-D convertor 55, being entirely of modular form, is essentially as already described with reference to Figure 5. However, by way of modification, the Latch 66 is shown as being composed of two separate latches 94 and 95 for providing an output digital number in binary coded decimal on two sets of output leads 96 and 97. WHAT WE CLAIM IS:

1. A ramp voltage generator arrangement comprising, a variable slope ramp voltage generator for generating a ramp voltage, a clock pulse source for generating clock pulses, a counter for counting the number of clock pulses occurring in recurrent periods of ramp voltage generation, each such period corresponding notionally to n clock pulse periods and said counter being operable to produce a first output signal having one or the other of two values according as the number of clock pulses actually occurring in such a period is less or greater than n, a comparator for comparing during each such period the amplitude of a reference voltage with the progressively changing instantaneous amplitude of said ramp voltage and being responsive to produce a second output signal having one or the other of two values according as the amplitude of said ramp voltage is less or greater than that of said reference voltage, a logic circuit which is responsive to said first and second output signals to provide an increment signal or a decrement signal when the number of clock pulses occurring in said period is greater or less than n before the ramp voltage amplitude exceeds the reference voltage amplitude, and a feedback control circuit which is operable to apply the variable slope ramp voltage generator a feedback control signal for determining the slope of the ramp voltage, said feedback control circuit being an analogue voltage store which is adapted to store the feedback voltage control signal which is increased and decresed, respectively, in amplitude by a fixed amount in response to each increment signal and each decrement signal whereby to vary the ramp voltage slope towards a rate appropriate for achieving equality of amplitude of said ramp and reference voltages in a period of ramp voltage generation corresponding to n clock pulse periods.

2. A ramp voltage generator arrangement as claimed in Claim 1, wherein said analogue voltage store comprises a storage capacitor which in incrementally charged and discharged by two diode pump circuits which are responsive, respectively, to the increment signals and to the decrement signals.

3. A ramp voltage generator arrangement as claimed in Claim 1 or Claim 2, wherein said fixed amount is made such that correction of the slope of the ramp voltage towards its notional correct slope is made over a number of periods of ramp voltage generation.

4. A ramp voltage generator arrangement as claimed in Claim 3, wherein each increment/decrement signal occurs at the clock pulse frequency.

5. A ramp voltage generator arrangement as claimed in any preceding Claim, wherein said counter is a binary counter a selected bit output of which changes from a '0' to a '1' after the n clock pulses applied to the counter.

6. A ramp voltage generator arrangement as claimed in any preceding Claim, embodied in an A-to-D convertor arrangement which comprises one or more effective A-to-D convertors, the or each A-to-D convertor being connected to use the clock pulses and the ramp voltage of the ramp voltage generator arrangement to produce a digital number which corresponds to a clock pulse count in a period taken for the ramp voltage amplitude to reach equality (or other given relationship) with an input analogue signal voltage amplitude.

7. An A-to-D convertor arrangement as claimed in Claim 6, wherein the or each A-to-D convertor comprises a comparator for comparing an input analogue signal voltage with said ramp voltage, and a counter for counting the number of clock pulses occurring in a period from the start of the ramp voltage to the detection of equality (or other given relationship) between the amplitude of the ramp voltage and that of the input analogue signal voltage, the or each A-to-D convertor further comprising a gate through which the clock pulses are applied to the counter and which is closed by the comparator signal output upon said detection, and a latch which is responsive to said comparator signal output to store the count of the counter as a digital number which is representative of the input analogue signal voltage applied to the A-to-D convertor.

8. A ramp voltage generator arrangement substantially as hereinbefore described with reference to Figures 4, 6 and 7 of the accompanying drawings.

9. An A-to-D convertor arrangement

substantially as hereinbefore described with reference to Figures 4, 5, 6 and 7 of the accompanying drawings.