JP4967084B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

A semiconductor device capable of increasing the stability of high-speed operation of a circuit by reducing a parasitic capacity and having at least two or more upper and lower layers of wires (1, 2) for connecting elements to each other installed on a silicon substrate having the elements provided thereon, characterized in that columns (3, 4) connected to a lower surface (2d) of the upper layer wire (2) and supporting the upper layer wire (2) are formed, and a space (5) continuing from a clearance (arrow 5a) between the lower layer wires (2) to at least a part of the lower surface (2d) (arrows 5b, 5c) of the upper layer wire (2) is formed.

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, a semiconductor device capable of preventing an increase in parasitic capacitance (wiring capacitance) due to narrowing of the wiring interval in the same layer and stabilizing high-speed operation of an integrated circuit, and It relates to the manufacturing method.
[0002]
[Prior art]
  Conventionally, as a technique for reducing the parasitic capacitance between wirings, it has become common knowledge to cover the upper layer, lower layer, and the same layer of wirings with an insulating film. Usually, silicon dioxide (SiO2) having a low dielectric constant is used as an insulating film material.₂) Is used. However, in recent years, the interval between wirings has further narrowed, and it has become impossible to reduce the parasitic capacitance as expected only with an insulator that fills between the wirings. Since the increase in parasitic capacitance causes inductive noise, stable circuit operation is hindered particularly in a circuit that operates at high speed. Therefore, various techniques for reducing the capacitance by providing holes or cavities in the insulator between the wirings are disclosed. The voids or cavities reduce the capacitance between the wirings, reduce the time constant during charging, and ensure high-speed operation of the elements and circuits.
[0003]
  FIG. 21 shows an example of a semiconductor device having such a cavity (Japanese Patent Laid-Open No. 10-335459), and FIGS. 22 and 23 show the manufacturing method thereof.
[0004]
  In FIG. 21, insulating films 103 and 104 are formed between the lower layer wiring 101 and the upper layer wiring 102, and a cavity 105 is formed between the insulating films 103 and 104. The buried metal 106 electrically connects the upper layer wiring 102 and the lower layer wiring 101, and below the interlayer insulating film 107 is a lower layer wiring or a semiconductor substrate having a semiconductor element.
[0005]
  In FIG. 22, the lower layer wiring 101 is patterned on the interlayer insulating film 107, and the insulating film 103 is formed so as to cover the lower layer wiring 101 (see FIG. 22A). The insulating film 103 is, for example, an oxide film. After a plasma oxide film or a bias sputtered oxide film is grown by 1.5 μm, the insulating film 103 is polished and planarized by a CMP (Chemical Mechanical Polishing) method. The film is formed with a film thickness of 800 nm.
[0006]
  Next, a cavity forming opening 108 (0.3 μm □) and a via hole opening 109 (0.4 μm □) are simultaneously formed by a normal photoresist method and anisotropic etching method (see FIG. 22B). ). When the wiring interval is 0.9 μm or more, two cavity forming openings 108 a and 108 b having a width of 0.3 μm are formed. By performing excessive etching, the depth of the cavity forming opening can be sufficiently deeply formed to the lower surface of the lower layer wiring 101. For example, when the excessive etching amount is about 80%, the depth is about 1400 nm.
[0007]
  Next, tungsten serving as the buried metal 106 is grown in the via hole opening 109 by a CVD (Chemical Vapor Deposition) method. For example, WF as a growth gas₆At about 400 ° C.₂Or SiH₄When reduced with, tungsten grows only on the metal (see FIG. 23C).
[0008]
  In addition, the insulating film 110 (oxide film: plasma oxide film or bias sputtered oxide film) is used under such a condition that the RF power is reduced to reduce the embedding property and the upper portion of the space forming opening 108 is easily blocked. Then, an interlayer insulating film 110 is formed on the entire surface until only the upper part 104 of the space forming opening 108 is sufficiently blocked. As a result, a sealed cavity 105 is formed in the insulating film 103 between the lower layer wirings 101 (see FIG. 23D).
[0009]
  Next, the interlayer insulating film 110 is polished and planarized using a wafer polishing technique (CMP) until the embedded metal 106 is exposed (see FIG. 23E), and then using a normal photoresist method and etching method. Upper layer wiring 102 is formed.
[0010]
[Problems to be solved by the invention]
  However, in the above-described conventional example, since the cavity 105 is formed in a columnar shape in the insulating film 103 by anisotropic etching, the cavity 105 has a sufficient depth (below the line on the lower surface of the lower layer wiring 101) by excessive etching. However, there is a limit to the reduction in parasitic capacitance. In other disclosed prior arts (Japanese Patent Laid-Open No. 2-86146 and Japanese Patent Laid-Open No. 5-21617), a hole is obtained by performing an anisotropic etching process or the like on an insulator existing between wirings. Alternatively, since the cavity is provided, there is a limit to the reduction of the parasitic capacitance due to space reasons, and it is not possible to sufficiently cope with the further miniaturization of design rules. In addition, as the formation technology of a structure of a semiconductor device such as a transistor advances three-dimensionally, three-dimensional wiring (between wirings in the same layer, wirings in upper and lower layers, wirings in a twisted position, etc.) ) Or between elements, it is essential to reduce parasitic capacitance.
[0011]
  The present invention has been made in view of the above-described problems, and a main object thereof is to provide a semiconductor device capable of dramatically reducing parasitic capacitance between three-dimensional wiring as well as two-dimensional wiring and a method for manufacturing the same. There is to do.
[0012]
  Another object of the present invention is to obtain a stable semiconductor device by increasing the manufacturing accuracy of the support supporting the upper layer wiring, and to damage the wiring and elements in forming the space for reducing the parasitic capacitance. There is no process to provide.
[0013]
[Means for solving the problems and effects thereof]
  referenceThe present invention provides a semiconductor device in which wirings connecting the elements are provided on a silicon substrate provided with a plurality of elements so as to form at least two layers above and below, and connected to the lower surface of the upper layer wirings. Forming a column supporting the wiring, forming a continuous space from the gap between the lower layer wirings to at least a part of the lower surface of the upper layer wiring, and providing an insulating layer between the lower layer wiring and the substrate surface; By forming a recess for separating elements on the surface of the substrate between the lower layer wirings so as to penetrate the insulating layer, the elements are electrically insulated, and the space is Keep it in the recessIt will be.
[0014]
  A space is formed between the same layer and the upper and lower layers by the support columns. This space extends three-dimensionally between the wirings (between the same layer, upper and lower layers, and twisted positions), and the parasitic capacitance can be sufficiently reduced even if the wiring interval is reduced.
[0015]
  In addition, by forming the recesses between the elements, the insulation between the elements can be increased, and the parasitic capacitance can be reduced. Further, miniaturization between elements can be promoted.
[0016]
  Further, by forming the support posts with an electrical insulator, it is possible to sufficiently reduce the parasitic capacitance when the wiring interval is narrowed while ensuring the insulation between the wirings. A conductive metal may be provided in a columnar shape at a location where electrical connection is desired between upper and lower layers (including a vertical relationship that is one layer or more apart). In this case, the columnar conductive metal does not need to support the upper layer wiring and may be thin.
[0017]
  In the semiconductor device, the support includes a first support that is provided on the lower wiring and supports the upper wiring, and a second support that supports the upper wiring in a portion on the silicon substrate without the lower wiring. In this case, at least one of the first struts may be embedded with a conductive metal.
[0018]
  In this way, the upper and lower layers can be electrically connected by the conductive metal embedded in the support column.
[0019]
  Further, the support may be a conductor, and in this case, it can also serve as a wiring for electrically connecting the upper and lower layers. Therefore, the structure is simplified, and the process of burying a conductive metal can be omitted in the manufacturing method. In the case of a metal support, it can be insulated by being provided on an insulating layer.
[0020]
  The semiconductor device may be formed by forming a recess in the substrate surface between the elements and continuing the space in the recess.
[0021]
  By forming the recesses between the elements, the insulation between the elements can be improved, and the parasitic capacitance can be reduced. Further, miniaturization between elements can be promoted.
[0022]
  Claim 1According to the invention, in a semiconductor device in which a wiring connecting the elements is provided on a silicon substrate provided with a plurality of elements so as to form at least two layers above and below, the semiconductor device is coupled to the lower surface of the upper layer wiring. A support for supporting the upper layer wiring is formed, a continuous space is formed from the gap between the lower layer wirings to at least a part of the lower surface of the upper layer wiring, and a recess for separating elements on the substrate surface between the elements is formed. The space is formed continuously in the recess, and an etching resistant film is formed on the inner surface of the inter-element isolation recess.
[0023]
  The element surface is not damaged during etching. In addition, since etching does not proceed in the lateral direction of the silicon substrate, it is easy to control the dimensions between elements.
[0024]
  Further, a gettering material may be provided in the space of the semiconductor device.
[0025]
  The gettering material is a substance having an action of adsorbing gas molecules and removing it from the gas phase, that is, an exhaust action. As such, in addition to commonly known barium, magnesium, calcium, titanium, tantalum, zirconium, vanadium, yttrium and the like can be used. By placing a gettering material in the space, after the semiconductor device is completed, that is, after the space is formed, the outgas discharged from the material in contact with the space is adsorbed to prevent the outgas from being stored and increase the degree of vacuum in the space. be able to. Realization of a high degree of vacuum facilitates reduction of parasitic capacitance. Furthermore, corrosion due to outgas and deterioration of wiring can be prevented, and the life of the semiconductor device can be extended.
[0026]
  As the gettering material, in the space between the wirings, it is preferable to provide a post on the interlayer insulating film or a support for it, and place it as a solid on the interlayer insulating film so as to exert the effect after the semiconductor manufacturing. Among these, titanium, zirconium, yttrium, and the like can be given. In addition, these are preferably placed in such a shape that the surface area is the largest when arranged. Furthermore, when titanium is used, the plasma used for isotropic etching is SF.₆A gas is preferred.
[0027]
  Further, a capping layer may be provided that covers the upper and lower wirings from above the uppermost upper layer wiring and hermetically closes the space provided with the gettering material.
[0028]
  By doing so, the space is sealed by the capping layer, so that the gas adsorbing action of the gettering material in the space works effectively, and the degree of vacuum in the space is increased.
[0029]
  Claim2The invention according to, RawA manufacturing method of a semiconductor device provided with a recess for separating between children,
(A) forming the lower layer wiring on an interlayer insulating film provided on the silicon substrate;
(B) forming a sacrificial layer so as to cover between the lower layer wiring and the upper surface thereof;
(C) forming a photoresist film by a photolithography method in a region other than the region where the upper layer wiring support is formed;
(D) etching the sacrificial layer in the strut formation region;
(E) forming a support by depositing and filling an insulating film in the etched region;
(F) Forming a contact hole opening pattern mask for embedding a metal for conducting the upper layer wiring with one or more lower layer wirings, and etching the support and / or sacrificial layer in the metal embedding region Forming a contact hole;
(G) burying a metal in the etched contact hole;
(H) forming the upper wiring layer;
(I) a step of isotropically etching the sacrificial layer to form a space in the same layer between the upper and lower wires, the upper and lower layers, and a portion other than the pillars between the wires in a twisted positional relationship;
Including
  Between the step (a) and the step (b),
(A-1) A photoresist mask for forming a through hole in the interlayer insulating film for exposing a region for forming an inter-element isolation recess of the silicon substrate is formed on the interlayer insulating film and the lower layer wiring. Forming a photolithographic method thereon,
(A-2) The interlayer insulating film in a region not covered with the photoresist mask is etched to form the through hole, and an inter-element isolation recess forming region of the silicon substrate under the interlayer insulating film is formed through the through hole. Exposing, and
(A-3) Step of removing the photoresist mask formed in the step (a-1)
Is inserted,
  In the step (i), the exposed inter-element isolation recess formation region is dug by isotropic etching to form an inter-element isolation recess.
[0030]
  The upper wiring layer forming step (h) includes a step of forming a metal film for upper wiring after removing the contact hole opening pattern mask and embedding a buried metal, and an extra metal film according to the wiring pattern. And a step of etching such a portion. In addition, a method conventionally used as a method for forming a wiring layer (metal film) can also be used.
[0031]
  In the present invention, a photoresist film (mask) is formed by a photolithography method, and an insulating film is formed and embedded in a sacrificial layer etched into a columnar shape to form a column, and the column can be formed with high accuracy. it can. In addition, since the space is formed by removing all the sacrificial layer by isotropic etching after the support is formed, the molding accuracy is high.
[0032]
  Further, in the present invention, prior to the step (b) of covering the lower layer wiring with the sacrificial layer, in the steps (a-1) to (a-3), the interlayer insulating film under the lower layer wiring is etched to form an inter-element A region where the separation recess is formed is exposed, and a sacrificial layer is formed on this region in step (b). By doing so, at the time of isotropic etching in the final step (i), the sacrificial layer is removed to form a space, and at the same time, the region is dug down to form a recess for element isolation. . Therefore, the process can be simplified.
[0033]
  Claims3The described invention is, RawRecess for separation between childrenPartA method for manufacturing a formed semiconductor device, comprising:
(A) forming the lower layer wiring on an interlayer insulating film provided on the silicon substrate;
(B) forming a sacrificial layer so as to cover between the lower layer wiring and the upper surface thereof;
(C) forming a photoresist film by a photolithography method in a region other than the region where the upper layer wiring support is formed;
(D) etching the sacrificial layer in the strut formation region;
(E) forming a support by depositing and filling an insulating film in the etched region;
(F) Forming a contact hole opening pattern mask for embedding a metal for conducting the upper layer wiring with one or more lower layer wirings, and etching the support and / or sacrificial layer in the metal embedding region Forming a contact hole;
(G) burying a metal in the etched contact hole;
(H) forming the upper wiring layer;
(I) a step of isotropically etching the sacrificial layer to form a space in the same layer between the upper and lower wires, the upper and lower layers, and a portion other than the pillars between the wires in a twisted positional relationship;
Including
Between the step (a) and the step (b),
(A-1-1) forming a photoresist mask for forming a recess for separating elements on the silicon substrate on the interlayer insulating film and on the lower layer wiring by a photolithography method;
(A-2-1) Etching the region not covered with the photoresist mask, penetrating the interlayer insulating film above the inter-element isolation recess formation region, and further digging the silicon substrate directly below it to a predetermined depth Forming a recess for separating the elements;
(A-2-2) forming an etching resistant film on the inner surface of the inter-element separation recess;
(A-3-1) Step of removing the photoresist mask formed in the step (a-1-1)
Has been inserted.
[0034]
  In the present invention, the anisotropic etching in the step (a-2-1) is controlled, and simultaneously with the etching of the interlayer insulating film, the element isolation region of the silicon substrate immediately below is etched anisotropically, The separation recess can be formed to a predetermined depth. Further, by forming an etching resistant film (for example, an oxide film), it has an etching resistant effect against etching for removing the sacrificial layer in the final step (i) and does not damage the element. In addition, the dimensional accuracy can be improved, and further miniaturization of design rules can be supported.
[0035]
  Claims4The invention according to, RawA manufacturing method of a semiconductor device provided with a recess for separating between children,
(A) forming the lower layer wiring on an interlayer insulating film provided on the silicon substrate;
(B) forming a sacrificial layer so as to cover between the lower layer wiring and the upper surface thereof;
(C) forming a photoresist film by a photolithography method in a region other than the region where the upper layer wiring support is formed;
(D) etching the sacrificial layer in the strut formation region;
(E-1) forming a conductive column by depositing and embedding a metal in the etched region;
(H) forming the upper wiring layer;
(I) a step of isotropically etching the sacrificial layer to form a space in the same layer between the upper and lower wires, the upper and lower layers, and a portion other than the pillars between the wires in a twisted positional relationship;
Including
  Between the step (a) and the step (b),
(A-1) A photoresist mask for forming a through hole in the interlayer insulating film for exposing a region for forming an inter-element isolation recess of the silicon substrate is formed on the interlayer insulating film and the lower layer wiring. Forming a photolithographic method thereon,
(A-2) The interlayer insulating film in a region not covered with the photoresist mask is etched to form the through hole, and an inter-element isolation recess forming region of the silicon substrate under the interlayer insulating film is formed through the through hole. Exposing, and
(A-3) Step of removing the photoresist mask formed in the step (a-1)
Is inserted,
  In the step (i), the exposed recess formation region for element isolation is dug by isotropic etching to form an isolation trench for element isolation.
[0036]
  In this case, the manufacturing method is simplified as compared with a semiconductor having an insulating pillar.
[0037]
  Claims5The invention according to, RawA method of manufacturing a semiconductor device in which an etching-resistant film is formed in a recess for separation between children,
  A method of manufacturing a semiconductor device, wherein a wiring connecting the elements on a silicon substrate provided with a plurality of elements is provided so as to form at least two layers above and below,
(A) forming the lower layer wiring on an interlayer insulating film provided on the silicon substrate;
(B) forming a sacrificial layer so as to cover between the lower layer wiring and the upper surface thereof;
(C) forming a photoresist film by a photolithography method in a region other than the region where the upper layer wiring support is formed;
(D) etching the sacrificial layer in the strut formation region;
(E-1) forming a conductive column by depositing and embedding a metal in the etched region;
(H) forming the upper wiring layer;
(I) a step of isotropically etching the sacrificial layer to form a space in the same layer between the upper and lower wires, the upper and lower layers, and a portion other than the pillars between the wires in a twisted positional relationship;
Including
  Between the step (a) and the step (b),
(A-1-1) forming a photoresist mask for forming a recess for separating elements on the silicon substrate on the interlayer insulating film and on the lower layer wiring by a photolithography method;
(A-2-1) Etching the region not covered with the photoresist mask, penetrating the interlayer insulating film above the inter-element isolation recess formation region, and further digging the silicon substrate directly below it to a predetermined depth Forming a recess for separating the elements;
(A-2-2) forming an etching resistant film on the inner surface of the inter-element separation recess;
(A-3-1) Step of removing the photoresist mask formed in the step (a-1-1)
Is inserted.
[0038]
  Even in this case, the manufacturing method is simplified as compared with a semiconductor having an insulating pillar.
[0039]
  And claims6The present invention relates to a method of manufacturing a semiconductor device having a gettering material in the same layer as a lower layer wiring.2Thru5In addition to the invention described in (2), before or after the step (a),
(I) a step of forming a gettering material forming mask;
(II) forming a gettering material film; and
(III) A step of removing the gettering material forming mask to obtain a gettering material layer
Has been inserted.
[0040]
  In the present invention, a gettering material is disposed on the interlayer insulating film in the same layer as the lower layer wiring. In combination with the manufacturing method described below, a gettering material can be provided in the same layer as the upper wiring layer.
[0041]
  And claims7The present invention relates to a manufacturing method in which a gettering material is provided in the same layer as the upper wiring,2Thru6In addition to the invention described in any of the above, before or after the step (h),
(I) a step of forming a gettering material forming mask;
(II) forming a gettering material film; and
(III) A step of removing the gettering material forming mask to obtain a gettering material layer
Has been inserted.
[0042]
  In the present invention, a pillar or the like is formed on the interlayer insulating film in the same layer as the upper layer wiring, and a gettering material is disposed thereon. Of course, two or more layers may be provided in one space by combining the same layer as the lower layer wiring and the same layer as the upper layer wiring.
[0043]
  The step (g) of filling the etched contact hole with a metal and the step (h) of forming the upper wiring layer may be performed simultaneously.
[0044]
  In this way, the buried metal made of the same material and the upper layer wiring are formed at the same time, and the process is simplified.
[0045]
  Furthermore, the step (e-1) and the step (h) may be performed at the same time. In this way, the steps are further simplified.
[0046]
  Further, in the method for manufacturing the semiconductor device, after the step (i),
(J) A step of forming a capping layer on the uppermost upper layer wiring so as to hermetically close the space.
May be included.
[0047]
  In this case, the space hermetically sealed by the capping layer is sucked into the vacuum by the gettering material.
[0048]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings. 1 to 5 are cross-sectional views showing first and fifth embodiments of the semiconductor device of the present invention, respectively. 6 and 7 show a manufacturing method of the first embodiment (semiconductor device shown in FIG. 1) of the present invention. Further, by adopting FIG. 8 instead of FIG. 7 and performing the steps of FIGS. 6 and 8, the third embodiment of the present invention (semiconductor device shown in FIG. 3) is obtained. 9 and 10 show a manufacturing method of the fourth embodiment (semiconductor device shown in FIG. 4) of the present invention, and FIGS. 11 and 12 show the fifth embodiment ( 6 shows a manufacturing method of the semiconductor device shown in FIG.
[0049]
  13 to 20 illustrate the present invention having a gettering material in a space. FIG. 13 shows a sixth embodiment of the present invention in which a gettering material is arranged in the same layer as a lower layer wiring. FIG. 14 is a cross-sectional view of a seventh embodiment of the present invention in which a gettering material is arranged in the same layer as the upper layer wiring, and FIGS. 15 to 17 show the sixth embodiment (FIG. 13). 18 and FIG. 19 show a method for manufacturing the seventh embodiment (the semiconductor device shown in FIG. 14). FIG. 20 shows the configuration and manufacturing method of the embodiment of FIG.
[0050]
  In FIG. 1, the lower layer wiring 1 is provided on the interlayer insulating film 7, and the upper layer wiring 2 is supported on the interlayer insulating film 7 or the lower layer wiring 1 by support columns 3 and 4. The first support column 3 is provided on the interlayer insulating film 7 to support the upper layer wiring 2, and the second support column 4 is provided on the lower layer wiring 1 to support the upper layer wiring 2. The upper layer wiring 2 is lifted by the first and second support columns 3 and 4, and a space 5 is formed between the upper and lower wirings 1 and 2. The space 5 is geometrically formed between the side surfaces 1a and 1b of the adjacent lower layer wirings 1 and 5b between the upper surface 1c of the lower layer wiring 1 and the lower surface 2d of the upper layer wiring 2 between the upper and lower sides directly above and below. It becomes a three-dimensional space having 5c between the lower layer wiring 1 and the upper layer wiring 2 at the position of twist.
[0051]
  In FIG. 1, support columns 3 and 4 are formed of an electrical insulator, and the upper and lower layers 1 and 2 are electrically connected by a metal 6 embedded in the second support column 4. The metal 6 is appropriately provided where necessary.
[0052]
  In FIG. 2, the metal 16 electrically connects the upper and lower layers 1 and 2. In the second embodiment, the upper layer wiring 2 is sufficiently supported by the support columns 3 and 4, and the thickness of the metal 16 is not limited. However, the thickness of the metal 16 can be appropriately used to replace the column.
[0053]
  In FIG. 3, the columns 53 and 56 are made of a conductor and have an appropriate thickness. The support column 56 provided on the lower layer wiring 1 also serves to electrically connect the upper and lower layers 1 and 2. A portion that does not need to be electrically connected is appropriately provided on the insulating film like the column 53.
[0054]
  1 to 3, only the upper and lower two-layer wirings 1 and 2 are shown on the interlayer insulating film 7. However, the present invention is not limited to this, and the upper-layer wiring is further provided above the upper-layer wiring 3. Of course, the number of layers or more is also included, and in that case, the upper layer wiring or the lower layer wiring is referred to in a vertical relationship. The same applies to FIG. 4 and subsequent figures.
[0055]
  The upper and lower layer wirings 1 and 2 are made of a single body or a laminate of aluminum (Al), aluminum alloy, copper (Cu), tungsten (W), tungsten silicide (WSi), titanium nitride (TiN), titanium silicide (TiSi), or the like. Become. The same applies to the buried metal 6 (see FIG. 1) and the conductive metal 16 (see FIG. 2).
[0056]
  When the columns 3 and 4 are made of an insulating material, they are made of SiO._xN_x, SiO_x, SiOF, amorphous fluorocarbon (aC: F) and the like are preferable. Moreover, it is preferable that the strength capable of supporting the upper layer wiring can be ensured.
[0057]
  The support columns 53 and 56 (see FIG. 3) formed of a conductor are made of aluminum (Al), aluminum alloy, copper (Cu), tungsten (W), tungsten silicide (WSi), like the upper and lower wiring layers 1 and 2. , Titanium nitride (TiN), titanium silicide (TiSi), or the like.
[0058]
  Interlayer insulating film 7 is, for example, an oxide film such as a plasma oxide film or a bias sputtered oxide film.
[0059]
  In the case of a multilayer structure in which the upper and lower layer wirings 1 and 2 are sequentially stacked via the interlayer insulating film 7, a conductive metal 17 is buried in the interlayer insulating film 7 as shown in FIG. . Although not shown, a metal may be embedded in the second support column 3 and the interlayer insulating film 7 to connect the upper layer wiring 2 and the upper layer wiring 2 thereon.
[0060]
  FIG. 4 shows a semiconductor device according to a fourth embodiment of the present invention, in which a through hole 8 is provided in an interlayer insulating film 7 and a recess 10 for separating elements and a through hole provided in a silicon substrate 9 immediately below. 8 communicates. The inter-element separation recess 10 is for enhancing the insulation between the elements, and like the space 5, it is preferably a space or a space close to a vacuum rather than being filled with an insulator. . The through hole 8 is provided in order to form the inter-element separation recess 10.
[0061]
  FIG. 5 shows a fifth embodiment of the semiconductor device of the present invention. In addition to the semiconductor device shown in FIG. 4, an etching resistant film 11 is further formed on the surface of the inter-element isolation recess 10. Yes. The etching resistant film 11 is for preventing the recess 10 from being eroded during the manufacturing process.
[0062]
  As the etching resistant film 11, SiO_xN_x, SiO_xThere is. The etching resistant film 11 can be formed by performing oxygen plasma irradiation under appropriate conditions without peeling off the resist mask when etching the interlayer insulating film.
[0063]
  Next, based on FIGS. 6 and 7, a manufacturing method of the first embodiment (see FIG. 1) and the second embodiment (see FIG. 2) of the semiconductor device of the present invention will be described.
[0064]
  In FIG. 6, first, (a) the lower layer wiring 1 is formed on the interlayer insulating film 7. In this step (a), for example, the lower layer wiring 1 is formed by patterning or etching a single body or a laminate of the above-described materials such as aluminum alloy and copper. For the formation, for example, using a DC magnetron sputtering apparatus, the DC voltage is about −1 kW, the gas used is Ar (plasma ions), and the flow rate is about 0.1 liters per minute (however, all the standard conditions (0 C., 0.1 MPa (1 atm)), the pressure in the reaction chamber is about 3 Pa, and the target is Al. Thereafter, an excessive portion of the Al thin film formed by sputtering is removed by forming a resist mask and subsequent metal etching (anisotropic dry etching) to obtain an Al wiring (lower layer wiring). In addition, a CVD method, a plating method, or the like is also possible. The upper layer wiring can be formed in the same manner. Further, the above method is effective for embedding metal in the contact hole.
[0065]
  Next, (b) a sacrificial layer 22 is formed so as to cover the lower layer wiring 1. The sacrificial layer 22 is formed by depositing amorphous silicon, for example. In this film formation, for example, the gas used is SiH by a low pressure CVD apparatus.₄And Ar (or H₂) As SiH₄The flow rate of about 0.05 to 0.2 liters per minute, the flow rate of Ar is about 0.5 to 2 liters per minute, the pressure in the reaction chamber is several tens of Pa, and the substrate temperature is about 350 ° C. or lower and 150 ° C. or higher. .
[0066]
  Next, (c) the sacrificial layer 22 is planarized by a method such as CMP (Chemical Mechanical Polishing), and then a photoresist mask 23 is formed.
[0067]
  Next, (d) a portion of the sacrificial layer 24 not covered with the mask 23 is removed by etching. This etching is preferably anisotropic etching from the viewpoint of dimensional control. For example, an ICP-RIE apparatus (Inductively Coupled Plasma-Reactive Ion Etching) is used to form a coil. About 1200 W, the platen is about 30 W, the pressure in the reaction chamber is about 2.67 Pa, SF₆And fluorocarbon gas are preferably used at flow rates of about 0.1 liter per minute and about 0.05 liter per minute, respectively.
[0068]
  Next, in FIG. 7, (e) after removing the mask 23, an insulating film is buried in the portion 24 of the sacrificial layer that has been dug down to form a column 25. For the formation of the column 25, SiO₂Film formation is preferred. This film formation is performed using an ECR-CVD apparatus (Electron Cyclotron Resonance Plasma-CVD apparatus) with a microwave power of about 1 kW, a coil current of about 20 A, and a working gas of SiH.₄And O₂And Ar, the flow rates are about 0.01 liters per minute, about 0.02 liters per minute, and about 0.05 liters per minute, respectively, and the pressure in the reaction chamber is several × 10^-1Pa, the substrate temperature is about 300 ° C. to 450 ° C., and the RF power is about 200 W.
[0069]
  Next, (f) a photoresist mask 27 is formed on the pillars 25 and the remaining sacrificial layer 22 formed in the above step, and contact holes 26 are formed by performing anisotropic etching. The anisotropic etching in this case depends on the material of the support column 25, but as described above, SiO 2₂When formed with a film, SiO₂Perform anisotropic etching of the film. For example, with an ICP-RIE apparatus, the coil is about 1000 W, the platen is about 500 W, the pressure in the reaction chamber is about 0.33 Pa, and fluorocarbon gas is used at a flow rate of about 0.02 liters per minute under standard conditions. Although not shown, the contact hole is not limited to the support 25, and may be formed in the sacrificial layer 22 if necessary. In that case, the manufacturing method is determined in consideration of the material of both the support column 25 and the sacrificial layer 22.
[0070]
  Next, (g) the photoresist mask 27 is removed, and then the metal 6 is embedded in the contact hole 26. This embedding is performed using an ECR-CVD apparatus with a microwave power of about 1 kW, a coil current of about 20 A, and a working gas of WF.₆And H₂And Ar, the flow rates are about 0.01 liters per minute, about 0.02 liters per minute and about 0.05 liters per minute, respectively, the pressure in the reaction chamber is about 0.7 Pa, and the substrate temperature is about 300 liters. The RF power is about 200 W at a temperature not lower than 450 ° C and not higher than 450 ° C.
[0071]
  Next, (h) the upper wiring 2 is formed. The upper layer wiring 2 can be formed by the same method and using the same material as the lower layer wiring 1 described above, but the material and manufacturing method of the lower layer wiring 1 and the upper layer wiring 2 may be different in one semiconductor device.
[0072]
  Next, (i) the space 5 is formed by etching the sacrificial layer 22. For this purpose, isotropic etching is preferable from the viewpoint of facilitating etching under the upper wiring and between the upper and lower layers. For example, SF₆Using ICP (inductively coupled plasma) conditions, the coil is about 600 W, the platen is about 5 W, the pressure in the reaction chamber is about 2.7 Pa, the gas used and the flow rate are SF.₆About 0.1 liter per minute. Under ECR conditions, the microwave power by the ECR-CVD apparatus is about 1 kW, the coil current is about 20 A, and the SF of the gas used₆The flow rate of Ar and Ar is about 0.05 liters per minute and about 0.05 liters per minute, the pressure in the reaction chamber is about 0.7 Pa, and the substrate temperature is about 300 ° C. to 450 ° C.
[0073]
  For isotropic etching for removing the sacrificial layer 22, XeF₂gasTheIt can also be used. In that case, the pressure in the reaction chamber is about 0.4 Pa or less.
[0074]
  The step (g) (formation of the buried metal 6) and the step (h) (formation of the upper layer wiring 2) can be performed simultaneously. In that case, the material of the buried metal 6 and the upper wiring 2 is aluminum (Al), aluminum alloy, copper (Cu), tungsten (W), tungsten silicide (WSi), titanium nitride (TiN), titanium silicite (TiSi). These are formed by a sputtering method or a CVD method using a single body or a laminated body.
[0075]
  In the present invention, the sacrificial layer is not limited to the above-described film formation of amorphous silicon. For example, a resist (model number AZ1350) can be used as the sacrificial layer. In this case, either isotropic or anisotropic can be used for resist etching. When using isotropic etching, the conditions are, for example, a coil of about 600 W, a platen of about 10 W, a pressure in the reaction chamber of about 5.32 Pa, a working gas and a flow rate of₂About 0.03 liters per minute. In the case of anisotropic etching, the coil is about 600 W, the platen is about 15 W, the pressure in the reaction chamber is about 0.27 Pa, the gas used and the flow rate O₂Approx. 0.02 liter per minute. In addition, a conventionally used method can be used as appropriate.
[0076]
  Next, a manufacturing method of the third embodiment (see FIG. 3) of the semiconductor device of the present invention will be described. The first half of this semiconductor device manufacturing method is the same as steps (a) to (d) shown in FIG. The latter half part, (e-1) process, (h) process, and (i) process are demonstrated based on FIG.
[0077]
  In FIG. 8, (e-1) after removing the mask 23 (see FIG. 6), a support 28 is formed by embedding a conductor in the portion 24 of the sacrificial layer dug down. The conductive pillars 28 can be formed of the same material as the upper and lower layer wirings 1 and 2 by the same method. Subsequently, (h) the upper layer wiring 2 is formed. Similarly, the upper layer wiring 2 can be formed by the same method using the same material as the lower layer wiring 1 described above. (I) The process of forming the space 5 by etching the sacrificial layer 22 is the same as in FIG.
[0078]
  In the manufacturing method in FIG. 8, the step (e-1) of forming the column 28 and the step (h) of forming the upper layer wiring 2 can be performed simultaneously.
[0079]
  Further, in the manufacturing process in FIG. 8, the steps (f) and (g) for embedding the metal 6 for electrically connecting the upper and lower layer wirings 1 and 2 in FIG. 7 are omitted.
[0080]
  Next, a process of forming the inter-element isolation recess 10 (see FIGS. 4 and 5) will be described with reference to FIGS. There are two methods for forming the inter-element isolation recess 10. The first method is a method in which the sacrificial layer 22 is etched simultaneously with removal. The second method is a method of etching simultaneously with the interlayer insulating film 7. In the first method, since the isotropic etching is used to remove the sacrificial layer 22, it is difficult to accurately control the depth of the recess, but the manufacturing process shown in FIGS. 6 and 7 described above, Alternatively, it can be easily added to the steps shown in FIGS. In the second method, the depth of the recess can be accurately controlled by using anisotropic etching when forming the through-hole 8 in the interlayer insulating film 7, but it is sacrificed in the final step (i). Care must be taken when removing the layer 22 so that the recess is not eroded. Therefore, as in the fifth embodiment shown in FIG. 5, an etching resistant film 11 is provided to protect the inner surface of the recess 10 in preparation for the final step (i).
[0081]
  9 and 10 show the first method described above, that is, the manufacturing method of the fourth embodiment shown in FIG.
[0082]
  In FIG. 9, an interlayer insulating film 7 is provided on the silicon substrate 9. The metal 17 is appropriately embedded in the interlayer insulating film 7 in order to electrically connect the element and the lower layer wiring 1. (A) The process of forming the lower layer wiring 1 is the same as that of FIG.
[0083]
  Next, (a-1) in order to expose the inter-element isolation recess formation region 10a of the silicon substrate 9 immediately below the interlayer insulating film 7, the interlayer insulating film 7 and the lower layer wiring 1 are photo-exposed except for the portion 7a corresponding to the upper portion. Cover with a mask 30 such as a resist mask.
[0084]
  Next, (a-2) the interlayer insulating film 7 is etched. Etching is anisotropic etching, ICP-RIE, coil about 1000 W, platen about 500 W, reaction chamber pressure about 0.33 Pa, working gas is fluorocarbon gas, its flow rate is about 0.02 liters per minute Can be done in the state.
[0085]
  Next, (a-3) the mask 30 is removed. A through hole 8 is formed in the interlayer insulating film 7, and the inter-element isolation recess forming region 10 a of the silicon substrate 9 is exposed.
[0086]
  Subsequently, steps (b) to (h) in FIG. 10 are the same as those in FIGS. 6 and 7, but in the final (i-1) step, isotropic etching is performed, and the sacrificial layer 22 is formed. At the same time as the removal, the silicon substrate 9 is dug from the exposed element isolation recess formation region 10a, and the element isolation recess 10 is formed.
[0087]
  11 and 12 show the above-described second method, that is, the manufacturing method of the fifth embodiment shown in FIG. Step (a) in FIG. 11 is the same as that in FIGS. 6 and 9.
[0088]
  Next, in FIG. 11, (a-1-1) In order to form the inter-element isolation recess 10 in the silicon substrate 9, the interlayer insulating film 7 and the lower layer wiring 1 are removed from the photoresist mask except for the upper portion 7 a. And so on.
[0089]
  Next, (a-2-1) the interlayer insulating film 7 and the silicon substrate 9 directly therebelow are etched to form an inter-element isolation recess. Etching is anisotropic etching as in the step (a-2) of FIG. 9, but is appropriately controlled so that the depth of the inter-element isolation recess 10 becomes a predetermined depth.
[0090]
  Next, (a-2-2) the etching resistant film 11 is formed on the inner surface of the inter-element separation recess 10. The material of the etching resistant film 11 is SiO._xN_x, SiO_xand so on. The etching resistant film 11 can be formed by performing oxygen plasma irradiation under appropriate conditions without peeling off the resist mask 30 when the interlayer insulating film 7 is etched. When forming the through-hole 8 in the interlayer insulating film 7, since anisotropic etching is used, it is easy to control the depth of the recess 10 for separating elements, and an excellent semiconductor device can be accurately manufactured. it can.
[0091]
  Next, in FIG. 12, (a-3-1) the mask 30 is removed. Hereinafter, the steps (b) to (i) are the same as the steps (b) to (i) shown in FIGS. 6 and 7, but in the final (i) step, the etching resistant film 11 is used. The isotropic etching for removing the sacrificial layer 22 does not adversely affect the semiconductor elements in the vicinity of the inter-element isolation recess 10.
[0092]
  In the above-described manufacturing method embodiment, the low pressure CVD method or the ECR-CVD method is used, but other CVD methods (thermal CVD method (normal pressure CVD method), plasma CVD method, photo-CVD method, ICP (inductive coupling) are used. The effect is the same even when a plasma) -CVD method, a helicon-CVD method, a SWP (surface wave plasma) -CVD method, another CVD method, or another HDP (high density plasma) -CVD method) is used. Further, the same effect can be obtained by using a sputtering method or a plating method instead of the CVD method. Further, in this embodiment, the ICP-RIE method is used in the etching method, but other RIE methods (RIE method using plasma method used in the above-described CVD method, DRM-RIE method) are used. But the effect is the same.
[0093]
  In the present invention, as shown in FIGS. 13 and 14, the gettering material 50 is disposed in the space 5 described above, and the camping layer 52 is provided on the uppermost wiring, thereby outgassing from the space 5. Can be removed, and the degree of vacuum in the space can be increased. 13 and FIG. 14 show the arrangement of the gettering material 50 in the space 5 of the first embodiment shown in FIG. 1, but naturally the space 5 of the embodiment shown in FIGS. Can be similarly arranged. The manufacturing method is the same. Among these, the structure and the manufacturing method will be described with reference to FIG. 20 for the structure in which the gettering material 50 is provided in the space 5 of the embodiment shown in FIG.
[0094]
  In FIG. 13, the gettering material 50 is provided on the interlayer insulating film 7. In FIG. 14, the gettering material 50 is provided on the support column 51. The support column 51 may be an insulator or a conductor. The space 5 is a hermetically closed space when the capping layer is provided and the semiconductor device is completed. Therefore, by arranging a substance having an action of adsorbing gas molecules, such as the gettering material 50, the gas originally existing in the space 5 and the gas discharged from the material after the completion of the semiconductor device (outgas) are adsorbed. Thus, it can be excluded from the space 5 and the degree of vacuum of the space 5 can be increased. By increasing the degree of vacuum, the dielectric constant of the gas between the wirings can be reduced, and as a result, the capacitance between the wirings can be further reduced. In addition, since corrosive gas can be eliminated, the life of the semiconductor device can be extended.
[0095]
  Examples of gettering materials include barium, magnesium, calcium, titanium, tantalum, zirconium, vanadium, yttrium, etc., but in the present invention, titanium, zirconium, It is preferable to use yttrium or the like. These are preferably placed in such a shape that the area of the surface is the largest when arranged. Further, when titanium is used, the plasma used for isotropic etching for removing the sacrificial layer 22 when the space 5 is formed is SF.₆A gas is preferred.
[0096]
  The capping layer 52 is an insulating film made of silicon dioxide (SiO 2).₂In addition, fluorine (F) or carbon (C) -containing oxide films (SiOF, SiOC), organic SOG, porous SOG, organic polymer, amorphous fluorocarbon (aC: F), silicon nitride (SiN), etc. are preferable. .
[0097]
  Next, a method for manufacturing the semiconductor device (sixth embodiment) shown in FIG. 13 will be described with reference to FIGS.
[0098]
  In FIG. 15, (a) the process of forming the lower layer wiring 2 is the same as that in FIG. Next, in order to place the gettering material 50 at an appropriate position on the interlayer insulating film 7, (a-I-1) the resist film 31a is applied and cured, and (a-I-2) resist exposure is performed. The photoresist mask 31 is formed by patterning. Next, the (a-II) gettering film 32 is formed. For this formation, a sputtering method is preferable. For example, the sputtering is performed under argon plasma with titanium as a target. When the gettering film 32 has an appropriate thickness, the (a-III) mask 31 is removed. Hereinafter, in FIG.16 and FIG.17, the (b) process-(i) process is the same as the (b) process-(i) process shown by FIG.6 and FIG.7.
[0099]
  The capping layer 52 is formed to cover the uppermost wiring 2 in the uppermost layer in the step (j) after the gettering material 50 is formed in the space 5 in the step (i) in FIG. The capping layer 52 is made of, for example, SiO.₂Is formed. In this film formation, for example, the gas used is SiH by a low pressure CVD apparatus.₄And O₂(Or NO₂) As SiH₄The flow rate of about 0.05 to 0.2 liters per minute, O₂The flow rate is about 0.6-2 liters per minute, the pressure in the reaction chamber is about 130 Pa, and the substrate temperature is about 350 ° C. or lower and 150 ° C. or higher.
[0100]
  In FIG. 15, after the upper layer wiring 2 is formed, the gettering material 50 is disposed in the same layer, but before this step (a), the step of disposing the gettering material ( I) to (III) may be arranged.
[0101]
  Further, a method for manufacturing the semiconductor device (seventh embodiment) shown in FIG. 14 will be described with reference to FIGS. The support column 51 is the same as the formation process of the support column 25 shown in FIGS. 6 and 7, and the process leading to the first half steps (a) to (h) is the same as FIGS. 6 and 7.
[0102]
  In FIG. 18, (h-I-1) resist film 31a is applied and cured, and (h-I-2) patterning is performed by resist exposure to form a photoresist mask 31. Next, the (h-II) gettering film 32 is formed. This formation is the same as the above-described step (a-II). When the gettering film 32 has an appropriate thickness, the mask 31 is removed in step (h-III) as shown in FIG. Next, the process of removing the sacrificial layer 22 is the same as the process (i) shown in FIG. 7, and as shown in FIG. 14, the gettering material 50 is provided on the support column 51 provided in the space 5. It is done. Subsequently, as shown in step (j), a capping layer 52 is formed in the same manner as in step (j) of FIG. 17 so as to cover the uppermost wiring 2 of the uppermost layer.
[0103]
  18 and 19, (h-I), (h-) so that the gettering material 50 is disposed at a predetermined position after the step (h) in which the upper layer wiring 2 is formed. Steps II) and (h-III) are provided, but the gettering material disposing steps (I) to (III) may be performed before or after the formation of the upper layer wiring 2. Therefore, after the mask 27 for cutting 6 pieces of metal is removed in the step (g) shown in FIG. 7 and before the upper wiring 2 is formed, (g-I), (g-II) and (g -III) It may be provided as a step.
[0104]
  As shown in FIG. 4 or 5, the capping layer 52 can also be formed in the space 5 that is continuous with the inter-element isolation recess 10. Also in this case, the steps (I) to (III) for forming the gettering layer 50 are inserted after the step (g) or (h), and finally the capping layer 52 is formed in the step (j). . For example, when the gettering layer 50 is formed on the way, the step (i-1) in FIG. 10 is as shown in (i-1) in FIG. Subsequently, a capping layer 52 is formed, and as shown in FIG. 20 (j), an airtight space 5 continuing to the inter-element isolation recess 10 is formed.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device of the present invention.
FIG. 2 is a cross-sectional view showing a second embodiment of the semiconductor device of the present invention.
FIG. 3 is a cross-sectional view showing a third embodiment of the semiconductor device of the present invention.
FIG. 4 is a cross-sectional view showing a fourth embodiment of the semiconductor device of the present invention.
FIG. 5 is a cross-sectional view showing a fifth embodiment of the semiconductor device of the present invention.
FIG. 6 is a first half of a method for manufacturing a semiconductor device according to the first embodiment of the present invention;
FIG. 7 is a second half of the continuation of the manufacturing method of FIG. 6;
FIG. 8 illustrates a method for manufacturing a semiconductor device according to a third embodiment of the present invention.
FIG. 9 is a first half of a method for manufacturing a semiconductor device according to a fourth embodiment of the present invention.
FIG. 10 shows the latter half of the continuation of the manufacturing method of FIG.
FIG. 11 shows the first half of a method for manufacturing a semiconductor device according to a fifth embodiment of the present invention.
FIG. 12 is a diagram showing the latter half of the manufacturing method of FIG. 11;
FIG. 13 is a cross-sectional view showing a sixth embodiment of the semiconductor device of the present invention.
FIG. 14 is a cross-sectional view showing a semiconductor device according to a seventh embodiment of the present invention.
FIG. 15 is a drawing showing the first half of the manufacturing method of the sixth embodiment of the semiconductor device of the present invention.
FIG. 16 shows an intermediate part of the manufacturing method of FIG.
FIG. 17 shows the latter half of the manufacturing method of FIG.
FIG. 18 illustrates the first half of the essential part of the method of manufacturing a semiconductor device according to the seventh embodiment of the present invention.
FIG. 19 illustrates the latter half of the main part of the manufacturing method of FIG.
FIG. 20 illustrates a configuration and a manufacturing method of a semiconductor device according to an eighth embodiment of the present invention.
FIG. 21 is a cross-sectional view showing an example of a conventional semiconductor device.
FIG. 22 is a view showing the first half of the method for manufacturing the conventional semiconductor device of FIG. 21;
FIG. 23 is a diagram showing the latter half of the conventional manufacturing method of FIG.
[Explanation of symbols]
          1 Lower layer wiring
          2 Upper layer wiring
          3 Second support (insulating)
          4 First support (insulating)
          5 space
    6,16 metal
          7 Interlayer insulation film
          8 Through hole
          9 Silicon substrate
        10 Inter-element separation recess
        10a Recess formation region for element separation
        11 Etch-resistant film
        22 Sacrificial layer
        23 Photoresist mask (for strut formation)
        24 Sacrificial layer (digging part)
        25 Insulator
        26 Contact hole
        27 Photoresist mask (for buried metal)
        28 Conductor
        30 Photoresist mask (for forming recesses for separating elements)
        50 Gettering material
        51 Prop (for gettering material support)
        52 Capping layer
  53, 56 Prop (conductive)

Claims (7)

In a semiconductor device provided on a silicon substrate provided with a plurality of elements so that wirings connecting the elements form at least two layers above and below,
  A strut connected to the lower surface of the upper layer wiring to support the upper layer wiring is formed, and a continuous space is formed from the gap between the lower layer wirings to at least a part of the lower surface of the upper layer wiring,
  Forming a recess for separating the elements on the substrate surface between the elements, and allowing the space to continue in the recess;
  An etching resistant film is formed on the inner surface of the inter-element separation recess. A method of manufacturing a semiconductor device, wherein a wiring connecting the elements on a silicon substrate provided with a plurality of elements is provided so as to form at least two layers above and below,
(A) forming the lower layer wiring on an interlayer insulating film provided on the silicon substrate;
(B) forming a sacrificial layer so as to cover between the lower layer wiring and the upper surface thereof;
(C) forming a photoresist film by a photolithography method in a region other than the region where the upper layer wiring support is formed;
(D) etching the sacrificial layer in the strut formation region;
(E) forming a support by depositing and filling an insulating film in the etched region;
(F) Forming a contact hole opening pattern mask for embedding a metal for conducting the upper layer wiring with one or more lower layer wirings, and etching the support and / or sacrificial layer in the metal embedding region Forming a contact hole;
(G) burying a metal in the etched contact hole;
(H) forming the upper wiring layer;
(I) a step of isotropically etching the sacrificial layer to form a space in the same layer between the upper and lower wires, the upper and lower layers, and a portion other than the pillars between the wires in a twisted positional relationship;
Including
  Between the step (a) and the step (b),
(A-1) A photoresist mask for forming a through hole in the interlayer insulating film for exposing a region for forming an inter-element isolation recess of the silicon substrate is formed on the interlayer insulating film and the lower layer wiring. Forming a photolithographic method thereon,
(A-2) The interlayer insulating film in a region not covered with the photoresist mask is etched to form the through hole, and an inter-element isolation recess forming region of the silicon substrate under the interlayer insulating film is formed through the through hole. Exposing, and
(A-3) Step of removing the photoresist mask formed in the step (a-1)
Is inserted,
  In the step (i), the exposed element forming recess forming region is dug by isotropic etching to form an element separating recess. A method of manufacturing a semiconductor device, wherein a wiring connecting the elements on a silicon substrate provided with a plurality of elements is provided so as to form at least two layers above and below,
(A) forming the lower layer wiring on an interlayer insulating film provided on the silicon substrate;
(B) forming a sacrificial layer so as to cover between the lower layer wiring and the upper surface thereof;
(C) forming a photoresist film by a photolithography method in a region other than the region where the upper layer wiring support is formed;
(D) etching the sacrificial layer in the strut formation region;
(E) forming a support by depositing and filling an insulating film in the etched region;
(F) Forming a contact hole opening pattern mask for embedding a metal for conducting the upper layer wiring with one or more lower layer wirings, and etching the support and / or sacrificial layer in the metal embedding region Forming a contact hole;
(G) burying a metal in the etched contact hole;
(H) forming the upper wiring layer;
(I) a step of isotropically etching the sacrificial layer to form a space in the same layer between the upper and lower wires, the upper and lower layers, and a portion other than the pillars between the wires in a twisted positional relationship;
Including
  Between the step (a) and the step (b),
(A-1-1) forming a photoresist mask for forming a recess for separating elements on the silicon substrate on the interlayer insulating film and on the lower layer wiring by a photolithography method;
(A-2-1) Etching the region not covered with the photoresist mask, penetrating the interlayer insulating film above the inter-element isolation recess formation region, and further digging the silicon substrate directly below it to a predetermined depth Forming a recess for separating the elements;
(A-2-2) forming an etching resistant film on the inner surface of the inter-element separation recess;
(A-3-1) A method of manufacturing a semiconductor device, wherein a step of removing the photoresist mask formed in the step (a-1-1) is inserted. A method of manufacturing a semiconductor device, wherein a wiring connecting the elements on a silicon substrate provided with a plurality of elements is provided so as to form at least two layers above and below,
(A) forming the lower layer wiring on an interlayer insulating film provided on the silicon substrate;
(B) forming a sacrificial layer so as to cover between the lower layer wiring and the upper surface thereof;
(C) forming a photoresist film by a photolithography method in a region other than the region where the upper layer wiring support is formed;
(D) etching the sacrificial layer in the strut formation region;
(E-1) forming a conductive column by depositing and embedding a metal in the etched region;
(H) forming the upper wiring layer;
(I) a step of isotropically etching the sacrificial layer to form a space in the same layer between the upper and lower wires, the upper and lower layers, and a portion other than the pillars between the wires in a twisted positional relationship;
Including
Between the step (a) and the step (b),
(A-1) A photoresist mask for forming a through hole in the interlayer insulating film for exposing a region for forming an inter-element isolation recess of the silicon substrate is formed on the interlayer insulating film and the lower layer wiring. Forming a photolithographic method thereon,
(A-2) The interlayer insulating film in a region not covered with the photoresist mask is etched to form the through hole, and an inter-element isolation recess forming region of the silicon substrate under the interlayer insulating film is formed through the through hole. Exposing, and
(A-3) Step of removing the photoresist mask formed in the step (a-1)
Is inserted,
In the step (i), the exposed element forming recess forming region is dug by isotropic etching to form an element separating recess. A method of manufacturing a semiconductor device, wherein a wiring connecting the elements on a silicon substrate provided with a plurality of elements is provided so as to form at least two layers above and below,
(A) forming the lower layer wiring on an interlayer insulating film provided on the silicon substrate;
(B) forming a sacrificial layer so as to cover between the lower layer wiring and the upper surface thereof;
(C) forming a photoresist film by a photolithography method in a region other than the region where the upper layer wiring support is formed;
(D) etching the sacrificial layer in the strut formation region;
(E-1) forming a conductive column by depositing and embedding a metal in the etched region;
(H) forming the upper wiring layer;
(I) a step of isotropically etching the sacrificial layer to form a space in the same layer between the upper and lower wires, the upper and lower layers, and a portion other than the pillars between the wires in a twisted positional relationship;
Including
Between the step (a) and the step (b),
(A-1-1) forming a photoresist mask for forming a recess for separating elements on the silicon substrate on the interlayer insulating film and on the lower layer wiring by a photolithography method;
(A-2-1) Etching the region not covered with the photoresist mask, penetrating the interlayer insulating film above the inter-element isolation recess formation region, and further digging the silicon substrate directly below it to a predetermined depth Forming a recess for separating the elements;
(A-2-2) forming an etching resistant film on the inner surface of the inter-element separation recess;
(A-3-1) Step of removing the photoresist mask formed in the step (a-1-1)
A method for manufacturing a semiconductor device, comprising: Before or after the step (a),
(I) a step of forming a gettering material forming mask;
(II) forming a gettering material film; and
(III) A step of removing the gettering material forming mask to obtain a gettering material layer
The method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is inserted. Before or after the step (h),
(I) a step of forming a gettering material forming mask;
(II) forming a gettering material film; and
(III) A step of removing the gettering material forming mask to obtain a gettering material layer
A method for manufacturing a semiconductor device according to claim 2, wherein the semiconductor device is inserted.

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