Connect public, paid and private patent data with Google Patents Public Datasets

Semiconductor device and method of manufacturing the device

Info

Publication number
WO2001095390A1
WO2001095390A1 PCT/JP2000/008194 JP0008194W WO2001095390A1 WO 2001095390 A1 WO2001095390 A1 WO 2001095390A1 JP 0008194 W JP0008194 W JP 0008194W WO 2001095390 A1 WO2001095390 A1 WO 2001095390A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
upper
lower
layer
device
wire
Prior art date
Application number
PCT/JP2000/008194
Other languages
French (fr)
Inventor
Hiroto Kanao
Hiroaki Kouno
Original Assignee
Sumitomo Precision Products Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device capable of increasing the stability of high-speed operation of a circuit by reducing a parasitic capacity and having at least two or more upper and lower layers of wires (1, 2) for connecting elements to each other installed on a silicon substrate having the elements provided thereon, characterized in that columns (3, 4) connected to a lower surface (2d) of the upper layer wire (2) and supporting the upper layer wire (2) are formed, and a space (5) continuing from a clearance (arrow 5a) between the lower layer wires (2) to at least a part of the lower surface (2d) (arrows 5b, 5c) of the upper layer wire (2) is formed.
PCT/JP2000/008194 2000-06-02 2000-11-20 Semiconductor device and method of manufacturing the device WO2001095390A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2000166661 2000-06-02
JP2000/166661 2000-06-02
JP2000/338950 2000-11-07
JP2000338950A JP4967084B2 (en) 2000-06-02 2000-11-07 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
WO2001095390A1 true true WO2001095390A1 (en) 2001-12-13

Family

ID=26593262

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/008194 WO2001095390A1 (en) 2000-06-02 2000-11-20 Semiconductor device and method of manufacturing the device

Country Status (2)

Country Link
JP (1) JP4967084B2 (en)
WO (1) WO2001095390A1 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4827639B2 (en) * 2006-07-12 2011-11-30 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
KR101486712B1 (en) 2013-12-28 2015-01-28 (재)한국나노기술원 Method of Producing a Three-Dimensional Metal Structure on Flexible Substrate

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4835779A (en) * 1971-09-10 1973-05-26
JPS60244045A (en) * 1984-05-18 1985-12-03 Hitachi Ltd Semiconductor device
JPH01264243A (en) * 1988-04-14 1989-10-20 Nec Corp Semiconductor device and its manufacture
EP0476625A2 (en) * 1990-09-18 1992-03-25 Nec Corporation A semiconductor device comprising interconnections
JPH05218212A (en) * 1992-01-31 1993-08-27 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH06310612A (en) * 1993-04-27 1994-11-04 Hitachi Ltd Wiring structure of semiconductor indegrated circuit and its manufacture
JPH0964172A (en) * 1995-08-18 1997-03-07 Sony Corp Semiconductor integrated circuit device
EP0812016A1 (en) * 1996-06-04 1997-12-10 Harris Corporation Integrated circuit air bridge structures and methods of fabricating same
US5998293A (en) * 1996-06-05 1999-12-07 Advanced Micro Devcies, Inc. Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07245301A (en) * 1994-03-03 1995-09-19 Fujitsu Ltd Manufacture of semiconductor device
JP3665490B2 (en) * 1998-10-05 2005-06-29 シャープ株式会社 Wiring structure of a semiconductor device and a method of forming the

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4835779A (en) * 1971-09-10 1973-05-26
JPS60244045A (en) * 1984-05-18 1985-12-03 Hitachi Ltd Semiconductor device
JPH01264243A (en) * 1988-04-14 1989-10-20 Nec Corp Semiconductor device and its manufacture
EP0476625A2 (en) * 1990-09-18 1992-03-25 Nec Corporation A semiconductor device comprising interconnections
JPH05218212A (en) * 1992-01-31 1993-08-27 Mitsubishi Electric Corp Manufacture of semiconductor device
JPH06310612A (en) * 1993-04-27 1994-11-04 Hitachi Ltd Wiring structure of semiconductor indegrated circuit and its manufacture
JPH0964172A (en) * 1995-08-18 1997-03-07 Sony Corp Semiconductor integrated circuit device
EP0812016A1 (en) * 1996-06-04 1997-12-10 Harris Corporation Integrated circuit air bridge structures and methods of fabricating same
US5998293A (en) * 1996-06-05 1999-12-07 Advanced Micro Devcies, Inc. Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect

Also Published As

Publication number Publication date Type
JP4967084B2 (en) 2012-07-04 grant
JP2002057215A (en) 2002-02-22 application

Similar Documents

Publication Publication Date Title
US6465892B1 (en) Interconnect structure for stacked semiconductor device
US6727116B2 (en) Semiconductor devices including peripherally located bond pads, assemblies, packages, and methods
US5481133A (en) Three-dimensional multichip package
US5731222A (en) Externally connected thin electronic circuit having recessed bonding pads
US6452247B1 (en) Inductor for integrated circuit
US6462423B1 (en) Flip-chip with matched lines and ground plane
US5903050A (en) Semiconductor package having capacitive extension spokes and method for making the same
US6730540B2 (en) Clock distribution networks and conductive lines in semiconductor integrated circuits
US20060094165A1 (en) Method for fabricating semiconductor components
US5016087A (en) Integrated circuit package
US6380048B1 (en) Die paddle enhancement for exposed pad in semiconductor packaging
US6022758A (en) Process for manufacturing solder leads on a semiconductor device package
US5786630A (en) Multi-layer C4 flip-chip substrate
US6124149A (en) Method of making stackable semiconductor chips to build a stacked chip module
US7084500B2 (en) Semiconductor circuit with multiple contact sizes
US20090294947A1 (en) Chip package structure and manufacturing method thereof
US6614092B2 (en) Microelectronic device package with conductive elements and associated method of manufacture
US6628527B2 (en) Mounting structure for electronic parts and manufacturing method thereof
US6586825B1 (en) Dual chip in package with a wire bonded die mounted to a substrate
US20040094826A1 (en) Leadframe pakaging apparatus and packaging method thereof
US7466028B1 (en) Semiconductor contact structure
US20050087875A1 (en) Method of forming gas dielectric with support structure
US20040140559A1 (en) Electronic device configured as a multichip module, leadframe, panel with leadframe positions, and method for producing the electronic device
WO2005022631A1 (en) Semiconductor package and manufacturing method thereof
US20040058520A1 (en) Support structures for wirebond regions of contact pads over low modulus materials

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): KR US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase