WO2001095390A1 - Semiconductor device and method of manufacturing the device - Google Patents

Semiconductor device and method of manufacturing the device

Info

Publication number
WO2001095390A1
WO2001095390A1 PCT/JP2000/008194 JP0008194W WO0195390A1 WO 2001095390 A1 WO2001095390 A1 WO 2001095390A1 JP 0008194 W JP0008194 W JP 0008194W WO 0195390 A1 WO0195390 A1 WO 0195390A1
Authority
WO
Grant status
Application
Patent type
Prior art keywords
forming
wiring
layer
step
semiconductor device
Prior art date
Application number
PCT/JP2000/008194
Other languages
French (fr)
Japanese (ja)
Inventor
Hiroto Kanao
Hiroaki Kouno
Original Assignee
Sumitomo Precision Products Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

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Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device capable of increasing the stability of high-speed operation of a circuit by reducing a parasitic capacity and having at least two or more upper and lower layers of wires (1, 2) for connecting elements to each other installed on a silicon substrate having the elements provided thereon, characterized in that columns (3, 4) connected to a lower surface (2d) of the upper layer wire (2) and supporting the upper layer wire (2) are formed, and a space (5) continuing from a clearance (arrow 5a) between the lower layer wires (2) to at least a part of the lower surface (2d) (arrows 5b, 5c) of the upper layer wire (2) is formed.

Description

Specification

Semiconductor device and manufacturing method art

The present invention relates to a semiconductor device and a manufacturing method thereof, particularly to prevent an increase in parasitic due to wiring interval of the same layer is narrowed capacitance (wiring capacitance), a semiconductor device and it is possible to stabilize the high-speed operation of the integrated circuit that relates to the production how. BACKGROUND

Conventionally, as a technique for reducing the parasitic capacitance between wirings, upper wiring, it is to cover the lower layer and the interlayer with an insulating film has been commonplace, usually small dielectric constant in the insulating film materials dioxide silicon (S ί Ο 2) it is used. However, in recent years, further progress in narrowing the wiring interval, only Insulator satisfying between wires has a parasitic capacitance Teki Summer can not be reduced as expected. Since the increase in the parasitic capacitance leads to the generation of induced noise, stable circuit operation is prevented in the circuit, especially the high-speed operation. Therefore, a technique for reducing the capacitance provided holes or cavities in the insulation between the wires have been variously disclosed. Pores or which by reducing the electrostatic capacitance between wirings cavity, a small time constant for charging Li is the high speed operation of the element and the circuit is ensured. Figure 2 1 shows an example of a semiconductor device (JP-1 0 3 3 5 4 5 9 JP) having such a cavity, 2 2 and 2 3 depicts the preparation .

2 1, the cavity between the insulating film 1 0 3, 1 0 4 are formed, the insulating film 1 0 3 1 0 4 between the lower wiring 1 0 1 and the upper wiring 1 0 2 1 0 5 is formed. Buried metal 1 0 6 is intended to electrically connect the upper wiring 1 0 2 and the lower wiring 1 0 1, under the interlayer insulating film 1 0 7, further lower wiring below or a semiconductor element there is a semiconductor substrate having. 2 2, on the interlayer insulating film 1 0 7, lower wiring 1 0 1 putter training has been our Li, an insulating film 1 0 3 so as to cover the lower wiring 1 0 1 are formed (FIG. 2 2 (a) see). The insulating film 1 0 3, for example, oxide film der Li, after a plasma oxide film or bias sputtered oxide film was 1 5 / m growth, CMP.: By (C hemical M echanical P olishing chemical mechanical polishing) method polishing ■ planarized is formed on the wiring layer thickness 8 0 0 nm.

Next, typical follower Torejisu preparative method and cavity type formed opening 1 0 8 by anisotropic etching (0. 3 m □) and the via hole openings 1 0 9 (0. 4 fl mn) at the same time form (refer to FIG. 2 2 (b)). When the wiring interval is 0. The above 9 m is, 0. 3 jU m cavity formation opening 1 0 8 a width, 1 0 8 b for the two forms. Overetch to be in the depth of the opening mouth portion cavity formed to the lower surface of a lower layer wiring 1 0 1 as possible out to sufficiently deeply formed. For example, by about 80% over-etching amount, the depth is about 1 4 0 0 nm.

Then, the via hole opening 1 0 9, buried metal 1 0 6 become tungsten 亍 ^ ¾: CVD, C emica IV apor D Θ position: growing in of Gakuki deposition) method. For example, using WF 6 as a growth gas, reduced with H 2 or S i H 4 at 4 0 0 ° C approximately, data down Dasuten grows only on the metal (see FIG. 2 3 (c)).

On this, further, the insulating film 1 1 0: (oxidation film plasma oxide film or bus Iasusupatta oxide film), to reduce the embedding property by overlooked the RF power, blocked the upper space forming opening 1 0 8 with easy condition: only the upper 1 0 4 of the opening 1 space shaped formation 0 8 to form an interlayer insulating film 1 1 0 over the entire surface to clogged sufficiently. It to Li, the cavity 1 0 5 which is sealed in the insulating film 1 0 3 between the lower wiring 1 0 1 is formed (see FIG. 2 3 (d)).

Next, the polishing of the interlayer insulating film 1 1 0 to expose buried metal 1 0 6 using wafer polishing technique (CMP) - (see FIG. 2 3 (Θ)) is flattened, followed by conventional follower Torejisu preparative method and forming an upper wiring 1 0 2 by using an etching method.

However, in the conventional example described above, since the cavity 1 0 5 by anisotropic etching is formed in a columnar shape in the insulating film 1 0 3, Te cowpea excessive etching, cavities 1 0 5 deep enough (lower layer even if the attempted to have down to) than the wiring 1 0 1 of the lower surface of the line, believed to be a limit to the reduction of parasitic capacitance. Other the disclosed prior art (JP-A-2 - 8 6 1 4 6 JP Contact and Hei 5 - 2 1 6 1 7 JP) even in anisotropic with respect to the insulator existing between wirings because are provided holes or cavities by etching or the like process, it can not be taken sufficiently cope with miniaturization of space specific limit to the reduction of the parasitic capacitance reasons there Li, design rules to intensify They are out. Further, in the technique for forming the structure of a semiconductor device such as transistors proceed in three dimensions, between the three-dimensional wiring (between the same layer wiring, such as inter-wiring in a wiring between and skewed upper and lower layer ) or you can have Nitsu like between devices, reduce the parasitic capacitance is indispensable.

Has been made in view of the problems as described above of the present invention, the main object is, among three-dimensional wiring not planar only provide a semiconductor device and its manufacturing method can dramatically reduce the parasitic capacitance It is to. Another object of the present invention is to obtain a semiconductor device stably by increasing the manufacturing precision of the supports for the upper layer interconnection, also causing damage to the wiring and the element in forming between air to reduce parasitic capacitance there to be subjected Hisage a free process. Disclosure of the Invention

In the present invention, a semiconductor device that is provided so as to form two or more layers vertically least is that connecting lines between the element on a silicon substrate in which a plurality of elements are provided, coupled to the lower surface of the upper wiring is characterized in that to form the supports for the upper layer wiring, the least the lower surface of the upper layer wiring through the gap between the lower wiring was allowed form a space for continuously toward a portion Te. By the strut, the space in the same layer and the upper and lower layers is formed. Between the sky, three-dimensional wiring between (the interlayer, the vertical between the interlayer and skewed) is therefore wider on, be narrower wiring spacing can be reduced sufficiently parasitic capacitance.

In the present invention, the strut is preferably an insulating material.

By forming the pillar in electrical insulation, while ensuring the insulation between wires, upon narrowing of wire spacing can be more than enough satisfy the reduction of parasitic capacitance. The upper and lower layers (points to be electrically connected comprising a distant vertical relation above one layer>, a metal for conduction provided columnar. Pillar-shaped conductive metal in this case is not necessary to support the upper wiring may be thinner. in the present invention, when forming the pillar with an insulating material, the posts, a first post for supporting said upper wiring provided on the lower layer wiring, the lower wiring includes a second standoff to support the upper wiring in the portion of free silicon substrate, it is preferred that the metals are embedded for conducting the both one least of said first strut.

It electrically connects the upper and lower layers of metal for conducting embedded in the strut.

Meanwhile, in the present invention, it is also preferable that the conductor said strut. In that case, by the post and conductor, it is possible to concurrently the role of wires for electrically connecting the upper and lower layers. Therefore, the structure is simplifies, in process, can be omitted the step of embedding the metal for conducting. In the case of the metal posts can be insulated by providing on the insulating layer.

Furthermore, in the present invention, a recess in the substrate surface between said elements, between the air it is preferable to continuously into the recess.

By forming the recess between the elements, it is possible to it is possible to increase the insulation between elements, reduced parasitic capacitance. Further, promoting of Seuru miniaturization between elements.

Case in which the inter-element recesses, in the course of the manufacturing process of the semiconductor device, prior to the Etsuchin grayed step, it is preferable to form the etching resistant film on the inner surface of the inter-element recesses.

By forming the etching resistant layer on the inner surface of the element between the recess, it is not damaged element surface during Etsuchin grayed. Further, the etching does not proceed in the lateral direction of the silicon substrate, it is easy to dimension control between devices.

Furthermore, the present invention is characterized in that a gettering material into the space between the wires.

Gettering material, acts to exclude from the gas phase to adsorb gas molecules, a material having a knob re exhaust action. As such, it is commonly known, barium, magnesium, calcium, titanium, tantalum, di Rukoniumu addition to vanadium, as possible out utilizing like Germany thorium. In the present invention, by being placed in the space, after complete semiconductor device, i.e., after the space formed by adsorbed the § © Togasu coming discharged from the material in contact with the space, to prevent accumulation of Au Togasu, space vacuum for the purpose of Rukoto increase the degree. The realization of high vacuum, reducing the parasitic capacitance is promoted. Furthermore, it is possible to prevent corrosion due to Au Togasu, the deterioration of the wiring, it is possible to prolong life of the semiconductor device.

In the present invention, the gettering material, in the space between wires, such as by placing in a solid thereon provided struts interlayer insulating film or for it, can take effect after semiconductor manufacturing those are preferred, as the such, can be mentioned titanium, zirconium, and the like cum thorium. These, upon arrangement, it is preferable that the area of ​​the surface is placed in the most widely made shape. Furthermore, when using titanium, plasma used isotropic etching, arbitrary preferred that a SF 6 gas.

In the present invention, the upper and lower wiring covering from the top of the uppermost layer wiring, said gate jitter closing a space ring member is provided hermetically capping layer is al provided.

According to the present invention, since the space is sealed by Kiyabbingu layer, gas adsorption action of the getter material in the space works effectively, the degree of vacuum in the space is increased.

Next, as a manufacturing method of the semiconductor device described above, first, the production method of the present invention for manufacturing a semiconductor device comprising by embedding the metal for conducting the insulator made of the struts,

(A) a step of forming the lower layer wiring in the interlayer insulating film provided on the silicon substrate,

(B) and as E forming a sacrificial layer so as to cover between and the upper surface of the lower wiring,

Forming a follower Torejisu bets film by (c) follower Torisogu Rafi one method in a region other than the region where posts of the upper layer wiring is formed,

And (d) etching the sacrificial layer of the strut forming region,

Forming a pillar (theta) is embedded by forming an insulating film on the etched region,

(F) shaping the contactor Tohoru opening pattern mask for setting buried metal for conducting the lower layer wiring of the lower one or more layers of the upper wiring, etching the struts and or sacrificial layer of metal buried region where forming a contactor Tohoru Te,

(G) a step of embedding a metal in the etched contactor Tohoru

(H) forming the upper wiring layer,

(I) the sacrificial layer isotropically same layers of etched and upper and lower wiring, forming a space portion other than the strut between the wires at the top and bottom layers and twisted positional relationship

It is characterized in that it comprises a.

Incidentally, the step of forming the upper wiring layer (h), after embedding the embedded metal by removing the pattern mask contactor Tohoru opening, forming a metal film for upper wiring, excess metal film according to the wiring pattern the a portion in which a step of etching. Besides, it is also possible to use a method which has been used as a method of forming a wiring layer (metal film) conventionally.

In this method, a follower Torejisu preparative film (mask) by follower tri lithography of the Act, forms a strut crowded padded by forming an insulating film on the sacrificial layer is etched in a columnar shape, accurately it is possible to form the pillars. Further, after forming the posts, to form isotropic space with the exception up the sacrificial layer Te to base by etching, a high molding accuracy.

On the other hand, in the manufacturing method of the present invention for manufacturing a semiconductor device having a conductive pillar, the step (g), a step of embedding a metal in the etched contactor Tohoru, the step (h), the upper wiring layer and forming may be performed at the same time.

A buried metal and the upper wiring are both conductive materials, can be formed by the same material, the Te and the (h) by performing steps simultaneously Unishi step (g) further simplified steps be able to.

Further, as a method of manufacturing a semiconductor device strut is made of a conductor, the manufacturing method of the present invention,

(A) a step of forming the lower layer wiring in the interlayer insulating film provided on the silicon substrate,

(B) and as E forming a sacrificial layer so as to cover between and the upper surface of the lower wiring,

Forming a follower Torejisu bets film by (c) follower tri Seo Rafi one method in a region other than the region where posts of the upper layer wiring is formed,

And (d) etching the sacrificial layer of the strut forming region,

(E - 1) and the step of forming the conductive pillar is embedded by forming a metal in the etched areas,

(H) forming the upper wiring layer,

(I) the sacrificial layer isotropically same layers of etched and upper and lower wiring, forming a space portion other than the strut between the wires at the top and bottom layers and twisted positional relationship

It is characterized in that it comprises a.

Method in comparison with the semiconductor having an insulator standoff is simplified.

If the embedded metal and the upper wiring even in the above method to form the same material, wherein (e - 1) Ki de be carried out step and said step (h) at the same time, further steps can be simplified .

In addition to the aforementioned method of a semiconductor device, in the present invention, after the step (i), further, (j) on the uppermost layer wiring, Kiya' Bing layer to close the space airtight the step of forming the

Contains. Rukoto is preferable.

According to this method, the space is airtight by Kiyabbingu layer is sucked into the vacuum by Getting data ring material.

Further, as a method of manufacturing a semiconductor device in which the separating recesses between the elements is provided, in the manufacturing method of the present invention, between the (a) said step (b) Step

(A - 1) follower Torre Soo mask the interlayer insulating film and the lower layer of the through-holes for forming the interlayer insulating film for exposing a region for forming the device isolation recess of the silicon substrate a step of by re formed follower birds Seo Rafi one method over the wiring,

(A - 2) the follower Torejisu the covering non region in mask layers an insulation Enmaku is etched to form the through hole, the element isolation recess forming region of the silicon substrate under the interlayer insulating film through the through hole exposing a, (a - 3) wherein (a - 1) a step of divided the formed follower Torejisu mask in step

There has been inserted.

In this method, prior to step (b) is covered with a sacrificial layer to the lower layer wiring, (a - 1) Step - - In (a 3) step, by Etsuchin grayed an interlayer insulating film under the lower wiring, between the elements allowed to expose regions forming isolation recess, so that the sacrificial layer is formed on the (b) at higher E, this region. In a child this, when the isotropic etching in the final step (i), at the same time space sacrificial layer is removed is formed, the region is dug down, is formed separate recesses between the elements that. Therefore, Ru can be simplified steps. Further, as a method of manufacturing a semiconductor equipment which is resistant Etsuchingu film formed on the concave portion for separating between elements, the production method of the present invention, between said step (a) the step (b),

And (1 a - - 1) a step of by re form follower Torejisu mask for forming an element isolation recess in the silicon substrate in the Photo lithography of the Act on the interlayer insulating film and on said lower wiring,

(A - 2 - 1) the follower Bok Regis Etsuchi areas not covered by the mask Ngushi, through the upper interlayer insulating film of the element isolation recess formed region, in addition, a silicon substrate a predetermined depth immediately below the drill down to, and forming a recess for separation between the elements,

And (2 a - - 2) that form a etching resistant film on the inner surface of the separation recesses between the element step,

(A - 3 - 1) wherein (a - 1 - 1) formed in step the Photo Regis removing the Tomah disk

There has been 揷入.

In this method, (a - 2 - 1) by controlling the anisotropic etching in the step, simultaneously with the etching of the interlayer insulating film, contact Li element content releasing region of the silicon substrate directly under the anisotropically etched , it is possible to form a recess for separation between the elements to a predetermined depth. Further, (For example, oxide film) etching resistant film in the recess inner surface forms a can exhibit the etching resistant effect on etching for sacrificial layer removal in the final step (i). Accordingly, without damaging the element improves the dimensional accuracy as a result, it may correspond to further miniaturization of design rules.

In the production method of the present invention, the sacrificial layer has preferably be a silicon layer

If silicon layer, can easily be removed this using isotropic etching, can be reduced damage of wiring and devices. For example, by providing a suitable E Tsuchingu conditions for the material other than silicon, so it has a selectivity (5 0 0 or more in the most favorable conditions) 1 0 0 or more. Thus, receiving Keru bad transient portion from wiring and strut in contact with the formed space. Is very small.

In the manufacturing method of the present invention, it is preferred that the sacrificial layer is a registry layer.

It is used registry layer as a sacrificial layer can be formed of a semiconductor device of the present invention as well.

Further, as a method of manufacturing a semiconductor device having a gettering material in the lower layer wiring in the same layer, the production method of the present invention, before or after step (a),

(I) forming a getter-ring material for forming the mask,

([Pi) step of forming a getter-ring material film, and

(M) obtaining a getter-ring material layer by removing the gettering material forming mask

There has been 揷入.

This method, the lower layer wiring in the same layer can be provided a getter phosphorus. Grayed material on the interlayer insulating film. Moreover, can be combined with the manufacturing method to be described later, it provided gettering material in the upper layer wiring in the same layer.

And a manufacturing method of providing a gettering material in the upper layer wiring in the same layer, the production method of the present invention, before or after the step (h),

(I) forming a getter-ring material for forming the mask,

([Pi) step of forming a gettering material film, and

(M) obtaining a gettering material layer by removing the gettering material forming mask

There has been 揷入. In this way, the upper layer wiring in the same layer, as with the upper wiring is allowed to form a pillar or the like on the interlayer insulating film, for distributing the gettering material thereon. Of course, in one space, combined with those of the lower wiring in the same layer, those of the upper wiring in the same layer, may be provided two or more. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a sectional view showing a first embodiment of a semiconductor device of the present invention. Figure 2 is a sectional view showing a second embodiment of a semiconductor device of the present invention. Figure 3 is a sectional view showing a third embodiment of a semiconductor device of the present invention. Figure 4 is a sectional view showing a fourth embodiment of the semiconductor device of the present invention. Figure 5 is a sectional view showing a fifth embodiment of the semiconductor device of the present invention. Figure 6 is a first part of the method of manufacturing the semiconductor device of the first embodiment of the present invention.

Figure 7 is a second part of the continuation of the manufacturing method of FIG.

Figure 8 describes a method of manufacturing the semiconductor device of the third embodiment of the present invention.

Figure 9 is a first half of a manufacturing method of a semiconductor device according to a fourth embodiment of the present invention.

Figure 1 0 shows the latter part of the continuation of the process of FIG.

Figure 1 1 shows a front half portion of the method of manufacturing the semiconductor device of the fifth embodiment of the present invention.

Figure 1 2 is a diagram illustrating the latter half portion of FIG. 1 1 of the process.

1 3, 1 4 is a sectional view showing a sixth embodiment of the semiconductor device of the present invention, FIG. 1 5 is a sectional view showing a semiconductor device of the seventh embodiment of the present invention, the present is a diagram illustrating the first half portion component of the manufacturing method of the sixth embodiment of the semiconductor device of the invention.

Figure 1 6 shows the intermediate portion of Figure 1 4 production method.

Figure 1 7 shows the second half of FIG. 1 4 production method.

1 8 describes a first part of a main part of a method of manufacturing a semiconductor device of the seventh embodiment of the present invention.

1 9 describes the second part of the main part of the manufacturing process of FIG 8.

2 0, describes the configuration and manufacturing how the semiconductor device of the eighth embodiment of the present invention.

Figure 2 1 is a sectional view showing an example of a conventional semiconductor device.

2 2 is a view to view the first half of the method of manufacturing a conventional semiconductor device of FIG 1.

Figure 2 3 is a diagram showing the second half of the conventional method of FIG 2. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, specific embodiments of the present invention, described with reference to the accompanying drawings. 1 to 5, respectively, an embodiment of a semiconductor device of the present invention, is a cross-sectional view showing the first to fifth. 6 and 7 show a manufacturing method of the first embodiment of the present invention (the semiconductor device shown in FIG. 1). Moreover, it adopted 8 instead of 7, by going through the steps of FIGS. 6 and 8, a third embodiment of the present invention (the semiconductor device shown in FIG. 3) is obtained. Further, FIGS. 9 and 1 0 shows a manufacturing method of the fourth embodiment of the present invention (semiconductor equipment shown in FIG. 4), 1 1 and 1 2, the fifth of the present invention It shows a manufacturing method of implementation forms (the semiconductor device shown in FIG. 5) of the.

Furthermore, Figure 1 3 to 2 0, is intended to be illustrative of the present invention having a gettering material in the space, Figures 1 to 3, of the present invention which arranged gettering material in the lower layer wiring and the sixth layer a cross section of the embodiment, FIG. 1 4 is a cross-sectional view of a seventh embodiment of the present invention which arranged gettering material on the upper layer wiring in the same layer, FIG. 5 to FIG. 1 7 6 a embodiment method of manufacturing (a semiconductor device shown in FIG. 1 3) 1 8 and 1 9, show a manufacturing method of the seventh embodiment (the semiconductor device is shown in Figure 1 4) there. Also, FIG. 2 0 shows the configuration and manufacturing method of the embodiment of FIG.

In Figure 1, the lower layer wiring 1 is provided on the interlayer insulating film 7, the upper layer wiring 2 by the struts 3, 4 are supported on the interlayer insulating film 7 or the lower layer wiring 1. The second strut 3, support upper wiring 2 be on the interlayer insulating film 7, first support column 4 is installed to support the upper layer wiring 2 be on the lower layer wiring 1. Upper layer wiring 2, these first, will form were Lift by the second support column 3, 4, the space 5 is formed between the upper and lower wiring 1, 2. During the space 5, and 5 a between the lower layer wiring 1 side 1 a, 1 b adjacent, directly above, the upper surface 1 c and the upper wiring 2 of the lower surface 2 d of the lower layer wiring 1 between the bottom on the right below 5 and b, a geometrically to the lower layer wiring 1 and the three-dimensional space that have a and 5 c between the upper layer wiring 2 in skewed.

In Figure 1, column 3, 4 is formed by an electrical insulator, a metal 6 which is embedded in the first support column 4, the upper and lower layers 1, 2 between are electrically connected. Metal 6 are those appropriately provided in required locations. 2, metal 1 6 serves to electrically connect the upper and lower layers 1, 2. In this second embodiment, the upper layer wiring 2, which is fully supported by the support column 3, 4, not the this is defined, the thickness of the metal 1 6. However, in the proper thickness of the metal 1 6, it can be substituted for the posts.

Further, in FIG. 3, support 5 3, 5 6, made of a conductive material and a. Those having an appropriate thickness. Struts 5 6 provided on the lower layer wiring 1 is also responsible for electrically connecting the upper and lower layers 1, 2. Need not part component for electrically connecting, like the support 5 3, appropriately upright on the insulating film.

In FIGS. 1 to 3, is shown FIG wiring 1, 2 only the upper and lower layers on the interlayer insulating film 7, the present invention is not limited thereto, 3 with upper wiring further above the upper wiring more than the layer also contains naturally, in that case is referred to as an upper wiring or lower wiring on the top and bottom of the relative relationship. This also FIG later.

Upper and lower layer wiring 1, 2, aluminum (AI), aluminum alloy, copper (C u), tungsten (W), tungsten silicon Sai de (WS i), titanium nitride (Τ ί Ν), Chitanshirisai de (T i S i) consisting of a single or laminate such as. Embedded metal 6 (see FIG. 1) and, conduction metal 1 6 (see FIG. 2) is similar.

Column 3, 4, the case made of insulating material, S i O x N x, S i O x, S i OF, amorphous full O b carbon. (A - C: F) with a low dielectric constant material, such as certain it is preferable. Further, it is preferable as it can secure the strength to support the upper layer wiring. .

Struts 5 3 molded by conductor 5 6 (see FIG. 3), similar to the upper and lower layer wiring 1, 2, aluminum (AI), aluminum alloy, copper (C u), tungsten (W), tungsten silicon Sai de (WS i), Chi nitride Tan (T i N), consisting of simple substance or a laminate of such Chitanshirisai de (T i S ί).

Interlayer insulating film 7, for example, an oxide film such as a plasma oxide film or bias sputtered oxide film.

Incidentally, those of the upper and lower layer wiring 1, 2 are sequentially stacked multilayer structure with an interlayer insulating film 7, as shown in FIG. 4, in the interlayer 铯縁 film 7, metal 1 7 for conduction buried It is. Although not illustrated, the metal is embedded in the second support column 3 and the layer insulating film 7 may be connected further upper layer wiring 2 thereon and the upper layer wiring 2.

Figure 4 shows a fourth embodiment of the semiconductor device of the present invention, through ¾ 8 is formed in the interlayer insulation Enmaku 7, an element isolation recess 1 0 provided on the silicon substrate 9 directly below through hole 8 is communicated. Element separating recess 1 0 is intended to improve the insulation between elements, like the space 5 than are filled with an insulating material, space, or, to be space near vacuum preferable. Through-holes 8 are al provided to form a separate recess 1 0 between the elements.

Figure 5 shows a fifth embodiment of the semiconductor device of the present invention, in addition to the semiconductor device shown in FIG. 4, further, resistance to etching film 1 1 in the element isolation recess 1 0 of the surface forming It is. Resistant etching film 1 1, such a degree production over is for recesses 1 0 from being eroded.

It is an anti-etching film 1 1, there is S i O x N x, S i O x. The anti-etching film 1 1 is cut with formation by performing an oxygen plasma irradiation under appropriate conditions without peeling the Regis mask for etching the interlayer insulating film.

Next, with reference to FIGS. 6 and 7, the first embodiment forms state (see FIG. 1) of the semiconductor device of the present invention, and the second embodiment that describes the manufacturing method (see FIG. 2).

6, first, in this (a) forming a lower layer wiring 1 on (a) the interlayer insulating film 7, for example, aluminum alloy, copper etc. alone or laminates of the above-mentioned wood charge is etched after patterning and the like to form the lower layer wiring 1. Its formation, for example, by using a DC magnetic Tron sputtering apparatus, DC voltage about a 1 k W, a use gas A r (Purazumaio down), the flow rate of about 0.1 liters per minute (although, below to Baie Te standard conditions the volume of (0 ° C, 0. 1 P a (1 atm))), the pressure in the reaction chamber was about 3 P a, to the target and AI. Then, unnecessary portions of the AI ​​thin film formed by sputtering is removed by such Regis mask formation and subsequent main barrel etching (anisotropic dry etching), to obtain AI wiring (lower wiring). Also, In addition also, CVD method, it is also possible, such as a plating method. Incidentally, it is possible to the upper layer wiring is also formed in the same manner. Furthermore, the method also embedding the metal contactee Tohoru is valid.

Next, a sacrificial layer 2 2 so as to cover the (b) lower-layer wiring 1.

Sacrificial layer 2 2, for example, an amorphous silicon is deposited. This film formation, for example, by low pressure CVD apparatus, a gas used as the S i H 4 and A r (or H 2), S i H about 0.0 5-0 a flow rate of 4.2 Li Tsu Torr min, the flow rate of the a r of about 0.5 to 2 liters per minute, 1 the number of pressure of the reaction chamber OP a, a substrate temperature of about 3 5 0 ° C or less 1 5 0 ° C or higher and to.

Next, a (c) the sacrificial layer 2 2 CMP (chemical mechanical poly Tsu Thing, C h Θ mica IM echanical P olishing) After planarized) method such as, follower Torejisu mask 2 3. Next, remove the sacrifice layer 2 4 which is not covered by (d) the mask 2 3 etch ring. This etching, it is anisotropic etching, from the viewpoint of dimensional control, for example, ICP- RIE apparatus (inductively coupled plasma-stage reaction ion etching (I nductiv Θ I y C oup I θ d P lasma - the R eactive I on E tching)) , about 1 2 0 0 W coil, the platen was about 3 0 W, the pressure in the reaction応室about 2. 6 7 P a, it SF 6 and Furuoroka one Bongasu is about 0.1 liters per minute and about 0. 0 5 and Mochiiruko at a flow rate of l per minute are preferred. Next, in FIG. 7, (theta) after removing the mask 2 3, to form the support post 2 5 embed an insulating film portion 2 4 dug-down sacrificial layer. The formation of the standoff 2 5, S i Ο 2 film formation is preferred. This film formation, ECR- CVD so! ^ - The (E lectron C yclotron R Θ sonanc Θ p I asma CVD apparatus), 〃 wave power of about 1 k W, U I tail current of about 2 OA, the use gas S i H 4 0 2 and A r and a, and the flow amount of each about 0.0 1 liter per minute and about 0.0 2 liters per minute and about 0. 0 5 liters per minute, the pressure in the reaction chamber, the number X 1 0- 1 P a, the substrate temperature, about 3 0 0 ° C over 4 5 0 ° C or less, then the RF power and about 2 0 0 W, strut 2 which is formed by (f) said step 5 and forms a follower Torejisu mask 2 7 on the remaining sacrificial layer 2 2, to form a Rikontaku Tohoru 2 6 Manzanillo and this performing anisotropic etching. Anisotropy Etsuchin grayed in this case, depending on the material of the support post 2 5, as described above, when forming at S i O 2 film, the anisotropic etching of S i O 2 film do. This was example, if, ICP- by RIE apparatus, a coil about 1 0 0 0 W, the platen to approximately 5 0 0 W, about 0. 3 3 P a pressure in the reaction chamber, the standard state Furuoroka one carbon gas in use at a flow rate of about 0.0 2 liters per minute. Although not shown contactor Tohoru is not limited to only support 2 within 5, if necessary, it may be formed on the sacrificial layer 2 2. In this case, process is determined in consideration of both of the material of the tower 2 5 and the sacrifice layer 2 2.

Next, eliminate the (g) follower Torejisu mask 2 7 embeds the metal 6 in contactor Tohoru 2 6. This padding, ECR-by CVD equipment, a wave power of about 1 k W, about 2 0 A coil current, and the and the WF 6 using gas H 2 and A r, the flow rate of about respectively 0.0 1 and Li Tsu torr per minute and about 0.0 2 liters per minute and about 0.0 5 liters per minute, the pressure in the reaction chamber, about 0 · 7 P a, the substrate temperature, about 3 0 0 ° C or more 4 5 0 ° C or less, the RF power of about 2 0 OW.

Next, a (h) upper layer wiring 2. Upper layer wiring 2 can be formed by the same method with the same material as the lower layer wiring 1 described above, may be made different lower layer wiring 1 and the upper wiring 2 of the material and the manufacturing method of one semiconductor device following to, to form a re-space 5 due to (i) the sacrificial layer 2 2 of the etching. This includes isotropic etching, from the viewpoint of facilitating the etching of the upper layer wiring under and upper and lower layers. For example, by using SF 6 plasma, the ICP (inductively coupled plasma) conditions, the coil about 6 0 OW, the bra Ten to about 5 W, the pressure in the reaction chamber to about 2. 7 P a, and use gas the flow SF 6, about 0.1, it is preferable that the l per minute. Also, in the ECR conditions, ECR-by CVD device, 〃 wave power of about 1 k W, about 2 0 A coil current, the flow rate of SF 6 and A r gas used, about 0.0 5 Li Tsu torr per minute and about 0.0 5 liters per minute, a pressure of about 0. 7 P a reaction chamber, a substrate temperature, and 4 5 0 ° C or less to about 3 0 0 ° C or higher.

Note that the isotropic etching for removing the sacrificial layer 2 2, can also be X e F 2 gas used. In that case, the pressure in the reaction chamber is more than about 0. 4 P a.

Described above and (g) step (formation of buried metal 6) (h) step (formation of the upper layer wiring 2> may be carried out simultaneously. In that case, the material embedded metal 6 and the upper wiring 2, aluminum (AI) , aluminum alloy, copper (C u>, data tungsten (W), tungsten silicon Sai de (WS i), titanium nitride (T i N), alone or laminates of such Chitanshirisai bets (T i S ί), scan Roh Tsu be formed by other method or the CVD method.

In the present invention, the sacrificial layer is not limited to that due to the formation of the above-mentioned amorphous silicon. For example, it may be a sacrificial layer of registry (model AZ 1 3 5 0). Isotropic in registry etching in this case, may be used either anisotropic. When using the isotropic etching, the conditions, for example, a coil about 6 0 0 W, the platen about 1 0 W, about the pressure in the reaction chamber 5. 3 2 P a, the use gas and flow rate 0 2, approximately 0.0 3, liters per minute. In the case of anisotropic etching, the coil about 6 0 0 W, the platen about 1 5 W, a pressure of about 0. 2 7 P a reaction chamber, using gas and flow rate O 2, about 0.0 2 Li Tsu and torque per minute. Besides that, it is possible to suitably use a method which has been conventionally used.

Next, explaining the manufacturing method of the third embodiment of the semiconductor device of the present invention (see FIG. 3). First part of a method of manufacturing the semiconductor device is similar to the step (a) ~ (d) the steps shown in FIG. Second half, (e - 1) process will be described with reference to FIG. 8 step (h) and (i) step.

In FIG. 8, (theta - 1) after removing the mask 2 3 (see FIG. 6), the part 2 4 sacrificial layer is lowered digging, to form a strut 2 8 embed a conductor. Post 2 8 having the conductivity can be formed similar manner Nyori the same material as the upper and lower layer wiring 1, 2. Subsequently, a (h) an upper layer wiring 2. The upper layer wiring 2 can likewise be formed by the same method with the same material as the lower layer wiring 1 described above. (I) also forming a space 5 by etching of the sacrificial layer 2 2. Is the same as FIG.

In the production method in Figure 8, - it can be carried out (theta 1) forming a support post 2 8, at the same time the step of forming the upper wiring 2 (h).

In the manufacturing process in FIG. 8, the upper and lower layer wiring 1, 2 between the electrical process for embedding the metal 6 for connecting (f) and in shown in FIG. 7 (g) is omitted.

Next, a description will be given of a step of forming an element isolation recess 1 0 (see FIGS. 4 and 5) in FIGS. 9 to 1 2. A method of forming an element isolation recess 1 0 is twofold. The first method is a method of simultaneously etching and this when removing the sacrificial layer 2 2. The second method is a method of etching simultaneously with the interlayer insulating film 7. In the first method, for Meniwa that removing the sacrificial layer 2 2, isotropic etching is used, but it is difficult precise control of the depth of the recess, as shown in FIGS. 6 and 7 described above prepared step or, in steps shown in FIGS. 6 and 8, are easily added. In the second method, by the the use of anisotropic etching in forming the through-¾ 8 in the interlayer insulating film 7 Li, it is possible to perform accurate control of the depth of the recess, the final step (i) in the case of removing the sacrificial layer 2 2, not Tsukenake Repa care so that the recess is not eroded. Therefore, as in the fifth embodiment shown in FIG. 5, 耐E Tsuchingu film 1 1 it is provided to protect the inner surface of the recess 1 0 includes the final step (i).

9 and 1 0, the first method described above, i.e., illustrates a manufacturing method of the fourth embodiment shown in FIG.

9, on a silicon substrate 9, the interlayer insulating film 7 is provided. Metal 1 7 is properly embedded in the interlayer insulating film 7 in order to electrically connect the element and the lower wiring 1.(A) forming a lower layer wiring 1 is the same as FIG.

Then, (a - 1) to expose the element isolation recess formed region 1 O a silicon substrate 9 directly under the interlayer insulating film 7, with the exception of the upper portion corresponding 7 a, an interlayer insulating film 7 and the lower wiring 1 covered with a mask 3 0 such as follower Torejisu mask.

Next, - etching the (a 2) an interlayer insulating film 7. Etching, in anisotropic etching, by ICP- RIE, coil about 1 OOOW, bra Ten about 5 0 0 W, a pressure of about 0 in the reaction chamber. 3 3 P a, the gas used in Furuoro carbon gas, the flow rate it can be carried out in a state of approximately 0.0 2 liters per minute.

Next, - removing (a 3) Mask 3 0. Interlayer insulating film 7 through-holes 8 are formed on and you re, the element isolation recess formed region 1 0 a silicon substrate 9 is exposed.

Then, (b) step ~ (h) the step of FIG. 1 0, which is similar to that of FIGS. 6 and 7, the final - in the (i 1) step, isotropic etching is performed, the sacrificial layer 2 2 with the removal of the silicon substrate 9 is lowered dug from the exposed device isolation recesses forming region 1 O a, element separating recess 1 0 Ru is formed.

Figure 1 1 and Figure 1 2, the second method described above, that is, show a manufacturing method of the fifth embodiment shown in FIG. Figure 1 1 (a) step is the same as FIG. 6 and Figure 9.

Next, in FIG. 1 1, the (a - 1 - 1) for forming an element isolation recess 1 0 in the silicon substrate 9, with the exception of the upper portion corresponding 7 a, an interlayer insulating film 7 and the lower wiring 1 covered with a mask 3 0 such as follower Torejisu mask. Next, - to form a (a 2-1) interlayer insulating film 7 and the silicon substrate 9 is etched recess for separation between the elements below it. Etching, 9 - similar to the (a 2) step, an anisotropic etching, so that the depth of the inter-element separating recess 1 0 is a predetermined one, are controlled appropriately.

Next, - to form a (a 2-2) anti-etching film 1 1 on the inner surface of the device isolation recesses 1 0. It is an anti-etching film 1 1 of the material, S i O x N x, and the like S i O x. The anti-etching film 1 1 may be formed by performing oxygen bra Zuma irradiated under appropriate conditions without peeling the register mask 3 0 when Etsu quenching the layers. Between the insulating film 7. When that form the through-holes 8 in the interlayer insulating film 7, since use of anisotropic etching, is easy to control the depth of the device isolation recesses 1 0, to produce accurately an excellent semiconductor device be able to.

Then, 1 2, - removing (a 3- 1) Mask 3 0. Hereinafter, (b) to step ~ (ί) step is similar to step (b) ~ (i) steps shown in FIGS. 6 and 7, in the final step (i), the etching resistant film 1 1 in isotropic etching when removing the sacrificial layer 2 2, are not adversely affected the semiconductor device of the device isolation recesses 1 0 around.

The aforementioned embodiment of the method, but using the low pressure CVD method or ECR-CVD method other CVD methods (thermal CVD method (atmospheric pressure CVD), plasma CVD, Koichi CVD method, ICP (inductively coupled plasma ) - CVD method, single CVD method Recon to, SWP (surface wave plasma) Single CVD method, and other CVD methods, other HDP (high density plasma) effect even with an CVD method) is the same. Moreover, can have use sputtering or plated method instead of the CVD method effect is the same. Furthermore, in also the present embodiment in the etching process, ICP- RIE method is used, but other RIE method (RIE method using a plasma method, which is used in the CVD method described above, DRM- RIE method) using even if the effect is the same.

In the present invention, further, as shown in FIGS. 1-3 and FIGS. 1-4, the space 5 described above, to place the getter material 5 0, by providing the Kyanpi ring layer 5 2 on the uppermost wiring to remove § © Togasu from the space 5, it is possible to increase the degree of vacuum space. 1 3 and 1 4, embodiments but is obtained by placing the gettering material 5 0 in the space 5 of the first embodiment Ru shown in FIG. 1, of course, it is shown in FIGS. 2-5 it can be arranged as well to space 5. Process is the same. Among them, the ones in which a gettering material 5 0 in the space 5 of the embodiment shown in FIG. 4, illustrating the structure thereof and production method in Figure 2 0. 1 3, the gettering material 5 0 is found provided on the interlayer insulating film 7. 1 4, gettering material 5 0 is kicked set on stilts 5 1. Struts 5 1 may be a conductor in the insulating material. Space 5, the semiconductor device key Yabbingu layer is provided when completed, the closed space airtight. Therefore, as in the getter-ring member 5 0, by placing a substance having an action of adsorbing a gas component child, originally or gas present in the space 5, the gas (Au discharged from the material after completion of the semiconductor device Togasu) by adsorbing excluded from the space 5, the degree of vacuum of the space 5 can and Ageruko. By raising the degree of vacuum, the dielectric constant of the gas between the wires low Hesi can result to further reduced inter-wiring capacitance. Further, since it is also possible to eliminate the corrosive gas, it is possible to prolong life of the semiconductor device.

Is a getter-ring material, barium, magnesium, calcium, titanium, tantalum, zirconium, vanadium, and the like acme thorium, in the present invention, and of Chasse of placement in between wires, from the viewpoint of production process, titanium, zirconium, or the like is preferably used Germany thorium. These, upon arrangement, it is preferable that the area of ​​the surface is placed in the most widely made shape. Furthermore, when using titanium, plasma used isotropic etching for removal of the sacrificial layer 2 2 when forming the space 5 is preferably a SF 6 gas.

Kiyabbingu layer 5 2 is an insulating film, the material, in addition dioxide Kei element (S ί Ο 2), fluorine (F) Moshiku the force one carbon (C) containing oxide film (S i OF, S i OC), organic SOG, porous SOG, organic polymer primary, amorphous full O b carbon (a - C: F), such as nitride Kei element (S i N) is preferred.

Next, based on FIG 1 5 1 7, explaining the manufacturing method of the semiconductor device shown in FIG. 1 4 (sixth embodiment).

1 5, the step of (a) forming a lower wiring 2 is similar to FIG. Then, the getter-ring member 5 0, the appropriate position on the interlayer insulating film 7 for placement,. (A - I - 1) the registry film 3 1 a coating 'is cured, (a - 1 - 2) it is patterned by registry exposure, to form the follower Torejisu mask 3 1. Next, - to form a (a [pi) gettering layer 3 2. The formation of this is preferably a sputtering method, for example, carried out in a plasma under argon to a titanium target Bok. By the gettering film 3 2 becomes appropriate thickness, - removing (a ΠΙ) mask 3 1. Hereinafter, 1 6 and 1 7, (b) step ~ (i) steps are the same as shown in FIGS. 6 and 7 (b) step ~ (i) step.

Kiyabbingu layer 5 2, in Figure 1 7: (i) step, is formed as in step (j) after formed getter-ring member 5 0 in the space 5, to cover the upper wiring 2 of the top layer . Kiyabbingu layer 5 2, for example, be formed by forming a S i O 2. This film formation, for example, by low pressure CVD apparatus, a use gas as the S i H 4 0 2 (or N 0 2), 5;. 1 ~ 1 4 of the flow rate of about 0 0 5-0 - 2 liters per minute, about the flow rate of O 2 0. 6 ~ 2 liters and per minute, about 1 3 0 the pressure in the reaction chamber P a, about 3 5 0 ° C or less 1 5 the substrate temperature and 0 ° C or more.

Incidentally, FIG. 1. 5, after the formation of the upper layer wiring 2, although disposed gettering material 5 0 to the same layer, prior to the step (a), disposing the getter-ring material it may be arranged step (I) ~ (ΙΠ) to.

Furthermore, with reference to FIGS. 1 8 and 1 9, illustrating the preparation of a semiconductor device shown in FIG. 1 4 Seventh Embodiment. Struts 5 1 is the same as the process of forming the strut 2 5 which is shown in Figure 6 and Figure 7, steps leading to higher half of the step (a) ~ (h) E is the same as in FIG. 6 and FIG. 7 is there. In FIG 1 8, (h - I - 1) Registry film 3 1 a coated 'is cured, (h - I one 2) it is patterned by registry exposure, to form the follower Torejisu preparative mask 3 1. Next, - it forms a (h [pi) gettering layer 3 2. The formation of the above - is the same as (a [pi) process. By the gettering film 3 2 becomes appropriate thickness, as shown in FIG. 1 9, - removing the mask 3 1 in step (h). Next, the step of removing the sacrificial layer 2 2 is the same as (i) the steps shown in FIG. 7, as shown in FIG. 1 4, gettering material on struts 5 1 provided in the space 5 5 0 is provided. Continued have, as shown in step (j), is Kiyabbingu layer 5 2 so as to cover the upper wiring 2 of the uppermost layer, is formed similarly to the step (j) of FIG 7.

Incidentally, as in the manufacturing method of FIG. 8 and FIG 9, arranging a gettering material 5 0 in position after step (h) of the upper layer wiring 2 is formed, (h - I), (h - [pi) and (h - ΠΙ) but step is provided, this

Gettering material disposed steps (I) ~ (m) are, or may be before or after the formation of the upper layer wiring 2. Thus, after the mask 2 7 metals six switching principal is removed in step (g) shown in FIG. 7, before forming the upper wiring 2, (g - I), (g - Π) and ( g - ΙΠ) may be provided as a step.

Kiya' Bing layer 5 2, as shown in FIG. 4 or 5 can also be formed in a space 5 which is continuous with the element isolation recess 1 0. Also in this case, the step of forming the gettering layer 5 0 (I) ~ (IE), inserted after the step (g) or step (h), and finally with step (j), Kiyabbingu layer 5 2 to form. For example, if the gettering layer 5 0 is formed in the middle, Figure 1 0 (i - 1) step, 2 0 - is as (i 1). And Subsequently, a Kiya' Bing layer 5 2, as shown in (j) of FIG. 2 0, airtight space 5 consecutive inter-element isolation recess 1 0 is formed. Industrial Applicability

As described above, the semiconductor device 'and a manufacturing method thereof according to the present invention, suitable for the miniaturization of integrated circuits, and stabilization of high-speed operation of the integrated circuit, can be realized an extended service life of Hanmichitai device.

Claims

The scope of the claims
1. And have you into a plurality of element semiconductor device provided so as to form two or more layers vertically least the wiring for connecting the element on a silicon substrate provided with,
That coupled to said lower surface of the upper layer wiring by forming a pillar for supporting the upper layer interconnection, and less from the gap between the lower surface of the upper wiring between the lower layer wiring is also allowed form a space for continuous Calls part the semiconductor device according to claim.
2. The struts semiconductor device of claim 1 wherein an insulating material.
3. The strut comprises a first strut for supporting the upper wiring provided on the lower layer wiring, includes a second strut underpin the upper wiring portion on a silicon substrate without the lower wiring, the at least the semiconductor device according the second term metal for conduction is embedded in one of the first strut.
4. The pillar semiconductor device of claim 1 wherein a conductor.
5. The a recess for separating the element to the substrate surface between the elements, the semiconductor device according to any of the previous SL the first term comprising brought continuously space in the recess to the fourth term. .
6. The semiconductor device of the fifth term, wherein the anti-etching film is formed on the inner surface of the separation recesses between the elements.
7. The semiconductor device according to any one of paragraphs 1 through 6 wherein characterized in that a getter-ring material in the space.
8. The upper and lower wiring covering from the top of the uppermost layer wiring, a semiconductor device according to the claim 7 wherein comprising providing a Kiyabbingu layer closing the getter-ring material is provided space airtight.
9. A manufacturing method of a plurality of elements semiconductor device provided so as to form two or more layers vertically least the wiring for connecting the element on a silicon substrate provided with, (a) the a step of forming the lower layer wiring on the interlayer insulating film provided on a silicon substrate,
(B) and as E forming a sacrificial layer so as to cover between and the upper surface of the lower wiring,
Forming a the Photo registry film by (c) follower Torisogu Rafi one method in a region other than the region where posts of the upper layer wiring is formed,
And (d) etching the sacrificial layer of the strut forming region,
Forming a pillar (theta) is embedded by forming an insulating film on the etched region,
(F) shaping the contactor Tohoru opening pattern mask for setting buried metal for conducting the lower layer wiring of the lower one or more layers of the upper interconnection, etching the struts and Roh or sacrificial layer of metal buried region where forming a contactor Tohoru and,
Burying a metal in (g) the etched contactor Tohoru,
(H) forming the upper wiring layer,
(I) the sacrificial layer isotropically same layers of etched and upper and lower wiring, forming a space portion other than the strut between the wires at the top and bottom layers and twisted positional relationship
The method of manufacturing a semiconductor device, which comprises a.
1 0. Step (g) and the (h) the production method of performing step simultaneously the item 9 to serial mounting of the semiconductor device.
1 1. A method of manufacturing a plurality of semiconductor devices element is provided so as to form two or more layers vertically least wiring for connecting the element on a silicon substrate provided,
(A) a step of forming the lower layer wiring in the interlayer insulating film provided on the silicon substrate,
(B) E of forming a sacrificial layer so as to cover between and the upper surface of the lower wiring
Forming a the Photo registry film in a region other than the region where (c) the upper wiring strut is formed by a follower tri Seo Rafi one method,
And (d) etching the sacrificial layer of the strut forming region,
(Theta - 1) forming a conductive pillar is embedded by forming a metal to the etched region,
(H) forming the upper wiring layer,
(I) the sacrificial layer isotropically same layers of etched and upper and lower wiring, forming a space portion other than the strut between the wires at the top and bottom layers and twisted positional relationship
The method of manufacturing a semiconductor device, which comprises a.
. 1 2 wherein (e - 1) step and the (h) The method of manufacturing a semiconductor device of the first 1 wherein performing steps simultaneously.
After about one 3. The (i) E,
(J) a step of forming on the uppermost layer wiring, a Kiya' Bing layer to close airtight the space
The method of manufacturing a semiconductor device according to any comprise that of the paragraph 9 to the first two terms of.
1 4. Between said step (a) the step (b),
(A - 1) follower Torre Soo mask the interlayer insulating film and the lower layer of the through-holes for forming the interlayer insulating film for exposing a region for forming the device isolation recess of the silicon substrate forming a follower Torisogu Rafi one method over the wiring,
(A - 2) the follower Torejisu the covering non region in mask layers an insulation Enmaku is etched to form the through hole, the element isolation recess forming region of the silicon substrate under the interlayer insulating film through the through hole exposing a,
(A - 3) wherein (a - 1) formed in step the Photo Regis mask step of divided the
, Semiconductor equipment manufacturing method according to any one of paragraph 9 to the first three terms are inserted.
Between 1 5. Step (a) and the step (b),
And - (1 one 1 a) forming by the Photo lithographic one method the silicon substrate follower Torejisu for forming an element isolation recess to mask the interlayer insulating film and on said lower wiring,
(A - 2 - 1) the follower Torejisu areas not covered by the mask etch Ngushi, through the upper interlayer insulating film of the element isolation recess formed region, in addition, a silicon substrate a predetermined depth immediately below the drill down, forming a recess for separation between the elements,
And (2 a - - 2) that form a etching resistant film on the inner surface of the separation recesses between the element step,
(A - 3 - 1) wherein (a - 1 - 1) formed in step the Photo Regis removing the Tomah disk
There semiconductor equipment manufacturing method according to any one of paragraph 9 to the first three terms are inserted.
1 6. The method of manufacturing a semiconductor device according to the sacrificial layer is either the said paragraph 9 to the first 5, wherein a silicon layer.
7. The method of manufacturing a semiconductor device according to the sacrificial layer is either the said paragraph 9 to the first 5, wherein a registry layer.
1 8. The (a) prior to step or after,
Forming a (I) getter-ring material forming mask, the step of forming the ([pi) getter-ring material film, and
(M) obtaining a gettering material layer by removing the gettering material forming mask
There semiconductor equipment manufacturing method according to any one of paragraph 9 to the first section 7 is inserted.
1 9. Before or after the step (h),
(I) forming a getter-ring material for forming the mask,
([Pi) step of forming a getter-ring material film, and
(ΠΙ) obtaining a gettering material layer by removing the gettering material forming mask
There semiconductor equipment manufacturing method according to any one of paragraph 9 to the first item 8 has been inserted.
PCT/JP2000/008194 2000-06-02 2000-11-20 Semiconductor device and method of manufacturing the device WO2001095390A1 (en)

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