JP4961148B2 - IC package, electronic control device and interposer board - Google Patents

IC package, electronic control device and interposer board Download PDF

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Publication number
JP4961148B2
JP4961148B2 JP2006049597A JP2006049597A JP4961148B2 JP 4961148 B2 JP4961148 B2 JP 4961148B2 JP 2006049597 A JP2006049597 A JP 2006049597A JP 2006049597 A JP2006049597 A JP 2006049597A JP 4961148 B2 JP4961148 B2 JP 4961148B2
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conductor pattern
terminal
discharge
substrate
ic package
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JP2007227825A (en
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隆芳 本多
淳二 杉浦
和由 網代
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ルネサスエレクトロニクス株式会社
株式会社デンソー
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48228Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad being disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

  The present invention relates to an IC package, an electronic control device, and an interposer substrate, and more particularly to a technique for protecting against discharge breakdown.

  As an example, the electronic control device includes a circuit board, a connector mounted on the circuit board, and an IC package mounted on the circuit board. Sensor signals, switch signals, and the like are sent to the circuit board side through the connector. The signal is sent to the actuator side via the connector after being processed by the IC package and processed by the IC package.

  When a ball grid array (BGA) is used as the IC package, the external terminal arrangement surface of the ball grid array (BGA) has a large number of balls 102 as external terminals formed on the interposer substrate 101 as shown in FIG. Yes.

  As shown in FIG. 14, a ground pattern (GND pattern) that connects the periphery of the ball 102a to the grounding ball 102b in order to prevent breakdown due to discharge from a predetermined pin (ball 102a) to an adjacent functional pin (ball 102c). 110 is enclosed so as not to discharge to surrounding balls (adjacent balls) 102c.

  More specifically, since the terminals (balls) of the ball grid array (BGA) are connected to, for example, a switch touched by a person via a connector, the ball (applying pin) 102a is caused by static electricity generated when the person touches it. As shown in FIG. 15, it is discharged to the adjacent ball 102c, and the IC chip 120 is destroyed through the wiring in the interposer substrate 101. In order to prevent this, the periphery of the ball 102a is surrounded by a ground pattern 110 so as not to discharge to the adjacent ball 102c.

Patent Document 1 discloses a configuration in which the periphery of an NC pin (non-connect pin) is surrounded by a ground wiring provided to be exposed on the surface of a printed circuit board. By discharging electrostatic noise applied to the non-connect pin to the ground wiring, discharge to the adjacent input pin is prevented.
JP 2002-198466 A

  However, in the measures shown in FIGS. 14 and 15, since the ground pattern 110 is covered with the resist 111 (see FIG. 15), the dielectric constant of the resist material is compared with the case where the ground pattern 110 is not covered with the resist. Therefore, there is a problem that the resistance value becomes high and energy discharged from the ball 102a cannot be sufficiently absorbed and it is difficult to obtain a complete countermeasure effect.

  In addition, in FIG. 13, there are balls 102 (lands formed on the interposer substrate 101) that are not electrically connected to the IC chip (non-connect pins). This is the case when the number of pins of the interposer substrate is larger than the number of electrode pads of the IC chip, or when the non-connect pins are intentionally provided when mounted on the system substrate. In the case where such non-connect pins exist, even if the ground pattern 110 is not covered with a resist as in Patent Document 1, the IC chip in the IC package is still electrostatically destroyed. There was a problem. As a result of intensive analysis of the electrostatically damaged IC package, the inventors of the present application were able to independently obtain the following knowledge.

  The IC chip and the land of the interposer substrate are electrically connected via the wiring formed on the interposer substrate. The land corresponding to the input / output portion of the IC chip that is electrostatically damaged and the non-connect pin (land) Are not necessarily adjacent to each other. The input / output portion of the IC chip connected to the land at a position farther away from the non-connect pin has been ESD-destructed. Further analysis by the inventors of the present application reveals that electrostatic breakdown is not the relative position between lands, but the distance between the plating wiring connected to the non-connect pin (land) at the end of the interposer substrate and the plating wiring of other lands. It turned out to depend on. That is, as is known in the art, it has been found that there is a condition that surge discharge is more likely to occur between the plating wirings at the end of the interposer substrate than the surge discharge occurs between lands. This is because, when the plating wiring interval is narrower than the ball interval, discharge occurs in a state where the discharge voltage is lower.

  The present invention has been made paying attention to the above problems, and an object thereof is to provide an IC package, an electronic control device, and an interposer substrate capable of reliably protecting an integrated circuit (IC) from discharge breakdown. It is in.

  According to the first aspect of the present invention, on the terminal ball forming surface of the interposer substrate, the first discharge conductor extends from the land of the terminal ball to which an instantaneous overvoltage may be applied and the tip is exposed on the side surface of the substrate. A pattern is formed, and at least one of the terminal ball formation surface and the other conductor pattern formation surface of the interposer substrate, one end is electrically connected to the land of the terminal ball with low impedance, and the other end is A second discharge conductor pattern exposed on the side surface of the substrate is formed so as to be adjacent to the first discharge conductor pattern on the side surface of the substrate. Between the exposed portion on the substrate side surface in the first discharge conductor pattern and the exposed portion on the substrate side surface in the second discharge conductor pattern The IC package discharge path to lower the terminal balls of impedance is formed is set to its gist.

  According to a second aspect of the present invention, the terminal ball forming surface of the interposer substrate in the IC package extends from the land of the terminal ball to which an instantaneous overvoltage may be applied. And at least one of the terminal ball forming surface of the interposer substrate and the other conductor pattern forming surface, one end is electrically connected to the land of the terminal ball having a low impedance, The second discharge conductor pattern with the other end exposed on the side surface of the substrate is formed so as to be adjacent to the first discharge conductor pattern on the side surface of the substrate, and there is a possibility that the instantaneous overvoltage may be applied. The exposed portion of the first discharge conductor pattern from the ball for the first discharge conductor pattern and the second discharge conductor pattern of the substrate side surface The electronic control unit discharge path impedance of the low terminal balls is formed through between the exposed portion and the gist thereof.

  According to the first and second aspects of the present invention, when an instantaneous overvoltage is applied to the terminal ball, the exposed portion on the side surface of the substrate in the first discharge conductor pattern and the second The discharge conductor pattern is discharged to the terminal ball having a low impedance through the space between the exposed portion on the side surface of the substrate. Therefore, the integrated circuit (IC) can be reliably protected from discharge breakdown.

As described in claims 3 and 4, a plated wire used for supplying molten solder to the land when solder balls are joined to the land may be used as the first discharge conductor pattern.
According to the fifth aspect of the present invention, the discharge lead frame is extended from the portion sealed with the mold resin in the terminal lead frame with low impedance so that the instantaneous overvoltage is applied. The gist of the present invention is an IC package in which a discharge path is formed from a potential terminal lead frame to a terminal lead frame having a low impedance through an exposed portion from the mold resin in the discharge lead frame.

  According to the sixth aspect of the present invention, the discharge lead frame is extended from the portion sealed with the mold resin in the low-impedance terminal lead frame in the IC package so as to be exposed to the instantaneous overvoltage. The gist of the present invention is an electronic control device in which a discharge path is formed from a terminal lead frame that may be applied to the terminal lead frame having a low impedance through an exposed portion from the mold resin in the discharge lead frame. .

  According to the fifth and sixth aspects of the present invention, when an instantaneous overvoltage is applied to the terminal lead frame, the terminal lead frame has a low impedance through the exposed portion from the mold resin in the discharge lead frame. Discharged to the lead frame. Therefore, the integrated circuit (IC) can be reliably protected from discharge breakdown.

  According to the seventh aspect of the present invention, on one surface of the circuit board, the first of the connector pins extending from the land of the connector pin to which an instantaneous overvoltage may be applied is exposed at the side surface of the board. A discharge conductor pattern is formed, and at least one of the one surface of the circuit board and the other conductor pattern formation surface, one end is electrically connected to a land of a connector pin having a low impedance, and the other end Is formed on the side surface of the substrate, and a second discharge conductor pattern is formed on the side surface of the substrate from the connector pin to which the instantaneous overvoltage may be applied. A discharge path to a connector pin with a low impedance is not formed between the exposed portion on the side surface of the substrate in the conductive pattern for discharge. The electronic control unit is set to its gist.

  According to the seventh aspect of the present invention, when an instantaneous overvoltage is applied to the connector pin, the exposed portion on the side surface of the substrate in the first discharge conductor pattern and the second discharge conductor pattern from the connector pin. It discharges to the connector pin with low impedance through the space between the exposed parts on the side of the board. Therefore, the integrated circuit (IC) can be reliably protected from discharge breakdown.

  As described in claims 8, 9, and 10, even if a terminal or connector pin to which an instantaneous overvoltage may be applied is a terminal or connector pin connected to a switch touched by a person, As described in claim 13, even if a terminal or connector pin to which an instantaneous overvoltage may be applied is a terminal or connector pin connected to an ignition device, as described in claim 14, 15, or 16, The terminal or connector pin to which the overvoltage may be applied may be a non-connect terminal or connector pin having no wiring to the IC chip.

  As described in claim 17, in the IC package according to claim 1 or 5, the terminal to which the instantaneous overvoltage may be applied may be a terminal touched by a person or a manufacturing apparatus.

  According to an eighteenth aspect of the present invention, the interposer substrate is electrically connected to a plurality of lands on which terminal balls are mounted, one end of which is not connected to the electrode pad, and the other end is the interposer substrate. A first discharge conductor pattern extending to the end surface of the interposer substrate is formed, and one end of the interposer substrate is connected to a land to which a power supply potential or a ground potential is applied and the other end is an end surface of the interposer substrate. The gist of the present invention is an IC package in which the second discharge conductor pattern extending to the end is formed so as to be adjacent to the first discharge conductor pattern on the substrate end face.

  According to a twenty-third aspect of the present invention, there is provided a plurality of lands on which the terminal balls are mounted, and one end is electrically connected to a land not connected to the electrode pad and the other end extends to the substrate end surface. A discharge conductor pattern, one end of which is connected to a land to which a power supply potential or a ground potential is applied, and the other end extends to the substrate end surface, and is adjacent to the first discharge conductor pattern on the substrate end surface. The gist is an interposer substrate on which a discharge conductor pattern is formed.

  According to the invention described in claims 18 and 23, when an instantaneous overvoltage is applied to the terminal ball for the land that is not connected to the electrode pad, the first discharge conductor pattern from the terminal ball is applied. Through the space between the substrate end surface and the substrate end surface of the second discharge conductor pattern, discharge is performed to a terminal ball for a land to which a power supply potential or a ground potential is applied. Therefore, the integrated circuit (IC) can be reliably protected from discharge breakdown.

  19. The IC package according to claim 18, wherein the first discharge conductor pattern and the second discharge conductor pattern are formed on the same surface of the interposer substrate, as described in claim 19. The second discharge conductor pattern is arranged so as to sandwich the first discharge conductor pattern at an end surface of the interposer substrate, or as described in claim 20, on both the front and back surfaces of the interposer substrate. The first discharge conductor pattern is formed on one surface, the second discharge conductor pattern is formed on the other surface, and the first discharge conductor pattern and the second discharge conductor are formed. The pattern is arranged on the end surface of the interposer substrate so that at least part of it overlaps when viewed from the direction orthogonal to the IC chip mounting surface of the substrate. The interposer substrate has a multilayer wiring structure, and the first discharge conductor pattern is a second discharge formed in an intermediate layer of the interposer substrate. The conductor pattern and the end surface of the interposer substrate may be arranged so that at least a part thereof overlaps when viewed from the direction orthogonal to the IC chip mounting surface of the substrate.

  Also. As described in claim 22, in the IC package according to claim 19, the second discharge conductor pattern may be formed so as to surround the land that is not connected to the electrode pad. .

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a circuit diagram showing an electrical configuration of the electronic control device according to the present embodiment. The electronic control device 10 is an on-vehicle electronic control device and is an engine control electronic control device.

In FIG. 1, the electronic control device 10 includes a microcomputer 11, an A / D converter 12, input circuits 13 and 14, and an output circuit 15. An intake pipe pressure signal, a cooling water temperature signal, an intake air temperature signal, and an O 2 sensor signal are sent to the electronic control device 10 as analog signals, and are sent to the A / D converter 12 via the input circuit 13 in the electronic control device 10. The analog signal is converted into a digital signal by the A / D converter 12 and sent to the microcomputer 11. On the other hand, a starter signal, a neutral signal, an air conditioner switch signal, an electric load signal, and a signal from the ignition switch 21 are sent to the electronic control device 10 as digital signals, and are sent to the microcomputer 11 via the input circuit 14 in the electronic control device 10. It is done. The microcomputer 11 executes various calculations based on each signal.

  Various actuators including an igniter 23 and an injector are connected to the microcomputer 11 via an output circuit 15. An ignition coil 24 is connected to the igniter 23. The microcomputer 11 drives an engine such as an injector and an igniter 23 to operate the engine in an optimum state. Specifically, with respect to the ignition operation, the power switching element of the igniter 23 is turned off to cut off the primary current of the ignition coil 24 and generate a high voltage in the secondary coil to perform the ignition operation with the spark plug.

FIG. 2 is a perspective view of the electronic control device 10. In FIG. 2, the case of the electronic control device is omitted, and the configuration inside the case is shown.
The electronic control device 10 includes a circuit board 30, a connector 40, electronic components 50, 95, and the like. A connector 40 is attached to the circuit board 30. Specifically, the connector pins 41 are soldered in a state of penetrating the circuit board 30. On the circuit board 30, a microcomputer IC package 50, an A / D converter IC package 95, and other electronic components are mounted. Sensors, switches, actuators, and the like are connected to the connector 40 by wires.

  A ball grid array (BGA) excellent in miniaturization is used as the microcomputer IC package 50, and FIG. 3 is a bottom view of the microcomputer IC package 50. FIG. 4 is a partial longitudinal sectional view of an IC package (ball grid array) 50.

  In FIG. 4, a plurality of lands 52 are formed on the lower surface of the interposer substrate 51, and solder balls 53 as terminal balls are joined to the lands 52. The lower surface of the interposer substrate 51 is covered with a resist 54. On the other hand, a wiring 55 is patterned on the upper surface of the interposer substrate 51, and the wiring 55 is electrically connected to the land 52 through a through hole 56. The upper surface of the interposer substrate 51 is covered with a resin film 57, and an IC chip 58 is disposed on the resin film 57. The IC chip 58 has a plurality of electrode pads 58a. The electrode pad 58 a of the IC chip 58 and the wiring 55 are electrically connected by a bonding wire 59. Further, the IC chip 58 and the wire 59 are covered with a resin film 60 on the upper surface of the interposer substrate 51. Thus, the IC chip 58 is mounted on the interposer substrate 51 in the IC package 50.

  In FIG. 3, a plurality of solder balls 53 including at least a grounding solder ball are formed on the terminal ball forming surface (lower surface) of the interposer substrate 51. In FIG. 3, the solder balls 61 at the corners on the lower surface of the rectangular interposer substrate 51 are terminal balls to which an instantaneous overvoltage may be applied. Specifically, for example, a switch that is touched by a person, specifically a terminal ball connected to the ignition switch 21.

  In the present embodiment, measures against discharge destruction are taken for the IGSW solder ball connected to the ignition switch (IGSW) 21 as the terminal solder ball 61 to which this instantaneous overvoltage may be applied. The integrated circuit (IC) is prevented from being damaged by discharge due to static electricity.

This will be described in detail below.
FIG. 5A is a side view of a corner portion of the IC package (ball grid array) 50, FIG. 5B is a bottom view of the interposer substrate 51, and FIG. It is a top view about the interposer board | substrate 51 in the corner | angular part of the (array) 50. FIG.

  As shown in FIG. 5B, a grounding solder ball (GND ball) 62 as a terminal ball having a low impedance is disposed near the IGSW solder ball 61 at a corner portion on the lower surface of the interposer substrate 51. Yes.

  A first discharge conductor pattern 63 is formed on the terminal ball forming surface (lower surface) of the interposer substrate 51. The conductor pattern 63 extends linearly from the land 64 of the IGSW solder ball 61 and is exposed at the side surface of the substrate 51 at one side 51 a of the interposer substrate 51 having a square shape. Here, as the first discharge conductor pattern 63, a plated wire used for supplying molten solder to the land 64 when the solder ball 61 is joined to the land 64 is used. Specifically, molten solder is supplied onto the land 64 through the upper surface of the plated wire, and then the solder ball 61 is placed on the land 64 and pressed and heated to join the solder ball 61 to the land 64.

  A second discharge conductor pattern 65 is formed on the terminal ball forming surface (lower surface) of the interposer substrate 51. The conductor pattern 65 extends from the land 66 of the grounding solder ball 62, branches and extends so as to surround the land 64 and the conductor pattern 63 of the IGSW solder ball 61, and the tip thereof is one side 51 a of the interposer substrate 51. It is exposed on the side of the board. That is, one end is electrically connected to the land 66 of the grounding solder ball 62 and the other end is exposed on the side surface of the substrate. The exposed portion 65a on the substrate side surface in the second discharge conductor pattern 65 and the exposed portion 63a on the substrate side surface in the first discharge conductor pattern 63 are close to each other, and the distance is d1. The second discharge conductor pattern 65 and the first discharge conductor pattern 63 are adjacent to each other at the end (side surface) of the interposer substrate 51.

  As a result, the exposed portion 63a and the second discharge conductor pattern 65 on the side surface of the substrate in the first discharge conductor pattern 63 from the solder ball for IGSW (terminal ball to which an instantaneous overvoltage may be applied) 61 are formed. A discharge path to the grounding solder ball 62 is formed through the space between the exposed portion 65a on the side surface of the substrate. Here, the above-described plated wire is used as the second discharge conductor pattern 65.

  As shown in FIG. 6, the second discharge conductor pattern 67 is formed on the conductor pattern formation surface (upper surface) other than the terminal ball formation surface of the interposer substrate 51. One end of the conductor pattern 67 is electrically connected to the discharge conductor pattern 65 on the lower surface of the substrate through the through hole 68, and thereby one end is electrically connected to the land 66 of the grounding solder ball 62. The other end of the conductor pattern 67 is exposed on the side surface of the substrate at one side 51 a of the interposer substrate 51. The exposed portion 67a on the substrate side surface in the second discharge conductor pattern 67 is located immediately above the exposed portion 63a on the substrate side surface in the first discharge conductor pattern 63 (see FIG. 5A). The distance is d2. The second discharge conductor pattern 67 and the first discharge conductor pattern 63 are adjacent to each other at the end (side surface) of the interposer substrate 51.

  Thus, the exposed portion 63a and the second discharge conductor pattern 67 on the side surface of the substrate in the first discharge conductor pattern 63 from the IGSW solder ball (terminal ball to which an instantaneous overvoltage may be applied) 61 are formed. A discharge path to the grounding solder ball 62 is formed between the exposed portion 67a on the side surface of the substrate. Here, the second discharge conductor pattern 67 is formed (patterned) simultaneously with the formation of the plated wire.

  Then, when static electricity generated when a person touches the ignition switch 21 is applied to the IGSW solder ball 61, the exposed portion 63 a on the side surface of the substrate in the first discharge conductor pattern 63 from the IGSW solder ball 61. The second discharge conductor pattern 65 is discharged to the grounding solder ball 62 through the exposed portion 65a on the substrate side surface or the exposed portion 67a on the substrate side surface in the second discharge conductor pattern 67. That is, in FIG. 5B, the IGSW solder ball 61 is discharged to the ground side through the grounding solder ball 62 without being discharged to the adjacent solder balls 69 and 70 as functional pins. Therefore, the integrated circuit (IC) can be reliably protected from discharge breakdown.

  That is, since the discharge conductor patterns 63, 65, and 67 are not covered with the resin film (resist 54) on the side surface of the interposer substrate, the impedance of the portions of the discharge conductor patterns 63, 65, and 67 on the substrate side surface is low. It is easy to discharge, avoiding discharging to other functional pins (adjacent solder balls), and preventing the IC from being destroyed through the adjacent terminals.

  Here, in FIGS. 5A and 5B, the distance d1 between the exposed portion 63a on the substrate side surface in the first discharge conductor pattern 63 and the exposed portion 65a on the substrate side surface in the second discharge conductor pattern 65. The distance d2 between the exposed portion 63a on the substrate side surface in the first discharge conductor pattern 63 and the exposed portion 67a on the substrate side surface in the second discharge conductor pattern 67 is a distance d3, d4 between adjacent balls. If it is made shorter (d1 <d3, d2 <d3, d1 <d4, d2 <d4), it is easier to discharge.

  Further, as the discharge conductor patterns 63 and 65, plating wires used for supplying molten solder to the lands 64 and 66 when the solder balls 61 and 62 are joined to the lands 64 and 66 are used. By using it, it is possible to easily take measures against static electricity without using special new technology.

  The second discharge conductor pattern (65, 67) has one end electrically connected to the land 66 of the grounding solder ball 62 and the other end exposed on the side surface of the substrate. This is the interposer. Although it provided in the terminal ball formation surface (lower surface) and the opposite surface (upper surface) of the board | substrate 51, you may provide only in any one.

  Further, although a single layer substrate is used as the interposer substrate 51 of the IC package, instead of this, a multilayer substrate may be used as shown in FIG. 7 (in FIG. 7, the insulating layers 75a, 75b, 75c and 75d are laminated). 4 layer substrate).

  In this case, the first discharge conductor pattern 63 extending from the land 64 of the IGSW solder ball 61 and having the tip exposed on the side surface of the substrate 75 is formed on the terminal formation surface of the substrate 75, and other than the terminal formation surface of the substrate 75. A second discharge in which one end is electrically connected to the land 66 of the grounding solder ball 62 and the other end is exposed to the side surface of the conductor pattern forming surface (between the insulating layer 75a and the insulating layer 75b in FIG. 7). The conductive pattern 76 for ground is formed, and is grounded through the exposed portion 63a on the substrate side surface in the first discharge conductor pattern 63 and the exposed portion 76a on the substrate side surface in the second discharge conductor pattern 76 from the solder ball 61 for IGSW. An electrostatic discharge path to the solder ball 62 is formed. In short, the second discharge conductor pattern is electrically connected to the land 66 of the grounding solder ball 62 at one end of at least one of the terminal ball forming surface and the other conductor pattern forming surface of the interposer substrate (51, 75). As long as the other end is exposed to the side surface of the substrate. At this time, the exposed portion 76a on the side surface of the substrate in the second discharge conductor pattern 76 is located immediately above (closest to) the exposed portion 63a on the side surface of the substrate in the first discharge conductor pattern 63. It is good to be.

Further, as an alternative to FIG. 5, as shown in FIG. 8, the first discharge conductor pattern 63 and the second discharge conductor pattern 67 are arranged on the side surface (end face) of the interposer substrate 51 on the IC chip mounting surface of the substrate. As viewed from the direction orthogonal to the direction, they may be arranged so as to partially overlap rather than completely overlap. Alternatively, as shown in FIG. 9, the first discharge conductor pattern 63 and the second discharge conductor pattern 67 have different widths on the side surface (end surface) of the interposer substrate 51, and the IC chip mounting surface of the substrate You may arrange | position so that it may overlap seeing from the direction orthogonal to. The point is that the first discharge conductor pattern 63 and the second discharge conductor pattern 67 overlap at least partially on the side surface (end surface) of the interposer substrate 51 when viewed from the direction orthogonal to the IC chip mounting surface of the substrate. It is good to be arranged in. The same applies to the first discharge conductor pattern 63 and the second discharge conductor pattern 76 when the multilayer substrate shown in FIG. 7 is used, and from the direction orthogonal to the IC chip mounting surface of the substrate at the substrate end surface. It is good to arrange so that at least a part overlaps when seen.
(Second Embodiment)
Next, the second embodiment will be described focusing on the differences from the first embodiment.

  In the first embodiment, a ball grid array is used for the IC package. However, in this embodiment, a QFP (quad flat package) is used, and measures against discharge destruction are taken for this QFP.

10A is a plan view of the QFP 80, FIG. 10B is a longitudinal sectional view taken along line AA of FIG. 10A, and FIG. 10C is a side view of the QFP 80.
An IC chip 81 is bonded on the support plate 82. A heat sink 83 is fixed to the lower surface of the support plate 82. A plurality of terminal lead frames 85 including a ground lead frame 84 as a terminal lead frame with low impedance and the IC chip 81 are electrically connected by bonding wires 86. The IC chip 81 is sealed with a mold resin 87 in a state where one end of each terminal lead frame 85 is exposed.

  A discharge lead frame 88 extends from the portion sealed with the mold resin 87 in the ground lead frame 84 (is formed so as to be branched), and a terminal lead to which an instantaneous overvoltage may be applied. It branches on both sides of an IGSW lead frame 89 as a frame, and the tip is exposed from the mold resin 87. In the discharge lead frame 88, the exposed portion 88a from the mold resin 87 and the IGSW lead frame 89 are close to each other. Further, the front end portion (exposed portion 88 a) of the discharge lead frame 88 is flush with the outer surface of the mold resin 87.

  As a result, a discharge path is formed from the lead frame for IGSW 89 connected to the ignition switch 21 as a switch touched by a person to the ground lead frame 84 through the exposed portion 88a from the mold resin 87 in the discharge lead frame 88.

  When static electricity is applied to the lead frame 89, the lead frame 89 is discharged to the ground lead frame 84 through the exposed portion 88 a from the mold resin 87 in the discharge lead frame 88. That is, the lead frame 89 is discharged to the ground side through the ground lead frame 84 without being discharged to the lead frame 90 which is an adjacent functional pin. Therefore, the integrated circuit (IC) can be reliably protected from discharge breakdown.

Here, in FIG. 10A, the distance d11 between the exposed portion 88a of the discharge lead frame 88 from the mold resin 87 and the IGSW lead frame 89 is made shorter than the distance d12 between the adjacent lead frames. (D11 <d12), it is easier to discharge.
(Third embodiment)
Next, the third embodiment will be described focusing on the differences from the first embodiment.

  In the first and second embodiments, the case where measures against discharge destruction are taken for the IC package has been described. However, in this embodiment, measures against discharge destruction are taken for the circuit board (motherboard) 30 of the electronic control device 10. .

FIG. 11A is a plan view of the circuit board 30, and FIG. 11B is a longitudinal sectional view taken along line AA of FIG. 11A.
In the connector 40, a plurality of connector pins 41 are supported through the connector body 42, and the connector pins 41 include grounding connector pins 43. That is, the connector 40 has a plurality of connector pins 41 including grounding connector pins 43 as connector pins with low impedance.

  As shown in FIG. 11B, the circuit board 30 has a conductor 32 as a wiring patterned on the upper surface of an insulating plate 31. The upper surface of the insulating plate 31 is covered with a resin film 33 and the lower surface of the insulating plate 31 is covered with a resin film 34. The circuit board 30 (insulating plate 31) is soldered with the connector pins 41 of the connector 40 penetrating therethrough. As described with reference to FIGS. 2 and 4, the IC package 50 is mounted on the circuit board 30, and the IC chip 58 is built in the IC package 50.

  12A is a plan view of the circuit board 30 in a state where the connector pins are supported by penetration, and FIG. 12B is a longitudinal sectional view taken along line AA in FIG. 12 (c) is a side view of the circuit board 30.

  In FIG. 12, a connector pin 44 among the connector pins is a connector pin connected to a switch (ignition switch 21) touched by a person. A first discharge conductor pattern 35 is formed on the upper surface of the circuit board 30 (insulating plate material 31). The conductor pattern 35 linearly extends from the land 36 of the IGSW connector pin (connector pin to which an instantaneous overvoltage may be applied) 44, and has a tip on the side surface of the side 30a of the circuit board 30 having a square shape. Exposed.

  A second discharge conductor pattern 37 is formed on the upper surface of the circuit board 30 (insulating plate material 31). The conductor pattern 37 extends from the land 38 of the grounding connector pin 43, and the tip is exposed on the side surface of the circuit board 30 on one side 30 a. That is, one end is electrically connected to the land 38 of the ground connector pin 43 and the other end is exposed on the side surface of the substrate. The exposed portion 37a on the substrate side surface in the second discharge conductor pattern 37 and the exposed portion 35a on the substrate side surface in the first discharge conductor pattern 35 are close to each other, and the distance is d21.

  Thus, the grounding connector pin passes from the IGSW connector pin 44 between the exposed portion 35a on the substrate side surface in the first discharge conductor pattern 35 and the exposed portion 37a on the substrate side surface in the second discharge conductor pattern 37. A discharge path to 43 is formed.

  Then, when static electricity is applied to the IGSW connector pin 44, the exposed portion 35a on the substrate side surface in the first discharge conductor pattern 35 and the substrate side surface in the second discharge conductor pattern 37 are exposed from the connector pin 44. It is discharged to the ground connector pin 43 through the space between the portions 37a. That is, in FIG. 12, the IGSW connector pin 44 is discharged to the ground side through the grounding connector pin 43 without being discharged to the connector pin 45 which is an adjacent functional pin. Therefore, the integrated circuit (IC) can be reliably protected from discharge breakdown.

  Here, in FIG. 12, the distance d21 between the exposed portion 35a on the substrate side surface in the first discharge conductor pattern 35 and the exposed portion 37a on the substrate side surface in the second discharge conductor pattern 37 is an adjacent connector pin ( If the distance d22 between the pins 44 to 45 in FIG. 12 is made shorter (d21 <d22), it is easier to discharge.

  As described with reference to FIG. 7, a multilayer substrate may be used as the circuit board 30. In short, the second discharge conductor pattern 37 is formed on one surface (upper surface in FIG. 12) of the circuit board 30 and It suffices that at least one of the other conductor pattern forming surfaces is electrically connected to the land 38 of the connector pin 43 having a low impedance and the other end is exposed to the side surface of the substrate.

The first to third embodiments may be modified as follows.
In the embodiment, the grounding terminal (ground terminal) is used as the low impedance terminal in the IC package, but a terminal other than the ground terminal such as a power supply terminal may be used. The same applies to the connector pins of the connector, and power supply pins or the like may be used instead of the grounding connector pins.

  Terminals that may be subject to instantaneous overvoltage in IC packages are terminals connected to switches touched by humans. Specifically, they are applied to terminals connected to ignition switches. However, the present invention is not limited to this. You may apply to the terminal connected to another switch. The same applies to the connector pins of the connector, and it may be applied to connector pins connected to switches other than the ignition switch.

  Further, a terminal to which an instantaneous overvoltage may be applied in the IC package may be a terminal connected to an ignition device (igniter 23 in FIG. 1). More specifically, in FIG. 1, it is useful when the surge voltage when the primary current of the ignition coil 24 is interrupted to generate a high voltage in the secondary coil easily enters the signal line between the output circuit 15 and the igniter 23. It becomes. The same applies to the connector pin of the connector, and the connector pin to which an instantaneous overvoltage may be applied may be a connector pin connected to the ignition device (igniter 23).

  Further, a terminal to which an instantaneous overvoltage may be applied in the IC package may be a non-connect terminal (NC terminal) without wiring to the IC chips 58 and 81. Since the NC terminal has no wiring to the IC chip, the impedance becomes high, and when it receives static electricity, it easily discharges to the adjacent terminal. By taking measures against this NC terminal, it is possible to prevent destruction due to static electricity. The same applies to the connector pins of the connector, and the connector pin to which an instantaneous overvoltage may be applied may be a connector pin without wiring to the IC chip 58.

As described above, the terminal to which an instantaneous overvoltage may be applied may be a terminal touched by a person, or may be a terminal touched by a manufacturing apparatus.
A specific configuration for protecting against discharge breakdown in the case of having an NC terminal will be described below.

5, 6, and 7, a ball denoted by reference numeral 61 (land denoted by reference numeral 64) is used as an NC terminal, and a ball denoted by reference numeral 62 (land denoted by reference numeral 66) is used as a ground or power supply terminal.
Therefore, in FIG. 5, the IC package 50 is obtained by mounting an IC chip 58 having a plurality of electrode pads (58a) on an interposer substrate 51. The interposer substrate 51 has terminal balls 61 and 62 mounted thereon. A plurality of lands 64, 66, one end of which is electrically connected to a land 64 not connected to the electrode pad (58 a), and the other end extends to the end surface of the interposer substrate 51, and a first discharge conductor pattern 63. Is formed, and one end of the interposer substrate 51 is connected to a land 66 to which a power supply potential or a ground potential is applied, and the other end extends to the end surface of the interposer substrate 51. , 67 are formed adjacent to the first discharge conductor pattern 63 on the substrate end face. Further, as shown in FIG. 5, the interposer substrate 51 is mounted with an IC chip 58 having a plurality of electrode pads (58a), and includes a plurality of lands 64, 66 on which terminal balls 61, 62 are mounted, and one end. However, a first discharge conductor pattern 63 that is electrically connected to a land 64 that is not connected to the electrode pad (58a) and has the other end extending to the end face of the substrate, one end is supplied with a power supply potential or a ground potential. Second discharge conductor patterns 65 and 67 are formed which are connected to the land 66 and have the other end extending to the substrate end surface and adjacent to the first discharge conductor pattern 63 on the substrate end surface.

  With these configurations, when an instantaneous overvoltage is applied to the terminal ball 61 for the land 64 that is not connected to the electrode pad (58a), the substrate end surface of the first discharge conductor pattern 63 from the terminal ball 61 is applied. And the second discharge conductor patterns 65 and 67 are discharged to the terminal balls 62 for the lands 66 to which the power supply potential or the ground potential is applied. Therefore, the integrated circuit (IC) can be reliably protected from discharge breakdown.

  Here, as shown in FIG. 5, the first discharge conductor pattern 63 and the second discharge conductor pattern 65 are formed on the same surface of the interposer substrate 51, and the second discharge conductor pattern 65 is The first discharge conductor pattern 63 is disposed on the end face of the interposer substrate 51 so as to sandwich the first discharge conductor pattern 63. The second discharge conductor pattern 65 is formed so as to substantially surround the land 64 that is not connected to the electrode pad (58a).

  As shown in FIGS. 5, 8, and 9, the first discharge conductor pattern 63 is formed on one of the front and back surfaces of the interposer substrate 51, and the second discharge conductor pattern 67 is formed on the other surface. In addition, the first discharge conductor pattern 63 and the second discharge conductor pattern 67 are arranged so that at least a part thereof overlaps the end surface of the interposer substrate 51 when viewed from the direction orthogonal to the IC chip mounting surface of the substrate. Has been.

  Further, as shown in FIG. 7, the interposer substrate (75) has a multilayer wiring structure, and the first discharge conductor pattern 63 includes a second discharge conductor pattern 76 formed in the intermediate layer of the interposer substrate. The end face of the interposer substrate (75) is arranged so that at least a part thereof overlaps when viewed from a direction orthogonal to the IC chip mounting surface of the substrate.

FIG. 2 is a circuit diagram showing an electrical configuration of the electronic control device according to the embodiment. The perspective view of an electronic controller. The bottom view of IC package for microcomputers. 1 is a partial longitudinal sectional view of an IC package (ball grid array) in a first embodiment. (A) is a side view in the corner | angular part of IC package (ball grid array), (b) is a bottom view about an interposer board | substrate. The top view about the interposer board | substrate in the corner | angular part of IC package (ball grid array). The longitudinal cross-sectional view in the case of using a multilayer board | substrate as an interposer board | substrate of IC package. (A) is a side view in the corner | angular part of IC package (ball grid array), (b) is a bottom view about an interposer board | substrate. (A) is a side view in the corner | angular part of IC package (ball grid array), (b) is a bottom view about an interposer board | substrate. (A) is a top view of QFP in 2nd Embodiment, (b) is a longitudinal cross-sectional view in the AA line of (a), (c) is a side view of QFP. (A) is a top view of the circuit board in 3rd Embodiment, (b) is a longitudinal cross-sectional view in the AA of (a). (A) is a top view of the circuit board in 3rd Embodiment, (b) is a longitudinal cross-sectional view in the AA line of (a), (c) is a side view of a circuit board. The external terminal arrangement | positioning figure of the ball grid array for demonstrating background art. The external terminal arrangement | positioning figure of the ball grid array for demonstrating background art. The longitudinal cross-sectional view of the ball grid array for demonstrating background art.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 23 ... Igniter, 24 ... Ignition coil, 30 ... Circuit board, 35 ... First discharge conductor pattern, 35a ... Exposed portion, 36 ... Land, 37 ... Second discharge conductor pattern, 37a ... Exposed portion, 38 ... Land, 40 ... Connector, 41 ... Connector pin, 43 ... Grounding connector pin, 44 ... Connector pin for IGSW, 50 ... IC package for microcomputer, 51 ... Interposer substrate, 53 ... Solder ball, 58 ... IC chip, 61 ... IGSW Solder ball 62, grounding solder ball 63 ... first discharge conductor pattern, 63a ... exposed portion, 64 ... land, 65 ... second discharge conductor pattern, 65a ... exposed portion, 66 ... land, 67 ... second discharge conductor pattern, 67a ... exposed portion, 80 ... QFP, 81 ... IC chip, 84 ... ground lead frame, 85 ... terminal Lead frame, 87 ... mold resin, 88 ... discharge lead frame, 88a ... exposed portion, lead frame for 89 ... IGSW.

Claims (23)

  1. An IC chip (58) having a plurality of electrode pads (58a) is mounted on the interposer substrate (51), and at least a low-impedance terminal ball (62) is provided on one surface of the interposer substrate (51). A plurality of terminal balls (53) including an IC package (50) formed through lands (64, 66),
    On the terminal ball forming surface of the interposer substrate (51), a first discharge is extended from the land (64) of the terminal ball (61) to which an instantaneous overvoltage may be applied, and the tip is exposed on the substrate side surface. A conductor pattern (63) is formed, and at least one of the terminal ball formation surface of the interposer substrate (51) and the other conductor pattern formation surface, one end of the land (62) of the terminal ball (62) has a low impedance. 66) and the second discharge conductor pattern (65, 67), the other end of which is exposed on the side surface of the substrate, is adjacent to the first discharge conductor pattern (63) on the side surface of the substrate. To the first discharge conductor pattern (63) from the terminal ball (61) to which the instantaneous overvoltage may be applied. The discharge path to the terminal ball (62) having a low impedance through the exposed portion (63a) on the surface and the exposed portion (65a, 67a) on the side surface of the substrate in the second discharge conductor pattern (65, 67) An IC package characterized by being formed.
  2. A circuit board (30);
    A connector (40) mounted on the circuit board (30);
    An IC chip (58) having a plurality of electrode pads (58a) is mounted on the interposer substrate (51), and at least a low-impedance terminal ball (62) is provided on one surface of the interposer substrate (51). A plurality of terminal balls (53) including a land (64, 66) and an IC package (50) mounted on the circuit board (30);
    An electronic control device comprising:
    In the terminal ball forming surface of the interposer substrate (51) in the IC package (50), the tip extends from the land (64) of the terminal ball (61) to which an instantaneous overvoltage may be applied, and the tip is on the substrate side surface. An exposed first discharge conductor pattern (63) is formed, and at least one of the terminal ball forming surface and the other conductor pattern forming surface of the interposer substrate (51) has one end having a low impedance. The second discharge conductor pattern (65, 67), which is electrically connected to the land (66) of the ball (62) and the other end is exposed on the side surface of the substrate, is formed on the side surface of the substrate. (63) is formed adjacent to the terminal ball (61) to which the instantaneous overvoltage may be applied. A terminal ball having a low impedance passing through between the exposed portion (63a) on the substrate side surface in the lead (63) and the exposed portion (65a, 67a) on the substrate side surface in the second discharge conductor pattern (65, 67). An electronic control device characterized in that a discharge path to (62) is formed.
  3. The first discharge conductor pattern (63) is a plating wire used for supplying molten solder to the land (64) when the solder ball (61) is joined to the land (64). The IC package according to claim 1.
  4. The first discharge conductor pattern (63) is a plating wire used for supplying molten solder to the land (64) when the solder ball (61) is joined to the land (64). The electronic control device according to claim 2.
  5. An IC package in which an IC chip (81) is sealed with a mold resin (87) so that one end portions of a plurality of terminal lead frames (85) including a terminal lead frame (84) with low impedance are exposed. 80)
    The discharge lead frame (88) is extended from the portion sealed with the mold resin (87) in the terminal lead frame (84) with low impedance so as to be exposed from the mold resin (87), and an instantaneous overvoltage is generated. Discharge from the terminal lead frame (89) that may be applied to the terminal lead frame (84) having low impedance through the exposed portion (88a) from the mold resin (87) in the discharge lead frame (88). An IC package characterized in that a path is formed.
  6. A circuit board (30);
    A connector (40) mounted on the circuit board (30);
    The IC chip (81) is sealed with a mold resin (87) in a state in which one end portions of a plurality of terminal lead frames (85) including a terminal lead frame (84) with low impedance are exposed, An IC package (80) mounted on a circuit board (30);
    An electronic control device comprising:
    The lead frame (88) for discharge is extended from the portion sealed with the mold resin (87) in the terminal lead frame (84) with low impedance in the IC package (80) so as to be exposed from the mold resin (87). The terminal lead having a low impedance through the exposed portion (88a) from the mold resin (87) in the discharge lead frame (88) from the terminal lead frame (89) to which an instantaneous overvoltage may be applied An electronic control device characterized in that a discharge path to the frame (84) is formed.
  7. A circuit board (30);
    A plurality of connector pins (41) including a connector pin (43) having low impedance, and a connector (40) mounted on the circuit board (30);
    An IC package (50) having a built-in IC chip (58) and mounted on the circuit board (30);
    An electronic control device comprising:
    One surface of the circuit board (30) extends from the land (36) of the connector pin (44) to which an instantaneous overvoltage of the connector pins (41) may be applied. An exposed first discharge conductor pattern (35) is formed, and at least one of the one surface of the circuit board (30) and the other conductor pattern formation surface, one end is a connector pin having a low impedance ( 43) a connector that is electrically connected to the land (38) and has the other end exposed on the side surface of the substrate and is exposed to the instantaneous overvoltage. From the pin (44) to the exposed portion (35a) on the side surface of the substrate in the first discharge conductor pattern (35) and in the second discharge conductor pattern (37) An electronic control unit, characterized in that the discharge path of the impedance of the low connector pin (43) through between the exposed portion of a plate side (37a) is formed.
  8. The IC package according to claim 1, wherein the terminal to which the instantaneous overvoltage may be applied is a terminal connected to a switch touched by a person.
  9. The electronic control device according to claim 2, wherein the terminal to which the instantaneous overvoltage may be applied is a terminal connected to a switch touched by a person.
  10. 8. The electronic control device according to claim 7, wherein the connector pin (44) to which the instantaneous overvoltage may be applied is a connector pin connected to a switch touched by a person.
  11. The IC package according to claim 1 or 5, wherein the terminal to which the instantaneous overvoltage may be applied is a terminal connected to an ignition device (23).
  12. The electronic control device according to claim 2 or 6, wherein the terminal to which the instantaneous overvoltage may be applied is a terminal connected to an ignition device (23).
  13. The electronic control device according to claim 7, wherein the connector pin (44) to which the instantaneous overvoltage may be applied is a connector pin connected to an ignition device (23).
  14. 6. The IC package according to claim 1, wherein the terminal to which the instantaneous overvoltage may be applied is a non-connect terminal having no wiring to the IC chip (58, 81).
  15. The electronic control unit according to claim 2 or 6, wherein the terminal to which the instantaneous overvoltage may be applied is a non-connect terminal having no wiring to the IC chip (58, 81).
  16. The electronic control device according to claim 7, wherein the connector pin (44) to which the instantaneous overvoltage may be applied is a connector pin without wiring to the IC chip (58).
  17. The IC package according to claim 1, wherein the terminal to which the instantaneous overvoltage may be applied is a terminal touched by a person or a manufacturing apparatus.
  18. An IC package (50) in which an IC chip (58) having a plurality of electrode pads (58a) is mounted on an interposer substrate (51),
    The interposer substrate (51) is electrically connected to a plurality of lands (64, 66) on which the terminal balls (61, 62) are mounted and one end of which is not connected to the electrode pad (58a). And a first discharge conductor pattern (63) having the other end extending to the end face of the interposer substrate (51) is formed. The interposer substrate (51) further has one end connected to a power source. A second discharge conductor pattern (65, 67) is connected to the land (66) to which a potential or a ground potential is applied and the other end extends to the end face of the interposer substrate (51). An IC package formed so as to be adjacent to the discharge conductor pattern (63).
  19.   The first discharge conductor pattern (63) and the second discharge conductor pattern (65) are formed on the same surface of the interposer substrate (51), and the second discharge conductor pattern (65). 19. The IC package according to claim 18, wherein the IC package is disposed so as to sandwich the first discharge conductor pattern (63) at an end surface of the interposer substrate (51).
  20.   The first discharge conductor pattern (63) is formed on one of the front and back surfaces of the interposer substrate (51), and the second discharge conductor pattern (67) is formed on the other surface. The first discharge conductor pattern (63) and the second discharge conductor pattern (67) are at least a part of the end surface of the interposer substrate (51) when viewed from the direction orthogonal to the IC chip mounting surface of the substrate. The IC package according to claim 18, wherein the IC packages are arranged so as to overlap each other.
  21.   The interposer substrate has a multilayer wiring structure, and the first discharge conductor pattern (63) is formed on the end surface of the interposer substrate with the second discharge conductor pattern (76) formed in the intermediate layer of the interposer substrate. 19. The IC package according to claim 18, wherein the IC package is disposed so that at least a part thereof overlaps when viewed from a direction orthogonal to the IC chip mounting surface of the substrate.
  22.   20. The IC package according to claim 19, wherein the second discharge conductor pattern (65) is formed so as to surround a land (64) not connected to the electrode pad (58a).
  23. An interposer substrate (51) on which an IC chip (58) having a plurality of electrode pads (58a) is mounted,
    A plurality of lands (64, 66) on which terminal balls (61, 62) are mounted, one end is electrically connected to a land (64) not connected to the electrode pad (58a), and the other end is a substrate. A first discharge conductor pattern (63) extending to the end face, one end is connected to a land (66) to which a power supply potential or a ground potential is applied, and the other end extends to the board end face. An interposer substrate comprising a second discharge conductor pattern (65, 67) adjacent to the first discharge conductor pattern (63).
JP2006049597A 2006-02-27 2006-02-27 IC package, electronic control device and interposer board Active JP4961148B2 (en)

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