JP2008311379A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2008311379A
JP2008311379A JP2007156969A JP2007156969A JP2008311379A JP 2008311379 A JP2008311379 A JP 2008311379A JP 2007156969 A JP2007156969 A JP 2007156969A JP 2007156969 A JP2007156969 A JP 2007156969A JP 2008311379 A JP2008311379 A JP 2008311379A
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Prior art keywords
pad
bonding wire
semiconductor element
signal
gnd
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JP2007156969A
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Japanese (ja)
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Masanori Kikuchi
正則 菊池
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Canon Inc
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Canon Inc
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Priority to JP2007156969A priority Critical patent/JP2008311379A/en
Publication of JP2008311379A publication Critical patent/JP2008311379A/en
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To secure a return path of a power source and GND for signals by reducing a power source-GND noise causing malfunction. <P>SOLUTION: A semiconductor element 104 is mounted on a package 100, which is electrically connected to the semiconductor element 104 by bonding wires 101 to 103. The semiconductor element 104 has a GND pad 202 and a power source pad 203 disposed inside and outside a signal pad 201, and the package 100 has a GND pad 320 and a power source pad 303 disposed inside and outside a signal pad 301. The signal bonding wire 101 is sandwiched between the power source bonding wire 103 and GND bonding wire 102 from above and below to constitute a shield and the return path for the power source-GND noise. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

本発明は、ワイヤボンディング技術を用いて半導体素子をパッケージに接続した半導体装置に関するものである。   The present invention relates to a semiconductor device in which a semiconductor element is connected to a package using wire bonding technology.

半導体をパッケージに接続する技術として、ワイヤボンディング技術がある。ワイヤボンディング技術は、フリップチップ等他の接続技術と比較して低コストで実現できるため、広く使用されている。   There is a wire bonding technique as a technique for connecting a semiconductor to a package. The wire bonding technique is widely used because it can be realized at a lower cost than other connection techniques such as flip chip.

近年の半導体素子の高速化、高集積化に伴い、低電圧で多数の信号が動作するようになってきている。そのため、従来よりもノイズに対する耐性が小さく、わずかなノイズによっても誤動作を起こす危険性がある。   With the recent increase in speed and integration of semiconductor devices, a large number of signals are operating at a low voltage. For this reason, the tolerance to noise is smaller than in the prior art, and there is a risk of malfunction caused by a slight amount of noise.

半導体素子の誤動作の原因となるノイズの1つに、放射ノイズがある。放射ノイズは、半導体チップ及びワイヤボンディングも含めた構造がアンテナとなり、半導体チップ自体から電磁波が放射され、他素子の誤動作の原因となる現象や、外来ノイズを受けて半導体素子自身が誤動作を起こす現象をさす。信号用ボンディングワイヤはそれ自身が基準となる電源・ＧＮＤから電気的に距離があるため、放射ノイズの影響を受けやすい。   Radiation noise is one of the causes of malfunction of semiconductor elements. Radiation noise is a phenomenon in which the structure including the semiconductor chip and wire bonding serves as an antenna, and electromagnetic waves are radiated from the semiconductor chip itself, causing malfunctions of other elements, and phenomena that cause malfunction of the semiconductor elements due to external noise. Point. Since the signal bonding wire itself is electrically distant from the reference power supply / GND, it is easily affected by radiation noise.

また、半導体チップの電源・ＧＮＤのワイヤボンディング接続が弱いと電源・ＧＮＤノイズが大きくなり、誤動作の原因となるため、電源・ＧＮＤノイズに対する対策が重要になっている。   In addition, if the wire bonding connection of the power supply / GND of the semiconductor chip is weak, the power supply / GND noise increases and causes malfunctions. Therefore, countermeasures against the power supply / GND noise are important.

さらに、誤動作を起こさないためには、信号の安定化が必要であるが、ワイヤボンディングはパッケージやプリント配線板上とは異なり、基準となる電源・ＧＮＤのリターンパスを十分に考慮し難いため、信号が高速となった場合は問題となりやすい。   Furthermore, in order not to cause malfunction, signal stabilization is necessary, but wire bonding is different from the package and printed wiring board, and it is difficult to fully consider the reference power supply / GND return path. It is likely to be a problem when the signal becomes high speed.

外来ノイズの影響を回避するための手法としては、図１６に示すように、パッケージ５００に接合された半導体素子５０４を絶縁材５０６で被覆し、その上を導電体５０５により覆う構成が提案されている（特許文献１参照）。   As a technique for avoiding the influence of external noise, as shown in FIG. 16, a configuration in which a semiconductor element 504 bonded to a package 500 is covered with an insulating material 506 and covered with a conductor 505 is proposed. (See Patent Document 1).

また、図１７に示すようなボンディングワイヤ５０１を使用して半導体素子５０４のシールドを行う方法も提案されている（特許文献２参照）。   In addition, a method of shielding the semiconductor element 504 using a bonding wire 501 as shown in FIG. 17 has been proposed (see Patent Document 2).

電源・ＧＮＤノイズを回避するためには、図１８に示すように半導体素子５０４の電源・ＧＮＤ用パッド６０４を信号用パッド６０１の配列の外側に延長し、ボンディングワイヤ５１４を複数用いて電源・ＧＮＤのインダクタンスを下げる方法がある。   In order to avoid power supply / GND noise, as shown in FIG. 18, the power supply / GND pad 604 of the semiconductor element 504 is extended outside the array of signal pads 601 and a plurality of bonding wires 514 are used to supply power / GND. There is a way to lower the inductance.

また、図１９に示すように、信号用ボンディングワイヤ５０１の下方に電源及びＧＮＤ用ボンディングワイヤ５０２、５０３を多数接続することができるように、帯状の導体６０２、６０３、７０２、７０３を配置した構成も提案されている（特許文献３参照）。   Further, as shown in FIG. 19, a configuration in which strip-shaped conductors 602, 603, 702, 703 are arranged so that a large number of power source and GND bonding wires 502, 503 can be connected below the signal bonding wires 501. Has also been proposed (see Patent Document 3).

さらに、図２０に示すように、半導体素子５０４の電源・ＧＮＤ用パッド６０４を大面積として、電源・ＧＮＤ用ボンディングワイヤ径を太くすることで、電源・ＧＮＤのインダクタンスを下げる方法も提案されている（特許文献４参照）。   Further, as shown in FIG. 20, there is also proposed a method of reducing the inductance of the power supply / GND by increasing the power supply / GND bonding wire diameter by making the power supply / GND pad 604 of the semiconductor element 504 large in area. (See Patent Document 4).

特開平６−２６８１００号公報JP-A-6-268100 特許３７４５１５６号公報Japanese Patent No. 3745156 特開２００１−２４４２９３号公報JP 2001-244293 A 特開２００５−１９１４４７号公報JP 2005-191447 A

しかしながら、上記従来の手法では、以下のような問題点があった。   However, the above conventional method has the following problems.

特許文献１に示されたように、半導体素子を絶縁体で被覆したのち、導電体により覆う方法では、プロセスが増えるためにコストが高くなる。また、特許文献２に示すように、ワイヤボンディングを使用して半導体素子のシールドを行う方法は、外来ノイズに対しては安価な対策となりえるが、電源・ＧＮＤノイズに対する効果がない。   As disclosed in Patent Document 1, a method of covering a semiconductor element with an insulator and then covering the semiconductor element with an electric conductor increases the cost because of an increase in processes. Moreover, as shown in Patent Document 2, a method of shielding a semiconductor element using wire bonding can be an inexpensive measure against external noise, but has no effect on power supply / GND noise.

電源・ＧＮＤ用パッドを外側に延長し、ワイヤボンディングを複数接続することで、電源・ＧＮＤのインダクタンスを下げる方法は、信号用ボンディングワイヤと半導体素子に対する放射ノイズ耐性が充分ではない。また、特許文献４に示すような、電源・ＧＮＤ用ボンディングワイヤを多数接続することができる形態や、特許文献５のように、電源・ＧＮＤ用ボンディングワイヤ径を太くして、電源・ＧＮＤのインダクタンスを下げる方法も同様である。   The method of reducing the inductance of the power supply / GND by extending the power supply / GND pad to the outside and connecting a plurality of wire bondings does not have sufficient radiation noise resistance to the signal bonding wire and the semiconductor element. Further, as shown in Patent Document 4, a large number of power supply / GND bonding wires can be connected, and as shown in Patent Document 5, the power supply / GND bonding wire diameter is increased to increase the inductance of the power supply / GND. The method of lowering is the same.

さらに、上記いずれの方法も信号用ワイヤボンディングに対して電源及びＧＮＤ双方のリターンパスを考慮するものではない。   Further, none of the above methods considers both the power source and GND return paths for signal wire bonding.

本発明は、半導体素子の誤動作の原因となる電源・ＧＮＤノイズが少なくて、しかも信号に対して電源・ＧＮＤ双方のリターンパスを考慮できる半導体装置を提供することを目的とするものである。   SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that has less power supply / GND noise causing a malfunction of a semiconductor element and can take into account both the power supply / GND return paths for a signal.

上記目的を達成するため、本発明の半導体装置は、パッケージ上に半導体素子が実装され、ワイヤボンディングによって前記パッケージと前記半導体素子とを接続する半導体装置において、前記半導体素子の上面においては、信号用パッドの内側に基準電位用パッドが配置され、前記パッケージの上面においては、信号用パッドの外側に基準電位用パッドが配置され、前記半導体素子の前記信号用パッドと前記パッケージの前記信号用パッドとを接続する信号用ボンディングワイヤの上に、前記半導体素子の前記基準電位用パッドと前記パッケージの前記基準電位用パッドとを接続する基準電位用ボンディングワイヤが配置されることを特徴とする。   In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device in which a semiconductor element is mounted on a package and the package and the semiconductor element are connected by wire bonding. A reference potential pad is disposed inside the pad, and on the upper surface of the package, a reference potential pad is disposed outside the signal pad. The signal pad of the semiconductor element and the signal pad of the package A reference potential bonding wire for connecting the reference potential pad of the semiconductor element and the reference potential pad of the package is disposed on the signal bonding wire for connecting.

上部に配置された基準電位用ボンディングワイヤによって、信号用ボンディングワイヤをシールドすることができ、リターンパスも確保できる。   The signal bonding wire can be shielded by the reference potential bonding wire arranged at the upper portion, and a return path can be secured.

加えて、信号用ボンディングワイヤの下にも基準電位用ボンディングワイヤを配置することで、信号用ボンディングワイヤを上下からシールドすることができる。   In addition, by arranging the reference potential bonding wire under the signal bonding wire, the signal bonding wire can be shielded from above and below.

本発明を実施するための最良の形態を図面に基づいて説明する。   The best mode for carrying out the present invention will be described with reference to the drawings.

図1は一実施形態による半導体装置を示す模式断面図である。この装置は、パッケージ１００と、信号用ボンディングワイヤ１０１、ＧＮＤ用ボンディングワイヤ１０２及び電源用ボンディングワイヤ１０３によってパッケージ１００に接続された半導体素子１０４と、を有する。ＧＮＤ用ボンディングワイヤ１０２と電源用ボンディングワイヤ１０３は、信号用ボンディングワイヤ１０１を上下から挟むように配置される。そして、ＧＮＤ用ボンディングワイヤ１０２と電源用ボンディングワイヤ１０３は、それぞれ信号用ボンディングワイヤ１０１に対してリターンパスとして働く。   FIG. 1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. This apparatus includes a package 100 and a semiconductor element 104 connected to the package 100 by a signal bonding wire 101, a GND bonding wire 102, and a power supply bonding wire 103. The GND bonding wire 102 and the power supply bonding wire 103 are arranged so as to sandwich the signal bonding wire 101 from above and below. The GND bonding wire 102 and the power supply bonding wire 103 each serve as a return path for the signal bonding wire 101.

半導体素子１０４の上面にはシールド導体面１０５が形成されており、電源用ボンディングワイヤ１０３と接続され、半導体素子１０４を覆うシールド構造を形成している。さらに、半導体素子１０４とボンディングワイヤ１０１〜１０３はモールド樹脂１０６で覆われている。   A shield conductor surface 105 is formed on the upper surface of the semiconductor element 104 and is connected to the power bonding wire 103 to form a shield structure that covers the semiconductor element 104. Further, the semiconductor element 104 and the bonding wires 101 to 103 are covered with a mold resin 106.

このように、半導体素子上にはシールド導体面１０５が形成され、半導体素子１０４の信号用パッド２０１の外側と内側にはＧＮＤ用パッド２０２と電源用パッド２０３が形成され、電源用パッド２０３は導体面１０５と導通している。パッケージ上の信号用パッド３０１の内側と外側には、それぞれＧＮＤ用パッド３０２と電源用パッド３０３が配置される。   Thus, the shield conductor surface 105 is formed on the semiconductor element, the GND pad 202 and the power supply pad 203 are formed on the outside and inside of the signal pad 201 of the semiconductor element 104, and the power supply pad 203 is a conductor. Conductive with the surface 105. A GND pad 302 and a power supply pad 303 are disposed inside and outside the signal pad 301 on the package, respectively.

これにより、信号用ボンディングワイヤ１０１の上下に、ＧＮＤ用ボンディングワイヤ１０２と電源用ボンディングワイヤ１０３を配置することが可能となり、信号用ボンディングワイヤ１０１に対する上下双方のリターンパスと、上下からのシールドを実現する。   As a result, the GND bonding wire 102 and the power supply bonding wire 103 can be arranged above and below the signal bonding wire 101, and both the upper and lower return paths to the signal bonding wire 101 and the shield from above and below are realized. To do.

なお、電源及びＧＮＤ用パッドの形状は上記の形状に限定されるもではなく、パッド同士が接続されている帯状でも構わない。   Note that the shapes of the power supply and the GND pad are not limited to the above-described shapes, and may be a band shape in which the pads are connected to each other.

図２及び図３は、実施例１による半導体装置の構成を示す。樹脂モールドは省略して示されている。   2 and 3 show the configuration of the semiconductor device according to the first embodiment. The resin mold is not shown.

図２の（ａ）、（ｂ）にそれぞれ平面図と断面図で示すように、半導体素子１０４においては、信号用パッド２０１の内側に電源又はＧＮＤ用パッド２０４が配置される。パッケージ１００においては、信号用パッド３０１の外側に電源又はＧＮＤ用パッド３０４が配置される。   As shown in a plan view and a cross-sectional view in FIGS. 2A and 2B, in the semiconductor element 104, a power supply or GND pad 204 is disposed inside the signal pad 201. In the package 100, a power supply or GND pad 304 is disposed outside the signal pad 301.

図３は、図２に信号用ボンディングワイヤ１０１と、電源又はＧＮＤ用ボンディングワイヤ１１４を加えた構成を示す。信号用ボンディングワイヤ１０１の上部には電源又はＧＮＤ用ボンディングワイヤ１１４が配置され、信号用ボンディングワイヤ１０１のリターンパスとなり、かつ、上方からのシールド構造を形成している。   FIG. 3 shows a configuration in which a signal bonding wire 101 and a power supply or GND bonding wire 114 are added to FIG. A power supply or GND bonding wire 114 is disposed above the signal bonding wire 101 to form a return path for the signal bonding wire 101 and to form a shield structure from above.

このように、パッケージ上に半導体素子１０４が実装され、ワイヤボンディングによってパッケージ１００と半導体素子１０４とを接続する。半導体素子１０４の上面においては、信号用パッド２０１の内側に基準電位用パッドである電源又はＧＮＤ用パッド２０４が配置される。パッケージ１００の上面においては、信号用パッド３０１の外側に基準電位用パッドである電源又はＧＮＤ用パッド３０４が配置される。そして、半導体素子１０４とパッケージ１００とを接続する信号用ボンディングワイヤ１０１の上に、基準電位用ボンディングワイヤである電源又はＧＮＤ用ボンディングワイヤ１１４が配置される。   Thus, the semiconductor element 104 is mounted on the package, and the package 100 and the semiconductor element 104 are connected by wire bonding. On the upper surface of the semiconductor element 104, a power supply or GND pad 204 that is a reference potential pad is disposed inside the signal pad 201. On the upper surface of the package 100, a power supply or GND pad 304 that is a reference potential pad is disposed outside the signal pad 301. A power supply or GND bonding wire 114 as a reference potential bonding wire is disposed on the signal bonding wire 101 that connects the semiconductor element 104 and the package 100.

図４及び図５は、実施例２による半導体装置の構成を示す。樹脂モールドは省略して示されている。   4 and 5 show the configuration of the semiconductor device according to the second embodiment. The resin mold is not shown.

図４の（ａ）、（ｂ）にそれぞれ平面図と断面図で示すように、半導体素子１０４においては、信号用パッド２０１の外側と内側にＧＮＤ用パッド２０２と電源用パッド２０３が配置される。パッケージ１００においては、信号用パッド３０１の内側と外側にＧＮＤ用パッド３０２と電源用パッド３０３が配置される。   As shown in a plan view and a cross-sectional view in FIGS. 4A and 4B, in the semiconductor element 104, a GND pad 202 and a power supply pad 203 are disposed outside and inside the signal pad 201. . In the package 100, a GND pad 302 and a power supply pad 303 are arranged inside and outside the signal pad 301.

図５は、図４に信号用ボンディングワイヤ１０１と、ＧＮＤ用ボンディングワイヤ１０２及び電源用ボンディングワイヤ１０３を加えた構成を示す。信号用ボンディングワイヤ１０１を挟むように、ＧＮＤ用ボンディングワイヤ１０２と電源用ボンディングワイヤ１０３が配置され、信号用ボンディングワイヤ１０１のリターンパスとなり、かつ、上下からのシールド構造を形成している。   FIG. 5 shows a configuration in which a signal bonding wire 101, a GND bonding wire 102, and a power supply bonding wire 103 are added to FIG. A GND bonding wire 102 and a power supply bonding wire 103 are arranged so as to sandwich the signal bonding wire 101, which serves as a return path for the signal bonding wire 101 and forms a shield structure from above and below.

このように、半導体素子１０４の上面においては、信号用パッド２０１の内側と外側に基準電位用パッドである電源用パッド２０３とＧＮＤ用パッド２０２が配置される。パッケージ１００の上面においては、信号用パッド３０１の外側と内側に基準電位用パッドである電源用パッド３０３とＧＮＤ用パッド３０２が配置される。そして、半導体素子１０４とパッケージ１００とを接続する信号用ボンディングワイヤ１０１の上と下に、基準電位用ボンディングワイヤである電源用ボンディングワイヤ１０３とＧＮＤ用ボンディングワイヤ１０２がそれぞれ配置される。   Thus, on the upper surface of the semiconductor element 104, the power supply pad 203 and the GND pad 202, which are reference potential pads, are arranged inside and outside the signal pad 201. On the upper surface of the package 100, a power supply pad 303 and a GND pad 302, which are reference potential pads, are arranged outside and inside the signal pad 301. A power supply bonding wire 103 and a GND bonding wire 102, which are reference potential bonding wires, are disposed above and below the signal bonding wire 101 that connects the semiconductor element 104 and the package 100, respectively.

図６及び図７は、実施例３による半導体装置の構成を示す。樹脂モールドは省略して示されている。   6 and 7 show the configuration of the semiconductor device according to the third embodiment. The resin mold is not shown.

図６の（ａ）、（ｂ）にそれぞれ平面図と断面図で示すように、半導体素子１０４においては、信号用パッド２０１の四方に電源又はＧＮＤ用パッド２０４が配置される。パッケージ１００においては、信号用パッド３０１の四方に電源又はＧＮＤ用パッド３０４が配置される。   As shown in a plan view and a cross-sectional view in FIGS. 6A and 6B, in the semiconductor element 104, power supply or GND pads 204 are arranged on four sides of the signal pads 201. In the package 100, power supply or GND pads 304 are arranged on four sides of the signal pads 301.

図７は、図６に信号用ボンディングワイヤ１０１と、電源又はＧＮＤ用ボンディングワイヤ１１４を加えた構成を示す。信号用ボンディングワイヤ１０１を四方から囲むように電源又はＧＮＤ用ボンディングワイヤ１１４が配置され、信号用ボンディングワイヤ１０１のリターンパスとなり、かつ、四方からのシールド構造を形成している。   FIG. 7 shows a configuration in which a signal bonding wire 101 and a power supply or GND bonding wire 114 are added to FIG. A power supply or GND bonding wire 114 is disposed so as to surround the signal bonding wire 101 from four directions, which serves as a return path for the signal bonding wire 101 and forms a shield structure from four directions.

このように、信号用ボンディングワイヤ１０１の上下及び両側に、基準電位用ボンディングワイヤである電源又はＧＮＤ用ボンディングワイヤ１１４が配置される   In this way, the power supply or GND bonding wires 114 that are reference potential bonding wires are arranged on the upper and lower sides and both sides of the signal bonding wire 101.

図８及び図９は、実施例４による半導体装置の構成を示す。樹脂モールドは省略して示されている。   8 and 9 show the configuration of the semiconductor device according to the fourth embodiment. The resin mold is not shown.

図８の（ａ）、（ｂ）にそれぞれ平面図と断面図で示すように、半導体素子１０４においては、信号用パッド２０１の外側と内側にＧＮＤ用パッド２０２と電源用パッド２０３が配置される。パッケージ１００においては、信号用パッド３０１の内側と外側にＧＮＤ用パッド３０２と電源用パッド３０３が配置される。半導体素子１０４の上面には、フィルム状のシールド用の導体面１１５が形成され、半導体素子１０４の電源用パッド２０３は導体面１１５と導通している。   As shown in a plan view and a cross-sectional view in FIGS. 8A and 8B, in the semiconductor element 104, the GND pad 202 and the power supply pad 203 are disposed outside and inside the signal pad 201. . In the package 100, a GND pad 302 and a power supply pad 303 are arranged inside and outside the signal pad 301. A film-like shield conductor surface 115 is formed on the upper surface of the semiconductor element 104, and the power supply pad 203 of the semiconductor element 104 is electrically connected to the conductor surface 115.

図９は、図８に信号用ボンディングワイヤ１０１と、ＧＮＤ用ボンディングワイヤ１０２及び電源用ボンディングワイヤ１０３を加えた構成を示す。信号用ボンディングワイヤ１０１を挟むように、ＧＮＤ用ボンディングワイヤ１０２と電源用ボンディングワイヤ１０３が配置され、信号用ボンディングワイヤ１０１のリターンパスとなり、かつ、上下からのシールド構造を形成している。   FIG. 9 shows a configuration in which a signal bonding wire 101, a GND bonding wire 102, and a power supply bonding wire 103 are added to FIG. A GND bonding wire 102 and a power supply bonding wire 103 are arranged so as to sandwich the signal bonding wire 101, serving as a return path for the signal bonding wire 101 and forming a shield structure from above and below.

図１０及び図１１は、実施例５による半導体装置の構成を示す。樹脂モールドは省略して示されている。   10 and 11 show the configuration of the semiconductor device according to the fifth embodiment. The resin mold is not shown.

図１０の（ａ）、（ｂ）にそれぞれ平面図と断面図で示すように、半導体素子１０４においては、信号用パッド２０１の四方に電源又はＧＮＤ用パッド２０４が配置される。パッケージ１００においては、信号用パッド３０１の四方に電源又はＧＮＤ用パッド３０４が配置される。半導体素子１０４の上面はフィルム状の導体面１１５によって覆われており、半導体素子１０４の電源パッド２０３は導体面１１５と導通している。   As shown in FIGS. 10A and 10B in a plan view and a cross-sectional view, respectively, in the semiconductor element 104, power supply or GND pads 204 are arranged on four sides of the signal pads 201. In the package 100, power supply or GND pads 304 are arranged on four sides of the signal pads 301. The upper surface of the semiconductor element 104 is covered with a film-like conductor surface 115, and the power supply pad 203 of the semiconductor element 104 is electrically connected to the conductor surface 115.

図１１は、図１０に信号用ボンディングワイヤ１０１と、電源又はＧＮＤ用ボンディングワイヤ１１４を加えた構成を示す。信号用ボンディングワイヤ１０１を四方から囲むように電源又はＧＮＤ用ボンディングワイヤ１１４が配置され、信号用ボンディングワイヤ１０１のリターンパスとなり、かつ、四方からのシールド構造を形成している。   FIG. 11 shows a configuration in which a signal bonding wire 101 and a power source or GND bonding wire 114 are added to FIG. A power supply or GND bonding wire 114 is disposed so as to surround the signal bonding wire 101 from four directions, which serves as a return path for the signal bonding wire 101 and forms a shield structure from four directions.

図１２及び図１３は、実施例６による半導体装置の構成を示す。樹脂モールドは省略して示されている。   12 and 13 show the configuration of the semiconductor device according to the sixth embodiment. The resin mold is not shown.

図１２の（ａ）、（ｂ）にそれぞれ平面図と断面図で示すように、半導体素子１０４においては、信号用パッド２０１の外側と内側にＧＮＤ用パッド２０２と電源用パッド２０３が配置される。パッケージ１００においては、信号用パッド３０１の内側と外側にＧＮＤ用パッド３０２と電源用パッド３０３が配置される。半導体素子上にはメッシュ状の導体面１１６が形成され、半導体素子１０４の電源用パッド２０３は導体面１１６と導通している。   As shown in a plan view and a cross-sectional view in FIGS. 12A and 12B, in the semiconductor element 104, a GND pad 202 and a power supply pad 203 are disposed outside and inside the signal pad 201. . In the package 100, a GND pad 302 and a power supply pad 303 are arranged inside and outside the signal pad 301. A mesh-shaped conductor surface 116 is formed on the semiconductor element, and the power supply pad 203 of the semiconductor element 104 is electrically connected to the conductor surface 116.

図１３は、図１２に信号用ボンディングワイヤ１０１と、ＧＮＤ用ボンディングワイヤ１０２及び電源用ボンディングワイヤ１０３を加えた構成を示す。信号用ボンディングワイヤ１０１を挟むように、ＧＮＤ用ボンディングワイヤ１０２と電源用ボンディングワイヤ１０３が配置され、信号用ボンディングワイヤ１０１のリターンパスとなり、かつ、上下からのシールド構造を形成している。   FIG. 13 shows a configuration in which a signal bonding wire 101, a GND bonding wire 102, and a power supply bonding wire 103 are added to FIG. A GND bonding wire 102 and a power supply bonding wire 103 are arranged so as to sandwich the signal bonding wire 101, serving as a return path for the signal bonding wire 101 and forming a shield structure from above and below.

図１４及び図１５は、実施例７による半導体装置の構成を示す。樹脂モールドは省略して示されている。   14 and 15 show the configuration of the semiconductor device according to the seventh embodiment. The resin mold is not shown.

図１４の（ａ）、（ｂ）にそれぞれ平面図と断面図で示すように、半導体素子１０４においては、信号用パッド２０１の四方に電源又はＧＮＤ用パッド２０４が配置される。パッケージ１００においては、信号用パッド３０１の四方に電源又はＧＮＤ用パッド３０４が配置される。半導体素子上にはメッシュ状の導体面１１６が形成され、半導体素子１０４の電源又はＧＮＤ用パッド２０４は導体面１１６と導通している。   As shown in FIGS. 14A and 14B in a plan view and a cross-sectional view, respectively, in the semiconductor element 104, power supply or GND pads 204 are arranged on four sides of the signal pads 201. In the package 100, power supply or GND pads 304 are arranged on four sides of the signal pads 301. A mesh-like conductor surface 116 is formed on the semiconductor element, and the power supply or GND pad 204 of the semiconductor element 104 is electrically connected to the conductor surface 116.

図１５は、図１４に信号用ボンディングワイヤ１０１と、電源又はＧＮＤ用ボンディングワイヤ１１４を加えた構成を示す。信号用ボンディングワイヤ１０１を四方から囲むように電源又はＧＮＤ用ボンディングワイヤ１１４が配置され、信号用ボンディングワイヤ１０１のリターンパスとなり、かつ、四方からのシールド構造を形成している。   FIG. 15 shows a configuration in which a signal bonding wire 101 and a power supply or GND bonding wire 114 are added to FIG. A power supply or GND bonding wire 114 is disposed so as to surround the signal bonding wire 101 from four directions, which serves as a return path for the signal bonding wire 101 and forms a shield structure from four directions.

なお、上記実施例１〜７において、電源とＧＮＤはそれぞれ限定されるものではなく、入れ替えても同電位であってもかまわない。   In the first to seventh embodiments, the power supply and GND are not limited to each other, and may be replaced or have the same potential.

一実施形態による半導体装置を示す模式断面図である。1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment. 実施例１による半導体装置の一部分を、ボンディングワイヤを除いた状態で示す平面図及び断面図である。FIG. 4 is a plan view and a cross-sectional view illustrating a part of the semiconductor device according to the first embodiment with a bonding wire removed. 図２の半導体素子とパッケージを、ボンディングワイヤで接続した状態を示す平面図及び断面図である。FIG. 3 is a plan view and a cross-sectional view illustrating a state in which the semiconductor element and the package of FIG. 2 are connected by bonding wires. 実施例２による半導体装置の一部分を、ボンディングワイヤを除いた状態で示す平面図及び断面図である。It is the top view and sectional drawing which show a part of semiconductor device by Example 2 in the state which excluded the bonding wire. 図４の半導体素子とパッケージを、ボンディングワイヤで接続した状態を示す平面図及び断面図である。It is the top view and sectional drawing which show the state which connected the semiconductor element and package of FIG. 4 with the bonding wire. 実施例３による半導体装置の一部分を、ボンディングワイヤを除いた状態で示す平面図及び断面図である。It is the top view and sectional drawing which show a part of semiconductor device by Example 3 in the state which excluded the bonding wire. 図６の半導体素子とパッケージを、ボンディングワイヤで接続した状態を示す平面図及び断面図である。It is the top view and sectional drawing which show the state which connected the semiconductor element and package of FIG. 6 with the bonding wire. 実施例４による半導体装置の一部分を、ボンディングワイヤを除いた状態で示す平面図及び断面図である。It is the top view and sectional drawing which show a part of semiconductor device by Example 4 in the state except a bonding wire. 図８の半導体素子とパッケージを、ボンディングワイヤで接続した状態を示す平面図及び断面図である。FIG. 9 is a plan view and a cross-sectional view showing a state where the semiconductor element and the package of FIG. 8 are connected by bonding wires. 実施例５による半導体装置の一部分を、ボンディングワイヤを除いた状態で示す平面図及び断面図である。It is the top view and sectional drawing which show a part of semiconductor device by Example 5 in the state which removed the bonding wire. 図１０の半導体素子とパッケージを、ボンディングワイヤで接続した状態を示す平面図及び断面図である。It is the top view and sectional drawing which show the state which connected the semiconductor element and package of FIG. 10 with the bonding wire. 実施例６による半導体装置の一部分を、ボンディングワイヤを除いた状態で示す平面図及び断面図である。FIG. 16 is a plan view and a cross-sectional view showing a part of the semiconductor device according to Example 6 with a bonding wire removed. 図１２の半導体素子とパッケージを、ボンディングワイヤで接続した状態を示す平面図及び断面図である。It is the top view and sectional drawing which show the state which connected the semiconductor element and package of FIG. 12 with the bonding wire. 実施例７による半導体装置の一部分を、ボンディングワイヤを除いた状態で示す平面図及び断面図である。FIG. 16 is a plan view and a cross-sectional view showing a part of the semiconductor device according to Example 7 with a bonding wire removed. 図１４の半導体素子とパッケージを、ボンディングワイヤで接続した状態を示す平面図及び断面図である。It is the top view and sectional drawing which show the state which connected the semiconductor element and package of FIG. 14 with the bonding wire. 一従来例による半導体装置を示す模式断面図である。It is a schematic cross section which shows the semiconductor device by one prior art example. 別の従来例による半導体装置を示す模式断面図である。It is a schematic cross section which shows the semiconductor device by another prior art example. さらに別の従来例による半導体装置を示す図である。It is a figure which shows the semiconductor device by another prior art example. さらに別の従来例による半導体装置を示す図である。It is a figure which shows the semiconductor device by another prior art example. さらに別の従来例による半導体装置を示す図である。It is a figure which shows the semiconductor device by another prior art example.

符号の説明Explanation of symbols

１００ パッケージ
１０１ 信号用ボンディングワイヤ
１０２ ＧＮＤ用ボンディングワイヤ
１０３ 電源用ボンディングワイヤ
１０４ 半導体素子
１０５、１１５、１１６ 導体面
１１４ 電源又はＧＮＤ用ボンディングワイヤ
１１５、１１６ 導体面
２０１、３０１ 信号用パッド
２０２、３０２ ＧＮＤ用パッド
２０３、３０３ 電源用パッド
２０４、３０４ 電源又はＧＮＤ用パッド DESCRIPTION OF SYMBOLS 100 Package 101 Signal bonding wire 102 GND bonding wire 103 Power supply bonding wire 104 Semiconductor element 105, 115, 116 Conductor surface 114 Power supply or GND bonding wire 115, 116 Conductor surface 201, 301 Signal pad 202, 302 For GND Pad 203, 303 Power supply pad 204, 304 Power supply or GND pad

Claims (5)

パッケージ上に半導体素子が実装され、ワイヤボンディングによって前記パッケージと前記半導体素子とを接続する半導体装置において、
前記半導体素子の上面においては、信号用パッドの内側に基準電位用パッドが配置され、
前記パッケージの上面においては、信号用パッドの外側に基準電位用パッドが配置され、
前記半導体素子の前記信号用パッドと前記パッケージの前記信号用パッドとを接続する信号用ボンディングワイヤの上に、前記半導体素子の前記基準電位用パッドと前記パッケージの前記基準電位用パッドとを接続する基準電位用ボンディングワイヤが配置されることを特徴とする半導体装置。 In a semiconductor device in which a semiconductor element is mounted on a package and the package and the semiconductor element are connected by wire bonding,
On the upper surface of the semiconductor element, a reference potential pad is disposed inside the signal pad,
On the upper surface of the package, a reference potential pad is disposed outside the signal pad,
The reference potential pad of the semiconductor element and the reference potential pad of the package are connected to a signal bonding wire that connects the signal pad of the semiconductor element and the signal pad of the package. A semiconductor device comprising a reference potential bonding wire. パッケージ上に半導体素子が実装され、ワイヤボンディングによって前記パッケージと前記半導体素子とを接続する半導体装置において、
前記半導体素子の上面においては、信号用パッドの内側と外側に基準電位用パッドが配置され、
前記パッケージの上面においては、信号用パッドの外側と内側に基準電位用パッドが配置され、
前記半導体素子の前記信号用パッドと前記パッケージの前記信号用パッドとを接続する信号用ボンディングワイヤの上と下に、前記半導体素子の前記基準電位用パッドと前記パッケージの前記基準電位用パッドとを接続する基準電位用ボンディングワイヤがそれぞれ配置されることを特徴とする半導体装置。 In a semiconductor device in which a semiconductor element is mounted on a package and the package and the semiconductor element are connected by wire bonding,
On the upper surface of the semiconductor element, reference potential pads are arranged inside and outside the signal pads,
On the upper surface of the package, reference potential pads are arranged outside and inside the signal pads,
The reference potential pad of the semiconductor element and the reference potential pad of the package are connected above and below a signal bonding wire that connects the signal pad of the semiconductor element and the signal pad of the package. A semiconductor device, wherein bonding wires for reference potential are respectively disposed. パッケージ上に半導体素子が実装され、ワイヤボンディングによって前記パッケージと前記半導体素子とを接続する半導体装置において、
前記半導体素子の上面においては、信号用パッドの四方に基準電位用パッドが配置され、
前記パッケージの上面においては、信号用パッドの四方に基準電位用パッドが配置され、
前記半導体素子の前記信号用パッドと前記パッケージの前記信号用パッドとを接続する信号用ボンディングワイヤの上下及び両側に、前記半導体素子の前記基準電位用パッドと前記パッケージの前記基準電位用パッドとを接続する基準電位用ボンディングワイヤが配置されることを特徴とする半導体装置。 In a semiconductor device in which a semiconductor element is mounted on a package and the package and the semiconductor element are connected by wire bonding,
On the upper surface of the semiconductor element, reference potential pads are arranged on four sides of the signal pads,
On the upper surface of the package, reference potential pads are arranged on four sides of the signal pads,
The reference potential pad of the semiconductor element and the reference potential pad of the package are provided above and below and on both sides of a signal bonding wire that connects the signal pad of the semiconductor element and the signal pad of the package. A semiconductor device comprising a reference potential bonding wire to be connected. 前記半導体素子は、前記上面を覆う導体面を有し、前記導体面は、前記基準電位用パッドに接続されていることを特徴とする請求項１ないし３いずれか１項記載の半導体装置。   4. The semiconductor device according to claim 1, wherein the semiconductor element has a conductor surface that covers the upper surface, and the conductor surface is connected to the reference potential pad. 5. 前記半導体素子の前記導体面はメッシュ状であることを特徴とする請求項４記載の半導体装置。   The semiconductor device according to claim 4, wherein the conductor surface of the semiconductor element has a mesh shape.
JP2007156969A 2007-06-14 2007-06-14 Semiconductor device Pending JP2008311379A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101004684B1 (en) * 2008-12-26 2011-01-04 주식회사 하이닉스반도체 Stacked semiconductor package
JP2012520572A (en) * 2009-03-13 2012-09-06 テッセラ，インコーポレイテッド Microelectronic assembly with impedance controlled wire bond and reference wire bond

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101004684B1 (en) * 2008-12-26 2011-01-04 주식회사 하이닉스반도체 Stacked semiconductor package
US8310062B2 (en) 2008-12-26 2012-11-13 Hynix Semiconductor Inc. Stacked semiconductor package
JP2012520572A (en) * 2009-03-13 2012-09-06 テッセラ，インコーポレイテッド Microelectronic assembly with impedance controlled wire bond and reference wire bond

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