JP4960830B2 - Reconfigurable integrated circuit, circuit reconfiguration method, and circuit reconfiguration apparatus - Google Patents

Description

  The present invention relates to a dynamic reconfiguration arithmetic circuit capable of dynamically changing a logical configuration. In particular, the present invention relates to hardware resources required for changing the configuration of the dynamic reconfiguration arithmetic circuit.

In recent years, a dynamic reconfigurable operation circuit (generally called dynamic reconfigurable logic) that can change the logical configuration by a program has been proposed to achieve both the flexibility of software processing and the high speed of hardware processing. ing.
As devices capable of changing the logical configuration by a program, FPGA (Field Programmable Gate Array) and PLD (Programmable Logic Device) are well known. These FPGAs and PLDs have a configuration in which a circuit having different functions as a whole can be reconstructed by dynamically changing the connection between internal transistors to some extent by a program.
JP-T-2004-505488

However, a simple FPGA or PLD has many hardware resources necessary for switching the configuration, and causes an increase in area. Specifically, the hardware resources necessary for switching are storage means for storing configuration information defining the configuration such as an FPGA, a wiring group for appropriately distributing the configuration information to each reconfigurable element, and the like. .
It is an object of the present invention to provide a circuit reconfiguration device, a circuit reconfiguration method, and an integrated circuit that can suppress the area occupied by hardware resources required for changing the configuration of a dynamic reconfiguration arithmetic circuit.

  In order to solve this problem, the present invention is an integrated circuit capable of changing its internal configuration, and corresponds to a plurality of reconfigurable operation cells and each of the plurality of operation cells. A plurality of cell storage units storing original configuration information indicating all or part of the configuration of the computation cells, and an output set comprising a plurality of original configuration information stored in the plurality of cell storage units Output and receive an input set including a part of the original configuration information in the output set and one or more alternative configuration information in place of the original configuration information, and the original configuration information and the alternative configuration information included in the received input set One or more alternative configuration information indicating all or part of a new configuration of a calculation cell whose configuration is to be changed among the plurality of calculation cells, A storage means that controls the reconstruction calculation block, obtains the output set from the reconstruction calculation block, and replaces the corresponding original configuration information in the output set for the calculation cell whose configuration is to be changed. Selecting the alternative configuration information stored in the storage means, selecting the corresponding original configuration information in the output set for the operation cell whose configuration is not changed, and selecting the selected original configuration information and the selected alternative And a control means for outputting the input set comprising configuration information to the reconstruction calculation block.

  The present invention is also a circuit reconfiguration method used in an integrated circuit whose internal configuration can be changed, wherein the integrated circuit corresponds to a plurality of reconfigurable operation cells and each of the plurality of operation cells. A plurality of cell storage units storing original configuration information indicating all or a part of the configuration of the corresponding operation cell, and a plurality of original configurations stored in the plurality of cell storage units Output an output set comprising information, receiving an input set comprising a part of the original configuration information of the output set and one or more alternative configuration information in place of the original configuration information, and receiving the original set included in the received input set Reconfigurable operation block for reconfiguring each operation cell in accordance with configuration information and alternative configuration information, and showing all or part of a new configuration of the operation cell whose configuration is to be changed among the plurality of operation cells Storage means for storing one or more replacement configuration information, wherein the circuit reconfiguration method controls the reconfiguration arithmetic block, acquires the output set from the reconfiguration arithmetic block, and changes the configuration For the arithmetic cell to be selected, the alternative configuration information stored in the storage means is selected instead of the corresponding original configuration information in the output set, and the arithmetic cell in which the configuration is not changed is selected in the output set. The method includes a control step of selecting the corresponding original configuration information and outputting the input set including the selected original configuration information and the selected alternative configuration information to the reconstruction calculation block.

  Further, the present invention is a circuit reconfiguration device, which corresponds to each of a plurality of reconfigurable operation cells and each of the plurality of operation cells, and shows all or part of the configuration of the corresponding operation cells. A plurality of cell storage units storing original configuration information, and outputting an output set composed of a plurality of original configuration information stored in the plurality of cell storage units, a part of the output set Reconfiguration operation block that receives an input set including original configuration information and one or more alternative configuration information in place of the original configuration information, and reconfigures each operation cell according to the original configuration information and the alternative configuration information included in the received input set Storage means for storing one or more alternative configuration information indicating all or part of a new configuration of a calculation cell whose configuration is to be changed among the plurality of calculation cells, and the reconfiguration calculation block The replacement is stored in the storage means in place of the corresponding original configuration information in the output set for the calculation cell whose configuration is to be changed by acquiring the output set from the reconstruction calculation block. For operation cells that select configuration information and do not change the configuration, select the corresponding original configuration information in the output set, and reconfigure the input set that includes the selected original configuration information and the selected alternative configuration information. And a control means for outputting to the calculation block.

  Here, the above-mentioned “reconfiguration arithmetic block” corresponds to the dynamic reconfiguration arithmetic block 2010 shown in FIG. 1 of the first embodiment. In addition, the “storage unit” has the function of the configuration information storage unit 3000 of the first embodiment. As the “control means”, the configuration information selector 3400, the cell address comparator 4000, the cell address counter 5000, the switching cell address storage means 6000, and the storage means address counter 8000 have the functions.

  According to this configuration, the control means selects the alternative configuration information for a calculation cell whose configuration is to be changed from among the received output sets, and the output set for a calculation cell whose configuration is not required to be changed. Corresponding original configuration information is selected, and an output set composed of the selected alternative configuration information and the selected original configuration information is output. The reconstruction operation block includes the original configuration information and the alternative configuration included in the output set. Each arithmetic cell is reconfigured according to the information.

Therefore, when changing the configuration of the reconfiguration arithmetic block, the storage means only needs to store alternative configuration information corresponding to the arithmetic cell whose configuration is to be changed, so that the capacity of the storage means is reduced. be able to.
Further, according to the present invention, the control means repeatedly outputs a timing signal to the reconstruction calculation block, acquires one piece of original configuration information constituting the output set for each output, and the acquired original configuration information is The method repeatedly selects one of the acquired original configuration information and the alternative configuration information and outputs the selected configuration information to the reconfiguration calculation block depending on whether the calculation cell corresponds to the calculation cell to be changed. It may be an integrated circuit.

 Further, in the integrated circuit of the present invention, the plurality of operation cells are connected to corresponding cell storage units, and the plurality of cell storage units are connected in series to form a shift register, and from the control means Each time a timing signal is received, the cell storage unit located at the end of the shift register outputs the original configuration information held by itself, and the other cell storage units transfer to the cell storage unit adjacent to the end of the shift register. The original configuration information or the alternative configuration information stored therein is shifted, and the cell storage unit at the tip of the shift register repeatedly stores one original configuration information or alternative configuration information included in the output set. Also good.

  In the above-mentioned Patent Document 1, a technique for reducing the capacity of the storage means for changing the configuration of the reconstruction calculation block is disclosed. According to this technique, a reconfiguration arithmetic block includes a shift register for transmitting configuration data, a data line for transmitting configuration data in a direction perpendicular to the shift register, and new configuration information for an arithmetic cell that does not change the configuration. A mask register for preventing transmission (corresponding to alternative configuration information of the present invention) is included. There is one data line for each row, and one mask register for each column. For this reason, when the scale of the reconstruction operation block increases, the area occupied by the data line, the mask register, etc. also increases.

In contrast to this, in the integrated circuit of the present invention, one original configuration information is output from the cell storage unit at the end of the shift register to the control means, triggered by the timing signal, and the other cell storage units The original configuration information or the alternative configuration information held by itself is shifted, and the cell storage unit at the tip of the shift register stores the original configuration information or the alternative configuration information output from the control means.
That is, in the reconfiguration arithmetic block, the only configuration related to the configuration change is the shift register. Further, the circuit scale of the control means is hardly affected by the scale of the reconstruction operation block. Therefore, when the scale of the reconstructed arithmetic block increases, that is, when the total number of arithmetic cells increases, the configuration in which the area increases is only the shift register. Therefore, compared with the technique of the above-mentioned patent document, the increase in the area of the whole circuit accompanying the expansion of the scale of the reconstruction operation block can be suppressed.

  Further, the plurality of operation cells are identified by different identification numbers, and the plurality of identification numbers are consecutive in the order in which the corresponding operation cells are connected to the shift register. One or more change target identification numbers indicating operation cells to be changed in configuration are stored, a counter value is held, the timing signal is repeatedly output, and a constant value is set to the held counter value every time it is output. Is added, the counter value after addition is compared with the stored identification number to be changed, and if they match, the alternative information is selected, and if they do not match, the output original configuration information is An integrated circuit that repeats selection may be used.

According to this configuration, the plurality of calculation cells are identified by different identification numbers, and the control unit compares the counter value after addition with the stored identification number to be changed, and if the two match, The substitute information is selected, and if the two pieces of information do not match, the outputted original configuration information is selected.
Therefore, in the present invention, the control means can perform the selection by a simple process of comparison.

 Further, in the integrated circuit, the control means stores one or more change target identification numbers indicating the operation cells whose configuration is to be changed, and stores a change cell identification number in order of the change target identification numbers; A cell address counter that holds the counter value, repeatedly outputs the timing signal, and adds a constant value to the counter value each time it is output, and an address that determines a read address of the storage means and the switching cell address storage unit A cell address comparison unit that compares the counter value after addition and the identification number stored in the read address determined by the address counter in the cell address storage unit each time the timing signal is output If the result of the comparison indicates that they match, the position indicated by the read address determined by the address counter in the storage means Select the stored alternative configuration information, and if the result of determination is that they do not match, select the original configuration information output from the shift register, and select the selected one as the cell storage unit at the tip of the shift register And an information selection unit that repeats output every time the comparison is performed, and the storage means stores one or more pieces of the alternative configuration information in association with one or more pieces of the change target identification numbers. Also good.

According to this configuration, the control means can be realized by combining simple circuits such as a counter, a comparator, and an adder.
The address counter may determine a value obtained by adding 1 to the read address as a new read address when it is determined that the two match as a result of the comparison by the cell address comparison unit.

According to this configuration, the address counter can update the read address by a simple operation of addition.
Further, in the integrated circuit, the address counter stores a start address of the switching cell address storage unit, obtains a change instruction for requesting a configuration change of the reconfiguration arithmetic block from the outside, and outputs the change instruction. If acquired, the head address may be determined as the read address.

Since the address counter stores the start address of the switching cell address storage unit, when the change instruction is acquired, the first read address can be quickly determined.
The address counter may store the end address of the switching cell address storage unit, and stop adding to the read address when the read address matches the end address.

According to this configuration, the address counter stops updating the read address when the read address matches the end address. It is conceivable that the cell address storage unit is realized by one area in a memory having a large capacity.
With the above configuration, the address counter stops updating the read address when the read address matches the end address. Therefore, the address counter is related to the configuration change of the reconfiguration arithmetic block stored in the memory. There is no reference to no data. Therefore, the integrated circuit of the present invention can reliably change the configuration of the reconfiguration arithmetic block.

In the present invention, the control means may stop the repetition when the counter value matches an identification number indicating a calculation cell corresponding to the cell storage at the tip of the shift register.
According to this configuration, the control unit stops the repetition when the counter value matches an identification number indicating a calculation cell corresponding to the cell storage unit at the tip of the shift register. Therefore, the original configuration information stored before starting the configuration change is returned to the cell storage unit corresponding to the computation cell whose configuration is not changed, and the cell storage unit corresponding to the computation cell whose configuration is to be changed is replaced. The configuration information is stored, and the configuration change of the reconfiguration arithmetic block can be completed without fail.

  Further, the plurality of cell storage units store, as the original configuration information, original calculation parameters indicating a part of the configuration of the calculation cell, and the storage unit includes the configuration of the calculation cell as the alternative configuration information. Alternative calculation parameters indicating a part of the calculation cell may be stored, and the reconfiguration calculation block may rewrite calculation parameters constituting each calculation cell according to the original calculation parameter or the alternative calculation parameter included in the input set. .

According to this configuration, only the calculation parameter is changed in the information indicating the configuration of the calculation cell. By doing so, the storage capacity of the storage means can be further reduced.
In the integrated circuit, the reconstruction calculation block and the control means are connected by a first wiring and a second wiring, and the storage means and the control means are connected by a third wiring, and the reconstruction calculation block is connected. The block outputs the output group to the control means via the first wiring, and the control means obtains the output group via the one wiring, and the one or more via the third wiring. Alternative configuration information is obtained, and the input group is output to the reconfiguration arithmetic block via the second wiring.

Further, the present invention is an image processing apparatus equipped with the integrated circuit, wherein the circuit reconfiguration apparatus executes reconfiguration of the reconfiguration arithmetic block in a vertical blanking period or a horizontal blanking period. And
Further, the present invention provides an information processing apparatus equipped with the integrated circuit, wherein the reconfiguration operation is performed on the circuit reconfiguration device during a period when processing by the circuit configured on the reconfiguration operation block is not required. An information processing apparatus characterized by executing block reconstruction may be used.

According to such a configuration, the device on which the integrated circuit is mounted can change the configuration of the reconfiguration arithmetic block effectively using time.
Further, the present invention is an integrated circuit whose internal configuration can be changed, and corresponds to a plurality of reconfigurable calculation cells and each of the plurality of calculation cells, and the configuration of the corresponding calculation cells A plurality of cell storage units storing original configuration information indicating all or a part of the plurality of cell storage units, and outputting an output set composed of a plurality of original configuration information stored in the plurality of cell storage units, Are received from the original configuration information and one or more alternative configuration information in place of the original configuration information, and each computation cell is re-executed according to the original configuration information and the alternative configuration information included in the received input set. A reconfigurable calculation block to be configured; an acquisition means for acquiring one or more of the alternative configuration information indicating all or part of a new configuration of the calculation cell whose configuration is to be changed among the plurality of calculation cells; Control the calculation operation block, acquire the output set from the reconfiguration calculation block, and for the calculation cell whose configuration is to be changed, the acquisition unit has acquired the acquisition unit instead of the corresponding original configuration information in the output set For an arithmetic cell that selects alternative configuration information, does not change the configuration, selects the corresponding original configuration information of the output set, and re-inputs the input set consisting of the selected original configuration information and the selected alternative configuration information. And a control means for outputting to the configuration calculation block.

  The present invention is also a circuit reconfiguration method used in an integrated circuit whose internal configuration can be changed, wherein the integrated circuit corresponds to a plurality of reconfigurable operation cells and each of the plurality of operation cells. A plurality of cell storage units storing original configuration information indicating all or a part of the configuration of the corresponding operation cell, and a plurality of original configurations stored in the plurality of cell storage units Output an output set comprising information, receiving an input set comprising a part of the original configuration information of the output set and one or more alternative configuration information in place of the original configuration information, and receiving the original set included in the received input set A reconfigurable operation block for reconfiguring each operation cell in accordance with the configuration information and the alternative configuration information, and the circuit reconfiguration method includes: An acquisition step for acquiring one or more of the alternative configuration information indicating all or part of the information, and an operation to control the reconstruction calculation block to acquire the output set from the reconstruction calculation block and to change the configuration For a cell, select the alternative configuration information acquired by the acquisition means instead of the corresponding original configuration information in the output set, and for the operation cell that does not change the configuration, the corresponding original configuration information in the output set And a control step of outputting the input set consisting of the selected original configuration information and the selected alternative configuration information to the reconstruction calculation block.

  Further, the present invention is a circuit reconfiguration device, which corresponds to each of a plurality of reconfigurable operation cells and each of the plurality of operation cells, and shows all or part of the configuration of the corresponding operation cells. A plurality of cell storage units storing original configuration information, and outputting an output set composed of a plurality of original configuration information stored in the plurality of cell storage units, a part of the output set Reconfiguration operation block that receives an input set including original configuration information and one or more alternative configuration information in place of the original configuration information, and reconfigures each operation cell according to the original configuration information and the alternative configuration information included in the received input set And an acquisition means for acquiring one or more of the alternative configuration information indicating all or part of a new configuration of a calculation cell whose configuration is to be changed among the plurality of calculation cells, and the reconfiguration calculation block. Then, the output set is acquired from the reconstructed calculation block, and for the calculation cell whose configuration is to be changed, the replacement configuration information acquired by the acquisition unit is selected instead of the corresponding original configuration information in the output set. Then, for the operation cell whose configuration is not changed, the corresponding original configuration information in the output set is selected, and the input set including the selected original configuration information and the selected alternative configuration information is output to the reconfiguration calculation block. Control means.

  According to this configuration, the original configuration information corresponding to the operation cell that does not require a configuration change in the output set can be reused.

1. Embodiment 1
Embodiment 1 of the present invention will be described below with reference to the drawings.
1.1 Configuration FIG. 1 is a functional block diagram showing a configuration of the dynamic reconfiguration arithmetic circuit 110 in Embodiment 1 of the present invention.

  This circuit includes a dynamic reconfiguration arithmetic block 2010, a configuration information storage unit 3000, a configuration information selector 3400, a cell address comparator 4000, a cell address counter 5000, a switching cell address storage unit 6000, a storage unit address counter 8000, and configuration information. An input bus 3100, a configuration information output bus 3200, a configuration information transmission bus 3300, a cell address comparator output line 4100, a cell address counter output line 5100, a switching cell address output line 6100, and a storage means address counter output line 8100 are configured.

  The dynamic reconfiguration arithmetic block 2010 is configured to include 16 dynamic reconfiguration arithmetic cells 2100-10, 2100-02, 2100-03... 2100-16, and arithmetic operations performed in each arithmetic cell. The type and the connection configuration for calculation data can be changed. Each arithmetic cell 2100 is assigned cell numbers 16 to 01 in descending order from the side closer to the input terminal of the shift register 2300. In the present specification, the dynamic reconfiguration arithmetic cell may be simply referred to as “arithmetic cell” in order to simplify the description.

Hereinafter, the arithmetic cells 2100-01, 2100-02, 2100-03,... 2100-16 are simply referred to as the arithmetic cell 2100 when it is not necessary to distinguish them.
Next, details of the shift register 2300 will be described with reference to FIG.
The shift register 2300 includes 16 storage units 2301, 2302, 2303, 2304, 2305, 2306, 2307, 2308, 2309, 2310, 2311, 2312, 2313, 2314, 2315, and 2316. Each storage means is connected to a corresponding arithmetic cell 2100-01, 2100-02, 2100-03,.

  Each storage unit stores configuration information of a corresponding calculation cell. The configuration information includes information indicating the type of calculation performed by the corresponding calculation cell, the calculation parameter, and the connection between the calculation cells 2100. For example, in the storage unit 2303 corresponding to the cell number 03, wiring information indicating that the calculation result of the calculation cell “cell number 01” is acquired, and the calculation parameter “+3” is “added” to the acquired calculation result. The contents are described.

The 16 storage units are cascade-connected in descending order of the cell address of the corresponding arithmetic cell 2100 to constitute a shift register 2300. The input terminal of the shift register 2300 is connected to the configuration information input bus 3100. The output terminal of the shift register 2300 is connected to the configuration information output bus 3200.
The storage units 2301 to 2316 constituting the shift register 2300 are connected to the cell address counter 5000 and receive a pulse signal from the cell address counter 5000. When receiving the pulse signal, the storage unit 2301 outputs the stored configuration information to the configuration information output bus 3200. At the same time, the storage unit 2302 outputs the stored configuration information to the storage unit 2301, and the storage unit 2303 outputs the stored configuration information to the storage unit 2302. Similarly, each storage unit outputs its own configuration information to the adjacent storage unit, so that the configuration information is sequentially shifted in the shift register 2300. At this time, configuration information corresponding to one arithmetic cell is input from the configuration information input bus 3100 and stored in the storage unit 2316.

  Next, a mechanism for inputting the configuration information to be changed to the shift register 2300 when changing the configuration of the dynamic reconfiguration arithmetic block 2010 will be described. Configuration information indicating a new configuration of the computation cell 2100 to be changed is stored in the configuration information storage unit 3000. The change of the configuration of the arithmetic cell 2100 is realized by writing the configuration information in the configuration information storage unit 3000 to the shift register 2300.

Transmission of configuration information to the shift register 2300 is performed via a configuration information selector 3400, a configuration information transmission bus 3300, a configuration information output bus 3200, and a configuration information input bus 3100.
The configuration information output from the configuration information storage unit 3000 is transmitted to the configuration information selector 3400 via the configuration information transmission bus 3300. The configuration information output from the shift register 2300 is transmitted to the configuration information selector 3400 through the configuration information output bus 3200.

The input terminal of the shift register 2300 is connected to the configuration information input bus 3100, and the configuration information input bus 3100 is connected to the output of the configuration information selector 3400. The configuration information selector 3400 is controlled by the cell address comparator 4000 via the cell address comparator output line 4100.
The cell address comparator 4000 is a functional unit that controls the configuration information selector 3400 and the storage means address counter 8000 based on the output value.

  The cell address comparator 4000 receives an output value (counter value to be described later) from the cell address counter 5000 via the cell address counter output line 5100 and outputs the switching cell address storage means 6000 via the switching cell address output line 6100. Takes a value and compares the two received values. When both are equal, the output value to the cell address comparator output line 4100 is set to 1, and when both are not equal, the output value is set to 0.

When 1 is output, the cell address comparator 4000 outputs 1 only during the time Δs, and returns the output value to 0 after the time Δs has elapsed. Here, Δs is shorter than the time interval Δt of counting up by the cell address counter 5000 (details will be described later with reference to FIG. 9).
The cell address counter 5000 is initialized to 0 by the storage means address counter 8000. When initialized, the counter value is incremented by one every certain time (Δt). The cell address counter 5000 outputs the counter value to the cell address comparator 4000 via the cell address counter output line 5100.

In addition, the cell address counter 5000 outputs a pulse signal to the shift register 2300 constituting the dynamic reconfiguration arithmetic block 2010 every time it counts up.
When the output value of the cell address comparator output line 4100 is 1, the configuration information selector 3400 selects data on the configuration information transmission bus 3300. When the output value of the cell address comparator output line 4100 is 0, the configuration information selector 3400 The data on the information output bus 3200 is selected. Next, the configuration information selector 3400 outputs the selected data to the configuration information input bus 3100.

  The configuration information storage unit 3000 stores the configuration information of the computation cell 2100 to be changed in ascending order of cell addresses. The switching cell address storage unit 6000 stores the cell addresses of the calculation cells 2100 to be changed in ascending order. Note that the cell address stored in the switching cell address storage unit 6000 and the configuration information stored in the configuration information storage unit 3000 have data corresponding to the same memory address.

6 and 7 show examples of configurations of the switching cell address storage unit 6000 and the configuration information storage unit 3000, respectively.
For example, data for switching the configuration of the dynamic reconfiguration arithmetic block 2010 from the configuration A to the configuration B is stored in the areas 3001 and 6001 of the memory addresses 0x00 to 0x01 of each storage unit.

In the area 6001 of the switching cell address storage unit 6000, the cell addresses “10” and “11” of the calculation cells whose configuration information needs to be changed in order to change from the configuration A to the configuration B are stored in ascending order. More specifically, the cell address “10” is stored in the area of the memory address 0x00, and the cell address “11” is stored in the area of the memory address 0x01.
Correspondingly, in the area 3001 of the configuration information storage unit 3000, configuration information necessary for changing from the configuration A to the configuration B is stored in ascending order of the cell addresses corresponding to the configuration information.

More specifically, the configuration information “2315” of the computation cell 2100-10 identified by the cell address “10” is stored in the area of the memory address 0x00, and the cell address is stored in the area of the memory address 0x01. The configuration information “5778” of “11” is stored.
Here, as an example, each piece of configuration information is described as a 4-digit decimal number. However, this is only an example. For example, binary configuration information having 64-bit length and 128-bit length is stored. Also good. Further, it may be more complicated configuration information or simple configuration information.

The switching cell address storage unit 6000 and the configuration information storage unit 3000 receive an address output from the storage unit address counter 8000 via the storage unit address counter output line 8100. When the address is received, the data stored in the received address is read and output to the switching cell address output line 6100 and the configuration information transmission bus 3300, respectively.
The storage unit address counter 8000 is a functional unit that controls the read addresses of the configuration information storage unit 3000 and the switching cell address storage unit 6000.

The storage means address counter 8000 is a combination of the start address and the end address of the area where data for switching the configuration of the dynamic reconfiguration arithmetic block 2010 is stored in the switching cell address storage means 6000 and the configuration information storage means 3000. I remember more than one.
Specifically, the start address “0x00” and the end address “0x01” of the areas 3001 and 6001 in which data for switching the configuration of the dynamic reconfiguration arithmetic block 2010 from the configuration A to the configuration B is stored are stored. Yes. Similarly, the start address “0x02” and the end address “0x04” of the area 3002 and the area 6002 in which data for switching from the configuration B to the configuration C are stored are stored. Further, the first address “0x05” and the end address “0x06” of the areas 3003 and 6003 in which data for switching from the configuration C to the configuration A is stored are stored.

  The storage unit address counter 8000 receives an instruction to start switching of the dynamic reconfiguration arithmetic block 2010 from the control mechanism of the device in which the dynamic reconfiguration arithmetic circuit 110 is mounted. The instruction received here includes information indicating the current configuration of the dynamic reconfiguration arithmetic block 2010 and the configuration that will be required in the future. For example, contents such as “change from configuration A to configuration B” are included.

Further, the storage means address counter 8000 stores information indicating the current configuration of the dynamic reconfiguration arithmetic block 2010, and the instruction from the control mechanism includes only information indicating the configuration that will be required from now on. May be.
Upon receiving the configuration change instruction, the storage means address counter 8000 selects a set of head address and end address based on the current dynamic reconfiguration arithmetic cell state and information indicating the configuration required from now on.

Note that the storage unit address counter 8000 may include the above-described head address and end address in the instruction from the control mechanism instead of selecting the pair of the head address and end address.
Subsequently, the storage unit address counter 8000 outputs the selected head address to the switching cell address storage unit 6000 and the configuration information storage unit 3000 via the storage unit address counter output line 8100. Also, the counter value of the cell address counter 5000 is initialized to zero.

  The storage means address counter 8000 receives 0 and 1 from the cell address comparator output line 4100 during the configuration change. When the output value from the cell address comparator output line 4100 is 1, the storage means address counter 8000 adds +1 to the output value to the storage means address counter output line 8100. As a result, the read addresses of the configuration information storage unit 3000 and the switching cell address storage unit 6000 are changed.

However, even if the output value from the cell address comparator output line 4100 is 1, if the value currently being output to the storage means address counter output line 8100 matches the end address, the storage means address counter 8000 outputs Do not increment the value.
Next, switching of the configuration of the dynamic reconfiguration arithmetic block 2010 will be specifically described.
1.2 Switching of Configuration over Time FIG. 3 is an operation scheduling diagram of configuration switching of the dynamic reconfiguration arithmetic block 2010 in the present embodiment. The configuration of the dynamic reconfiguration arithmetic block 2010 is switched in the order of configurations A, B, and C. Hereinafter, in the drawings, a dynamic reconfiguration arithmetic cell is abbreviated as an arithmetic cell as necessary.

  FIG. 4 shows a list of operation cell 2100 cell addresses that need to be changed in this switching. In addition, FIG. 5 shows a list of data values of configuration information of the dynamic reconfiguration arithmetic cells 2100-01 to 2100-16 constituting the dynamic reconfiguration arithmetic block 2010 in each configuration. Further, in this configuration switching, the cell address setting value of each configuration switching in the switching cell address storage unit 6000 is shown in FIG. 6, and the configuration information data setting value for each configuration switching in the configuration information storage unit 3000 is shown in FIG. .

To explain over time, in the period 9000, the dynamic reconfiguration arithmetic block 2010 is set to the configuration A. The configuration information of each dynamic reconfiguration arithmetic cell 2100 in the configuration A state is as shown in the column “configuration A” in FIG.
Subsequently, in period 9011, the configuration of the dynamic reconfiguration arithmetic block 2010 is switched from the configuration A to the configuration B, and the configuration information of the dynamic reconfiguration arithmetic cells 2100-10 and 2100-11 is changed by this switching. The

During the period 9001, the configuration of the dynamic reconfiguration arithmetic block 2010 is in the configuration B state. The configuration information of each dynamic reconfiguration arithmetic cell in configuration B is as shown in the column “configuration B” in FIG.
In the period 9012, the configuration of the dynamic reconfiguration arithmetic block 2010 is switched from the configuration B to the configuration C, and the configuration information of the dynamic reconfiguration arithmetic cells 2100-10, 2100-11, and 2100-12 is changed by this switching. Is done.

During the period 9002, the configuration of the dynamic reconfiguration arithmetic block 2010 is in the state of the configuration C, and the configuration information of each dynamic reconfiguration arithmetic cell at this time is as shown in the column “configuration C” in FIG. It is.
Subsequently, during the period 9013, the configuration of the dynamic reconfiguration arithmetic block 2010 is switched from the configuration C to the configuration A, and the configuration information of the dynamic reconfiguration arithmetic cells 2100-11 and 2100-12 is changed by this switching. The

During the subsequent period 9003, the state of the dynamic reconfiguration arithmetic block 2010 is configuration A.
Thus, when the configuration of the dynamic reconfiguration arithmetic block 2010 can be cyclically switched between the configuration A, the configuration B, and the configuration C, the dynamic reconfiguration arithmetic cells 2100-01, 2100-02, 2100-03, 2100 The configurations of −04, 2100-05, 2100-06, 2100-07, 2100-08, 2100-09, 2100-13, 2100-14, 2100-15, and 2100-16 are not changed. Only the configuration of the arithmetic cells 2100-10, 2100-11, and 2100-12 is changed.

Therefore, as shown in FIGS. 6 and 7, only the data relating to the arithmetic cells 2100-10, 2100-11, and 100-12 are stored in the switching cell address storage unit 6000 and the configuration information storage unit 3000.
1.3 Operation FIG. 8 is a flowchart showing a configuration switching operation. The configuration switching operation will be described below with reference to FIG.

In the switching operation from the configuration A to the configuration B in the period 9011, first, the storage unit address counter 8000 outputs the head address “0x00” (step S9501).
Also, the storage means address counter 8000 initializes the counter value of the cell address counter 5000 to 0 (step S9502).
Next, the cell address counter 5000 adds +1 to the counter value (step S9503).

The cell address comparator 4000 compares the output value from the cell address counter 5000 with the output value of the switching cell address storage unit 6000 (step S9504).
As a result of the comparison, if the two match (Y in step S9504), the cell address comparator 4000 outputs 1 for a predetermined time Δs (step S9506).
The configuration information selector 3400 receives 1 via the cell address comparator output line 4100. When 1 is received, the configuration information selector 3400 connects the configuration information transmission bus 3300 to the configuration information input bus 3100 (step S9507).

  Further, the storage means address counter 8000 that has received 1 via the cell address comparator output line 4100 has a termination corresponding to the data currently being output to the storage means address counter output line 8100 and the head address output in step S9501. The addresses are compared (step S9509), and if they do not match (N in step S9509), +1 is added to the data being output (step S9510).

If the two match as a result of the comparison (Y in step S9509), the storage means address counter 8000 moves to step S9513 without performing the addition in step S9510.
If they do not match in step S9504 (N in step S9504), the cell address comparator 4000 outputs 0 to the cell address comparator output line 4100 (step S9511).

Upon receiving 0, the configuration information selector 3400 connects the configuration information output bus 3200 to the configuration information input bus 3100 (step S9512).
Subsequently, the configuration data on the configuration information input bus 3100 is input to the shift register 2300 (step S9513).
Next, the cell address counter 5000 compares the counter value with the number of dynamic reconfiguration arithmetic cells 2100 (16 in this case). If the counter value is 16 or more (Y in step S9514), the configuration switching operation is performed. Exit.

If the counter value is less than 16 (N in step S9514), the process returns to step S9503, and the processes in steps S9503 to S9514 are repeated until the counter value becomes 16 or more.
In the case of the configuration switching from the configuration A to the configuration B, the dynamic reconfiguration arithmetic cells 2100-01, 2100-02, 2100-03, 2100-04, 2100-05, 2100 whose configuration is not changed by the processing shown in FIG. In −06, 2100-07, 2100-08, 2100-09, 2100-12, 2100-13, 2100-14, 2100-15, 2100-16, the configuration information is reused.

Only the configuration information of the dynamic reconfiguration arithmetic cells 2100-10 and 2100-11 is changed to the configuration information stored in the configuration information storage unit 3000.
Similarly, in the configuration switching from the configuration B to the configuration C and from the configuration C to the configuration A, the configuration information of the arithmetic cells whose configuration is not changed is reused according to the flowchart of FIG.
1.4 Detailed pipeline The pipeline of each component when switching from configuration A to configuration B is shown in FIG. Hereinafter, a detailed data transition at the time of configuration switching will be described with reference to FIG.

At time t0, the storage means address counter 8000 initializes the counter value of the cell address counter 5000 to zero. Along with this, the output value of the cell address counter output line 5100 also becomes zero. After the initialization, the cell address counter 5000 increments the counter value by 1 every time Δt (time t1, t2, t3...).
Further, the storage means address counter 8000 starts outputting the head address “0x00” to the storage means address counter output line 8100.

In response to the output of “0x00”, the switching cell address output line 6100 starts outputting the cell address “10”, and the configuration information transmission bus 3300 starts outputting the configuration information “2315”.
Since the configuration of the dynamic reconfiguration arithmetic block 2010 is the configuration A at time t0, the configuration information of the arithmetic cells 2100-16, 2100-12, 2100-11, 2100-10, and 2100-01 is “2222”, respectively. ”,“ 4500 ”,“ 5678 ”,“ 3333 ”, and“ 5000 ”(see configuration A in FIG. 5).

At time t1, the cell address counter 5000 counts up the counter value to “1”. In addition, a pulse signal is output to the shift register 2300.
Upon receiving the pulse signal, the storage means 2301 (corresponding to the arithmetic cell 2100-01) constituting the shift register 2300 outputs the stored configuration information “5000” to the configuration information output bus 3200, and the other storage means 2302 ˜2316 shifts the configuration information held by itself to the adjacent storage means. Each arithmetic cell 2100 loads the configuration information written in the corresponding storage means 2301 to 2315.

Since the output value “1” of the cell address counter output line 5100 does not match the output value “10” of the switching cell address output line 6100, the cell address comparator 4000 outputs 0 to the cell address comparator output line 4100.
The configuration information selector 3400 that has received the signal 0 connects the configuration information output bus 3200 to the configuration information input bus 3100, so that the configuration information “5000” is input to the shift register 2300 and stored in the storage unit 2316. The configuration information “5000” stored in the storage unit 2316 is loaded into the arithmetic cell 2100-16.

Accordingly, at this time, the configuration information of the arithmetic cells 2100-16, 2100-12, 2100-11, 2100-10, and 2100-01 are “5000”, “7843”, “4500”, “5678”, and “0010”, respectively. It is.
At time t2, the cell address counter 5000 counts up the counter value to “2”, and the output value of the cell address counter output line 5100 also becomes “2”. Also here, since the output value of the cell address counter output line 5100 and the output value of the switching cell address output line 6100 do not match, the configuration stored in the storage means 2301 constituting the shift register 2300 is the same as at time t1. The information is shifted to the storage unit 2316, and the configuration information stored in the storage units 2302 to 2316 is shifted to the adjacent storage unit. Each computation cell 2100 loads the stored configuration information held by the corresponding storage means.

Similar processing is repeated until time t9.
At time t10, the cell address counter 5000 counts up the counter value to “10” and outputs a pulse signal to the shift register 2300.
The shift register 2300 outputs the configuration information stored in the storage unit 2301 (corresponding to the arithmetic cell 2100-01) to the configuration information output bus 3200, and shifts the configuration information between the internal storage units.

At this time, since the output value of the cell address counter output line 5100 and the output value of the switching cell address output line 6100 are both “10”, the cell address comparator 4000 sends the time Δ to the cell address comparator output line 4100. Output 1 during s.
The configuration information selector 3400 that has received the signal 1 connects the configuration information transmission bus 3300 to the configuration information input bus 3100. Therefore, the configuration information “2315” output from the configuration information storage unit 3000 is input to the shift register 2300 and written to the storage unit 2316. The arithmetic cell 2100-16 loads the configuration information “2315” written in the storage unit 2316.

Further, the storage means address counter 8000 having received 1 from the cell address comparator output line 4100 adds +1 to the output value and starts outputting “0x01”.
The switching cell address storage unit 6000 that has received “0x01” via the storage unit address counter output line 8100 outputs the cell address “11” stored at the address “0x01” to the switching cell address output line 6100. .

Similarly, the configuration information storage unit 3000 that has received “0x01” starts outputting the configuration information “5778” stored at the address “0x01”.
At time t11, the output value of the cell address counter output line 5100 is “11”, which matches the output value of the switching cell address output line 6100. Accordingly, the cell address comparator 4000 outputs 1 via the cell address comparator output line 4100.

The configuration information selector 3400 that has received the signal 1 connects the configuration information transmission bus 3300 to the configuration information input bus 3100. Therefore, the configuration information “5778” is input to the shift register 2300 and written to the storage unit 2316. The arithmetic cell 2100-16 loads the configuration information “5778” written in the storage unit 2316.
At this time, the storage unit address counter 8000 receives 1 via the cell address comparator output line 4100, but the value “0x01” currently being output matches the end address, so the output value is not incremented. .

  Therefore, after time t12, since the output value of the switching cell address output line 6100 remains “11”, the output value of the cell address counter output line 5100 may match the output value of the switching cell address output line 6100. Absent. Accordingly, from time t12 to time t16, the cell address counter 5000 continues to count up the counter value, and the shift register 2300 cyclically reads the configuration information stored in the storage means 2301 to 2316 each time the count value is incremented. Shift.

At time t17, since the counter value of the cell address counter 5000 is already the number of operation cells 16, the cell address counter 5000 stops counting up and ends the configuration switching operation.
At this time, the configuration information of the computation cells 2100 at the cell addresses “10” and “11” has been changed, but the configuration information of the other computation cells 2100 is the same as before the configuration switching start.
1.5 Summary As described above, in the present invention, the dynamic reconfiguration arithmetic block includes a shift register composed of storage means coupled in series, and each dynamic reconfiguration is controlled by the control unit. The configuration information of the computation cell is circulated, only the configuration information that needs to be changed is replaced with new configuration information, and the other configuration information is reused.

Therefore, the configuration information storage means only needs to store new configuration information of the dynamic reconfiguration arithmetic cell that needs to be changed, and the memory capacity in the circuit can be reduced.
Further, the above-described Patent Document 1 also discloses a technique for realizing reduction of configuration information to be stored.
FIG. 19 is a schematic diagram of a dynamic reconfiguration arithmetic circuit disclosed in Patent Document 1. The dynamic reconfiguration arithmetic block 200 can change the arithmetic contents and connection configuration of the arithmetic cell 210 so as to be suitable for the arithmetic to be processed. The change of the calculation contents and connection of the dynamic reconfiguration calculation block 200 is achieved by transmitting the configuration information input from the shift register 230 to each calculation cell 210. The configuration information input to the shift register 230 is distributed by each data line 250. The configuration of the arithmetic cell 210 in the area specified by the address line 220 and not masked by the mask register 240 is changed according to the distributed configuration information.

Thus, by specifying the range to be changed, the configuration information of the arithmetic cell 210 whose configuration is not changed can be reused.
For this reason, it is only necessary to prepare the configuration information of the portion that needs to be changed, the data size of the configuration information can be reduced, and the capacity of the configuration information storage unit 300 can be suppressed.
However, the configuration of Patent Document 1 has a problem that the area of a large-scale reconfigurable logic circuit increases because hardware resources for configuration switching increase according to the number of arithmetic cells 210. Specifically, the total number of operation cells 210 is N, the area occupied by one operation cell 210 of the data line 250 is a, the number of operation cells vertically arranged is β, the number of operation cells 210 of the mask register 240 is Assuming that the area occupied by one is b and the area occupied by one operation cell 210 of the address line 220 is c, the hardware resource for switching the configuration occupies an area of (a + c) × N + b × β. Therefore, in a large-scale reconfigurable logic circuit with a large number of operation cells 210, the area for configuration switching becomes a problem.

Compared to this technique, in the present invention, the control unit has almost the same circuit scale even when the number of dynamic reconfiguration arithmetic cells in the dynamic reconfiguration arithmetic block increases. In addition, since the hardware resource related to the configuration change is only the shift register in the dynamic reconfiguration arithmetic block, even if the number of dynamic reconfiguration arithmetic cells increases, compared to the technique of Patent Document 1, An increase in the area of the entire dynamic reconfiguration arithmetic block can be suppressed. Therefore, it is possible to suppress an increase in area related to the configuration change of the dynamic reconfiguration arithmetic block.
1.6 Supplement Although the first embodiment has been described above, this is merely an example, and the following cases are also included in the present invention.

  (1) When the storage means address counter 8000 stores in advance the set of the start address and the end address of the area in the switching cell address storage means 6000 and the configuration information storage means 3000 in which data relating to the configuration change is stored. Although described, the start address and the end address may be instructed every time the configuration is changed from the control mechanism of the device on which the dynamic reconfiguration arithmetic circuit 110 is mounted.

(2) Although the storage means address counter 8000 is described as performing the initialization of the cell address counter 5000, this is also initialized by the control mechanism of the device in which the dynamic reconfiguration arithmetic circuit 110 is mounted. It may be.
(3) In the first embodiment, each time the configuration information stored in the corresponding storage means is changed, each arithmetic cell is rewritten according to the new configuration information. That is, in the configuration change of the dynamically reconfigurable calculation block including 16 calculation cells, the calculation cell is reconfigured every time the configuration information is shifted in the shift register, so that the reconfiguration is executed 16 times in total. However, it is not limited to this.

For example, after the configuration information is properly written in all the storage means, that is, when the counter value of the cell address counter 5000 reaches 16, the reconfiguration of 16 operation cells is performed at the same time. It is good.
2. Embodiment 2
Embodiment 2 of the present invention will be described below with reference to the drawings.
2.1 Configuration and Operation FIG. 10 shows a moving image quality enhancement device 18001 according to Embodiment 2 of the present invention.

The image quality improving device 18001 includes a moving image data generating unit 18000, a moving image image quality improving circuit 19000, an image feature amount data line 19100, and a display 11000.
The image quality improving device 18001 has a function of inputting the moving image data generated by the moving image data generating unit 18000 to the moving image quality improving circuit 19000 and displaying the image data with improved image quality on the display 11000.

The moving image high image quality improving circuit 19000 includes video frame buffers 17000 a and 17000 b and a dynamic reconfiguration arithmetic circuit 110.
The configuration of the dynamic reconfiguration arithmetic circuit 110 is the same as that of the first embodiment shown in FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
The image data input from the moving image data generation unit 18000 is stored in the video frame buffer 17000a, then subjected to high image quality processing by the dynamic reconfiguration arithmetic circuit 110, and stored in the video frame buffer 17000b. Thereafter, the image data is sent from the video frame buffer 17000b to the display 11000.

FIG. 11 and FIG. 12 show an example of calculation formulas for filter processing for improving the image quality performed by the dynamic reconfiguration arithmetic circuit 110.
FIG. 13 shows the order of images processed by the dynamic reconfiguration arithmetic circuit 110. As shown in FIG. 13, the image quality improvement processing is performed in the order of image data 20000, 20100, and 20200.

In the image quality improving device 18001, the image data is subjected to filter processing by the calculation shown in FIG. 11 or 12 according to the characteristics of the image data.
Specifically, for image data whose noise amount is less than a predetermined threshold, the arithmetic expression shown in FIG.
X2 '= (1 * X1 + 1 * X3) / 2
X1: Pixel data on the left side of the position of X2 X2: Pixel data to be corrected X3: Pixel data on the right side of the position of X2 X2 ′: Filter processing is performed using the pixel data after correction.

For image data including noise exceeding a predetermined threshold, the arithmetic expression shown in FIG.
X2 '= (1 * X1 + 2 * X2 + 1 * X3) / 4
X1: Pixel data on the left side of the position of X2 X2: Pixel data to be corrected X3: Pixel data on the right side of the position of X2 X2 ′: Filter processing is performed using the pixel data after correction.

  The moving image data generation unit 18000 has a function of detecting the noise amount of each image data. For example, when it is detected that the noise of the image data 20100 exceeds a predetermined threshold among the image data 20000, 20100, and 20200, the moving image data generation unit 18000 causes the image data 20100 to be noisy through the image feature data line 19100. Information indicating image data is transmitted to the dynamic reconfiguration arithmetic circuit 110.

In response to this information, the dynamic reconfiguration arithmetic circuit 110 subjects the image data 20000 and 20200 to filter processing using the arithmetic operation shown in FIG. 11, and filters the image data 20100 using the arithmetic operation shown in FIG. Apply processing.
In order to realize this, the dynamic reconfiguration arithmetic circuit 110 performs a configuration change between the processing of the image data 20000 and the processing of the image data 20100, and between the processing of the image data 20100 and the processing of the image data 20200.

As for the configuration change, as described in the first embodiment, the configuration information is changed only for the dynamic reconfiguration arithmetic cell that needs to be changed, and the configuration information before the configuration change is changed for the other dynamic reconfiguration arithmetic cells. Use.
Each image data is input to the dynamic reconstruction calculation circuit 110 in order from the upper horizontal line data. However, as shown in FIG. There is a time for invalid data to be transmitted.

The dynamic reconfiguration arithmetic circuit 110 detects this blanking region and starts the configuration change. The configuration change is completed at the time of the vertical blanking area 20010.
3. Embodiment 3
FIG. 15 is a diagram showing an external appearance of mobile communication device 10000 in Embodiment 3 of the present invention.

Examples of the mobile communication device 10000 include various devices such as a mobile phone, a PDA, a portable video player, a portable music player, and a digital camera.
As shown in FIG. 15, the mobile communication device 10000 includes a display 11000, an imaging unit 12000, a sound output unit 13000, a sound input unit 14000, a command input unit 15000, and an antenna 16000. In addition, the dynamic reconfiguration arithmetic circuit 110 described in the first embodiment is mounted inside.

The configuration of the dynamic reconfiguration arithmetic circuit 110 is the same as that of the first embodiment shown in FIG. The same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.
3.1 Function of Mobile Communication Device 10000 A specific example of the function of mobile communication device 10000 will be described below.
Note that these are examples, and other functions may be provided.

(1) Video Playback Function The dynamic reconfiguration arithmetic circuit 110 is connected to the display 11000 via a video frame buffer. The dynamic reconfiguration arithmetic circuit 110 performs still image decoding processing such as JPEG, moving image decoding processing such as MPEG, three-dimensional graphics processing such as a game, text drawing processing, and overlay processing of each video. Subsequently, the processed image data is written into the frame buffer.

The display 11000 acquires processed image data from the frame buffer, and displays a video based on the acquired image data.
(2) Imaging Function The dynamic reconfiguration arithmetic circuit 110 is connected to the imaging unit 12000 via a video frame buffer.

The imaging unit 12000 writes the captured image data in the video frame buffer.
The dynamic reconfiguration arithmetic circuit 110 acquires image data from the video frame buffer and performs an encoding process on the acquired image data. Specific examples of the encoding process include a still image encoding process such as JPEG and a moving image encoding process such as MPEG.

(3) Audio reproduction function Furthermore, the dynamic reconfiguration arithmetic circuit 110 is connected to the sound output means 13000 via an audio frame buffer. The dynamic reconfiguration arithmetic circuit 110 performs audio decoding processing such as MPEG and writes the decoded audio data to the audio frame buffer. The sound output unit 13000 reads audio data from the audio frame buffer, generates audio based on the read audio data, and outputs the audio.

(4) Recording function The dynamic reconfiguration arithmetic circuit 110 is connected to the sound input means 14000 via an audio frame buffer.
The sound input means 14000 includes a microphone or the like, collects sound, generates sound data, and writes the generated sound data in the audio frame buffer.

The dynamic reconfiguration arithmetic circuit 110 reads audio data from the audio frame buffer and performs audio encoding processing such as MPEG on the read audio data.
In the above (1) to (4), the dynamic reconfiguration arithmetic circuit 110 performs decoding processing and encoding processing compliant with standards such as JPEG and MPEG, but the video processing standard and audio processing standard are There are various types, and the contents of processing are different. This processing is different, and by processing a heavy load portion in the dynamic reconfiguration arithmetic block 2010 in the processor, it becomes possible to flexibly cope with processing of a plurality of standards.

(5) Communication Function The dynamic reconfiguration arithmetic circuit 110 is connected to the antenna 16000 and a radio frequency circuit block (not shown), and communication processing is performed by the dynamic reconfiguration arithmetic circuit 110 to configure a wireless network. The dynamic reconfiguration arithmetic circuit 110 also performs encryption / decryption processing of transmission / reception data.

There are various types of communication standards and encryption standards, and the contents of processing are different. This processing is different, and by processing a heavy load portion in the dynamic reconfiguration arithmetic block 2010 in the processor, it becomes possible to flexibly cope with processing of a plurality of standards.
(6) Reception of user operation The command input means 15000 includes a number of buttons as shown in FIG. For example, a play button, a stop button, a direction key, an enter button, and the like. The command input means 15000 accepts these button operations by the user, and sets the dynamic reconfiguration arithmetic circuit 110 so as to realize the various functions described in the above (1) to (5) according to the accepted operations. An instruction is output to each of the first components.
3.2 Summary Many communication systems, video processing systems, and security processing systems are equipped with a dynamic reconfiguration arithmetic circuit 110 like the mobile communication device 10000 of the present invention in order to support a plurality of standards. By changing the circuit configuration, processing conforming to each standard can be performed without installing a large number of hardware circuits.

Furthermore, the dynamic reconfiguration arithmetic circuit 110 is not limited to the mobile communication device described in this embodiment, but also a video display device such as a TV / DVD player / car navigation system, a DVD recorder / video camera / DSC / security camera, It can also be used for a video recording device such as an audio player, a device such as an audio player, a communication system in a communication device, and a security processing system.
4). Other Modifications Although the embodiment of the dynamic reconfiguration arithmetic circuit 110 according to the present invention has been described above, the present invention is not limited to the above-described embodiment itself. That is, the dynamic reconfiguration arithmetic circuit 110 shown in each embodiment may be partially modified as shown below.

(1) In Embodiment 1, the computation cells of the dynamic reconfiguration computation block 2010 are arranged in a 4 × 4 matrix format, but a 10 × 4 rectangular matrix format may be used. Moreover, you may arrange | position by the line unit and the structure of arrangement | positioning is not ask | required.
Further, the processing executed by the dynamic reconfiguration arithmetic cell 2100 can be multiplication, shift, addition, logical operation, division or subtraction, rotation operation, and the like. The types of processing that can be executed by the calculation cell 2100 that configures the dynamic reconfiguration calculation block 2010 are not particularly limited, and each calculation cell 2100 may be configured to execute a large number of processes. There may be few kinds. Further, all the calculation cells 2100 constituting the dynamically reconfigurable calculation block 2010 may have the same configuration, or, for example, calculation cells having different configurations may be mixed, for example, a specific calculation cell can be divided. good.

Moreover, although all the dynamic reconfiguration arithmetic cells 2100 can be switched in configuration, there may be an arithmetic cell 2100 in which some configurations are not switched.
The number of inputs / outputs of the dynamic reconfigurable operation cell 2100, such as 1-input 1-output and 3-input 2-output, may be changed. In that case, it can be coped with by increasing the number of inputs and the number of outputs of the operation cell 2100.

Note that the dynamic reconfiguration arithmetic cell 2100 may be operated with the same clock, or a plurality of clock lines may be provided to change the arithmetic operation clock for each arithmetic cell.
(2) In Embodiment 1, all the arithmetic cells 2100 are connected to one shift register 2300, but a plurality of shift registers 2300 may be provided. In that case, the number of operation cells connected to each shift register, the number of bits of configuration information, and the like may be different. The plurality of shift registers may be connected to one configuration information selector 3400, or may be connected to different configuration information selectors 3400 and configuration information storage means 3000.

  (3) In the first embodiment, reuse of configuration information is realized. As already described, the configuration information includes the type of calculation executed by each calculation cell, calculation parameters, and wiring information. Therefore, the configuration may be such that only the calculation parameters are reused, not the entire configuration information. In that case, each component may be configured to handle parameters for calculation instead of configuration information. Note that another means may be used for switching the calculation type and wiring information, and a separate set of hardware resources for switching the calculation type and wiring information is held, and switching is performed by the same operation as in the first embodiment. May be performed.

Further, when changing the operation parameter, the configuration information stored in each storage unit constituting the shift register 2300 may be circulated as in the first embodiment. In this case, the configuration information storage unit 3000 stores new calculation parameters of the dynamic reconfiguration calculation cell whose parameters should be changed.
The control unit 2000 circulates the configuration information held by each storage unit configuring the shift register 2300 in the same procedure as in the first embodiment.

When configuration information corresponding to the dynamic reconfiguration arithmetic cell whose parameter is to be changed is output (specifically, when the cell address comparator 4000 outputs 1), the configuration information selector 3400 outputs from the shift register 2300. In the configuration information, the calculation parameter portion is rewritten with the configuration information stored in the configuration information storage unit 3000 and input to the shift register 2300.
(4) In the first embodiment, the dynamic reconfiguration arithmetic circuit 110 individually holds the configuration information storage unit 3000 and the switching cell address storage unit 6000, but may be integrated into one storage unit. . In that case, if the configuration information and the cell address are stored in the same address in one storage means, the cell address of the output data is input to the cell address comparator 4000 and the configuration information is input to the configuration information selector 3400. Good.

(5) Although the configuration is changed in the vertical blanking region in the second embodiment, the configuration may be changed in the horizontal blanking region.
The moving picture image quality improving circuit 19000 includes two video frame buffers, but may be configured so as not to be included.
Although the moving image data generation unit 18000 detects the feature of the image, the moving image data generation unit 18000 may detect the feature of the image.

(6) The dynamic reconfiguration arithmetic circuit 110 described in the first embodiment is configured to include one dynamic reconfiguration arithmetic block 2010, but includes two or more dynamic reconfiguration arithmetic blocks. It may be.
In this case, each dynamic reconfiguration arithmetic block may be configured to include a control unit and configuration information storage means (hereinafter collectively referred to as a switching mechanism). The configuration of the reconfiguration arithmetic block may be changed.

An example in which the configuration of two dynamic reconfiguration arithmetic blocks is changed by one switching mechanism will be described below.
FIG. 16 is a block diagram excerpting and describing a part of the dynamic reconfiguration arithmetic circuit of this modification.
The same reference numerals are assigned to the same components as those in the first embodiment.

The dynamic reconfiguration arithmetic circuit includes a new dynamic reconfiguration arithmetic block 2020 and switches 1001 and 1002.
The dynamic reconfiguration arithmetic block 2020 includes 20 dynamic reconfiguration arithmetic cells 2400-17 to 2400-36 in a 4 × 5 matrix. Each dynamic reconfiguration arithmetic cell is connected to the shift register 2500, and cell addresses “17”, “18”, “19”... “36” are assigned in the order closer to the output terminal of the shift register. .

Similarly to the shift register 2300, the shift register 2500 is configured by serially connecting 20 storage units corresponding to the respective arithmetic cells. Each storage unit stores configuration information of a corresponding calculation cell.
Similar to the first embodiment, the cell address counter 5000 counts up the counter value every time Δt. At this time, the counter value and the pulse signal are output to the switch 1002.

The switch 1002 receives the pulse signal and the counter value from the cell address counter 5000. If the received counter value is equal to or less than the total number “16” of the arithmetic cells 2100 constituting the dynamic reconfiguration arithmetic block 2010, the signal line 5200 is coupled with the signal line 5400 and a pulse signal is sent to the dynamic reconfiguration arithmetic block 2010. Is entered.
If the received counter value is “17” or more, the switch 1002 couples the signal line 5200 and the signal line 5300 so that the pulse signal is input to the dynamic reconfiguration arithmetic block 2020.

With this configuration, a pulse signal is input to only one of the two dynamic reconfiguration arithmetic blocks. The shift register in one dynamic reconfiguration arithmetic block to which the pulse signal is input outputs the configuration information stored in the storage means closest to the output terminal to the configuration information output bus 3200, and the other storage means , Shift the configuration information to the adjacent storage means.
The cell address counter 5000 outputs the counter value to the switch 1001 via the cell address counter output line 5100.

The switch 1001 receives configuration information from the configuration information selector 3400 via the configuration information relay bus 3500. At this time, if the counter value received from the cell address counter 5000 is “16” or less, the configuration information relay bus 3500 and the configuration information input bus 3100 are connected.
If the received counter value is “17” or more, the configuration information relay bus 3500 and the configuration information input bus 3600 are connected.

Although not shown, the storage means address counter initializes the cell address counter 5000 to 0 at the start of the configuration change, and stops the cell address counter 5000 when the counter value of the cell address counter 5000 reaches 36.
With the above configuration, circuits having different functions can be constructed in the two dynamic reconfiguration arithmetic blocks.

Further, the storage means address counter 8000 is controlled so that the initial value of the cell address counter 5000 is “0” and the end value is “16”, so that there is no influence on the dynamic reconfiguration arithmetic block 2020. Only the dynamic reconfiguration arithmetic block 2010 can be changed without giving.
If the initial value of the cell address counter 5000 is “17” and the end value is “36”, only the dynamic reconfiguration arithmetic block 2020 is configured without affecting the dynamic reconfiguration arithmetic block 2010. You can make changes.

(7) In the above modification, an example is assumed in which a plurality of dynamic reconfiguration arithmetic blocks having the same number of dynamic reconfiguration arithmetic cells are mounted.
At this time, the storage means address counter controls the switch 1001 to connect the configuration information relay bus 3500 and all the configuration information input buses regardless of the counter value of the cell address counter, and the cell address comparator 4000. Is controlled to always output 0.

The initial value of the cell address counter is “0” and the end value is “16”. By doing in this way, the structure of all the dynamic reconfiguration arithmetic blocks can be made the same.
(8) In the above embodiment, the dynamic reconfiguration arithmetic block is composed of 16 dynamic reconfiguration arithmetic cells and a shift register, and the configuration information of each arithmetic block includes arithmetic operations executed by the arithmetic block. Type, calculation parameters, and calculation block from which data to be calculated is acquired.

However, the configuration of the dynamic reconfiguration arithmetic block is not limited to this, and for example, there is a configuration including an arithmetic cell that performs an operation and a connection resource that connects and disconnects a wiring between the arithmetic cells.
Even in such a case, as in the first embodiment, the configuration information is circulated by a shift register configured by serially connecting the storage units corresponding to the calculation cells and the connection resources, and the change is necessary. The configuration may be such that only the configuration information of the calculation cells and the connection resources is changed.

(9) Since the dynamic reconfiguration arithmetic circuit 110 according to the present invention only needs to hold the configuration information of the dynamic reconfiguration arithmetic cell 2100 that needs to be changed, the capacity of the configuration information storage unit 3000 can be suppressed.
Further, as a hardware resource for switching the configuration, an address line and a mask register whose area increases depending on the number of operation cells 2100 are not required.

This configuration is useful in a media processing apparatus using a large-scale reconfiguration arithmetic circuit in which the number of arithmetic cells 2100 to be updated is small and the number of arithmetic cells 2100 is large. It can also be used for communications and security.
(10) The present invention also provides a dynamic reconfiguration arithmetic block that can be changed to at least two types of configurations, a first wiring connected to an output terminal of the dynamic reconfiguration arithmetic block, and the dynamic reconfiguration arithmetic block. A second wiring connected to an input terminal of the configuration calculation block; a first storage; a third wiring connected to an output of the first storage; the first wiring; The dynamic reconfiguration arithmetic circuit device includes a selector that selects any one of the data of the third wiring and transmits the data to the second wiring.

  (11) In the modification (10), the dynamic reconfiguration arithmetic block is connected to a plurality of dynamic reconfiguration arithmetic cells that can be changed to at least two types of configurations, and the dynamic reconfiguration arithmetic cell. A plurality of second storage means, wherein the plurality of second storage means are connected in a chain, the output end of the chain is connected to the first wiring, and the input end of the chain is the second It may be a dynamic reconfiguration arithmetic circuit device characterized by being connected to wiring.

  (12) Further, in the above modification (11), the present invention provides a cell address counter in which the plurality of second storage units are uniquely assigned, and the address is changed in order, and the second storage. The selection means further comprises: a third storage means for storing the address for changing the held data; and a cell address comparator for comparing the cell address counter with an output of the third storage means. A dynamic reconfiguration arithmetic circuit device for determining which of the data of the first wiring and the third wiring is to be selected based on an output of the cell address comparator; Also good.

  (13) Further, in the dynamic reconfiguration arithmetic circuit device according to the modified example (12), the storage means address counter for calculating the read addresses of the first storage means and the third storage means, and the storage means address counter The third wiring connected to the output terminal of the storage means and the fourth wiring connected to the output terminal of the storage means address counter are held, and the third wiring is a read address input of the first storage means. The fourth wiring may be connected to an input end of a read address input of the third storage means.

(14) In the dynamic reconfiguration arithmetic device according to the modifications (10) to (13), the first storage unit stores configuration information of the dynamic reconfiguration arithmetic block, and the first and first The second wiring may transmit the configuration information, and the selector may select the configuration information.
(15) In the dynamic reconfiguration arithmetic device according to the modified examples (10) to (13), the first storage means stores arithmetic data of the dynamic reconfiguration arithmetic block, and The second wiring may transmit the calculation data, and the selector may select the calculation data.

(16) The dynamic reconfiguration arithmetic device according to any one of the modifications (10) to (15), wherein the dynamic reconfiguration arithmetic circuit according to any one of claims 1 to 6 is mounted, and calculation data that does not require processing is provided. The configuration may be such that the configuration of the dynamic reconfiguration arithmetic block is switched during the transfer period.
(17) Further, the present invention is an information processing apparatus equipped with the dynamic reconfiguration arithmetic device described in the above modifications (10) to (15).

(18) The configuration information storage unit 3000 and the cell address storage unit 6000 shown in FIG. 1 do not need to be arranged in the dynamic reconfiguration arithmetic circuit 110, and the dynamic reconfiguration arithmetic circuit 110 It is only necessary that a storage mechanism having a similar function exists in a device on which is mounted.
FIG. 17 is a block diagram showing an example of the configuration of the information processing apparatus 1200 having such a configuration. Here, as the information processing device 1200, various devices such as an image processing device, a mobile phone, and a game machine are applicable, and it is considered that the information processing device 1200 includes other functional units necessary for each device. For example, a mobile phone is considered to be provided with a microphone, a speaker, an antenna, an input key, and the like, but portions not directly related to the features of the present invention are omitted in the drawing.

  The information processing apparatus 1200 includes a dynamic reconfiguration arithmetic circuit 120, a main control unit 1000 configuration information storage unit 3000, and a switching cell address storage unit 6000. The configuration information storage unit 3000 is connected via a configuration information storage unit output line 3550. The switching cell address storage unit 6000 is connected to the main control unit 1000 via the switching cell address storage unit output line 6300. The dynamic reconfiguration arithmetic circuit 120 is connected to the main control unit 1000 via the control line 1100.

The configuration information storage unit 3000 and the switching cell address storage unit 6000 store information necessary for the configuration change of the dynamic reconfiguration arithmetic block 2010, as in the first embodiment.
When it is necessary to change the configuration of the dynamic reconfiguration arithmetic block 2010, the main control unit 1000 reads the corresponding information from the configuration information storage unit 3000 and the switching cell address storage unit 6000. For example, when the configuration is changed from the configuration A to the configuration B, the main control unit 1000 reads the cell addresses “10” and “11” stored in the area 6001 of the switching cell address storage unit 6000, and the configuration information storage unit The configuration information “2315” and “5778” stored in the 3000 area 3001 are read out.

Next, a switching instruction including the read cell address and configuration information is output to the dynamic reconfiguration arithmetic circuit 120.
The dynamic reconfiguration arithmetic circuit 120 has a configuration in which the configuration information storage unit 3000 and the switching cell address storage unit 6000 are excluded from the dynamic reconfiguration arithmetic circuit 110 described in the first embodiment.

  Further, unlike the storage unit address counter 8000 of the first embodiment, the storage unit address counter 8200 receives a switching instruction from the main control unit 1000 and temporarily stores the cell address and configuration information included in the received switching instruction. The stored cell address is output to the cell address comparator 4000 via the cell address output line 6200. Similarly, the stored configuration information is output to the configuration information selector 3400 via the configuration information transmission bus 3450. Further, while 0 is received from the cell address comparator 4000, the same cell address and configuration information are continuously output. However, when 1 is received, the cell address and configuration information to be output are changed.

The case where the configuration of the dynamic reconfiguration arithmetic block 2010 is changed from the configuration A to the configuration B will be specifically described below.
The storage means address counter 8200 receives a switching instruction including cell addresses “10” and “11” and configuration information “2315” and “5778” from the main control unit 1000. When the switching instruction is received, the counter value held by the cell address counter 5000 is initialized to zero. Subsequently, the cell address “10” received via the cell address output line 6200 is output to the cell address comparator 4000, and the configuration information “2315” is transmitted to the configuration information selector 3400 via the configuration information transmission bus 3450. Output.

The storage means address counter 8200 continues the above output while the output value from the cell address comparator 4000 is zero.
When 1 is received from the cell address comparator 4000, the cell address output to the cell address comparator 4000 is changed to “11”, and the configuration information output to the configuration information selector 3400 is changed to “5778”.

The functions of the other components in the dynamic reconfiguration arithmetic circuit 120 are the same as those in the first embodiment.
(19) Specifically, each of the above devices and circuits may be a computer system including a microprocessor, a ROM, a RAM, a hard disk unit, a display unit, a keyboard, a mouse, and the like. Computer programs are stored in the RAM, ROM, and hard disk unit. Each device achieves its function by the microprocessor operating according to the computer program. Here, the computer program is configured by combining a plurality of instruction codes indicating instructions for the computer in order to achieve a predetermined function.

FIG. 18 is a block diagram illustrating an example of an information processing apparatus 1700 that executes a configuration change of the dynamic reconfiguration arithmetic block 2010 using a program.
The information processing apparatus 1700 is considered to include various components in addition to the configuration described in the drawings, but only the portion related to the configuration change of the dynamic reconfiguration arithmetic block 2010 is described here. Yes.

  As shown in FIG. 18, the information processing apparatus 1700 includes a configuration information storage unit 3000, a switching cell address storage unit 6000, a main control unit 1300, and a dynamic reconfiguration arithmetic block 2010. The configuration information storage unit 3000 includes The switching cell address storage unit 6000 is connected to the main control unit 1300 via the switching cell address storage unit output line 6300. The switching cell address storage unit 6000 is connected to the main control unit 1300 via the information storage unit output line 3550. The dynamic reconfiguration arithmetic block 2010 is connected to the main control unit 1300 via a configuration information output bus 3200 and a configuration information input bus 3100. Further, the shift register in the dynamic reconfiguration arithmetic block 2010 receives a pulse signal from the main control unit 1300 via the pulse output line 5150.

The configurations of the configuration information storage unit 3000 and the switching cell address storage unit 6000 are the same as the configuration information storage unit 3000 and the switching cell address storage unit 6000 described in the first embodiment.
The main control unit 1300 is a computer system including a processor 1500 and a memory 1400. The memory 1400 stores various computer programs including a circuit reconfiguration program 1600. The processor 1500 operates according to a computer program stored in the memory 1400, whereby the information processing apparatus 1700 realizes a part of its functions.

Specifically, the circuit reconfiguration program 1600 stored in the memory 1400 describes the procedure for changing the configuration of the dynamic reconfiguration arithmetic block 2010 as shown in FIG. 8 in machine language readable by the processor 1500. It is a thing.
When the processor 1500 operates in accordance with the circuit reconfiguration program 1600, the main control unit 1300 periodically outputs a pulse signal, and each storage unit in the dynamic reconfiguration arithmetic block 2010 via the configuration information output bus 3200. The configuration information held in the configuration information is read out, and the configuration information corresponding to the computation cell that does not require the configuration change is input to the dynamic reconfiguration computation block 2010 via the configuration information input bus 3100, and the configuration change is required. The configuration information corresponding to the calculation cell is replaced with the configuration information held in the configuration information storage unit 3000 and input to the dynamic reconfiguration calculation block 2010. Thereby, the configuration change of the dynamic reconfiguration arithmetic block 2010 can be realized as in the first embodiment.

  (20) A part or all of the constituent elements constituting each of the above-described devices may be configured by one system LSI (Large Scale Integration). The system LSI is an ultra-multifunctional LSI manufactured by integrating a plurality of components on a single chip, and specifically, a computer system including a microprocessor, ROM, RAM, and the like. . A computer program is stored in the RAM. The system LSI achieves its functions by the microprocessor operating according to the computer program.

  (21) A part or all of the constituent elements constituting the above-described device or circuit may be constituted by a removable IC card or a single module. The IC card or the module is a computer system including a microprocessor, a ROM, a RAM, and the like. The IC card or the module may include the super multifunctional LSI described above. The IC card or the module achieves its function by the microprocessor operating according to the computer program. This IC card or this module may have tamper resistance.

(22) The present invention may be the method described above. Further, the present invention may be a computer program that realizes these methods by a computer, or may be a digital signal composed of the computer program.
The present invention also provides a computer-readable recording medium such as a flexible disk, hard disk, CD-ROM, MO, DVD, DVD-ROM, DVD-RAM, BD (Blu-ray Disc). ), Recorded in a semiconductor memory or the like. Further, the present invention may be the computer program or the digital signal recorded on these recording media.

Further, the present invention may transmit the computer program or the digital signal via an electric communication line, a wireless or wired communication line, a network represented by the Internet, a data broadcast, or the like.
The present invention may be a computer system including a microprocessor and a memory, wherein the memory stores the computer program, and the microprocessor operates according to the computer program.

In addition, the program or the digital signal is recorded on the recording medium and transferred, or the program or the digital signal is transferred via the network or the like and executed by another independent computer system. You may do that.
(23) Further, the present invention includes a case where not only all of the functional blocks but also a part of them are realized as an LSI. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them. The name used here is LSI, but it may also be called IC, system LSI, super LSI, or ultra LSI depending on the degree of integration.

Further, the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible.
(24) In the above embodiments and modifications, FPGAs and PLDs have been introduced as specific examples of the dynamic reconfiguration arithmetic block, but are not limited thereto. Furthermore, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out function block integration using this technology. Biotechnology can be applied as a possibility.

  (25) Moreover, you may combine said embodiment and modification.

  The present invention is an industry that manufactures and sells a dynamic reconfiguration arithmetic circuit, an industry that manufactures and sells various electric devices equipped with a dynamic reconfiguration arithmetic circuit, and an industry that provides services using the electric devices. It can be used continuously and repeatedly.

1 is a block diagram showing a configuration of a dynamic reconfiguration arithmetic circuit 110 according to Embodiment 1 of the present invention. FIG. 2 is a block diagram showing a configuration of a shift register 2300 in Embodiment 1 of the present invention. Operation scheduling diagram of configuration switching in dynamic reconfiguration arithmetic circuit 110 in Embodiment 1 of the present invention List of arithmetic cell 2100 numbers that require configuration switching in Embodiment 1 of the present invention Configuration information data value list of dynamic reconfiguration arithmetic block 2010 in each configuration in Embodiment 1 of the present invention Switching cell address setting diagram of each configuration area in switching cell address storage means 6000 in Embodiment 1 of the present invention Configuration information data setting diagram of each configuration area in configuration information storage means 3000 in Embodiment 1 of the present invention Control flow diagram of configuration switching in Embodiment 1 of the present invention Relationship diagram of each component in cycle units when switching from configuration A to configuration B in Embodiment 1 of the present invention FIG. 9 is a block diagram showing an image quality improving device 18001 using a dynamic reconfiguration arithmetic circuit 110 according to Embodiment 2 of the present invention. The figure which shows the calculation formula 1 of the filter process in the moving image image quality improvement circuit 19000 in Embodiment 2 of this invention. The figure which shows the calculation formula 2 of the filter process in the moving image image quality improvement circuit 19000 in Embodiment 2 of this invention. The figure which shows the processing order of the image in Embodiment 2 of this invention. Relationship diagram between vertical blanking area and effective area in image transmission in Embodiment 2 of the present invention External view of mobile communication device 10000 using dynamic reconfiguration arithmetic circuit 110 in Embodiment 3 of the present invention The figure which shows the modification of the dynamic reconfiguration arithmetic circuit of this invention It is a block diagram which shows one specific example of a modification (18). It is a block diagram which shows one specific example of a modification (19). Schematic diagram of dynamic reconfiguration arithmetic circuit device of Patent Document 1

Explanation of symbols

2100 Dynamic reconfiguration arithmetic cell 2300 Shift register 2301 Storage means 2301 to 2316 Storage means 2400 Dynamic reconfiguration arithmetic cell 2500 Shift register 3000 Configuration information storage means 3100 Configuration information input bus 3200 Configuration information output bus 3300 Configuration information transmission bus 3400 Configuration Information selector 3450 Configuration information transmission bus 4000 Cell address comparator 4100 Cell address comparator output line 5000 Cell address counter 5100 Cell address counter output line 5150 Pulse output line 6000 Switching cell address storage means 6100 Switching cell address output line 8000 Storage means address Counter 8100 Storage means Address counter output line 10000 Mobile communication device 11000 Display 12000 Imaging means 13000 Sound output means 14000 Sound input means 1 5000 Command input means 16000 Antenna 17000a Video frame buffer 17000b Video frame buffer 18000 Moving image data generation unit 18001 High image quality improving device 19000 Moving image high image quality improving circuit 19100 Image feature amount data line

Claims (18)

An integrated circuit capable of changing its internal configuration,
A plurality of reconfigurable operation cells, a plurality of cell storage units corresponding to each of the plurality of operation cells, and storing original configuration information indicating all or a part of the configuration of the corresponding operation cells; An output set consisting of a plurality of original configuration information stored in the plurality of cell storage units, and a part of the original configuration information in the output set and at least one original configuration information instead of the original configuration information A reconfiguration arithmetic block that receives an input set consisting of alternative configuration information and reconfigures each arithmetic cell according to the original configuration information and the alternative configuration information included in the received input set;
Storage means for storing one or more alternative configuration information indicating all or part of a new configuration of a calculation cell whose configuration is to be changed among the plurality of calculation cells;
Control the reconfiguration arithmetic block to obtain the output set from the reconfiguration arithmetic block, and for the arithmetic cell whose configuration is to be changed, instead of the corresponding original configuration information in the output set, the storage means Select the stored alternative configuration information, select the corresponding original configuration information of the output set for the computation cell that does not change the configuration, and the selected original configuration information and the selected alternative configuration information An integrated circuit comprising: control means for outputting an input set to the reconstruction calculation block. The control means repeatedly outputs a timing signal to the reconstruction calculation block, acquires one original configuration information constituting the output set for each output, and the acquired original configuration information changes the configuration. 2. The method according to claim 1, wherein selecting one of the acquired original configuration information and the alternative configuration information and outputting the selected configuration information to the reconfiguration calculation block is repeated depending on whether the calculation cell corresponds to a power calculation cell. Integrated circuit. The plurality of calculation cells are connected to corresponding cell storage units,
The plurality of cell storage units are connected in series to form a shift register, and each time a timing signal is received from the control means, the cell storage unit located at the end of the shift register stores the original configuration information held by itself. Output, the other cell storage unit shifts the original configuration information or the alternative configuration information stored in the cell storage unit adjacent to the terminal direction of the shift register, the cell storage unit at the tip of the shift register, The integrated circuit according to claim 2, wherein storing one piece of original configuration information or alternative configuration information included in the output set is repeated. The plurality of operation cells are identified by different identification numbers,
The plurality of identification numbers are consecutive in the order in which corresponding operation cells are connected to the shift register,
The control means includes
Storing at least one change target identification number indicating a calculation cell whose configuration is to be changed;
Holds the counter value, repeatedly outputs the timing signal, adds a fixed value to the held counter value each time it is output, and compares the counter value after addition with the stored identification number for change The integrated circuit according to claim 3, wherein when the data matches, the alternative information is selected, and when the data does not match, the output of the original configuration information is repeated. The control means includes
A switching cell address storage unit that stores one or more change target identification numbers indicating calculation cells to be changed in the order of the change target identification numbers;
A cell address counter that holds the counter value, repeatedly outputs the timing signal, and adds a constant value to the counter value each time it is output;
An address counter for determining a read address of the storage means and the switching cell address storage unit;
A cell address comparison unit that compares the counter value after addition with the identification number stored in the read address determined by the address counter in the cell address storage unit each time the timing signal is output;
If they match as a result of the comparison, the alternative configuration information stored in the storage means at the position indicated by the read address determined by the address counter is selected. For example, selecting the original configuration information output from the shift register, and outputting the selected one to the cell storage unit at the tip of the shift register includes an information selection unit that repeats for each comparison,
The integrated circuit according to claim 4, wherein the storage unit stores one or more pieces of the alternative configuration information in association with one or more of the change target identification numbers. 6. The address counter determines a value obtained by adding 1 to the read address as a new read address when it is determined as a result of the comparison by the cell address comparison unit that the two match. An integrated circuit according to 1. The address counter stores a start address of the switching cell address storage unit, obtains a change instruction for requesting a configuration change of the reconfiguration arithmetic block from the outside, and obtains the change instruction, The integrated circuit according to claim 6, wherein the integrated circuit is determined as the read address. The address counter stores an end address of the switching cell address storage unit, and stops addition to the read address when the read address matches the end address. An integrated circuit as described. 5. The integrated circuit according to claim 4, wherein the control unit stops the repetition when the counter value matches an identification number indicating a calculation cell corresponding to a cell storage unit at a tip of the shift register. 6. . The plurality of cell storage units store, as the original configuration information, original calculation parameters indicating a part of the configuration of the calculation cell,
The storage means stores, as the alternative configuration information, an alternative calculation parameter indicating a part of the configuration of the calculation cell,
4. The integrated circuit according to claim 3, wherein the reconfiguration arithmetic block rewrites arithmetic parameters constituting each arithmetic cell according to the original arithmetic parameter or the alternative arithmetic parameter included in the input set. 5. The reconfiguration arithmetic block and the control means are connected by a first wiring and a second wiring, the storage means and the control means are connected by a third wiring,
The reconstruction calculation block outputs the output group to the control means via the first wiring,
The control means acquires the output group via the one wiring, acquires the one or more alternative configuration information via the third wiring, and the reconfiguration arithmetic block via the second wiring. The integrated circuit according to claim 3, wherein the input group is output. An image processing apparatus equipped with the integrated circuit according to claim 3,
An image processing apparatus that causes the circuit reconstruction device to reconstruct the reconstruction operation block in a vertical blanking period or a horizontal blanking period. An information processing apparatus equipped with the integrated circuit according to claim 3,
An information processing apparatus that causes the circuit reconfiguration apparatus to reconfigure the reconfiguration arithmetic block during a period when it is not necessary to perform processing by a circuit configured on the reconfiguration arithmetic block. An integrated circuit capable of changing its internal configuration,
A plurality of reconfigurable operation cells, a plurality of cell storage units corresponding to each of the plurality of operation cells, and storing original configuration information indicating all or a part of the configuration of the corresponding operation cells; An output set consisting of a plurality of original configuration information stored in the plurality of cell storage units, and a part of the original configuration information in the output set and at least one original configuration information instead of the original configuration information A reconfiguration arithmetic block that receives an input set consisting of alternative configuration information and reconfigures each arithmetic cell according to the original configuration information and the alternative configuration information included in the received input set;
An acquisition means for acquiring one or more of the alternative configuration information indicating all or a part of a new configuration of a calculation cell whose configuration is to be changed among the plurality of calculation cells;
Control the reconfiguration arithmetic block to acquire the output set from the reconfiguration arithmetic block, and acquire the acquisition means instead of the corresponding original configuration information of the output set for the arithmetic cell whose configuration is to be changed For the calculation cell that does not change the configuration, the corresponding original configuration information of the output set is selected, and the input set including the selected original configuration information and the selected alternative configuration information is selected. An integrated circuit comprising: control means for outputting to the reconfiguration arithmetic block. A circuit reconfiguration method used in an integrated circuit capable of changing its internal configuration,
The integrated circuit corresponds to a plurality of reconfigurable operation cells and each of the plurality of operation cells, and stores a plurality of original configuration information indicating all or part of the configuration of the corresponding operation cells. A plurality of original configuration information stored in the plurality of cell storage units, and output to a part of the original configuration information and the original configuration information. A reconfiguration arithmetic block that receives an input set composed of one or more alternative configuration informations to be replaced, reconfigures each arithmetic cell according to the original configuration information and the alternative configuration information included in the received input set, and among the plurality of arithmetic cells Storage means for storing one or more of the alternative configuration information indicating all or part of the new configuration of the arithmetic cell whose configuration is to be changed,
The circuit reconfiguration method controls the reconfiguration arithmetic block, acquires the output set from the reconfiguration arithmetic block, and sets the corresponding original configuration information in the output set for an arithmetic cell whose configuration is to be changed. Instead, select the alternative configuration information stored in the storage means, select the corresponding original configuration information in the output set, and select the selected original configuration information and the selected operation cell for a computation cell that does not change the configuration. A circuit reconfiguration method comprising: a control step of outputting the input set comprising alternative configuration information to the reconfiguration arithmetic block. A circuit reconfiguring device,
A plurality of reconfigurable operation cells, a plurality of cell storage units corresponding to each of the plurality of operation cells, and storing original configuration information indicating all or a part of the configuration of the corresponding operation cells; An output set consisting of a plurality of original configuration information stored in the plurality of cell storage units, and a part of the original configuration information in the output set and at least one original configuration information instead of the original configuration information A reconfiguration arithmetic block that receives an input set consisting of alternative configuration information and reconfigures each arithmetic cell according to the original configuration information and the alternative configuration information included in the received input set;
Storage means for storing one or more alternative configuration information indicating all or part of a new configuration of a calculation cell whose configuration is to be changed among the plurality of calculation cells;
Control the reconfiguration arithmetic block to obtain the output set from the reconfiguration arithmetic block, and for the arithmetic cell whose configuration is to be changed, instead of the corresponding original configuration information in the output set, the storage means Select the stored alternative configuration information, select the corresponding original configuration information of the output set for the computation cell that does not change the configuration, and the selected original configuration information and the selected alternative configuration information And a control means for outputting an input set to the reconfiguration arithmetic block. A circuit reconfiguration method used in an integrated circuit capable of changing its internal configuration,
The integrated circuit corresponds to a plurality of reconfigurable operation cells and each of the plurality of operation cells, and stores a plurality of original configuration information indicating all or part of the configuration of the corresponding operation cells. A plurality of original configuration information stored in the plurality of cell storage units, and output to a part of the original configuration information and the original configuration information. A reconfigurable operation block that receives an input set composed of one or more alternative configuration information to be replaced, and reconfigures each operation cell according to the original configuration information and the alternative configuration information included in the received input set;
The circuit reconfiguration method includes:
An acquisition step of acquiring one or more of the alternative configuration information indicating all or a part of a new configuration of a calculation cell whose configuration is to be changed among the plurality of calculation cells;
The reconfiguration arithmetic block is controlled to acquire the output set from the reconfiguration arithmetic block, and for the arithmetic cell whose configuration is to be changed, instead of the corresponding original configuration information in the output set, the acquisition means The input set consisting of the selected original configuration information and the selected alternative configuration information by selecting the corresponding original configuration information of the output set for the computation cell that selects the acquired alternative configuration information and does not change the configuration. And a control step of outputting to the reconfiguration arithmetic block. A circuit reconfiguring device,
A plurality of reconfigurable operation cells, a plurality of cell storage units corresponding to each of the plurality of operation cells, and storing original configuration information indicating all or a part of the configuration of the corresponding operation cells; An output set consisting of a plurality of original configuration information stored in the plurality of cell storage units, and a part of the original configuration information in the output set and at least one original configuration information instead of the original configuration information A reconfiguration arithmetic block that receives an input set consisting of alternative configuration information and reconfigures each arithmetic cell according to the original configuration information and the alternative configuration information included in the received input set;
An acquisition means for acquiring one or more of the alternative configuration information indicating all or a part of a new configuration of a calculation cell whose configuration is to be changed among the plurality of calculation cells;
Control the reconfiguration arithmetic block to acquire the output set from the reconfiguration arithmetic block, and acquire the acquisition means instead of the corresponding original configuration information of the output set for the arithmetic cell whose configuration is to be changed For the calculation cell that does not change the configuration, the corresponding original configuration information of the output set is selected, and the input set including the selected original configuration information and the selected alternative configuration information is selected. And a control means for outputting to the reconfiguration arithmetic block.

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