JP4960545B2 - MEMORY WRITE DEVICE, MEMORY WRITE METHOD, AND RECORDING MEDIUM CONTAINING MEMORY WRITE PROGRAM - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a memory writing device that writes data to a memory of an arithmetic device on a network, and in particular, reduces communication errors by performing a write process on the memory after changing the communication speed of the arithmetic device in advance. The present invention also relates to a memory writing apparatus capable of performing high-speed writing processing.
[0002]
[Prior art]
As a conventional memory writing device, for example, there is a memory rewriting system disclosed in Japanese Patent Laid-Open No. 10-111863.
[0003]
As shown in FIG. 3, a conventional memory rewriting system 101 includes an engine control device (hereinafter referred to as an ECU) 102 that controls an internal combustion engine and is installed in an automobile, and an engine control device built in the ECU 102. The memory rewriting device 103 is connected to the ECU 102 when a program or data is rewritten or newly written.
[0004]
Further, the ECU 102 inputs signals from various sensors that detect the operating state of the engine and performs waveform processing, and performs various processes for controlling the engine based on the sensor signals from the input circuit 106. A single-chip microcomputer (hereinafter referred to as a microcomputer) 108 to be executed, and an output circuit 110 for outputting a drive signal to an actuator (fuel injection valve) or an igniter attached to the engine based on a control signal from the microcomputer 108 It has.
[0005]
The microcomputer 108 includes a CPU 118 that operates according to a program, a nonvolatile ROM 120 that stores programs and data necessary for operating the CPU 118, a RAM 122 that temporarily stores calculation results of the CPU 118, and the input circuit 106. In addition, an I / O 124 for receiving a signal from the above and outputting a control signal to the output circuit 110 and a communication circuit 125 for performing serial data communication with the memory rewriting device 103 are provided.
[0006]
Here, the ROM 120 includes a flash ROM 120a capable of electrically rewriting data (specifically, erasing and writing) and a mask ROM 120b incapable of rewriting data.
[0007]
On the other hand, the memory rewriting device 103 includes a microcomputer 130 having a built-in CPU, ROM, RAM, and the like for executing processing for causing the microcomputer 108 on the ECU 102 side to rewrite the flash ROM 120a, and a rewrite control program to be transmitted to the ECU 102 (in detail). The first ROM 134 storing the program code constituting the rewrite control program and the data to be referred to when the rewrite control program is executed, and the write data to be transmitted to the ECU 102 (that is, new control to be written to the flash ROM 120a) A second ROM 136 in which data constituting a program and control data are stored, and an input device 137 for an operator to input various instructions to the memory rewriting device 103.
[0008]
In the memory rewriting system 101 configured as described above, the microcomputer 108 (CPU 118) of the ECU 102 activates the boot program in the mask ROM 120b immediately after the reset, and at normal times when the memory rewriting device 103 is not connected. The engine control program (control program for engine control) in the flash ROM 120a is called by the boot program to control the engine.
[0009]
If the microcomputer 108 determines that the rewrite mode is set when the boot program is activated, the microcomputer 108 receives the rewrite control program transmitted from the memory rewrite device 103 without calling the control program in the flash ROM 120a. The current control program and control data stored in the flash ROM 120a are stored in the RAM 122, and executed on the RAM 122 by calling the rewrite control program. A process of rewriting the data (new control program and data constituting the control data) is performed.
[0010]
[Problems to be solved by the invention]
However, in the above-described memory rewriting system 101, the write control program (boot program) includes a communication speed change process, so even when there are multiple ECUs on the network, The communication speed was only changed.
[0011]
Therefore, when there are a plurality of ECUs on the network, there is a problem that a communication error occurs because the communication speed of other ECUs on the network is not changed.
[0012]
In addition, when the ECU of the high-speed communication network and the ECU of the low-speed communication network exist at the same time, the conventional memory rewriting system 101 reduces the communication speed after performing the writing process on the ECU on the high-speed communication network. Since then, writing to the ECU on the low-speed communication network was performed.
[0013]
Therefore, there is a problem that it takes a long time to rewrite the memory of the ECU on the networks having different communication speeds.
[0014]
The present invention has been made in view of the above circumstances, and an object of the present invention is to perform memory writing that can perform a high-speed writing process without a communication error even when a plurality of write target memories exist on the network. To provide an apparatus.
[0015]
[Means for Solving the Problems]
In order to achieve the above object, the memory writing device according to the first aspect of the present invention is provided when a plurality of write target arithmetic devices each having a write target memory that is electronically writable exist on a network. A memory writing device for writing to the write target memory, wherein a ready signal, which is a signal for bringing the arithmetic device into a normal communication stop state, is simultaneously transmitted to all the write target arithmetic devices to perform the writing a normal communication stopping means for all of the target computing device in the normal communication stop state, by the ready signal transmitted by the normal communication stop means, all of the write target computing device whether the normal communication stopped state Communication state confirmation means for confirming the communication state confirmation means, and when the communication state confirmation means confirms that all the write target arithmetic devices are in the normal communication stopped state, the write pair And all of said write target computing device to simultaneously transmit communication speed changing means for changing the communication speed to the same speed for all the write target computing device change signal is a signal for changing the communication speed of the computing device And a memory writing means for performing a writing process on the write target memory when receiving a return signal of the change signal transmitted by the communication speed changing means from all the write target arithmetic devices. It is characterized by.
[0016]
According to the first aspect of the present invention, even when there are a plurality of write target arithmetic devices on the network, there is no communication error, and the write process to the write target memory can be performed at high speed.
[0017]
According to a second aspect of the present invention, there is provided a memory writing method according to a second aspect of the present invention, wherein when there are a plurality of write target arithmetic devices each having a write target memory that can be written electronically on the network, A memory writing method for performing writing, wherein a ready signal, which is a signal for putting an arithmetic device into a normal communication stop state, is simultaneously transmitted to all the write target arithmetic devices , and all of the write target arithmetic devices are in normal communication A normal communication stop step for making a stop state, and a communication state check step for checking whether all of the write target arithmetic devices are in a normal communication stop state based on the ready signal transmitted in the normal communication stop step; When it is confirmed in this communication state confirmation step that all the write target arithmetic devices are in a normal communication stopped state, the write target arithmetic device And changing the communication speed step of changing the communication speed of all of said write target computing unit by transmitting at the same time the change signal is a signal for changing the communication speed for all of the write target computing device at the same speed, the communication A memory writing step of performing a writing process on the write target memory when receiving a return signal of the change signal transmitted in the speed changing step from all of the write target arithmetic devices. To do.
[0018]
According to the second aspect of the present invention, even when there are a plurality of write target arithmetic devices on the network, there is no communication error, and the write process to the write target memory can be performed at high speed.
[0019]
According to a third aspect of the present invention, there is provided a recording medium on which a memory writing program is recorded, when there are a plurality of write target arithmetic devices including a write target memory that can be written electronically on a network. A recording medium in which a memory writing program for writing into a memory to be embedded is recorded, and a ready signal, which is a signal for bringing the arithmetic device into a normal communication stop state, is simultaneously transmitted to all of the write target arithmetic devices to Whether or not all of the write target arithmetic devices are in the normal communication stop state by the normal communication stop processing for setting all the write target arithmetic devices in the normal communication stop state and the ready signal transmitted by the normal communication stop processing. Communication state confirmation processing for confirming whether or not, and this communication state confirmation processing confirms that all the write target arithmetic devices are in a normal communication stopped state. Sometimes, change the speed of all of the write target computing unit by transmitting at the same time the change signal is a signal for changing the communication speed for all of the write target computing device of the write target computing device at the same rate A communication speed change process to be performed, and when a return signal of the change signal transmitted by the communication speed change process is received from all the write target arithmetic devices, a memory book for performing a write process on the write target memory Including the processing.
[0020]
According to the third aspect of the present invention, even when there are a plurality of write target arithmetic units on the network, there is no communication error, and the write process to the write target memory can be performed at high speed.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
[0022]
First, FIG. 1 is a block diagram of a memory writing system in which writing to a memory is performed by the memory writing device of the present embodiment. Here, a flash memory will be described as an example of a write target memory that is a target of writing, and an engine control device (hereinafter abbreviated as an ECU) will be described as an example of a write target arithmetic device equipped with the flash memory. To do.
[0023]
As shown in FIG. 1, a memory writing device 1 that performs a writing process to a memory is connected to a bus 2 that is a network when the writing process is performed, and a plurality of ECUs 3A, 3B,.・ 3N is connected.
[0024]
Here, the memory writing device 1 includes a normal communication stopping unit 11 that transmits a ready signal, which is a signal for stopping the ECU to a normal communication state, to all the ECUs 3A, 3B,. 3N, communication state confirmation means 12 for confirming whether or not all of the ECUs are in a normal communication stop state by the ready signal transmitted by 11, and all the ECUs 3A, 3B,. Is confirmed to be in the normal communication stop state, the communication speed changing means 13 for transmitting a change signal, which is a signal for changing the communication speed of the ECU, to all the ECUs 3A, 3B,. When the return signal of the change signal transmitted by the changing means 13 is received from all the ECUs 3A, 3B,..., 3N Flash memory 17A, 17B, ···, and a memory writing unit 14 that writes processing to 17N.
[0025]
The memory writing device 1 is constituted by a normal computer system including a CPU for performing various processes and a storage means for storing instructions for the processing, and each processing performed in the memory writing device 1 is performed. Instructions and timing constraints are held in the storage means, and are loaded into the CPU and executed as necessary.
[0026]
The ECUs 3A, 3B,..., 3N drive signals to input circuits that perform waveform processing by inputting signals from various sensors that detect the operating state of the engine, and actuators such as injectors attached to the engine. , 15N, and 15N, 15B,..., 15N for executing various processes for controlling the engine. Yes.
[0027]
The microcomputers 15A, 15B,..., 15N include normal CPUs 16A, 16B,..., 16N that operate according to programs, and flash memories 17A that store programs and data necessary for the CPU 16 to operate. , 17N and RAMs 18A, 18B,..., 18N for temporarily storing the calculation results of the CPU 16, etc., respectively, and the memory write to the flash memories 17A, 17B,. The writing by the inserting device 1 is performed.
[0028]
However, the write target memory to be written to by the memory writing device 1 is not limited to the flash memory, and may be any electronically writable memory.
[0029]
Next, a writing process to the write target memory by the memory writing device 1 of the present embodiment will be described based on FIG.
[0030]
First, when the memory writing device 1 is connected to the bus 2 and initialization is performed (S201), the memory writing device 1 is connected to each ECU 3A, 3B,..., 3N operating in the normal mode. Then, a ready signal, which is a signal for stopping the normal mode, is transmitted by the broadcast method (S202).
[0031]
The ECUs 3A, 3B,..., 3N that have received this ready signal immediately end the normal mode and enter a normal communication stopped state (S203).
[0032]
On the other hand, when the ready signal is transmitted, the memory writing device 1 shifts to the bus monitor state and executes a bus line check by interrupt processing or the like for a predetermined time (S204). At this time, it is determined whether or not there is an ECU still operating in the normal mode (S205), and when there is an ECU operating in the normal mode, the process returns to step S202 to transmit a ready signal again (S202).
[0033]
When it is confirmed that all the ECUs are in the normal communication stopped state, the memory writing device 1 sends a change signal, which is a signal for changing the communication speed, to each of the ECUs 3A, 3B,. While transmitting by the broadcast method (S206), the communication speed of the memory writing device 1 is also changed to the communication speed transmitted by the change signal to increase the speed (S207). For example, the communication speed of 20 kbps is increased to 100 kbps.
[0034]
When the ECU 3A, 3B,..., 3N receive the change signal, the ECU 3A changes the communication speed recorded in the change signal to increase the speed (S208), and returns a change response signal that is a response to the change signal. At the same time (S209), a transition is made to a state in which write processing is performed (S210). However, the change response signal is transmitted after a set time such as 100 ms elapses in order to synchronize.
[0035]
Then, the memory writing device 1 determines whether or not the change response signal has been received from all the ECUs 3A, 3B,..., 3N (S211), and cannot receive the change response signal from all the ECUs. In addition, when there is an ECU whose communication speed is not increased including the memory writing device 1, the processing related to writing to the flash memory 17 to be written is not performed, and after power-on reset (S 212), the process returns to step S 201. The same processing is performed again.
[0036]
Further, when the memory writing device 1 receives a change response signal from all the ECUs 3A, 3B,..., 3N, a process related to writing is performed on the flash memory of each ECU (S213), and this embodiment The memory writing process by the memory writing device 1 ends.
[0037]
As described above, the memory writing device 1 of the present embodiment does not control the communication speed changing process in the writing process in the boot program, but controls the communication speeds of all ECUs in advance before performing the writing process. Since the speed is increased, it is possible to prevent a communication error from occurring because the communication speed between the memory writing device 1 and each ECU does not match.
[0038]
Further, the memory writing device 1 of the present embodiment increases the communication speed of all ECUs in advance even when writing to ECUs on networks with different communication speeds. It is not necessary to switch the communication speed after processing and perform writing processing to the low-speed network, so that high-speed writing processing can be performed.
[0039]
Note that a program for realizing each process of the memory writing device 1 described above can be stored in a recording medium. By reading the recording medium by a computer system, the program is executed to control the computer. However, each process of the memory writing device 1 described above can be realized. Here, the recording medium includes a device capable of recording a program, such as a memory device, a magnetic disk device, and an optical disk device.
[0040]
【Effect of the invention】
As described above, according to the memory writing device of the present invention, even when there are a plurality of arithmetic devices on the network, there is no communication error, and writing processing to the memory can be performed at high speed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of an embodiment of a memory writing system of the present invention.
FIG. 2 is a flowchart for explaining a write process to a write target memory by the memory writing system shown in FIG. 1;
FIG. 3 is a block diagram showing a configuration of a conventional memory rewriting system.
[Explanation of symbols]
1 Memory writing device 2 Buses 3A, 3B,..., 3N ECU
11 Normal communication stop means 12 Communication state confirmation means 13 Communication speed change means 14 Memory writing means 15A, 15B,..., 15N Microcomputers 16A, 16B,.
17A, 17B,..., 17N Flash memory

Claims (3)

A memory writing device that performs writing to the write target memory when there are a plurality of write target arithmetic devices provided with the electronically writable write target memory on the network,
Normal communication stopping means for simultaneously transmitting a ready signal, which is a signal for setting the arithmetic device to a normal communication stop state, to all the write target arithmetic devices to place all of the write target arithmetic devices in a normal communication stop state;
Communication state confirmation means for confirming whether or not all of the write target arithmetic devices are in a normal communication stopped state by the ready signal transmitted by the normal communication stopping means;
When it is confirmed by the communication state confirmation means that all the write target arithmetic devices are in a normal communication stopped state, a change signal that is a signal for changing the communication speed of the write target arithmetic device is sent to all the write operations. Communication speed changing means for simultaneously transmitting to the target arithmetic device and changing the communication speed of all the write target arithmetic devices to the same speed ;
A memory writing unit that performs a writing process on the write target memory when receiving a return signal of the change signal transmitted by the communication speed changing unit from all the write target arithmetic units. A memory writing device. A memory writing method for performing writing to the write target memory when there are a plurality of write target arithmetic devices provided with the electronically writable write target memory on a network,
A normal communication stop step of simultaneously sending a ready signal, which is a signal for setting the arithmetic device to a normal communication stop state, to all the write target arithmetic devices to make all of the write target arithmetic devices a normal communication stop state;
A communication state confirmation step for confirming whether or not all of the write target arithmetic devices are in a normal communication stop state by the ready signal transmitted in the normal communication stop step;
When it is confirmed in this communication state confirmation step that all the write target arithmetic devices are in a normal communication stopped state, a change signal that is a signal for changing the communication speed of the write target arithmetic device is sent to all the write operations. A communication speed change step for simultaneously transmitting to the target arithmetic device and changing the communication speed of all the write target arithmetic devices to the same speed ;
And a memory writing step of performing a writing process on the write target memory when receiving a return signal of the change signal transmitted in the communication speed changing step from all the write target arithmetic devices. A memory writing method. A recording medium that records a memory writing program for writing to a write target memory when there are a plurality of write target arithmetic devices having a write target memory that is electronically writable on the network. ,
An arithmetic unit and a normal communication stop process a ready signal by sending all of the write target computing device simultaneously for normal communication stop state all the write target computing device is a signal to the normal communication stop state,
A communication state confirmation process for confirming whether or not all of the write target arithmetic devices are in a normal communication stop state by the ready signal transmitted by the normal communication stop process;
When it is confirmed that all the write target arithmetic devices are in a normal communication stop state by this communication state confirmation processing, a change signal that is a signal for changing the communication speed of the write target arithmetic device is sent to all the write operations. A communication speed change process for simultaneously transmitting to the target arithmetic device and changing the communication speed of all the write target arithmetic devices to the same speed ;
And a memory write process for performing a write process on the write target memory when receiving a return signal of the change signal transmitted by the communication speed changing process from all the write target arithmetic units. A recording medium on which a memory writing program is recorded.

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