JP4957297B2 - Manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device having a transistor of two different operating voltages from each other.

  In order to fabricate high-efficiency transistors for power circuits, the limit is seen with silicon substrates. For this reason, power circuits using substrates using semiconductors with a larger band gap than silicon, such as SiC substrates and GaN substrates. The development of a transistor is being promoted (see Patent Document 1).

  When a semiconductor having a larger band gap than silicon is used as a substrate, the characteristics of the substrate are different from those of a conventional silicon substrate. For example, the diffusion coefficient of impurities is remarkably small. For this reason, the formation process of a transistor differs from the process of forming a transistor on a silicon substrate. For example, the activation process after the introduction of impurities and the heat treatment for recovering defects on the surface of the substrate generated during the introduction of impurities become high temperature. In addition, in order to manufacture a power circuit transistor, it is necessary to perform element isolation with a high breakdown voltage, and the element isolation structure becomes large.

  In addition, a transistor in which a semiconductor having a larger band gap than silicon is formed on a substrate is difficult to operate at a low voltage. For this reason, it is difficult to form the control circuit transistor on the power circuit transistor substrate, and the control circuit is formed on a different substrate from the power circuit transistor.

JP 2004-327782 A (60th paragraph, FIG. 2)

  As described above, when a semiconductor having a larger band gap than silicon is used as a substrate, it is difficult to form a transistor that operates at a low voltage on the substrate. For this reason, the control circuit is formed on a separate substrate from the power circuit transistor, and as a result, the semiconductor device has become larger.

The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is, for example, a semiconductor device in which two types of transistors having different operating voltages can be mounted on a substrate having a larger band gap than a silicon substrate. It is in providing the manufacturing method of.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a first transistor on a semiconductor substrate, and a first interlayer insulation on or above the first transistor and the semiconductor substrate. Forming a film, forming a metal wiring layer overlying the first transistor on the first interlayer insulating film, and forming a second interlayer insulating film on the metal wiring layer A step of forming a recess on the upper surface of the second interlayer insulating film, and forming a polycrystalline semiconductor film on the second interlayer insulating film and in the recess with a material different from that of the semiconductor substrate. And forming the semiconductor film located in the recess by annealing the polycrystalline semiconductor film by irradiating the polycrystalline semiconductor film with laser light and irradiating lamp light. The comprises the step of crystallizing the semiconductor film located on the second interlayer insulating film as a starting point, and forming a second transistor in said semiconductor film.

In the step of forming a recess in the upper surface of the second interlayer insulating film, it is desirable to form the recess so as not to overlap with the first transistor.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 and 2 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention. The semiconductor device manufactured by this method is, for example, a power supply module or a motor driver, and has a power transistor that is a part of a power circuit on the SiC substrate 1 and silicon formed above the SiC substrate 1. A control transistor which is part of the control circuit is included in the layer. The power transistor and the control transistor have different operating voltages.

First, as shown in FIG. 1A, a groove is formed in the SiC substrate 1, and an element isolation film 2 (for example, a plasma oxide film) is embedded in the groove. Next, the SiC substrate 1 is thermally oxidized. Thereby, gate insulating film 3 is formed on SiC substrate 1. The thickness of the gate insulating film 3 is thicker than the gate insulating film 23 described later, and is, for example, 200 nm to 400 nm. Next, a resist pattern (not shown) is formed on the gate insulating film 23 and the element isolation film 2, and impurities are introduced into the SiC substrate 1 at a high temperature (for example, 500 ° C.) using the resist pattern as a mask. A heat treatment (for example, 1700 ° C.) for activating the impurities is performed. Thereby, impurity regions 7 serving as a source and a drain are formed in SiC substrate 1. Thereafter, the resist pattern is removed. Next, a polysilicon film is formed on the entire surface including the gate insulating film 3, and this polysilicon film is selectively removed. Thereby, the gate electrode 4 is formed on the gate insulating film 3.
In this way, a power circuit transistor is formed on the SiC substrate 1. The withstand voltage of the power circuit transistor is, for example, 100 V or more and 1000 V or less.

  Next, an interlayer insulating film 8 is formed on the power circuit transistor and the element isolation film 2, and the surface of the interlayer insulating film 8 is planarized by CMP. Next, a resist pattern (not shown) is formed on the interlayer insulating film 8, and the interlayer insulating film 8 is etched using this resist pattern as a mask. As a result, a connection hole located on the impurity region 7 and a connection hole located on the gate electrode 4 are formed in the interlayer insulating film 8. Thereafter, the resist pattern is removed.

  Next, a tungsten film is formed in the connection holes and on the interlayer insulating film 8 by the CVD method, and the tungsten film located on the interlayer insulating film 8 is removed by the CMP method. As a result, the tungsten plug 9 a located on the gate electrode 4 and the tungsten plugs 9 b and 9 c located on the impurity region 7 are formed in the interlayer insulating film 8.

  Next, an Al alloy film is formed on the tungsten plugs 9 a, 9 b, 9 c and on the interlayer insulating film 8. Next, a resist pattern (not shown) is formed on the Al alloy film, and the Al alloy film is etched using the resist pattern as a mask. As a result, the Al alloy film is selectively removed, and the Al alloy wiring 10a connected to the tungsten plug 9a, the Al alloy wiring 10b connected to the tungsten plug 9b, and the Al alloy pattern 10c located on the tungsten plug 9c have interlayer insulation. It is formed on the film 8. Thereafter, the resist pattern is removed.

  Next, an interlayer insulating film 11 is formed on the Al alloy wirings 10a and 10b and the interlayer insulating film 8, and the surface of the interlayer insulating film 11 is planarized by CMP. Next, a resist pattern (not shown) is formed on the interlayer insulating film 11, and the interlayer insulating film 11 is dry-etched using this resist pattern as a mask. Thus, a connection hole located on the tungsten plug 9c is formed in the interlayer insulating film 11. Next, a tungsten film is formed in the connection hole and on the interlayer insulating film 11 by the CVD method, and the tungsten film located on the interlayer insulating film 11 is removed by the CMP method. As a result, a tungsten plug 15 a located on the Al alloy pattern 10 c is formed in the interlayer insulating film 11. The tungsten plug 15a may be formed in a portion other than above the tungsten plug 9c. Thereafter, the resist pattern is removed.

  Next, a resist pattern (not shown) is formed on the tungsten plug 15a and the interlayer insulating film 11, and the interlayer insulating film 11 is dry-etched using the resist pattern as a mask. As a result, a plurality of hole-shaped recesses 11 a are formed in the interlayer insulating film 11. Thereafter, the resist pattern is removed. The diameter of the recess 11a is, for example, 100 nm. Note that after forming the plurality of recesses 11a and before forming the polycrystalline silicon film, a silicon nitride film may be formed in the recesses 11a to reduce the diameter of the recesses 11a.

Next, as shown in FIG. 1B, a polycrystalline silicon film is formed on the tungsten plug 15a, the interlayer insulating film 11 and the plurality of recesses 11a by the CVD method. The thickness of the polycrystalline silicon film is, for example, not less than 50 nm and not more than 500 nm. Next, the polycrystalline silicon film is irradiated with a laser (for example, an excimer laser such as an XeCl pulse laser with a wavelength of 308 nm, pulse width of 30 nanoseconds, energy density of 0.4 to 1.5 J / cm ² ). Among them, the portion located on the interlayer insulating film 11 and the upper portion of the recess 11a is melted and annealed with a halogen lamp to be gradually solidified.

  This solidification process starts from each of the portions located within the bottoms of the plurality of recesses 11a. In the initial stage of the solidification process, several crystal grains may be generated at the bottom of the concave portion 11a. By setting the diameter of the concave portion 11a to be approximately the same as or slightly smaller than the diameter of these crystal grains, the upper surface of the concave portion 11a is formed. Then, one crystal grain comes to be exposed. Then, the annealing conditions in the halogen lamp are adjusted as appropriate. As a result, in the portion located on the interlayer insulating film 11, the solidification of silicon results in single crystal growth using the crystal grains exposed on the upper surfaces of the plurality of recesses 11a as seed crystals. As a result, the silicon melted on the interlayer insulating film 11 is substantially single crystallized starting from the portions located in the plurality of recesses 11a, and becomes a crystallized silicon film 20 which is an aggregate of a plurality of substantially single crystals.

In the step of melting the polycrystalline silicon film, the portion located in the recess 11a may be completely melted, but even in this case, the portion located in the recess 11a is cooled first, Solidification starts first at the bottom of the recess 11a, and as a result, the crystallized silicon film 20 can be obtained.
Thereafter, the surface of the crystallized silicon film 20 is planarized by a CMP method.

  Next, as shown in FIG. 1C, a pad oxide film (not shown) and a silicon nitride film (not shown) are formed on the crystallized silicon film 20, and an opening pattern is formed in the silicon nitride film and the pad oxide film. Form. Next, the crystallized silicon film 20 is etched using the silicon nitride film as a mask. As a result, a groove is formed in the crystallized silicon film 20. Next, a silicon oxide film is formed in the trench and on the silicon nitride film. Next, by performing CMP polishing using the silicon nitride film as a stopper, the silicon oxide film located on the silicon nitride film is removed. Thereby, the element isolation film 22 is embedded in the crystallized silicon film 20. The element isolation film 22 isolates the element region in which the control circuit transistor is formed from other regions. In addition, it is preferable that the element region is positioned above the concave portion 11a and positioned in one substantially single crystal. Thereafter, the silicon nitride film and the pad oxide film are removed.

  Next, as shown in FIG. 2A, the surface of the crystallized silicon film 20 is thermally oxidized. As a result, a gate insulating film 23 is formed in the crystallized silicon film 20 located in the element region. The thickness of the gate insulating film 23 is, for example, 25 nm. Next, a polysilicon film is formed on the gate insulating film 23 and the element isolation film 22, and the polysilicon film is selectively removed. As a result, a gate electrode 24 is formed on the gate insulating film 23.

Next, impurities are introduced into the crystallized silicon film 20 using the gate electrode 24 and the element isolation film 22 as a mask. As a result, a low concentration impurity region 26 is formed in the crystallized silicon film 20. Next, an insulating film is formed on the entire surface including the gate electrode 24, and this insulating film is etched back. As a result, a sidewall 25 is formed on the sidewall of the gate electrode 24. Next, impurities are introduced into the crystallized silicon film 20 using the sidewall 25, the gate electrode 24, and the element isolation film 22 as a mask. Thereafter, a heat treatment for activating the impurities is performed. As a result, impurity regions 27 serving as a source and a drain are formed in the crystallized silicon film 20 located in the element region.
In this way, a control circuit transistor is formed in the element region of the crystallized silicon film 20. The operating voltage of the control circuit transistor is, for example, 3 V or more and 5 V or less.

  Next, as illustrated in FIG. 2B, the interlayer insulating film 12 is formed over the control circuit transistor and the element isolation film 22. Next, a resist pattern (not shown) is formed on the interlayer insulating film 12, and the interlayer insulating film 12 and the element isolation film 22 are etched using the resist pattern as a mask. As a result, a connection hole 12 a located on the gate electrode 24 and a connection hole 12 b located on the impurity region 27 are formed in the interlayer insulating film 12. A tungsten plug 15 a is formed in the interlayer insulating film 12 and the element isolation film 22. A connection hole 12c located above is formed. Thereafter, the resist pattern is removed. Next, a resist film (not shown) having an opening located on the connection hole 12c is formed on the interlayer insulating film, and the crystallized silicon film 20 is etched using this resist film as a mask. As a result, the connection hole 12c is deepened, penetrates the crystallized silicon film 20, and is connected to the tungsten plug 15a.

  Next, a tungsten film is formed in each connection hole and on the interlayer insulating film 12, and the tungsten film located on the interlayer insulating film 12 is removed by a CMP method. Thereby, tungsten plugs 13a, 13b, and 13c are embedded in the connection holes 12a, 12b, and 12c, respectively. The tungsten plug 13a is connected to the gate electrode 24, the tungsten plug 13b is connected to the impurity region 27, and the tungsten plug 13c is connected to the tungsten plug 15a.

  Next, an Al alloy film is formed on each of the tungsten plugs 13 a to 13 c and on the interlayer insulating film 12. Next, a resist pattern (not shown) is formed on the Al alloy film, and the Al alloy film is etched using the resist pattern as a mask. As a result, the Al alloy film is selectively removed, and an Al alloy wiring 14 a connected to the tungsten plug 13 a and an Al alloy wiring 14 b connecting the tungsten plugs 13 b and 13 c are formed on the interlayer insulating film 12. Thereafter, the resist pattern is removed.

  As described above, according to the first embodiment of the present invention, the power circuit transistor is formed on the SiC substrate 1, and then the crystallized silicon film 20 is formed on the interlayer insulating film 11. A control circuit transistor is formed in the crystallized silicon film 20. For this reason, the power circuit transistor and the control circuit transistor having greatly different operating voltages can be mixedly mounted on the SiC substrate 1. Therefore, the power conversion efficiency of the semiconductor device (for example, a power supply module or a motor driver) is increased, and the semiconductor device can be downsized.

  Each drawing in FIG. 3 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment of the present invention. In the semiconductor device manufactured according to the present embodiment, the crystallized silicon film 20 is formed on the interlayer insulating film 8. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 3A, an element isolation film 2, a gate insulating film 3, a gate electrode 4, and an impurity region 7 of a power circuit transistor are formed on an SiC substrate 1. These forming methods are the same as those in the first embodiment. Next, an interlayer insulating film 8 is formed on the power circuit transistor and the element isolation film 2, and tungsten plugs 9 a and 9 c are embedded in the interlayer insulating film 8. These forming method and embedding method are the same as those in the first embodiment.

  Next, a recess 8 a is formed in the interlayer insulating film 8, and a crystallized silicon film 20 is formed on the tungsten plugs 9 a and 9 c, in the recess 8 a, and on the interlayer insulating film 8. The method for forming the recess 8a is the same as the method for forming the recess 11a in the interlayer insulating film 11 in the first embodiment. The method for forming the crystallized silicon film 20 is the same as that in the first embodiment.

  Next, as shown in FIG. 3B, the crystallized silicon film 20, the element isolation film 22, the gate insulating film 23 of the control circuit transistor, the gate electrode 24, the sidewall 25, the low-concentration impurity region 26, and the impurity Region 27 is formed. These forming methods are the same as those in the first embodiment.

Next, as shown in FIG. 3C, an interlayer insulating film 12, connection holes 12a, 12b, 12c, and 12d, tungsten plugs 13a, 13b, 13c, and 13d, and Al alloy wirings 14a, 14b, and 14c are formed. These forming methods are the same as the method of forming the interlayer insulating film 12, the connection holes 12a to 12c, the tungsten plugs 13a to 13c, and the Al alloy wirings 14a and 14b in the first embodiment. The connection hole 12d is formed by the same method as the connection hole 12c. In this embodiment, the tungsten plug 13c is connected to the tungsten plug 9c, and the tungsten plug 13d is connected to the tungsten plug 9a.
Also according to this embodiment, the same effect as that of the first embodiment can be obtained.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the first embodiment, before forming the recess 11a, the connection hole for embedding the tungsten plug 15a and the tungsten plug 15a need not be formed. In this case, in the step of etching the crystallized silicon film 20 to deepen the connection hole 12c, the crystallized silicon film 20 is etched, and then the interlayer insulating film 11 is etched to make the connection hole 12c an Al alloy pattern. Deepen until reaching 10c. In the step of embedding the tungsten plug 13c, the tungsten plug 13c reaches the Al alloy pattern 10c and is connected to the Al alloy pattern 10c.

  In the second embodiment, the connection holes and the tungsten plugs 9a and 9c in which the tungsten plugs 9a and 9c are embedded need not be formed before the recess 11a is formed. In this case, in the step of etching the crystallized silicon film 20 to deepen the connection holes 12c and 12d, after the crystallized silicon film 20 is etched, the interlayer insulating film 8 and the gate insulating film 3 are subsequently etched. The connection hole 12 c is deepened until it reaches the impurity region 7, and the connection hole 12 d is deepened until it reaches the gate electrode 4. Then, in the step of filling the tungsten plugs 13 c and 13 d, the tungsten plugs 13 c and 13 d reach the impurity region 7 and the gate electrode 4, respectively, and are connected to the impurity region 7 and the gate electrode 4.

  Further, instead of the above-described Al alloy wirings, Cu wirings may be embedded in the interlayer insulating film. Further, salicide may be formed on the surfaces of the gate electrode 24 and the impurity region 27. Similarly, salicide may be formed on the surfaces of the gate electrode 4 and the impurity region 7.

  Instead of the SiC substrate 1, a substrate formed of a semiconductor having a band gap larger than that of silicon may be used. For example, a substrate obtained by converting the Si substrate formed on the SOI substrate into SiC, a diamond substrate formed on the sapphire substrate, or a GaN substrate formed on the sapphire substrate or the silicon substrate may be used.

  Further, after the crystallized silicon film 20 is formed, unnecessary portions of the crystallized silicon film 20 may be removed before the step of forming the element isolation film 22. In the first and second embodiments, instead of the recesses 11a and 8a, a portion serving as a starting point for crystallization of the polycrystalline silicon film may be provided.

Each drawing is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the first embodiment. Each figure is a sectional view for explaining the next step of FIG. Each drawing is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... SiC substrate, 2, 22 ... Element isolation film, 3, 23 ... Gate insulating film, 4, 24 ... Gate electrode, 7, 27 ... Impurity region, 8, 11, 12 ... Interlayer insulating film, 8a, 11a ... Recessed part 9a-9c, 13a-13d, 15a ... tungsten plug, 10a, 10b, 14a-14c ... Al alloy wiring, 10c ... Al alloy pattern, 12a-12d ... connection hole, 20 ... crystallized silicon film, 25 ... side wall , 26 ... low concentration impurity region

Claims (2)

Forming a first transistor on a semiconductor substrate;
Forming a first interlayer insulating film on or above the first transistor and the semiconductor substrate;
Forming a metal wiring layer on the first interlayer insulating film so as to overlap the first transistor;
Forming a second interlayer insulating film on the metal wiring layer;
Forming a recess in the upper surface of the second interlayer insulating film;
Forming a polycrystalline semiconductor film on the second interlayer insulating film and in the recess by a material different from the semiconductor substrate;
By irradiating the polycrystalline semiconductor film with laser light and irradiating lamp light to anneal the polycrystalline semiconductor film, the semiconductor film located in the recess is used as the starting point. Crystallization of the semiconductor film located on the second interlayer insulating film;
Forming a second transistor in the semiconductor film;
A method for manufacturing a semiconductor device comprising: Wherein in the step of forming a concave portion on the upper surface of the second interlayer insulating film, a method of manufacturing a semiconductor device according to claim 1 for forming the recess so as not to overlap with the first transistor.

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