JP4957064B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP4957064B2
JP4957064B2 JP2006120846A JP2006120846A JP4957064B2 JP 4957064 B2 JP4957064 B2 JP 4957064B2 JP 2006120846 A JP2006120846 A JP 2006120846A JP 2006120846 A JP2006120846 A JP 2006120846A JP 4957064 B2 JP4957064 B2 JP 4957064B2
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adhesive layer
semiconductor chip
support member
resin
semiconductor
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JP2007294681A (en
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禎一 稲田
慎也 加藤
恵一 畠山
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Resonac Corp
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Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Resonac Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83191Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Adhesive Tapes (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an adhesive sheet excellent in heat resistance and moisture resistance and exhibiting improved filling properties to an irregular surface subjected to thermal hysteresis when it is used for bonding a semiconductor chip to a supporting member for mounting the semiconductor chip. <P>SOLUTION: The adhesive sheet is employed in a manufacturing process of a semiconductor device comprising a step for bonding a semiconductor chip to a supporting member 20 for mounting the semiconductor chip through an adhesive layer 10 having a modulus of elasticity in tension of 0.1-2 MPa at 170&deg;C when it is hardened by heating 5 hours at 170&deg;C and storage elasticity of 1-6 MPa at 200&deg;C under such a state as an air gap is left between the adhesive layer 10 and the irregular surface of the supporting member 20, and a step for resin sealing the semiconductor chip A1 connected to the supporting member 20 and filling the air gap with the adhesive layer 10. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、接着シート及びこれを用いて得られる半導体装置に関する。   The present invention relates to an adhesive sheet and a semiconductor device obtained using the adhesive sheet.

近年、半導体パッケージの小型化に伴い、半導体チップと同等のサイズを有するCSP(Chip Size Package)や、半導体チップを多段に積層したスタックドCSPと呼ばれるタイプの半導体装置が普及している(例えば、特許文献1〜5参照)。
特開2001−279197号公報 特開2002−222913号公報 特開2002−359346号公報 特開2001−308262号公報 特開2004−072009号公報
In recent years, with the miniaturization of semiconductor packages, CSP (Chip Size Package) having a size equivalent to that of a semiconductor chip and a semiconductor device of a type called stacked CSP in which semiconductor chips are stacked in multiple stages have become widespread (for example, patents). Reference 1-5).
JP 2001-279197 A JP 2002-222913 A JP 2002-359346 A JP 2001-308262 A Japanese Patent Laid-Open No. 2004-072009

このようなパッケージは、接着層を有する接着シートを用いた以下のような方法で製造することができる。まず、半導体ウエハ、接着層及びダイシングテープを0℃〜80℃で貼り合わせた後、これらを回転刃で同時に切断し(ダイシング工程)、洗浄する。次いで、半導体チップを、凹凸表面を有する半導体チップ搭載用の支持部材に接着層を介して接着し、半導体チップを支持部材にワイヤボンディングにより接続する。その後、さらに半導体チップを接着層を介して接着しながら積層して半導体チップを支持部材にワイヤボンディングにより接続する工程を必要に応じて繰り返して行う。これにより半導体チップが多段に積層される。そして、ワイヤボンディングにより接続する工程をすべて終了後、半導体チップを樹脂封止する。   Such a package can be manufactured by the following method using an adhesive sheet having an adhesive layer. First, after bonding a semiconductor wafer, an adhesive layer, and a dicing tape at 0 ° C. to 80 ° C., they are simultaneously cut with a rotary blade (dicing step) and washed. Next, the semiconductor chip is bonded to a semiconductor chip mounting support member having an uneven surface via an adhesive layer, and the semiconductor chip is connected to the support member by wire bonding. Thereafter, a process of further stacking the semiconductor chips while bonding them through the adhesive layer and connecting the semiconductor chips to the support member by wire bonding is repeated as necessary. As a result, the semiconductor chips are stacked in multiple stages. Then, after all the steps of connecting by wire bonding are completed, the semiconductor chip is sealed with resin.

しかしながら、半導体チップの接着の際、支持部材の凹凸表面を接着層によって完全に充填することは困難な場合が多い。特に、半導体チップが210μmより薄い場合、低い荷重で圧着する必要があるため、凹凸表面の充填が極めて困難となる。   However, when the semiconductor chip is bonded, it is often difficult to completely fill the uneven surface of the support member with the adhesive layer. In particular, when the semiconductor chip is thinner than 210 μm, it is necessary to press-bond with a low load, so that it is extremely difficult to fill the uneven surface.

この問題に関しては、半導体チップを接着する際には凹凸表面が接着層によって完全には充填されない状態としておき、半導体チップを樹脂封止する工程における圧力により凹凸表面を充填する方法が有効と考えられる。しかし、半導体チップの積層段数が増加すると、樹脂封止の前に、接着層が170℃程度の高温に1時間又はそれ以上に長い時間曝されることになる。そのため、半導体チップの積層段数が増加すると、樹脂封止の前に接着層の硬化が進行して高弾性率化し、樹脂封止の工程における圧力により凹凸表面を十分に充填することが困難になるという問題があった。充填が不十分であると、接着層と支持部材との間にボイドが多く発生し、半導体装置の製造歩留まりが低下してしまう。   Regarding this problem, it is considered effective to fill the uneven surface with the pressure in the process of resin-sealing the semiconductor chip while keeping the uneven surface completely filled with the adhesive layer when bonding the semiconductor chip. . However, when the number of stacked semiconductor chips increases, the adhesive layer is exposed to a high temperature of about 170 ° C. for 1 hour or longer before resin sealing. For this reason, when the number of stacked semiconductor chips increases, the adhesive layer cures before the resin sealing to increase the elastic modulus, and it becomes difficult to sufficiently fill the uneven surface by the pressure in the resin sealing process. There was a problem. If the filling is insufficient, many voids are generated between the adhesive layer and the support member, and the manufacturing yield of the semiconductor device is lowered.

また、半導体チップの積層数が増加すると、例えば、半導体装置を実装する際の高温加熱(例えば、はんだリフロー処理)により接着層が支持部材から剥離し易くなる傾向にある。この点からも、半導体装置の製造歩留まりが低下し易くなる。   Further, when the number of stacked semiconductor chips increases, for example, the adhesive layer tends to be peeled off from the support member by high-temperature heating (for example, solder reflow processing) when mounting the semiconductor device. Also from this point, the manufacturing yield of the semiconductor device tends to decrease.

本発明は、上記事情に鑑みてなされたものであり、半導体チップ搭載用の支持部材に半導体チップを接着するために用いられたときに、熱履歴を受けた後における凹凸表面への充填性が改善され、また、耐熱性及び耐湿性の点でも優れる接着シートを提供することを目的とする。   The present invention has been made in view of the above circumstances, and when used for bonding a semiconductor chip to a support member for mounting a semiconductor chip, the filling property to the uneven surface after receiving a thermal history is provided. An object of the present invention is to provide an adhesive sheet that is improved and also excellent in terms of heat resistance and moisture resistance.

本発明に係る接着シートは、170℃で5時間の加熱により硬化されたときに、170℃における引張弾性率が0.1〜2MPa、且つ、200℃における貯蔵弾性率が1〜6MPaとなる接着層を有し、半導体チップ搭載用の支持部材に、接着層を介して、該接着層と支持部材の凹凸表面との間に空隙が残された状態で半導体チップを接着する工程と、支持部材に接着された半導体チップをワイヤボンディングにより支持部材に接続する工程と、支持部材に接続された半導体チップを樹脂封止するとともに該半導体チップと支持部材との間の接着層によって上記空隙を充填する工程と、を備える半導体装置の製造方法に用いられる、接着シートである。   When the adhesive sheet according to the present invention is cured by heating at 170 ° C. for 5 hours, the tensile elastic modulus at 170 ° C. is 0.1 to 2 MPa, and the storage elastic modulus at 200 ° C. is 1 to 6 MPa. A step of bonding a semiconductor chip to a support member for mounting a semiconductor chip, with a gap left between the adhesive layer and the concavo-convex surface of the support member, and a support member Connecting the semiconductor chip bonded to the support member to the support member by wire bonding, sealing the semiconductor chip connected to the support member with resin, and filling the gap with an adhesive layer between the semiconductor chip and the support member And an adhesive sheet used in a method for manufacturing a semiconductor device.

上記製造方法は、支持部材に接続された半導体チップの支持部材と反対側に接着層を介して半導体チップを積層し、該半導体チップをワイヤボンディングにより支持部材に接続する工程を1又は2以上含む工程を更に備えていてもよい。   The manufacturing method includes one or more steps of laminating a semiconductor chip via an adhesive layer on the side opposite to the supporting member of the semiconductor chip connected to the supporting member, and connecting the semiconductor chip to the supporting member by wire bonding. You may further provide the process.

上記接着シートにおいて、上記接着層が、エポキシ樹脂及びその硬化剤並びにアクリルゴムを含む樹脂と、比表面積が30〜400m/gの粒子と、からなり、樹脂全体量に対して、エポキシ樹脂及びその硬化剤の合計量の割合が21〜26質量%、アクリルゴムの割合が74〜79質量%であり、樹脂100質量部に対して、粒子の割合が2〜20重量部であることが好ましい。 In the adhesive sheet, the adhesive layer includes an epoxy resin and a resin containing a curing agent thereof and acrylic rubber, and particles having a specific surface area of 30 to 400 m 2 / g. The proportion of the total amount of the curing agent is 21 to 26 mass%, the proportion of acrylic rubber is 74 to 79 mass%, and the proportion of particles is preferably 2 to 20 parts by weight with respect to 100 parts by mass of the resin. .

上記製造方法は、半導体ウエハ、接着層及びダイシングテープがこの順で積層された積層体から、半導体チップ、接着層及びダイシングテープがこの順で積層されたチップ積層体を回転刃によって切り出し、ダイシングテープを除去して接着層付き半導体チップを得る工程を更に備えていてもよい。この場合、当該接着層付き半導体チップを支持部材上に載置し、0.001〜1MPaで加圧することにより支持部材に半導体チップを接着する。   In the manufacturing method, a chip laminated body in which a semiconductor chip, an adhesive layer, and a dicing tape are laminated in this order is cut out from a laminated body in which the semiconductor wafer, the adhesive layer, and the dicing tape are laminated in this order, and the dicing tape is cut out. There may be further provided a step of removing the substrate to obtain a semiconductor chip with an adhesive layer. In this case, the semiconductor chip with the adhesive layer is placed on the support member, and the semiconductor chip is bonded to the support member by applying pressure at 0.001 to 1 MPa.

本発明に係る接着シートは、接着層に貼り合わされたダイシングテープを更に有していてもよい。   The adhesive sheet according to the present invention may further have a dicing tape bonded to the adhesive layer.

本発明に係る半導体装置は、支持部材及びこれの一面側に設けられた1又は2以上の半導体チップを備え、半導体チップと支持部材との間、及び/又は半導体チップ同士の間に、上記いずれかの接着シートの接着層が介在した構成を有する。   A semiconductor device according to the present invention includes a support member and one or more semiconductor chips provided on one surface side thereof, and any of the above is provided between the semiconductor chip and the support member and / or between the semiconductor chips. Such an adhesive sheet has an intervening adhesive layer.

本発明によれば、半導体チップ搭載用の支持部材に半導体チップを接着するために用いられたときに、熱履歴を受けた後における凹凸表面への充填性が改善され、また、耐熱性及び耐湿性の点でも優れる接着シートが提供される。   According to the present invention, when used for bonding a semiconductor chip to a support member for mounting a semiconductor chip, the filling property to the uneven surface after receiving a thermal history is improved, and the heat resistance and moisture resistance are improved. An adhesive sheet that is also excellent in terms of properties is provided.

以下、本発明の好適な実施形態について詳細に説明する。ただし、本発明は以下の実施形態に限定されるものではない。   Hereinafter, preferred embodiments of the present invention will be described in detail. However, the present invention is not limited to the following embodiments.

図1は、接着層付き半導体チップ及びこれが接着される支持部材の一実施形態を示す断面図である。本実施形態に係る接着シートが用いられる半導体装置の製造方法は、半導体チップ搭載用の支持部材20に、接着層10を介して、接着層10と支持部材20の凹凸表面との間に空隙が残された状態で半導体チップA1を接着する工程(接着工程)と、支持部材20に接着された半導体チップA1をワイヤボンディングにより支持部材20に接続する工程(ワイヤボンディング工程)と、支持部材に接続された半導体チップの支持部材と反対側に接着層を介して半導体チップを積層し、該半導体チップをワイヤボンディングにより支持部材に接続する工程を1又は2以上含む工程(積層工程)と、支持部材20に接続された半導体チップA1を樹脂封止するとともに半導体チップA1と支持部材20との間の接着層10によって上記空隙を充填する工程(封止工程)と、を備える。   FIG. 1 is a cross-sectional view illustrating an embodiment of a semiconductor chip with an adhesive layer and a support member to which the semiconductor chip is bonded. In the method for manufacturing a semiconductor device using the adhesive sheet according to the present embodiment, a gap is formed between the adhesive layer 10 and the concavo-convex surface of the support member 20 through the adhesive layer 10 in the support member 20 for mounting a semiconductor chip. The step of bonding the semiconductor chip A1 in the remaining state (bonding step), the step of connecting the semiconductor chip A1 bonded to the support member 20 to the support member 20 by wire bonding (wire bonding step), and the connection to the support member A step (lamination step) including a step of laminating the semiconductor chip on the side opposite to the support member of the formed semiconductor chip via an adhesive layer and connecting the semiconductor chip to the support member by wire bonding (lamination step); The semiconductor chip A1 connected to the semiconductor chip A1 is resin-sealed and the gap is filled by the adhesive layer 10 between the semiconductor chip A1 and the support member 20. Comprising the step (sealing step), the.

本実施形態に係る製造方法の場合、まず、半導体ウエハ、接着層10及びダイシングテープがこの順で積層された積層体から、半導体チップA1、接着層10及びダイシングテープがこの順で積層されたチップ積層体を回転刃によって切り出し、洗浄及び乾燥して、接着層付き半導体チップ15を得る。ダイシングテープは適宜除去される。   In the case of the manufacturing method according to the present embodiment, first, a chip in which the semiconductor chip A1, the adhesive layer 10 and the dicing tape are laminated in this order from the laminated body in which the semiconductor wafer, the adhesive layer 10 and the dicing tape are laminated in this order. The laminated body is cut out with a rotary blade, washed and dried to obtain a semiconductor chip 15 with an adhesive layer. The dicing tape is removed as appropriate.

上記積層体は、例えば、半導体ウエハ、接着層10及びダイシングテープを0℃〜80℃で貼り合わせる方法により製造される。接着層は単層であっても多層であってもよい。接着層が単層である場合には、半導体ウエハに接着層を貼り合わせ、次いで接着層にダイシングテープを貼り合わせればよい。多層の接着層を用いる場合には、半導体ウエハに第1の接着剤層、第2の接着剤層のように各層を順に貼り合わせてもよいし、予め第1の接着剤層及び第2の接着剤層等を含む多層の接着層を有する接着シートを作製しておき、これを半導体ウエハに貼り合わせてもよい。あるいは、単層又は多層の接着層と、ダイシングテープとを有するダイシングテープ一体型の接着シートを準備し、これを半導体ウェハに貼り合わせてもよい。   The laminated body is manufactured, for example, by a method in which a semiconductor wafer, an adhesive layer 10 and a dicing tape are bonded at 0 ° C. to 80 ° C. The adhesive layer may be a single layer or a multilayer. When the adhesive layer is a single layer, the adhesive layer is bonded to the semiconductor wafer, and then a dicing tape is bonded to the adhesive layer. When a multilayer adhesive layer is used, each layer may be bonded to the semiconductor wafer in order, such as the first adhesive layer and the second adhesive layer, or the first adhesive layer and the second adhesive layer may be bonded in advance. An adhesive sheet having a multilayer adhesive layer including an adhesive layer and the like may be prepared and bonded to a semiconductor wafer. Alternatively, a dicing tape-integrated adhesive sheet having a single-layer or multilayer adhesive layer and a dicing tape may be prepared and bonded to a semiconductor wafer.

接着層を半導体ウエハに貼り付ける温度、即ちラミネート温度は、好ましくは0〜80℃であり、より好ましくは15〜80℃であり、さらに好ましくは20〜70℃である。80℃を超えると接着層を貼り付けた後の半導体ウエハの反りが大きくなる傾向がある。   The temperature at which the adhesive layer is affixed to the semiconductor wafer, that is, the lamination temperature is preferably 0 to 80 ° C, more preferably 15 to 80 ° C, and further preferably 20 to 70 ° C. If it exceeds 80 ° C., the warp of the semiconductor wafer after the adhesive layer is attached tends to increase.

次いで、接着層付き半導体チップ15を支持部材20上に載置し、0.001〜1MPaで加圧することにより、支持部材20に、接着層10を介して、接着層10と支持部材20の凹凸表面との間に空隙が残された状態で半導体チップA1を接着する。言い換えると、支持部材の凹凸表面が完全には充填されない状態で支持部材20に半導体チップA1を接着層10を介して接着する。このとき加えられる荷重は0.01〜0.5MPaであることが好ましく、0.01〜0.3MPaであることがより好ましい。荷重が0.001MPa未満であると半導体チップが工程中で剥離しやすく、1MPaを超えると半導体チップが破損し易くなる傾向がある。なお、この工程後の凹凸表面が完全に充填されていなくても、そのことによる不都合は発生しないし、むしろ、揮発分が抜けやすいためにふくれが生じにくいという利点がある。   Next, the semiconductor chip 15 with the adhesive layer is placed on the support member 20 and pressed at 0.001 to 1 MPa, whereby the unevenness of the adhesive layer 10 and the support member 20 is applied to the support member 20 via the adhesive layer 10. The semiconductor chip A1 is bonded in a state where a gap is left between the surface and the surface. In other words, the semiconductor chip A1 is bonded to the support member 20 via the adhesive layer 10 in a state where the uneven surface of the support member is not completely filled. The load applied at this time is preferably 0.01 to 0.5 MPa, and more preferably 0.01 to 0.3 MPa. If the load is less than 0.001 MPa, the semiconductor chip is easily peeled in the process, and if it exceeds 1 MPa, the semiconductor chip tends to be damaged. Even if the uneven surface after this step is not completely filled, there is no inconvenience due to this, and rather, there is an advantage that blistering hardly occurs because volatile matter is easily removed.

支持部材20に接着された半導体チップA1は、ワイヤボンディングにより支持部材20に電気的に接続される。   The semiconductor chip A1 bonded to the support member 20 is electrically connected to the support member 20 by wire bonding.

続いて、支持部材20に接続された半導体チップA1の支持部材20と反対側に接着層10を介して半導体チップA1を積層し、該半導体チップA1をワイヤボンディングにより支持部材20に接続する工程を1又は2以上含む工程により、1又は2以上の半導体チップA1が積層された多層構造が形成される。通常、1〜20個の半導体チップが積層される。この積層の過程において、支持部材20と半導体チップとの間に介在する最下層の接着層10は、150〜190℃で10分〜300分間程度の熱履歴を受ける。ただし、支持部材に接着層を介して接着された上記半導体チップのみを有する半導体装置を製造することも可能である。   Subsequently, a step of stacking the semiconductor chip A1 via the adhesive layer 10 on the side opposite to the support member 20 of the semiconductor chip A1 connected to the support member 20, and connecting the semiconductor chip A1 to the support member 20 by wire bonding. By the process including one or two or more, a multilayer structure in which one or two or more semiconductor chips A1 are stacked is formed. Usually, 1 to 20 semiconductor chips are stacked. In the lamination process, the lowermost adhesive layer 10 interposed between the support member 20 and the semiconductor chip receives a thermal history at 150 to 190 ° C. for about 10 to 300 minutes. However, it is also possible to manufacture a semiconductor device having only the semiconductor chip bonded to the support member via an adhesive layer.

ワイヤボンディングによる接続が全て終了した後、複数の半導体チップA1を樹脂封止して、封止樹脂によって全体を覆う。同時に、このとき加えられる圧力により、半導体チップA1と支持部材20との間に介在する接着層10を変形させて、接着層10と支持部材20の凹凸表面との間に残されていた空隙を充填する。これにより、支持部材の凹凸表面が実質的に完全に充填される。すなわち、超音波探傷によって検知される程度のサイズの空隙が実質的に消失する。   After all the connections by wire bonding are completed, the plurality of semiconductor chips A1 are sealed with resin, and the whole is covered with sealing resin. At the same time, the adhesive layer 10 interposed between the semiconductor chip A1 and the support member 20 is deformed by the pressure applied at this time, and the gap left between the uneven surface of the adhesive layer 10 and the support member 20 is removed. Fill. Thereby, the uneven surface of the support member is substantially completely filled. That is, a gap having a size that can be detected by ultrasonic flaw detection substantially disappears.

本発明者らの知見によれば、封止工程において支持部材20の凹凸表面を十分に充填するためには、熱履歴を受けた後の接着層の引張弾性率及び貯蔵弾性率が所定の範囲内となるように調節することが有効である。具体的には、170℃で5時間の加熱により硬化されたときに、170℃における引張弾性率が0.1〜2MPaであり、且つ、200℃における貯蔵弾性率が1〜6MPaとなる接着層を用いる。170℃で5時間の加熱により、接着層は硬化度が95%以上のCステージ状態となる。接着層に係る特性を付与するための好適な組成については、詳細に後述される。   According to the knowledge of the present inventors, in order to sufficiently fill the uneven surface of the support member 20 in the sealing step, the tensile elastic modulus and storage elastic modulus of the adhesive layer after receiving the thermal history are within a predetermined range. It is effective to adjust so as to be within. Specifically, an adhesive layer having a tensile elastic modulus at 170 ° C. of 0.1 to 2 MPa and a storage elastic modulus at 200 ° C. of 1 to 6 MPa when cured by heating at 170 ° C. for 5 hours. Is used. By heating at 170 ° C. for 5 hours, the adhesive layer is in a C-stage state with a curing degree of 95% or more. A suitable composition for imparting the properties relating to the adhesive layer will be described in detail later.

上記引張弾性率は、好ましくは0.2〜1.5MPaであり、さらに好ましくは0.2〜1MPaである。この引張弾性率が低すぎると耐熱性が低下する傾向があり、大きすぎると樹脂封止時の充填性向上の効果が低下する傾向にある。   The tensile elastic modulus is preferably 0.2 to 1.5 MPa, and more preferably 0.2 to 1 MPa. If this tensile elastic modulus is too low, the heat resistance tends to decrease, and if it is too large, the effect of improving the filling property during resin sealing tends to decrease.

200℃における上記貯蔵弾性率は2〜6Maであることがより好ましく、2.5〜5MPaであることが更に好ましく、2.5〜4MPaであることがより一層好ましい。   The storage elastic modulus at 200 ° C. is more preferably 2 to 6 Ma, further preferably 2.5 to 5 MPa, and further preferably 2.5 to 4 MPa.

ダイシング性に優れる点から、接着層の硬化前(Bステージ状態)の25℃における貯蔵弾性率は200〜3000MPaであることが好ましい。更に、ダイシング性に優れ、かつ半導体ウエハとの密着性が優れる点でこの貯蔵弾性率は500〜2000MPaであることがより好ましい。また、硬化前(Bステージ状態)の接着層の80℃における貯蔵弾性率は0.1〜10MPaであることが好ましい。これにより、80℃程度の温度における半導体ウエハへの良好なラミネート性が得られる。特に半導体ウエハへの密着性が高い点で、80℃における貯蔵弾性率は0.5〜5MPaであることがより好ましい。   From the viewpoint of excellent dicing properties, the storage elastic modulus at 25 ° C. before curing of the adhesive layer (B stage state) is preferably 200 to 3000 MPa. Furthermore, it is more preferable that the storage elastic modulus is 500 to 2000 MPa in terms of excellent dicing properties and excellent adhesion to a semiconductor wafer. Moreover, it is preferable that the storage elastic modulus in 80 degreeC of the contact bonding layer before hardening (B stage state) is 0.1-10 Mpa. Thereby, the favorable laminating property to the semiconductor wafer in the temperature of about 80 degreeC is obtained. In particular, the storage elastic modulus at 80 ° C. is more preferably 0.5 to 5 MPa in terms of high adhesion to a semiconductor wafer.

接着層の貯蔵弾性率は、動的粘弾性測定装置(レオロジー社製「DVE−V4」等)を用いて測定することができる。測定条件は、サンプルサイズ:長さ20mm、幅4mm、温度範囲−30〜200℃、昇温速度5℃/min、引張りモード、10Hz、自動静荷重とされる。   The storage elastic modulus of the adhesive layer can be measured using a dynamic viscoelasticity measuring device (such as “DVE-V4” manufactured by Rheology). The measurement conditions are as follows: sample size: length 20 mm, width 4 mm, temperature range −30 to 200 ° C., temperature rising rate 5 ° C./min, tension mode 10 Hz, automatic static load.

接着シートにおける接着層の膜厚は、支持部材の配線回路等の凹凸表面を充填するために、3〜250μmであることが好ましい。この膜厚が3μmより薄いと凹凸表面を充填性向上の効果が低下する他、応力緩和効果や接着性が低下する傾向があり、250μmより厚いと経済的でなくなる上に、半導体装置の小型化の要求に応えることが困難になる傾向がある。この膜厚は、接着性が高く、また、半導体装置を薄型化できる点で20〜100μmがより好ましく、30〜70μmが更に好ましい。   The film thickness of the adhesive layer in the adhesive sheet is preferably 3 to 250 μm in order to fill the uneven surface such as the wiring circuit of the support member. If this film thickness is less than 3 μm, the effect of improving the fillability of the uneven surface tends to be reduced, and the stress relaxation effect and adhesiveness tend to be reduced. If it is thicker than 250 μm, it is not economical and the semiconductor device is downsized. It tends to be difficult to meet the demands. This film thickness is more preferably 20 to 100 μm, and more preferably 30 to 70 μm in terms of high adhesiveness and the ability to reduce the thickness of the semiconductor device.

本実施形態に係る接着シートが有する接着層は、樹脂及び粒子からなる。樹脂は、加熱により硬化する熱硬化性成分と、高分子量成分とを含む樹脂組成物から形成されていることが好ましい。接着層を半導体ウェハ又は半導体チップに貼り合わせる段階では、通常、接着層がBステージ状態にある。   The adhesive layer which the adhesive sheet which concerns on this embodiment has consists of resin and particle | grains. The resin is preferably formed from a resin composition containing a thermosetting component that is cured by heating and a high molecular weight component. In the stage where the adhesive layer is bonded to the semiconductor wafer or the semiconductor chip, the adhesive layer is usually in a B stage state.

熱硬化性成分は、半導体チップを実装する場合に要求される耐熱性及び耐湿性を接着層に付与するためには、エポキシ樹脂及びその硬化剤を主成分とすることが好ましい。   The thermosetting component preferably contains an epoxy resin and a curing agent thereof as main components in order to provide the adhesive layer with heat resistance and moisture resistance required for mounting a semiconductor chip.

エポキシ樹脂は、硬化して接着作用を奏するものであれば特に限定されない。具体的には、ビスフェノールA型エポキシ樹脂、ビスフェノールF型エポキシ樹脂、ビスフェノールS型エポキシ樹脂などの二官能エポキシ樹脂、フェノールノボラック型エポキシ樹脂やクレゾールノボラック型エポキシ樹脂などのノボラック型エポキシ樹脂などを使用することができる。また、多官能エポキシ樹脂、グリシジルアミン型エポキシ樹脂、複素環含有エポキシ樹脂または脂環式エポキシ樹脂など、一般に知られているものを適用することができる。   The epoxy resin is not particularly limited as long as it cures and exhibits an adhesive action. Specifically, bifunctional epoxy resins such as bisphenol A type epoxy resin, bisphenol F type epoxy resin and bisphenol S type epoxy resin, and novolak type epoxy resins such as phenol novolac type epoxy resin and cresol novolac type epoxy resin are used. be able to. Moreover, what is generally known, such as a polyfunctional epoxy resin, a glycidyl amine type epoxy resin, a heterocyclic ring-containing epoxy resin, or an alicyclic epoxy resin, can be applied.

特にBステージ状態での接着層の可撓性を高くすることができる点で、エポキシ樹脂の分子量は1000以下であることが好ましく、500以下であることがより好ましい。Bステージ状態での可撓性に優れる分子量500以下のビスフェノールA型又はビスフェノールF型エポキシ樹脂50〜90重量部と、硬化物の耐熱性に優れる分子量が800〜3000の多官能エポキシ樹脂10〜50重量部とを併用することが好ましい。   In particular, the molecular weight of the epoxy resin is preferably 1000 or less, and more preferably 500 or less in that the flexibility of the adhesive layer in the B-stage state can be increased. 50 to 90 parts by weight of a bisphenol A type or bisphenol F type epoxy resin having a molecular weight of 500 or less and excellent flexibility in a B stage state, and a polyfunctional epoxy resin 10 to 50 having a molecular weight of 800 to 3000 excellent in heat resistance of the cured product It is preferable to use in combination with parts by weight.

エポキシ樹脂の硬化剤としては、通常用いられている公知の硬化剤を使用することができる。例えば、アミン類、ポリアミド、酸無水物、ポリスルフィド、三フッ化ホウ素、ビスフェノールA、ビスフェノールF、ビスフェノールSのようなフェノール性水酸基を1分子中に2個以上有するビスフェノール類、フェノールノボラック樹脂、ビスフェノールAノボラック樹脂又はクレゾールノボラック樹脂等のフェノール樹脂などが挙げられる。   As the curing agent for the epoxy resin, a known curing agent that is usually used can be used. For example, bisphenols having two or more phenolic hydroxyl groups in one molecule such as amines, polyamides, acid anhydrides, polysulfides, boron trifluoride, bisphenol A, bisphenol F, and bisphenol S, phenol novolac resins, bisphenol A Examples thereof include phenolic resins such as novolak resin and cresol novolak resin.

エポキシ樹脂及びその硬化剤を含む硬化性成分の合計量の割合は10〜30質量%であることが好ましい。この割合の下限は17質量%であることが好ましく、21質量%であることがより好ましい。また、上限は26質量%であることが好ましく、25質量%であることがより好ましい。   It is preferable that the ratio of the total amount of the curable component containing the epoxy resin and its curing agent is 10 to 30% by mass. The lower limit of this ratio is preferably 17% by mass, and more preferably 21% by mass. Moreover, it is preferable that an upper limit is 26 mass%, and it is more preferable that it is 25 mass%.

接着層中の高分子量成分は、エポキシ基、アルコール性又はフェノール性水酸基、カルボキシル基等の架橋性官能基を有することが好ましい。架橋性官能基を有する高分子量成分としては、(メタ)アクリル共重合体((メタ)アクリル樹脂)、ポリイミド樹脂、、ウレタン樹脂、ポリフェニレンエーテル樹脂、ポリエーテルイミド樹脂、フェノキシ樹脂、変性ポリフェニレンエーテル樹脂等が挙げられる。これらの中でも、(メタ)アクリル基を有するモノマーを重合して得られる(メタ)アクリル共重合体が好ましい。   The high molecular weight component in the adhesive layer preferably has a crosslinkable functional group such as an epoxy group, an alcoholic or phenolic hydroxyl group, or a carboxyl group. Examples of the high molecular weight component having a crosslinkable functional group include (meth) acrylic copolymer ((meth) acrylic resin), polyimide resin, urethane resin, polyphenylene ether resin, polyetherimide resin, phenoxy resin, and modified polyphenylene ether resin. Etc. Among these, a (meth) acrylic copolymer obtained by polymerizing a monomer having a (meth) acrylic group is preferable.

(メタ)アクリル共重合体としては、(メタ)アクリル酸エステル共重合体、アクリルゴムなどを使用することができ、アクリルゴムがより好ましい。アクリルゴムは、アクリル酸エステルを主成分とし、主として、ブチルアクリレートとアクリロニトリルなどの共重合体や、エチルアクリレートとアクリロニトリルなどの共重合体などからなるゴムである。   As the (meth) acrylic copolymer, a (meth) acrylic acid ester copolymer, acrylic rubber or the like can be used, and acrylic rubber is more preferable. Acrylic rubber is a rubber mainly composed of an acrylate ester and mainly composed of a copolymer such as butyl acrylate and acrylonitrile, a copolymer such as ethyl acrylate and acrylonitrile, or the like.

(メタ)アクリル共重合体は、グリシジルアクリレート又はグリシジルメタクリレートなどの、エポキシ基を有するアクリルモノマーをモノマー単位として有することが好ましい。すなわち、(メタ)アクリル共重合体(好ましくはアクリルゴム)はエポキシ基を有することが好ましい。この場合、エポキシ基を有するアクリルモノマーの割合は、(メタ)アクリル共重合体の全体量に対して2〜5質量%が好ましい。この割合が大きくなると、架橋密度が大きくなって、樹脂封止時の充填性が低下する傾向にあり、小さすぎると耐熱性が低下する傾向にある。   The (meth) acrylic copolymer preferably has an acrylic monomer having an epoxy group such as glycidyl acrylate or glycidyl methacrylate as a monomer unit. That is, the (meth) acrylic copolymer (preferably acrylic rubber) preferably has an epoxy group. In this case, the ratio of the acrylic monomer having an epoxy group is preferably 2 to 5% by mass with respect to the total amount of the (meth) acrylic copolymer. When this ratio increases, the crosslinking density increases, and the filling property at the time of resin sealing tends to decrease, and when it is too small, the heat resistance tends to decrease.

高分子量成分の重量平均分子量は、好ましくは10万以上100万以下である。この分子量が10万未満であると接着層の硬化後の耐熱性が低下する傾向があり、分子量が100万を超えると接着層のフローが低下する傾向がある。なお、上記重量平均分子量は、ゲルパーミエーションクロマトグラフィー法(GPC)で標準ポリスチレンによる検量線を用いたポリスチレン換算値である。   The weight average molecular weight of the high molecular weight component is preferably 100,000 or more and 1,000,000 or less. When the molecular weight is less than 100,000, the heat resistance after curing of the adhesive layer tends to be reduced, and when the molecular weight exceeds 1,000,000, the flow of the adhesive layer tends to be reduced. In addition, the said weight average molecular weight is a polystyrene conversion value using the calibration curve by a standard polystyrene by the gel permeation chromatography method (GPC).

高分子量成分のガラス転移温度(Tg)は−50〜50℃であることが好ましい。特に、半導体ウエハダイシング時に接着シートの切断が容易になり、切断の際に樹脂くずが発生し難くなる点、及び耐熱性が高くなる点から、高分子量成分は、ガラス転移温度(Tg)が−20℃〜40℃で重量平均分子量が10万〜90万であることが好ましく、Tgが−10℃〜40℃で重量分子量が20万〜85万であることがより好ましい。   The glass transition temperature (Tg) of the high molecular weight component is preferably -50 to 50 ° C. In particular, the high molecular weight component has a glass transition temperature (Tg) of − from the point that it becomes easy to cut the adhesive sheet at the time of semiconductor wafer dicing, the resin waste is hardly generated at the time of cutting, and the heat resistance is high. The weight average molecular weight is preferably 100,000 to 900,000 at 20 ° C. to 40 ° C., and the weight molecular weight is more preferably 200,000 to 850,000 with a Tg of −10 ° C. to 40 ° C.

高分子量成分の割合は、樹脂全体量に対して70〜90質量%であることが好ましい。この割合の下限は74質量%であることが好ましく、75質量%であることがより好ましい。また、上限は83質量%であることが好ましく、79質量%であることがより好ましい。高分子量成分の割合が70質量%未満であると硬化後の弾性率が高すぎるため、樹脂封止時の圧力で凹凸表面を充填することが困難になる傾向があり、90質量%を超えると耐熱性が不足する傾向がある。   It is preferable that the ratio of a high molecular weight component is 70-90 mass% with respect to the resin whole quantity. The lower limit of this ratio is preferably 74% by mass, and more preferably 75% by mass. Moreover, it is preferable that an upper limit is 83 mass%, and it is more preferable that it is 79 mass%. If the proportion of the high molecular weight component is less than 70% by mass, the elastic modulus after curing is too high, and therefore it tends to be difficult to fill the uneven surface with the pressure at the time of resin sealing. There is a tendency for heat resistance to be insufficient.

接着層中の樹脂は、以上のような成分の他に、硬化促進剤、触媒、添加剤、カップリング剤等を含んでもよい。   The resin in the adhesive layer may contain a curing accelerator, a catalyst, an additive, a coupling agent and the like in addition to the above components.

接着層中の粒子の比表面積は、30〜400m/gであることが好ましい。これにより、接着層の流動性と表面平滑性が特に良好なものとなる。また、微細な粒子を少量添加すると、高温の弾性率が上昇するとともに充填性も良好となることから、比表面積は30〜200m/gであることがより好ましく、70〜140m/gであることが更に好ましい。なお、上記比表面積(BET比表面積)は、ブルナウアー・エメット・テーラー(Brunauer−Emmett−Teller)式により、粒子に窒素を吸着させてその表面積を測定した値である。このBET比表面積は市販されているBET装置により測定できる。 The specific surface area of the particles in the adhesive layer is preferably 30 to 400 m 2 / g. As a result, the fluidity and surface smoothness of the adhesive layer are particularly good. Further, when adding a small amount of fine particles, since the high-temperature elastic modulus becomes better packing property as well as increasing the specific surface area is more preferably from 30 to 200 m 2 / g, in 70~140m 2 / g More preferably it is. In addition, the said specific surface area (BET specific surface area) is the value which made nitrogen adsorb | suck to particle | grains and measured the surface area by Brunauer-Emmett-Teller (Brunauer-Emmett-Teller) type | formula. This BET specific surface area can be measured by a commercially available BET apparatus.

粒子の割合は、樹脂の全体量100重量部に対して2〜20重量部であることが好ましい。粒子の含有量が低いと耐熱性が低下する傾向があり、大きすぎると樹脂封止時の充填性向上の効果が低下する傾向がある。   The ratio of the particles is preferably 2 to 20 parts by weight with respect to 100 parts by weight of the total amount of the resin. If the content of the particles is low, the heat resistance tends to decrease, and if too large, the effect of improving the filling property at the time of resin sealing tends to decrease.

上記粒子は無機粒子であることが好ましい。無機粒子としては、水酸化アルミニウム、水酸化マグネシウム、炭酸カルシウム、炭酸マグネシウム、ケイ酸カルシウム、ケイ酸マグネシウム、酸化カルシウム、酸化マグネシウム、アルミナ、窒化アルミニウム、ほう酸アルミウイスカ、窒化ホウ素、結晶性シリカ、非晶性シリカ、アンチモン酸化物などが挙げられる。熱伝導性向上のためには、アルミナ、窒化アルミニウム、窒化ホウ素、結晶性シリカ、非晶性シリカ等が好ましい。溶融粘度の調整やチクソトロピック性の付与の目的には、水酸化アルミニウム、水酸化マグネシウム、炭酸カルシウム、炭酸マグネシウム、ケイ酸カルシウム、ケイ酸マグネシウム、酸化カルシウム、酸化マグネシウム、アルミナ、結晶性シリカ、非晶性シリカ等が好ましい。また、ダイシング性を向上させるためにはアルミナ、シリカが好ましい。   The particles are preferably inorganic particles. Inorganic particles include aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina, aluminum nitride, aluminum borate whisker, boron nitride, crystalline silica, non Examples thereof include crystalline silica and antimony oxide. In order to improve thermal conductivity, alumina, aluminum nitride, boron nitride, crystalline silica, amorphous silica and the like are preferable. For the purpose of adjusting melt viscosity and imparting thixotropic properties, aluminum hydroxide, magnesium hydroxide, calcium carbonate, magnesium carbonate, calcium silicate, magnesium silicate, calcium oxide, magnesium oxide, alumina, crystalline silica, non-crystalline silica Crystalline silica and the like are preferred. In order to improve dicing properties, alumina and silica are preferable.

本実施形態に係る接着シートは、例えば、上記樹脂及び粒子等の成分を有機溶媒中で混合、混練してワニスを調製し、このワニスの層を基材フィルム上に形成させ、加熱により乾燥した後、基材を除去して得ることができる。上記の混合、混練は、通常の撹拌機、らいかい機、三本ロール、ボールミル等の分散機を適宜、組み合わせて行うことができる。乾燥のための加熱の条件は、使用した溶媒が充分に揮散する条件であれば特に制限はないが、通常60℃〜200℃で、0.1〜90分間加熱して行う。   The adhesive sheet according to this embodiment is prepared by, for example, mixing and kneading components such as the resin and particles in an organic solvent to prepare a varnish, forming a layer of this varnish on a base film, and drying by heating. Thereafter, it can be obtained by removing the substrate. The above mixing and kneading can be carried out by appropriately combining dispersers such as a normal stirrer, a raking machine, a triple roll, and a ball mill. The heating condition for drying is not particularly limited as long as the solvent used is sufficiently volatilized, but the heating is usually performed at 60 to 200 ° C. for 0.1 to 90 minutes.

上記ワニスの調製に用いる有機溶媒は、材料を均一に溶解、混練又は分散できるものであれば制限はなく、従来公知のものを使用することができる。このような溶剤としては、例えば、ジメチルホルムアミド、ジメチルアセトアミド、N−メチルピロリドン、アセトン、メチルエチルケトン、シクロヘキサノンなどのケトン系溶媒、トルエン、キシレン等が挙げられる。これらの中でも、乾燥速度が速く、価格が安い点でメチルエチルケトン、シクロヘキサノンなどを使用することが好ましい。これら有機溶剤の一部は、通常、接着シート中の接着層に揮発分として残存する。   The organic solvent used for the preparation of the varnish is not particularly limited as long as the material can be uniformly dissolved, kneaded or dispersed, and conventionally known ones can be used. Examples of such a solvent include ketone solvents such as dimethylformamide, dimethylacetamide, N-methylpyrrolidone, acetone, methyl ethyl ketone, and cyclohexanone, toluene, xylene, and the like. Among these, it is preferable to use methyl ethyl ketone, cyclohexanone, etc. in terms of fast drying speed and low price. Some of these organic solvents usually remain as volatile components in the adhesive layer in the adhesive sheet.

接着層中に揮発分として残存する有機溶媒は、接着層全質量基準で0.01〜3重量%であることが好ましい。耐熱信頼性向上の観点からは、この割合は0.01〜2質量%であることがより好ましく、0.01〜1.5質量%であることがさらに好ましい。   The organic solvent remaining as a volatile component in the adhesive layer is preferably 0.01 to 3% by weight based on the total mass of the adhesive layer. From the viewpoint of improving heat resistance reliability, this ratio is more preferably 0.01 to 2% by mass, and further preferably 0.01 to 1.5% by mass.

接着シートは、接着層のみから構成されていてもよいし、支持体等の他の部材と組合わせた構成を有していてもよい。例えば、1又は2以上の接着層を従来公知のダイシングテープ上に積層したダイシングテープ一体型の接着シートが好適に用いられる。このダイシングテープ一体型の接着シートを用いると、半導体ウエハへのラミネート工程が一回で済むため、作業の更なる効率化が可能である。   The adhesive sheet may be composed only of the adhesive layer, or may have a configuration combined with another member such as a support. For example, a dicing tape-integrated adhesive sheet in which one or more adhesive layers are laminated on a conventionally known dicing tape is preferably used. When this dicing tape-integrated adhesive sheet is used, the laminating process on the semiconductor wafer is completed only once, so that the work efficiency can be further improved.

上記ダイシングテープとしては、例えば、ポリテトラフルオロエチレンフィルム、ポリエチレンテレフタレートフィルム、ポリエチレンフィルム、ポリプロピレンフィルム、ポリメチルペンテンフィルム、ポリイミドフィルムなどのプラスチックフィルム等が挙げられる。これらのフィルムに対して、必要に応じてプライマー塗布、UV処理、コロナ放電処理、研磨処理、エッチング処理等の表面処理を行ってもよい。   Examples of the dicing tape include plastic films such as a polytetrafluoroethylene film, a polyethylene terephthalate film, a polyethylene film, a polypropylene film, a polymethylpentene film, and a polyimide film. These films may be subjected to surface treatment such as primer application, UV treatment, corona discharge treatment, polishing treatment, etching treatment, etc., as necessary.

ダイシングテープは粘着性を有することが好ましい。そのため、上述のプラスチックフィルムに粘着性を付与したものを用いてもよいし、上述のプラスチックフィルムの片面に粘着剤層を設けても良い。粘着剤層は、液状成分の比率、高分子量成分のTgを調整すること等によって得られる適度なタック強度を有する樹脂組成物を塗布乾燥することで形成可能である。   The dicing tape preferably has adhesiveness. Therefore, you may use what gave the adhesiveness to the above-mentioned plastic film, and you may provide an adhesive layer in the single side | surface of the above-mentioned plastic film. The pressure-sensitive adhesive layer can be formed by applying and drying a resin composition having an appropriate tack strength obtained by adjusting the ratio of the liquid component and the Tg of the high molecular weight component.

接着シートを半導体装置を製造する際に用いる場合、接着層は、ダイシングの際には半導体チップが飛散しない粘着力を有し、その後のピックアップの際にはダイシングテープから容易に剥離することが望まれる。例えば、接着層の粘着性が高すぎるとピックアップが困難になることがある。そのため、適宜、接着層のタック強度を調節することが好ましい。そのためには、接着層の室温におけるフローを上昇させることにより、粘着強度及びタック強度が上昇する傾向があり、フローを低下させれば粘着強度及びタック強度が低下する傾向があることを利用すればよい。   When the adhesive sheet is used for manufacturing a semiconductor device, the adhesive layer should have an adhesive force that prevents the semiconductor chip from scattering during dicing, and should be easily peeled off from the dicing tape during subsequent pickup. It is. For example, if the adhesive layer is too sticky, picking up may be difficult. Therefore, it is preferable to appropriately adjust the tack strength of the adhesive layer. For that purpose, if the flow at room temperature of the adhesive layer is increased, the adhesive strength and tack strength tend to increase, and if the flow is decreased, the adhesive strength and tack strength tend to decrease. Good.

例えば、フローを上昇させるためには、可塑剤の含有量の増加、粘着付与材含有量の増加等の方法がある。逆にフローを低下させるためには、前記化合物の含有量を減らせばよい。前記可塑剤としては、例えば、単官能のアクリルモノマー、単官能エポキシ樹脂、液状エポキシ樹脂、アクリル系樹脂、エポキシ系のいわゆる希釈剤等が挙げられる。   For example, in order to increase the flow, there are methods such as increasing the plasticizer content and increasing the tackifier content. Conversely, in order to reduce the flow, the content of the compound may be reduced. Examples of the plasticizer include monofunctional acrylic monomers, monofunctional epoxy resins, liquid epoxy resins, acrylic resins, and epoxy-based so-called diluents.

ダイシングテープ上に接着層を積層する方法としては、印刷のほか、予め作成した接着層をダイシングテープ上にプレスやホットロールによってラミネートする方法が挙げられる。特に、連続的に製造でき、効率が良い点でホットロールによってラミネートする方法が好ましい。   Examples of the method for laminating the adhesive layer on the dicing tape include printing and a method of laminating a previously prepared adhesive layer on the dicing tape by a press or a hot roll. In particular, a method of laminating with a hot roll is preferable because it can be continuously produced and has high efficiency.

ダイシングテープの膜厚は、特に制限はなく、接着層の膜厚や接着シートの用途によって適宜、当業者の知識に基づいて定められるものであるが、経済性がよく、フィルムの取扱い性が良い点で好ましくは60〜150μm、より好ましくは70〜130μmである。   The film thickness of the dicing tape is not particularly limited, and is determined based on the knowledge of those skilled in the art as appropriate depending on the film thickness of the adhesive layer and the use of the adhesive sheet. However, the film thickness is good and the film is easy to handle. In this respect, the thickness is preferably 60 to 150 μm, more preferably 70 to 130 μm.

さらに他の実施形態として、接着層自体がダイシングテープとしての役割を果たしても良い。このような接着層を有する接着シートは、ダイシングダイボンド一体型接着シートなどと呼ばれ、一つのシートでダイシングテープとしての役割と、接着シートとしての役割をともに果たす。接着シートにこのような機能を持たせるには、例えば、接着層が、光硬化性高分子量成分、光硬化性モノマ、光開始剤等の光硬化性成分を含んでいればよい。   As yet another embodiment, the adhesive layer itself may serve as a dicing tape. An adhesive sheet having such an adhesive layer is called a dicing die bond integrated adhesive sheet or the like, and a single sheet serves as both a dicing tape and an adhesive sheet. In order to give such a function to the adhesive sheet, for example, the adhesive layer may contain a photocurable component such as a photocurable high molecular weight component, a photocurable monomer, or a photoinitiator.

本実施形態に係る接着シートを用いた半導体装置の製造において用いられる半導体ウェハとしては、単結晶シリコンの他、多結晶シリコン、各種セラミック、ガリウム砒素などの化合物半導体などが挙げられる。   Examples of the semiconductor wafer used in the manufacture of the semiconductor device using the adhesive sheet according to the present embodiment include single crystal silicon, polycrystalline silicon, various ceramics, and compound semiconductors such as gallium arsenide.

本実施形態に係る接着シートは、配線回路に起因して形成された凹凸表面の充填性が良好であり、半導体装置の製造における半導体チップと支持部材との間や半導体チップ同士の間を接着するための工程において、接着信頼性に優れる接着シートとして使用することができる。本実施形態に係る接着シートは、半導体素子搭載用の支持部材に半導体チップを実装する場合に必要な耐熱性、耐湿性、絶縁性を有し、かつ作業性にも優れる。   The adhesive sheet according to the present embodiment has a good filling property on the uneven surface formed due to the wiring circuit, and adheres between the semiconductor chip and the support member or between the semiconductor chips in the manufacture of the semiconductor device. Therefore, it can be used as an adhesive sheet having excellent adhesion reliability. The adhesive sheet according to the present embodiment has heat resistance, moisture resistance, insulating properties necessary for mounting a semiconductor chip on a semiconductor element mounting support member, and is excellent in workability.

図2は、本発明に係る半導体装置の一実施形態を示す断面図である。図2に示す半導体装置100は、同サイズの半導体チップを2つ以上備えるパッケージであって、いわゆるスタックドCSPと称されるものである。半導体装置100は、支持部材20及び支持部材20の一面側において積層された3個の半導体チップA1を備えている。そして、半導体チップA1と支持部材20との間、及び半導体チップA1同士の間に、上記実施形態に係る接着シートを用いて形成された接着層10aが介在している。接着層10aにおいては、上記樹脂中の熱硬化性成分が硬化している。   FIG. 2 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention. A semiconductor device 100 shown in FIG. 2 is a package including two or more semiconductor chips of the same size, and is called a so-called stacked CSP. The semiconductor device 100 includes a support member 20 and three semiconductor chips A1 stacked on one surface side of the support member 20. And the adhesive layer 10a formed using the adhesive sheet which concerns on the said embodiment is interposed between semiconductor chip A1 and the supporting member 20, and between semiconductor chips A1. In the adhesive layer 10a, the thermosetting component in the resin is cured.

支持部材20は、基板3と、基板3の一面上に設けられた配線4と、配線4の下方において基板3を貫通する貫通孔を通って基板3の他方面側に導出された端子5とから主として構成される。支持部材20の配線4側の面は、配線4が形成されているために凹凸表面が形成されている。各半導体チップA1は、ワイヤ2を介して配線4と接続されている。   The support member 20 includes a substrate 3, a wiring 4 provided on one surface of the substrate 3, and a terminal 5 led out to the other surface side of the substrate 3 through a through hole penetrating the substrate 3 below the wiring 4. Consists mainly of. The surface of the support member 20 on the wiring 4 side has an uneven surface because the wiring 4 is formed. Each semiconductor chip A1 is connected to the wiring 4 through the wire 2.

このような構成を有する半導体装置100の製造において、支持部材20の凹凸表面を埋込み、かつ上部の半導体チップA1との絶縁性を確保することが可能な接着シートが求められている。   In the manufacture of the semiconductor device 100 having such a configuration, an adhesive sheet capable of embedding the uneven surface of the support member 20 and ensuring insulation from the upper semiconductor chip A1 is required.

以下、実施例を挙げて本発明についてより具体的に説明する。ただし、本発明は以下の実施例に限定されるものではない。   Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited to the following examples.

(実施例1)
エポキシ樹脂「YDCN−703」(東都化成(株)製商品名、クレゾールノボラック型エポキシ樹脂、エポキシ当量210)36重量部と、エポキシ樹脂の硬化剤としてのフェノール樹脂「ミレックスXLC−LL」(三井化学(株)製商品名、フェノール樹脂)30.1重量部と、シランカップリング剤である「A−1160」(日本ユニカー(株)製商品名)2.1重量部及び「A−189」(日本ユニカー(株)製商品名)1.1重量部と、シリカフィラー(粒子)である「アエロジルR972」(日本アエロジル株式会社、平均粒径:0.016μm、比表面積120m/g)21.2重量部とからなる組成物にシクロヘキサノンを加え、攪拌混合してからビーズミルを用いて更に90分混練した。
Example 1
36 parts by weight of an epoxy resin “YDCN-703” (trade name, manufactured by Tohto Kasei Co., Ltd., cresol novolak type epoxy resin, epoxy equivalent 210) and a phenol resin “Mirex XLC-LL” (Mitsui Chemicals) as a curing agent for the epoxy resin 30.1 parts by weight (trade name, phenol resin) manufactured by Co., Ltd., and 2.1 parts by weight of “A-1160” (trade name, manufactured by Nihon Unicar Co., Ltd.), which is a silane coupling agent, and “A-189” ( Nippon Unicar Co., Ltd. product name) 1.1 parts by weight and silica filler (particles) “Aerosil R972” (Nippon Aerosil Co., Ltd., average particle size: 0.016 μm, specific surface area 120 m 2 / g) Cyclohexanone was added to the composition consisting of 2 parts by weight, mixed with stirring, and then kneaded for 90 minutes using a bead mill.

これにグリシジルアクリレート又はグリシジルメタクリレートに由来するモノマー単位を3質量%含むアクリルゴムである「HTR−860P−3」(ナガセケムテックス(株)製商品名、重量平均分子量80万)を200重量部、及び硬化促進剤としての「キュアゾール2PZ−CN」(四国化成(株)製商品名、1−シアノエチル−2−フェニルイミダゾール)0.075重量部を加え、攪拌混合して、接着剤組成物のワニスを得た。   200 parts by weight of "HTR-860P-3" (trade name, manufactured by Nagase Chemtex Co., Ltd., weight average molecular weight: 800,000), which is an acrylic rubber containing 3% by mass of a monomer unit derived from glycidyl acrylate or glycidyl methacrylate, And 0.075 parts by weight of “Curazole 2PZ-CN” (trade name, 1-cyanoethyl-2-phenylimidazole, manufactured by Shikoku Kasei Co., Ltd.) as a curing accelerator was added, mixed by stirring, and the varnish of the adhesive composition Got.

このワニスを、基材上に塗布し、90℃10分間、120℃で5分間加熱することにより乾燥して、Bステージ状態の接着層(膜厚40μm)がポリエチレンテレフタレートフィルム上に形成された接着シートを得た。この接着層のフローは220μmであった。基材は、厚さ50μmの離型処理したポリエチレンテレフタレートフィルムを用いた。   The varnish was applied on a substrate and dried by heating at 90 ° C. for 10 minutes and at 120 ° C. for 5 minutes to form a B-staged adhesive layer (film thickness 40 μm) on the polyethylene terephthalate film. A sheet was obtained. The flow of this adhesive layer was 220 μm. As the substrate, a polyethylene terephthalate film having a thickness of 50 μm and subjected to a release treatment was used.

接着層を半導体ウエハ(厚さ80μm)に80℃に加熱しながらラミネートし、端部を切断した。次いで、接着層上にダイシングテープを載置し、ホットロールラミネータ(Du Pont製Riston)を用いて25℃でラミネートした。ダイシングテープは古河電工(株)製「UC3004M−80」(膜厚100μm)を用いた。   The adhesive layer was laminated to a semiconductor wafer (thickness: 80 μm) while heating to 80 ° C., and the edge was cut. Next, a dicing tape was placed on the adhesive layer and laminated at 25 ° C. using a hot roll laminator (Riston manufactured by Du Pont). As the dicing tape, “UC3004M-80” (film thickness: 100 μm) manufactured by Furukawa Electric Co., Ltd. was used.

(実施例2、3)
配合比を表1の実施例2、3に示すように変更した以外は、実施例1と同様の工程を経て接着シートを作製した。
(Examples 2 and 3)
An adhesive sheet was produced through the same steps as in Example 1 except that the blending ratio was changed as shown in Examples 2 and 3 in Table 1.

(比較例1〜6)
配合比を表1の比較例1〜6に示すように変更した以外は、実施例1と同様の工程を経て接着シートを作製した。
(Comparative Examples 1-6)
Except having changed the compounding ratio as shown in Comparative Examples 1-6 of Table 1, the adhesive sheet was produced through the process similar to Example 1. FIG.

なお、実施例1〜3、及び比較例1〜3で用いた樹脂の溶融粘度(厚さ500μm)を測定したところ、20〜100万Pa・sであった。   In addition, when melt viscosity (500 micrometers in thickness) of resin used in Examples 1-3 and Comparative Examples 1-3 was measured, it was 20-1 million Pa.s.

(評価)
実施例1〜3及び比較例1〜7で得られた接着シートを用いて以下に示す評価項目について評価を行った。
(Evaluation)
Evaluation items shown below were evaluated using the adhesive sheets obtained in Examples 1 to 3 and Comparative Examples 1 to 7.

(1)ラミネート性
ホットロールラミネータ(60℃、0.3m/分、0.3MPa)により、幅10mmの接着層を半導体ウエハに貼り合わせた。次いで、25℃の雰囲気中、引張速度50mm/分で90°の角度で剥がしたときの応力を測定して、90°ピール強度を求めた。測定装置はTOYOBALWIN製UTM−4−100型テンシロンを用いた。この場合の90°ピール強度が30N/m以上の場合はラミネート性良好、90°ピール強度が30N/m未満の場合はラミネート性不良とした。
(1) Laminating property An adhesive layer having a width of 10 mm was bonded to a semiconductor wafer by a hot roll laminator (60 ° C., 0.3 m / min, 0.3 MPa). Then, the stress when peeled at an angle of 90 ° at a tensile speed of 50 mm / min in an atmosphere of 25 ° C. was measured to obtain a 90 ° peel strength. As a measuring apparatus, UTM-4-100 type Tensilon manufactured by TOYOBALWIN was used. In this case, when the 90 ° peel strength was 30 N / m or more, the laminate property was good, and when the 90 ° peel strength was less than 30 N / m, the laminate property was poor.

(2)充填性、耐リフロークラック性及び耐温度サイクル性
接着シートを半導体ウェハに貼り合せ、基材を剥離して、接着層に市販の紫外線硬化型ダイシングテープ(古河電工(株)製、商品名:UC−334 EP−110)を貼り合せた。このダイシングテープは基材上に粘着層が形成されたものであり、貼り合わせの際には、粘着層と接着層とが接合するようにした。続いて、ダイサーを用いて半導体ウェハ及び接着層をダイシングしてから、ダイシングテープの基材側から紫外線を照射(500J/cm)した。照射後、接着層からダイシングテープを剥離して、接着層付き半導体チップを得た。
(2) Fillability, reflow crack resistance and temperature cycle resistance Adhesive sheets are bonded to semiconductor wafers, the substrate is peeled off, and a commercially available UV curable dicing tape (Furukawa Electric Co., Ltd., product) Name: UC-334 EP-110). This dicing tape has a pressure-sensitive adhesive layer formed on a substrate, and the pressure-sensitive adhesive layer and the adhesive layer are bonded to each other at the time of bonding. Subsequently, the semiconductor wafer and the adhesive layer were diced using a dicer, and then irradiated with ultraviolet rays (500 J / cm 2 ) from the base material side of the dicing tape. After irradiation, the dicing tape was peeled off from the adhesive layer to obtain a semiconductor chip with an adhesive layer.

得られた接着層付き半導体チップを、配線が設けられた支持部材(凹凸5μmのガラスエポキシ基板)上に接着層が支持部材と密着する向きで載せ、150℃に加熱しながら0.4×9.8Nに3秒間加圧して、半導体チップを支持部材に圧着した。その後、170℃のホットプレート上で1時間又は5時間加熱する高温加熱処理により、ワイヤボンディングと同等の熱履歴を与えた。また、この高温加熱処理を行わなかったサンプルも準備した。   The obtained semiconductor chip with an adhesive layer was placed on a support member (a glass epoxy substrate with 5 μm unevenness) provided with wiring in a direction in which the adhesive layer was in close contact with the support member, and heated to 150 ° C. to 0.4 × 9. The semiconductor chip was pressure-bonded to the support member by applying pressure to 8N for 3 seconds. Then, the heat history equivalent to wire bonding was given by the high-temperature heat processing which heats on a 170 degreeC hotplate for 1 hour or 5 hours. Moreover, the sample which did not perform this high temperature heat processing was also prepared.

次に、エポキシ封止樹脂(日立化成工業(株)製、商品名:CEL−9700HF)を用いて180℃、6.75MPa、90秒の条件で樹脂封止して、半導体装置のサンプルを作製した。得られた半導体装置を、JEDEC(Joint Electron Device Engineering Council)で規定されるレベル2(吸湿条件:85℃/60%RH、168 h)の条件で加湿処理した。   Next, an epoxy sealing resin (manufactured by Hitachi Chemical Co., Ltd., trade name: CEL-9700HF) is used for resin sealing under conditions of 180 ° C., 6.75 MPa, 90 seconds, and a semiconductor device sample is manufactured. did. The obtained semiconductor device was humidified under the condition of level 2 (moisture absorption condition: 85 ° C./60% RH, 168 h) defined by JEDEC (Joint Electron Device Engineering Council).

Pbフリーはんだ実装に対応した高温リフロー試験として、サンプル表面の最高温度が260℃に20秒間保持されるように温度設定したIRリフロー炉にサンプルを通し、室温放置により冷却する処理を2回繰り返した。   As a high-temperature reflow test corresponding to Pb-free solder mounting, the process of passing the sample through an IR reflow furnace whose temperature was set so that the maximum temperature of the sample surface was maintained at 260 ° C. for 20 seconds, and cooling by standing at room temperature was repeated twice. .

リフロー試験前後の各サンプルについて、超音波探査映像装置を用いて、接着層が支持部材から剥離しているか否かを確認した。サンプル10個すべてでクラック、ボイド、未充填部が発生しなかった場合に「良」とし、1個以上発生した場合に「不良」とした。なお、上記評価の結果のうち、リフロー試験前は充填性に、リフロー試験後は耐リフロー性にそれぞれ対応する。   For each sample before and after the reflow test, it was confirmed whether or not the adhesive layer was peeled off from the support member using an ultrasonic exploration imaging apparatus. When no cracks, voids, or unfilled portions were generated in all 10 samples, “good” was determined, and when one or more samples were generated, “bad” was determined. In addition, among the results of the above evaluation, it corresponds to the filling property before the reflow test and corresponds to the reflow resistance after the reflow test.

また、耐温度サイクル性の評価のため、−55℃雰囲気に30分間放置した後125℃の雰囲気に30分間放置する工程を1サイクルとして、1000サイクルの熱履歴を各サンプルに与えた。そして、超音波探査映像装置を用いて剥離の状態を測定した。サンプル10個すべてで剥離が発生していなかった場合に「良」とし、1個以上発生した場合に「不良」とした。   In addition, for evaluation of temperature cycle resistance, each sample was given a heat history of 1000 cycles, with one cycle being a step of leaving in an atmosphere of −55 ° C. for 30 minutes and then in an atmosphere of 125 ° C. for 30 minutes. And the state of peeling was measured using the ultrasonic survey imaging device. When no peeling occurred in all 10 samples, it was judged as “good”, and when one or more pieces occurred, it was judged as “bad”.

(3)引張弾性率
170℃で1時間又は5時間の加熱により硬化した接着層から5×30mmの大きさに切り出した試験片に、20mmの間隔で2箇所に印を付し、その一端に荷重(W)のおもりを取り付けて吊り下げた状態で170℃の高温槽に投入した。投入から60秒後におけるフィルムの伸び量ΔLを測定し、その部分の断面積S(=100/(20+ΔL))を求めた。そして、高温弾性率E’をE’=20×W/(ΔL×S)の関係から算出した。なお、試験片の伸び量が5mm未満になるようにおもりの荷重を調整した。
(3) Tensile elastic modulus A test piece cut out to a size of 5 × 30 mm from an adhesive layer cured by heating at 170 ° C. for 1 hour or 5 hours is marked at two locations at intervals of 20 mm, and one end thereof. A weight (W) weight was attached and the suspension was suspended in a high-temperature bath at 170 ° C. The elongation amount ΔL of the film 60 seconds after the introduction was measured, and the cross-sectional area S (= 100 / (20 + ΔL)) of the portion was determined. And high temperature elastic modulus E 'was computed from the relationship of E' = 20 * W / ((DELTA) L * S). The weight load was adjusted so that the elongation of the test piece was less than 5 mm.

(4)貯蔵弾性率
170℃で1時間又は5時間の加熱により硬化した接着層について、動的粘弾性測定装置(レオロジー社製、DVE−V4)を用いた動的粘弾性測定により、200℃における貯蔵弾性率を測定した。動的粘弾性測定は、サンプルサイズ:長さ20mm、幅4mm、温度範囲−30℃〜200℃、昇温速度5℃/min、引張りモード、10Hz、自動静荷重の条件で行った。
(4) Storage elastic modulus About 200 degreeC by the dynamic viscoelasticity measurement using the dynamic viscoelasticity measuring apparatus (Rheology company make, DVE-V4) about the contact bonding layer hardened | cured by heating at 170 degreeC for 1 hour or 5 hours. The storage elastic modulus was measured. The dynamic viscoelasticity measurement was performed under the conditions of sample size: length 20 mm, width 4 mm, temperature range -30 ° C to 200 ° C, heating rate 5 ° C / min, tensile mode 10 Hz, automatic static load.

(5)ピール強度(硬化後)
接着層の両面にポリイミドフィルム(ユーピレックスS、厚さ50μm)を積層し、170℃で5時間の加熱により接着層を硬化した試験片を作製した。この試験片を幅10mmに切断し、25℃の雰囲気下でポリイミドフィルムの両端を50mm/minの速度で180°ピール強度を測定した。
(5) Peel strength (after curing)
A polyimide film (Upilex S, thickness 50 μm) was laminated on both surfaces of the adhesive layer, and a test piece was prepared by curing the adhesive layer by heating at 170 ° C. for 5 hours. This test piece was cut into a width of 10 mm, and 180 ° peel strength was measured at a speed of 50 mm / min at both ends of the polyimide film in an atmosphere of 25 ° C.

Figure 0004957064
Figure 0004957064

表1に示される結果から明らかなように、実施例1〜3の接着シートは、高いピール強度を発現するとともに、樹脂封止における凹凸表面への充填性や、耐リフロー性も良好であることがわかる。これに対して、比較例1〜7の接着シートは、いずれも充填性又は耐リフロー性が十分でないことがわかる。   As is clear from the results shown in Table 1, the adhesive sheets of Examples 1 to 3 exhibit high peel strength and have good filling properties on the uneven surface in resin sealing and reflow resistance. I understand. On the other hand, it can be seen that all of the adhesive sheets of Comparative Examples 1 to 7 are insufficient in filling property or reflow resistance.

以上の結果より、本発明によれば以下の作用効果が奏されることが確認された。すなわち、本発明に係る接着シートは、支持部材の凹凸表面を樹脂封止後に十分に充填することが可能であり、また、支持部材に半導体チップを実装するために必要な耐熱性及び耐湿性の点でも優れることが確認された。すなわち、本発明に係る接着シートによれば、半導体装置の信頼性の向上と共に、半導体装置の加工速度、歩留の向上を図ることが可能となる。   From the above results, it was confirmed that the following effects were exhibited according to the present invention. That is, the adhesive sheet according to the present invention can sufficiently fill the uneven surface of the support member after resin sealing, and has heat resistance and moisture resistance necessary for mounting a semiconductor chip on the support member. It was confirmed that it was excellent in terms. That is, according to the adhesive sheet of the present invention, it is possible to improve the processing speed and yield of the semiconductor device as well as improving the reliability of the semiconductor device.

接着層付き半導体チップ及びこれが接着される支持部材の一実施形態を示す断面図である。It is sectional drawing which shows one Embodiment of the semiconductor chip with an adhesive layer, and the supporting member to which this is adhere | attached. 本発明に係る半導体装置の一実施形態を示す断面図である。It is sectional drawing which shows one Embodiment of the semiconductor device which concerns on this invention.

符号の説明Explanation of symbols

A1…半導体チップ、2…ワイヤ、3…基板、4…配線、5…端子、10…接着層、10a…接着層(硬化後)、20…支持部材、100…半導体装置。   A1 ... Semiconductor chip, 2 ... Wire, 3 ... Substrate, 4 ... Wiring, 5 ... Terminal, 10 ... Adhesive layer, 10a ... Adhesive layer (after curing), 20 ... Support member, 100 ... Semiconductor device.

Claims (4)

導体チップ搭載用の支持部材に、170℃で5時間の熱履歴を受けたときに、170℃における引張弾性率が0.1〜2MPa、且つ、200℃における貯蔵弾性率が1〜6MPaとなる接着層を介して、該接着層と前記支持部材の凹凸表面との間に空隙が残された状態で半導体チップを接着する工程と、
前記支持部材に接着された半導体チップをワイヤボンディングにより前記支持部材に接続する工程と、
前記支持部材に接続された半導体チップを樹脂封止するとともに該半導体チップと前記支持部材との間の接着層によって前記空隙を充填する工程と、を備え
前記接着層が、エポキシ樹脂及びその硬化剤並びにアクリルゴムを含む樹脂と、比表面積が30〜400m /gである粒子と、からなり、前記硬化剤がフェノール樹脂で、前記粒子がシリカ粒子であり、
前記樹脂全体量に対して、エポキシ樹脂及びその硬化剤の合計量の割合が21〜26質量%、アクリルゴムの割合が74〜79質量%であり、
前記樹脂100重量部に対して、前記粒子の割合が1.8〜20重量部である、
半導体装置の製造方法。
A support member for semi-conductor chip mounting, when subjected to heat history of 5 hours at 170 ° C., 0.1 to 2 MPa tensile elastic modulus at 170 ° C., and the storage elastic modulus at 200 ° C. and a 1~6MPa via an adhesive layer formed, a step of bonding a semiconductor chip in a state where the gap is left between the uneven surface of the support member and the adhesive layer,
Connecting the semiconductor chip bonded to the support member to the support member by wire bonding;
Filling the gap with a bonding layer between the semiconductor chip and the support member while resin-sealing the semiconductor chip connected to the support member ,
The adhesive layer comprises an epoxy resin, a curing agent thereof, and a resin containing acrylic rubber, and particles having a specific surface area of 30 to 400 m 2 / g, the curing agent is a phenol resin, and the particles are silica particles. Yes,
The ratio of the total amount of the epoxy resin and its curing agent is 21 to 26% by mass, and the ratio of the acrylic rubber is 74 to 79% by mass with respect to the total amount of the resin.
The ratio of the particles is 1.8 to 20 parts by weight with respect to 100 parts by weight of the resin.
Production how of the semiconductor device.
記支持部材に接続された半導体チップの前記支持部材と反対側に接着層を介して半導体チップを積層し、該半導体チップをワイヤボンディングにより前記支持部材に接続する工程を1又は2以上含む工程を更に備える、請求項1記載の製造方法 Before SL via the adhesive layer to the support member and the opposite side of the connected semiconductor chip to a supporting member by stacking a semiconductor chip, a process the semiconductor chip including the step of connecting to the support member 1 or more by wire bonding The manufacturing method according to claim 1, further comprising : 導体ウエハ、接着層及びダイシングテープがこの順で積層された積層体から、半導体チップ、接着層及びダイシングテープがこの順で積層されたチップ積層体を回転刃によって切り出し、ダイシングテープを除去して接着層付き半導体チップを得る工程を更に備え、
当該接着層付き半導体チップを前記支持部材上に載置し、0.001〜1MPaで加圧することにより前記支持部材に半導体チップを接着する、請求項1又は2に記載の製造方法
Semiconductors wafers, a laminate adhesive layer and the dicing tape are laminated in this order, the semiconductor chip is cut out by the adhesive layer and the laminate chip dicing tape are laminated in this order rotary blade, to remove the dicing tape A step of obtaining a semiconductor chip with an adhesive layer;
Placing the adhesive layer with the semiconductor chip on the support member, bonding the semiconductor chip to the support member by pressurizing with 0.001~1MPa, The method according to claim 1 or 2.
請求項1〜3のいずれか一項に記載の製造方法により得られる、半導体装置 The semiconductor device obtained by the manufacturing method as described in any one of Claims 1-3 .
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