JP4956060B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  2. Description of the Related Art Conventionally, a structure called an IMPATT (Impactation Avalanche Transit Time) diode that performs a microwave oscillation operation is known as a semiconductor device. The operating principle of this IMPATT diode is that an alternating current is applied to a semiconductor, carriers are generated by impact ionization in the semiconductor, and the generated carriers are moved at a saturation drift velocity. More specifically, a reverse bias that is equal to or less than the breakdown voltage and close to the breakdown voltage is applied to the pn junction diode, and an AC bias is applied to the reverse bias. Adjust to exceed the voltage. As a result, when the applied bias is less than or equal to the breakdown voltage, no breakdown occurs and no current flows. When the applied bias exceeds the breakdown voltage, an avalanche breakdown occurs and a large current flows. As a result, a large current having the same frequency as the frequency of the AC voltage to be applied can be supplied to the external circuit. The current due to avalanche breakdown increases exponentially as soon as the avalanche breakdown voltage is exceeded.

A general structure of a general IMPATT diode is that an n-type avalanche breakdown layer, a drift layer in which electrons of an i-type saturation velocity travel, an n ⁺ -type ohmic contact layer on a p ⁺ -type semiconductor substrate. And an electrode in ohmic contact is provided on the upper surface of the n ⁺ -type ohmic contact layer and the lower surface of the semiconductor substrate. When the semiconductor substrate is n ⁺ type, the avalanche breakdown layer is p-type and the ohmic contact layer on the upper surface of the drift layer is p ⁺ -type. Here, the i type means an intrinsic type having a low impurity concentration.

  The drift layer in this IMPATT diode is a layer provided for the purpose of adjusting the time for electrons generated by avalanche breakdown to reach the upper surface electrode, and the arrival time of the electrons and the frequency of the applied AC bias do not match. They cancel each other's waves and cannot efficiently output high frequencies to the outside. In other words, the thickness and concentration of the drift layer are determined in accordance with the frequency of the AC bias applied to the IMPATT diode, and the breakdown voltage is determined only when the drift layer thickness and concentration are determined. It was very difficult to design for

  In addition, since the avalanche breakdown layer of the conventional IMPATT diode is formed on a smooth semiconductor substrate as described above and is a layer having a conductivity type opposite to that of the semiconductor substrate, the starting point of the avalanche breakdown is stronger than the surroundings. It becomes the part where the electric field was applied. For this reason, there is a problem that a large current flows locally due to crystal defects, concentration variations, and the like. When avalanche breakdown occurs, a very large current flows when a large voltage is applied, but the product of voltage and current is converted into heat in the element, and locally becomes a high temperature of several thousand degrees. Crystal defects (penetration defects) and abnormal diffusion of the electrode material occur, causing a short circuit between the upper surface electrode and the lower surface electrode. In the conventional IMPATT diode using Si, only a small current can flow because of its low thermal conductivity. In order to suppress such breakdown, it is necessary to suppress the applied bias in order to suppress the avalanche current that increases exponentially.

  By the way, although it is not an IMPATT diode, the power element using the field emission effect of the electron in solid is proposed conventionally (for example, refer to patent documents 1). Specifically, this power element is a trench gate type insulated gate bipolar transistor, and includes a sharpened portion at a part of a pn junction composed of a first conductivity type collector layer and a second conductivity type base layer, It has a structure with a curvature radius of 0.5 μm or less. In such a power element, it is disclosed that, for example, the element material is made of SiC, GaN, or diamond having high thermal conductivity in order to avoid thermal damage even when a large current flows.

JP 2000-106435 A

  The materials such as SiC, GaN, and diamond having high thermal conductivity as described above are wide band gap semiconductors, and no examples of applying such wide band gap semiconductors as IMPATT diodes have been known so far. Also, if these wide bandgap semiconductor materials are applied as they are to the known IMPATT diode structure, for example, an IMPATT diode made of SiC is used as a microwave oven and a high frequency of 2.45 GHz will be output. In this case, the avalanche breakdown voltage determined by the drift layer exceeds 1,000V. For this reason, the number of parts such as a step-up transformer, a protection circuit, and insulation is increased, resulting in an increase in cost and weight and a decrease in reliability.

  In the power element described in Patent Document 1, when the electric field concentration portion is formed at the junction between the first conductive type semiconductor region and the second conductive type semiconductor region, the upper surface of the first conductive type semiconductor region is formed. After forming a V-shaped groove by anisotropic etching and performing thermal oxidation to sharpen the tip portion to form an electric field concentration portion, the second conductivity type semiconductor region is epitaxially grown. At this time, the etching rate varies greatly due to variations in etchant concentration, system temperature distribution, impurity concentration in the etching region, etc., partly overetching, and variation in the height of the electric field concentration portion. There was a problem that it occurred. Also, the sharpened tip of the electric field concentration part is sharp, so that the physical strength is weak, and the tip may be damaged in the subsequent process, and this also causes variations in the height of the electric field concentration part. There was a problem that would occur.

  The present invention has been made in view of the above, and in a semiconductor device in which a reverse bias is applied to a pn junction to cause avalanche breakdown, a large current can flow, and an increase in cost and weight, and reliability. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that do not cause a decrease in the temperature. Another object of the present invention is to provide a semiconductor device in which the height of the electric field concentration portion provided in the semiconductor device does not vary and a manufacturing method thereof.

  In order to solve the above-described problems and achieve the object, the present invention provides a second conductivity type semiconductor that is epitaxially formed on a first conductivity type semiconductor substrate in order by a wide band gap semiconductor of the same type as the semiconductor substrate. Layer, drift layer, and ohmic contact layer of the second conductivity type semiconductor, first and second electrodes respectively formed on the lower surface of the semiconductor substrate and the upper surface of the ohmic contact layer, and the second conductivity type semiconductor layer A plurality of electric field concentration portions of a first conductivity type semiconductor formed in a convex shape upward from the semiconductor substrate side interface, and applying a reverse bias voltage between the first and second electrodes Then, avalanche breakdown is caused in a pn junction portion between the plurality of electric field concentration portions and the second conductive type semiconductor layer.

  The present invention also provides a second conductivity type semiconductor layer, a drift layer, and a second conductivity type semiconductor that are epitaxially formed on a first conductivity type semiconductor substrate in order by a wide band gap semiconductor of the same type as the semiconductor substrate. An ohmic contact layer, first and second electrodes formed on the lower surface of the semiconductor substrate and the upper surface of the ohmic contact layer, respectively, and formed in contact with the semiconductor substrate side interface in the second conductivity type semiconductor layer And a plurality of electric field concentration portions formed by second conductivity type impurities having a concentration higher than that of the second conductivity type semiconductor layer, and applying a reverse bias voltage between the first and second electrodes. An avalanche breakdown is caused in a pn junction portion between the semiconductor substrate and the plurality of electric field concentration portions.

  Furthermore, the present invention provides a second conductivity type semiconductor layer, a drift layer, and a second conductivity type semiconductor formed on a first conductivity type semiconductor substrate in an epitaxial manner by a wide band gap semiconductor of the same type as that of the semiconductor substrate. An ohmic contact layer, first and second electrodes respectively formed on a lower surface of the semiconductor substrate and an upper surface of the ohmic contact layer, and in contact with the second conductive semiconductor layer side interface in the semiconductor substrate And a plurality of electric field concentration portions formed by the second conductivity type impurities having a higher concentration than the second conductivity type semiconductor layer, and applying a reverse bias voltage between the first and second electrodes. Then, avalanche breakdown is caused in a pn junction portion between the semiconductor substrate and the plurality of electric field concentration portions.

  In order to solve the above-described problems and achieve the object, the present invention is a method of manufacturing a semiconductor device in which an avalanche breakdown is caused in a pn junction portion by applying a reverse bias voltage, on a semiconductor substrate of a first conductivity type. In addition, the step of epitaxially forming the first second conductivity type semiconductor layer using the same type of wide band gap semiconductor as the semiconductor substrate, and a mask in which holes having a predetermined diameter are formed with a predetermined surface density, A first conductivity type impurity is ion-implanted into the first second conductivity type semiconductor layer, the implanted first conductivity type impurity is activated, and the semiconductor substrate side is provided in the first second conductivity type semiconductor layer. Forming the pn junction portion between the electric field concentration portion and the first second-conductivity-type semiconductor layer by forming an electric field concentration portion convexly upward from the interface; Second conductivity type A step of epitaxially forming a drift layer and an ohmic contact layer of a second conductivity type semiconductor in order on the conductor layer by using the same type of wide band gap semiconductor as the semiconductor substrate, and a lower surface of the semiconductor substrate and an upper surface of the ohmic contact layer Forming a first electrode and a second electrode for applying the reverse bias voltage respectively.

  The present invention also relates to a method of manufacturing a semiconductor device in which an avalanche breakdown is caused in a pn junction portion by applying a reverse bias voltage, and a wide band gap of the same type as the semiconductor substrate is formed on a first conductivity type semiconductor substrate. Epitaxially implanting a second conductivity type impurity into the second conductivity type semiconductor layer using a step of epitaxially forming a second conductivity type semiconductor layer with a semiconductor and a mask having holes with a predetermined diameter formed at a predetermined surface density Then, the implanted second conductivity type impurity is activated so that the second conductivity type impurity in the second conductivity type semiconductor layer is in contact with the interface on the semiconductor substrate side and has a higher concentration than the second conductivity type semiconductor layer. Forming a pn junction portion between the electric field concentration portion and the semiconductor substrate, and forming the semiconductor on the second conductivity type semiconductor layer. A step of epitaxially forming a drift layer and an ohmic contact layer of a second conductivity type semiconductor in sequence using a wide band gap semiconductor of the same type as the substrate; and applying the reverse bias voltage to the lower surface of the semiconductor substrate and the upper surface of the ohmic contact layer, respectively. Forming a first electrode and a second electrode to be applied.

  Furthermore, the present invention is a method of manufacturing a semiconductor device in which an avalanche breakdown is caused in a pn junction portion by applying a reverse bias voltage, and the first method uses a mask in which holes having a predetermined diameter are formed with a predetermined surface density. A second conductivity type impurity is ion-implanted into the surface region of the conductive type semiconductor substrate, the implanted second conductivity type impurity is activated, and a plurality of electric field concentration portions of the second conductivity type semiconductor are formed in the surface region of the semiconductor substrate. Forming the pn junction between the electric field concentrating portion and the semiconductor substrate, and forming the plurality of electric fields on the semiconductor substrate by a wide band gap semiconductor of the same type as the semiconductor substrate. The second conductive type semiconductor layer containing the second conductive type impurity having a lower concentration than the concentrated portion, the drift layer, and the ohmic contact layer of the second conductive type semiconductor are sequentially epitaxially formed. A step of forming, characterized in that it comprises the steps of forming first and second electrodes for applying each of the reverse bias voltage lower surface of the semiconductor substrate and the upper surface of the ohmic contact layer.

  According to the present invention, by providing a plurality of electric field concentration portions in the semiconductor device, the potential at the tip of the electric field concentration portion is locally increased, and as a result, the avalanche breakdown does not provide the electric field concentration portion. This occurs at a voltage lower than the avalanche breakdown voltage, and has the effect that the drive voltage can be lowered. In addition, since the electric field concentration portion is provided so as to be evenly distributed on the pn junction surface in the semiconductor device, local overheating due to avalanche breakdown is suppressed, and the avalanche breakdown current is increased by increasing the electric field concentration portion. It has the effect that it can be done.

  In addition, according to the present invention, the electric field concentration portion in which the impurity concentration is changed as compared with the surroundings is formed in the already formed semiconductor layer or semiconductor substrate by ion implantation. The electric field concentration part is not damaged by the subsequent process, and variation in the height of the electric field concentration part can be prevented. Has an effect.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments. The cross-sectional views of the semiconductor devices used in the following embodiments are schematic, and the relationship between the thickness and width of the layers, the ratio of the thicknesses of the layers, and the like are different from the actual ones.

(First embodiment)
FIG. 1 is a cross-sectional view schematically showing the configuration of the semiconductor device according to the first embodiment of the present invention. This semiconductor device is an IMPATT diode that applies a reverse bias to an internal pn junction to cause avalanche breakdown to extract a large current, and is on a p-type semiconductor substrate 1 that is a wide band gap semiconductor having a large thermal conductivity. Furthermore, the avalanche breakdown layer 2 made of the same material as the semiconductor substrate 1 and made of n-type semiconductor layers 21 and 22, and the drift layer 3 made of an i-type semiconductor layer having a sufficiently lower impurity concentration than the semiconductor substrate 1 and the avalanche breakdown layer 2. , And an n ⁺ type semiconductor material are sequentially stacked, and a plurality of electric field concentrating portions made of a p-type semiconductor material are disposed in the first n-type semiconductor layer 21 on the side in contact with the semiconductor substrate 1. 8 is provided. In addition, a first electrode 5 having an ohmic junction is provided on the upper surface of the ohmic contact layer 4, and a second electrode 6 having an ohmic junction is provided on the lower surface of the semiconductor substrate 1. Here, the avalanche breakdown layer 2 is composed of two layers of n-type semiconductor layers 21 and 22, which are provided for the convenience of forming the electric field concentration portion 8. That is, the p-type electric field concentration portion 8 is formed from substantially the upper surface of the n-type semiconductor layer 21 by ion implantation. Therefore, if the n-type semiconductor layer 22 is not formed, the layer immediately above the electric field concentration portion 8 becomes a drift layer having a sufficiently low impurity concentration, and it becomes difficult to form a pn junction above the electric field concentration portion 8. . Therefore, it is desirable that an n-type semiconductor layer 22 is further provided on the n-type semiconductor layer 21. It may be omitted as necessary depending on the specifications of the element.

In this semiconductor device, the semiconductor substrate 1, the avalanche breakdown layer 2, the drift layer 3 and the ohmic contact layer 4 are made of the same type of semiconductor material, and the types and concentrations of the introduced impurities are different. . Here, the i-type semiconductor layer constituting the drift layer 3 is a semiconductor layer having a very low impurity concentration, and specifically, a semiconductor layer having an impurity concentration of about 1 × 10 ¹⁴ cm ⁻³ or less. Is defined. Although the conductivity type of this impurity may be n-type or p-type, it is preferable in manufacturing to have the same conductivity type as that of the avalanche breakdown layer 2 and the drift layer 3. As the first and second electrodes 5 and 6, a material such as Ni can be used for the ohmic contact of the n-type semiconductor, and a material such as Al—Ti can be used for the ohmic contact of the p-type semiconductor. it can.

  The thickness of the avalanche breakdown layer 2 is preferably about 0.1 to 2.5 μm. The thickness of the drift layer 3 is about 700 to 1,000 V when the electric field concentration portion 8 is not provided. However, when the electric field concentration portion 8 is provided, the operation point can be arbitrarily lowered. it can. In this case, the thickness of the drift layer 3 can be arbitrarily set along with the concentration of the drift layer 3 depending on how much voltage is set as the operating point.

  In the present specification, the wide band gap semiconductor means a semiconductor having a band gap larger than that of silicon (about 1.2 eV). In addition, as the wide band gap semiconductor having a large thermal conductivity used in the present invention, for example, SiC such as 4H—SiC, 6H—SiC, 3C—SiC, diamond, BN, or the like can be used. Further, as the semiconductor material to be used, it is desirable to select a material that hardly diffuses the ion-implanted impurity in a direction substantially perpendicular to the implantation direction when the electric field concentration portion 8 is formed by ion implantation.

  FIG. 2 is a cross-sectional view schematically showing an example of the cross-sectional shape of the electric field concentration portion. The electric field concentration portion 8 provided in the semiconductor layer is formed at the substrate side interface of the avalanche breakdown layer 2 by a convex body formed of the same p-type impurity as the semiconductor substrate 1. By forming the convex body in this way, as described later, a high electric field is applied to the pn junction portion at the tip of the convex body, and avalanche breakdown occurs in this portion. Therefore, the electric field concentrating portion 8 only needs to have a structure in which a high electric field is applied to the tip portion of the convex body. The base has a tapered shape (an isosceles trapezoidal shape or a triangular shape) longer than the width of the tip portion, and a reverse tapered shape having a bottom width shorter than the width of the tip portion. The example shown in FIG. 2 has a triangular shape. In the first embodiment, the electric field concentration portion 8 is formed as a semiconductor region into which impurities of a conductivity type different from the conductivity type in the avalanche breakdown layer 2 are ion-implanted in order to concentrate the electric field. Further, the electric field concentration portion 8 is provided in the avalanche breakdown layer 2 with a surface density at which electric field concentration occurs. The density varies depending on the semiconductor material to be used, and is determined by experiments as appropriate. It should be noted that an aspect ratio, which is a ratio of the height of the electric field concentrating portion 8 to the width of the base, is preferably 1 or more in order to concentrate the electric field.

  The first and second electrodes 5 and 6 of this semiconductor device are connected to a pn junction diode formed by the semiconductor substrate 1 and the first n-type semiconductor layer 21 at an avalanche breakdown voltage lower than the avalanche breakdown voltage in the electric field concentration portion 8. A reverse bias close to the breakdown voltage is applied from a power supply device (not shown), and an AC bias is applied to the reverse bias. Adjust to exceed. That is, a reverse bias is applied so that the second electrode 6 provided on the lower surface side of the semiconductor substrate 1 becomes a negative electrode and the first electrode 5 becomes a positive electrode, and an alternating voltage of a predetermined magnitude is applied. Applied.

  Next, a method for manufacturing a semiconductor device having such a structure will be described. 3-1 to 3-7 are cross-sectional views schematically showing an example of the procedure of the manufacturing method of the first embodiment of the semiconductor device according to the present invention. In the following, a case where SiC is used as a semiconductor material will be described as an example. First, a first n-type SiC film 21S having a predetermined thickness is formed on a SiC substrate 1S into which p-type impurities have been introduced (FIG. 3-1) by a film forming method such as a MOCVD (Metal Organic Chemical Vapor Deposition) method. Is epitaxially grown in a thickness range of about 0.1 to 2.5 μm (FIG. 3-2). The first SiC film 21 is formed to form the electric field concentration portion 8. This is because the electric field concentration portion 8 is formed by ion implantation in a later process, and the tip portion thereof is substantially the same as the first SiC film 21.

Here, the impurity concentration of the p-type SiC substrate 1S may be a high concentration of 1 × 10 ¹⁸ cm ⁻³ or more. In this example, for example, the impurity concentration is 1.4 × 10 ¹⁹ cm ^−3. . Further, it is assumed that P having a concentration of 5 × 10 ¹⁸ cm ⁻³ is implanted into the first n-type SiC film 21S as an n-type impurity. However, the concentration of the n-type impurity of the first n-type SiC film 21S is not limited to this, and the impurity concentration of the drift layer 3S to be formed later is set as the lower limit, and the impurity of the second n-type SiC film 22S It is desirable to determine the concentration as the upper limit. When the same concentration as that of the second n-type SiC film 22S is used, the first n-type SiC film 21S and the second n-type SiC film 22S can be continuously formed. In this case, the p-type semiconductor region 8 can be formed while suppressing ion implantation of the p-type impurity into the outermost surface in the subsequent ion implantation process of the p-type impurity. However, here, the first n-type SiC film 21S and the second n-type SiC film 22 are continuously formed, although the concentration is the same as that of the second n-type SiC film 22S formed in a later step. Without being described, the case of forming separately will be described. As an example, the thickness of the first n-type SiC film 21S is 1 μm. Note that the thickness of the first n-type SiC film 21S has substantially the same height as the electric field concentration portion formed in the semiconductor device.

  Next, an Al film or an Al-containing alloy film (hereinafter referred to as an Al-containing film) 31 is formed on the entire upper surface of the first n-type SiC film 21S by using various film forming methods such as sputtering and vapor deposition, plating methods, and the like. Deposits (FIG. 3-3). At this time, when the contact between the upper surface of the first n-type SiC film 21S and the metal (Al-containing film 31) is concerned, an extremely thin insulating film of about 20 nm, for example, is disposed as an intervening layer therebetween. May be. However, this insulating film needs to be insoluble in anodizing solutions such as sulfuric acid and oxalic acid. For example, when SiC is used as a material as described above, a silicon oxide film, a silicon nitride film, or the like is used. Can be used.

  Next, the p-type SiC substrate 1S on which the Al-containing film 31 is deposited is used as an anode, an oxide such as Pb is used as a cathode, and these are immersed in an anodic oxidation solution such as dilute sulfuric acid. Is applied to anodize the Al-containing film 31 formed on the upper surface of the p-type SiC substrate 1S. As a result, Al in the Al-containing film 31 is oxidized to alumite, and an alumite mask 32 having countless fine holes is formed after electricity is passed (FIG. 3-4). Since the current flowed in this anodizing treatment affects the diameter and interval of the micropores and the rate of anodization, it is desirable to obtain the anodizing conditions in advance so that the desired aperture and interval of the micropores can be obtained. . In this example, for example, the anodic oxidation may be performed under such conditions that the diameter of the micropores is about several tens to several hundreds of millimeters and the interval is several thousand to several μm. In addition, anodization is performed so that all the thickness of the deposited Al-containing film 31 is anodized in the shape of the fine holes having such diameters and intervals, and the thickness is about several to several tens of μm. An alumite mask 32 having the following is produced. FIG. 4 is a view showing an example of a top view of the manufactured alumite mask. As shown in FIG. 4, the anodized mask 32 has a honeycomb structure in which fine holes 34 are formed at positions where electric field concentration portions are formed. As the anodizing solution, in addition to dilute sulfuric acid, a solution capable of anodizing such as phosphoric acid, sulfuric acid, oxalic acid, chromic acid and boric acid can be used. For example, when anodization is performed using 4% phosphoric acid as an anodic oxidation solution and applying a voltage of 120 V between the two electrodes, the anodized mask 32 has a fine pore diameter of 330 mm and a fine hole interval of 3,000 mm. Is produced. However, in this example, it is assumed that the thickness of the alumite mask is 1.5 μm.

Next, using the alumite mask 32 formed in FIGS. 3-4 and 4 as a mask, p-type impurity ions are implanted into the first n-type SiC film 21S to form the p-type semiconductor region 8 that is the basis of the electric field concentration portion. (FIGS. 3-5). For example, the p-type semiconductor region 8 is selectively formed by performing multi-stage implantation with Al ions at a concentration of 1 × 10 ¹⁸ cm ⁻³ at 10 to 400 keV in the first n-type SiC film 21S. Note that the concentration of the p-type impurity in the p-type semiconductor region 8 is not limited to this, and may be in the range of 8 × 10 ¹⁷ cm ^{−3 to} 1 × 10 ¹⁹ cm ⁻³ . FIG. 5 is a diagram schematically showing a state of a cross section after ion implantation. The accelerated ion species spread not only in the implantation direction but also in the vertical direction depending on the energy. For example, when Al or P is ion-implanted into SiC, an alumite mask 32 (a mask opening at the time of ion implantation) is located at the position of the depth L, where L is the depth at which the p-type impurity is ion-implanted. It is known that an impurity diffusion region spreads by L / 4 from the end of the substrate. As a result, as shown in FIGS. 3-5 and 5, the p-type semiconductor region 8 has a conical shape (or a truncated cone shape) (the cross-sectional shape in the direction perpendicular to the substrate surface is larger than the upper side). The lower side is tapered longer).

  Thereafter, the anodized mask 32 is peeled off, and heat treatment is performed to activate the implanted ion species to form the electric field concentration portion 8 (FIGS. 3-6). At the time of this heat treatment, Al ions implanted into the SiC semiconductor layer are difficult to thermally diffuse, so that the profile during ion implantation does not greatly collapse. As described above, when the semiconductor material is SiC, the thermal diffusion coefficient after the activation annealing for ion implantation is very small and stays at almost the same place as the ion implantation region before annealing. The shape at the time of ion implantation is kept almost the same. In particular, when the ion implantation species are Al and P, this effect is very large. In addition, since the electric field concentration portion 8 is formed by ion implantation, the apexes thereof have almost the same height at any point.

Subsequently, the second n-type SiC film 22S, the drift layer 3S made of an i-type SiC film, and the ohmic contact layer 4S into which n-type impurities are introduced at a higher concentration than the drift layer 3S are epitaxially grown in order by MOCVD or the like ( Fig. 3-7). Here, the second n-type SiC film 22S is a layer formed in order to form a pn junction at the tip portion of the p-type electric field concentration portion 8 formed in the above process. That is, since the electric field concentration portion 8 is formed almost from the top surface of the first n-type SiC film 21S, it is difficult to form a pn junction as it is, but by providing the second n-type SiC film 22S, A pn junction can be formed at the tip of the p-type electric field concentration portion 8. In this example, P is doped into the second SiC film 22 at a concentration of 5 × 10 ¹⁸ cm ⁻³ as an n-type impurity. The concentration of the n-type impurity is not limited to this, and can be in the range of 1 × 10 ¹⁸ cm ^{−3 to} 3 × 10 ¹⁹ cm ⁻³ and higher than the p-type electric field concentration portion 8. desirable. In this example, the second n-type SiC film 22S is deposited to a thickness of 0.2 μm and the drift layer 3S is deposited to a thickness of 6 μm. Of course, these film thicknesses are not limited to these values. Note that these films can be formed continuously by changing the flow rate of nitrogen gas flowing during epitaxial growth. The ohmic contact layer 4S is formed by stacking the drift layer 3S by the thickness of the ohmic contact layer 4S, and then ion-implanting ions such as N and P from the drift layer 3S to a predetermined thickness range. Then, it may be formed by activation. The impurity concentration of the n-type SiC film constituting the ohmic contact layer 4S may be a high concentration of 1 × 10 ¹⁸ cm ⁻³ or more. Here, for example, an n-type SiC film having an impurity concentration of 1 × 10 ¹⁹ cm ⁻³ is used. It is assumed that a SiC film is formed. Then, an electrode material such as Ni is formed on the ohmic contact layer 4S, and an electrode material such as Ti—Al is formed on the back side of the SiC substrate 1S, and the contact resistance is lowered by heat treatment. First and second electrodes are formed. Further, in order to reduce the resistance, it is preferable to deposit Au on the upper surfaces of the first and second electrodes. Thus, the semiconductor device shown in FIG. 1 is obtained.

  3-4 to 3-5 show the case where a mask for ion implantation is formed with the alumite mask 32, the first n-type SiC is used by using a photolithography technique instead of the alumite mask 32. A resist may be applied on the film 21S to form an ion implantation mask having a honeycomb pattern shown in FIG.

  In FIG. 5, the optimum value of the lateral spreading distance at the time of ion implantation varies depending on the shape and height of the tip of the electric field concentration portion 8 formed in a taper shape as a design matter of the fine hole of the alumite mask 32. . For example, when the distance of the cross-section of the opening of the microhole in the direction perpendicular to the substrate surface is b, the distance between the elements in the finished shape is preferably 2b or more in terms of the center-center distance. This is because if the distance between the center and the center is less than 2b, the electric field concentration efficiency at the tip is deteriorated, that is, the oscillation efficiency is lowered. On the other hand, when the distance between the tip portions of adjacent electric field concentration portions is abnormally separated, the electric field intensity concentrated on the tip portion is lowered and the oscillation efficiency is lowered. Needs to be set to such an extent that does not worsen. However, it goes without saying that this varies depending on the semiconductor material, drift layer concentration, drift layer thickness, and other layer formation conditions. In addition, such a design shape may be difficult to realize a desired shape only by ordinary anodic oxidation. In such a case, first, anodization is performed under conditions that match the aperture of the micropores, and then a resist or the like is applied thereon and patterned, so that unnecessary alumite is formed so that the desired micropore spacing is obtained. A method of filling the fine holes and forming an ion implantation mask is effective.

Next, the operation of such a semiconductor device (IMPATT diode) will be described. 6A to 6C are diagrams schematically illustrating the operation state of the semiconductor device. When no voltage is applied between the first and second electrodes 5 and 6 of the semiconductor device, the semiconductor device is in a thermal equilibrium state as shown in FIG. When a reverse bias voltage V ₁ having a value lower than the avalanche breakdown voltage V _A is applied to the semiconductor device, a potential is generated in the semiconductor device as shown in FIG. The equipotential lines are formed in a direction substantially parallel to the substrate surface at a position near the first electrode 5 away from the electric field concentration portion 8, but the equipotential lines stand up at a position near the tip of the electric field concentration portion 8. The density is high. However, in this state, no avalanche breakdown has occurred yet. Then, as shown in FIG. 6-3, when a higher value of reverse bias voltage V ₂ (> V ₁ ) is applied to the semiconductor device, an equipotential line at a position near the tip of the electric field concentration portion 8 becomes very The voltage becomes locally higher than the avalanche breakdown voltage. As a result, when a strong electric field is applied to the depletion layer, carriers are generated and avalanche breakdown occurs. Carriers (electrons) emitted from the electric field concentration portion 8 pass through the drift layer 3, whereby a large current is extracted from the semiconductor device.

  In order to reduce the avalanche breakdown voltage of the wide band gap semiconductor, it is desirable that the aspect ratio of the electric field concentration portion formed in the semiconductor device is 1 or more. Hereinafter, a description will be given of a point where it is desirable that the aspect ratio of the electric field concentration portion is 1 or more. FIG. 7A is a diagram illustrating a potential state when a pn junction is formed flat, and FIG. 7B is a diagram illustrating a potential state near an electric field concentration portion having an aspect ratio of less than 1. FIG. 7C is a diagram illustrating a state of the potential in the vicinity of the electric field concentration portion having an aspect ratio of 1 or more. It is assumed that the radius of curvature of the sharpened portion of the electric field concentration portion 8 shown in FIGS. 7-2 and 7-3 is the same.

As shown in FIG. 7A, when the p-type layer 110 and the n ⁻ -type layer 120 are stacked and the pn junction is formed flat, the equipotential line 140 is a line parallel to the pn junction surface. Can be drawn with. In this case, local electric field concentration (a portion where the equipotential lines 140 are more crowded than other portions) does not occur in the depletion layer 130, and the avalanche breakdown voltage is determined by the breakdown electric field strength inherent to the semiconductor material. Become.

Further, as shown in FIG. 7B, when the aspect ratio of the electric field concentration portion 8 formed on the pn junction surface between the p-type layer 110 and the n ⁻ -type layer 120 is less than 1, the electric field concentration Although the equipotential lines 140 are crowded in the vicinity of the portion 8, the degree of crowding of the equipotential lines 140 in the vicinity of the electric field concentration portion 8 is moderate, and the electric field concentration is unlikely to occur. FIG. 8A is a diagram illustrating an example of a generally known method for forming an electric field concentration portion having an aspect ratio of less than 1. Conventionally, when silicon as a semiconductor material is wet-etched with a KOH aqueous solution, the (111) plane selectively appears to form a regular pyramid-shaped electric field concentration portion. Here, when a cross section of a regular quadrangular pyramid is selected as shown by the solid line in FIG. 8-2, the aspect ratio is about 0.707 as shown in FIG. 8-3. Further, when a cross section of a regular quadrangular pyramid is selected as shown by a solid line in FIG. 8-4, the aspect ratio is 0.5 as shown in FIG. 8-5. That is, in the conventional method of forming the electric field concentration portion 8 by etching with KOH, it is difficult to form the electric field concentration portion 8 having an aspect ratio of 1 or more, and electric field concentration is difficult to occur.

On the other hand, when the aspect ratio of the electric field concentration portion 8 formed on the pn junction surface between the p-type layer 110 and the n ⁻ -type layer 120 is 1 or more as shown in FIG. The line 140 is very crowded in the vicinity of the tip of the electric field concentration portion 8 on the side in contact with the n ⁻ -type layer 120, and electric field concentration is likely to occur. Furthermore, the crowded electric field locally increases the electric potential in the vicinity of the tip of the electric field concentrating portion 8, and the tip of the electric field concentrating portion 8 with an applied voltage lower than the avalanche breakdown voltage determined by the dielectric breakdown electric field strength inherent to the semiconductor material. Avalanche surrender can be caused near the area. As described above, the aspect ratio of the electric field concentration portion 8 is desirably 1 or more.

  In the first embodiment, ion implantation is used in the formation of the electric field concentration portion 8, but the ion species implanted into SiC is substantially in the ion implantation direction during ion implantation and activation annealing. Almost no diffusion in a perpendicular direction. Therefore, with reference to FIG. 5, the conditions under which an electric field concentration portion with an aspect ratio of 1 or more can be formed are considered. For example, if the diameter of the opening of the mask (alumite mask 32) is b, the cross-sectional shape of the electric field concentration portion 8 formed by ion implantation has a height of L, the upper base is b, and the lower base is b + L. An isosceles trapezoid that is / 2. The aspect ratio in this case is L / (b + L / 2) from the definition, and in order for this to be 1 or more, it is necessary to satisfy b ≦ L / 2. By forming the avalanche breakdown layer 2 (first n-type semiconductor layer 21) and the mask under such conditions, the electric field concentration portion 8 having an aspect ratio of 1 or more can be formed.

  In the above description, the case where the n-type semiconductor layer is stacked on the p-type semiconductor substrate 1 and the p-type electric field concentration portion is formed at the boundary by ion implantation has been described, but as shown in FIG. In the above description, the conductivity type may be changed. FIG. 9 is a cross-sectional view schematically showing another example of the configuration of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 9, an avalanche breakdown layer 2 composed of p-type semiconductor layers 21 and 22 is stacked on an n-type semiconductor substrate 1, and the boundary between the p-type avalanche breakdown layer 2 and the n-type semiconductor substrate 1 is formed. It is a figure which shows an example of the structure of the cross section of the semiconductor device which formed the electric field concentration part 8 which consists of an n-type semiconductor region by ion implantation. In this case, it is preferable to use, for example, N or P as the dopant of the n-type semiconductor substrate 1, and it is preferable to use, for example, Al or B as the dopant of the p-type semiconductor layer.

FIG. 10A is a sectional view schematically showing another example of the structure of the semiconductor device according to the first embodiment of the present invention. In the example of FIG. 10A, the semiconductor device of FIG. 1 includes a p ⁺ type semiconductor layer 11 having a predetermined thickness at a position x [μm] from the interface with the ohmic contact layer 4 in the drift layer 3. It has become. At this time, the drift layer 3a between the p-type semiconductor substrate 1 and the p ⁺ -type semiconductor layer 11 is an n ⁻ -type having an n-type impurity concentration lower than that of the electric field concentration portion 8, and the ohmic contact layer 4 and the p ⁺ -type are used. The drift layer 3b between the semiconductor layer 11 is i-type. According to such a structure, the p ⁺ type semiconductor layer 11 functions as a charge clamp, that is, since the drift layer 3 is composed of the i type semiconductor layer, it is considered that the charge is almost zero. When a reverse bias is applied between the first and second electrodes 5 and 6, the electric field drop due to electric charge is considered to be almost zero between the ohmic contact layer 4 and the p ⁺ type semiconductor layer, so the electric field distribution in this region Can be made substantially constant. As a result, since heat generation on the first electrode 5 side during operation is suppressed as compared with the case of FIG. 1, when the semiconductor device manufactured as described above is packaged, The soldering junction temperature can be made lower than in the case of FIG. 1, and a semiconductor device that is not easily broken can be realized. In this case, the conductivity type may be changed as shown in FIG. 10-2.

  According to the first embodiment, by providing a plurality of electric field concentration portions 8 in the pn junction surface of the semiconductor device, there is an effect that overheating due to local breakdown can be suppressed. Moreover, it has the effect of increasing the avalanche breakdown current by increasing the electric field concentration portion 8 which is the starting point of the avalanche breakdown. Furthermore, the provision of the electric field concentration portion 8 causes avalanche breakdown at a voltage lower than the avalanche breakdown voltage determined by the optimum combination of the drift layer thickness and the impurity concentration depending on the frequency used in the conventional IMPATT diode. This has the effect that the driving voltage can be lowered when the IMPATT diode is formed of a wide band gap semiconductor.

  In addition, since the electric field concentration portion 8 is produced by ion implantation and does not use etching such as wet etching or dry etching, the sharpened electric field concentration portion 8 formed after the conventional etching is performed by the subsequent process. It can prevent that it breaks and the dispersion | variation arises in the height of the electric field concentration part 8. FIG. Furthermore, by using the alumite mask 32 to form the electric field concentration portion 8, the diameter of the tip of the electric field concentration portion 8 can be easily controlled to several nanometers to several hundred nanometers, and there is no local bias of the electric field. , Can enable stable carrier release.

(Second Embodiment)
FIG. 11 is a cross-sectional view schematically showing the configuration of the semiconductor device according to the second embodiment of the present invention. This semiconductor device includes an avalanche breakdown layer 2 made of an n-type semiconductor layer made of the same material as the semiconductor substrate 1, on a p-type semiconductor substrate 1 which is a wide band gap semiconductor having a large thermal conductivity, and the semiconductor substrate 1 and the avalanche. A drift layer 3 made of an i-type semiconductor layer having an impurity concentration lower than that of the breakdown layer 2 and an ohmic contact layer 4 made of an n ⁺ -type semiconductor material are sequentially stacked, and the avalanche breakdown layer 2 has the avalanche breakdown layer 2. A plurality of electric field concentration portions 8 made of an n ⁺ type semiconductor material having an n type impurity concentration higher than that of the n ⁺ type semiconductor material is provided. In addition, a first electrode 5 having an ohmic junction is provided on the upper surface of the ohmic contact layer 4, and a second electrode 6 having an ohmic junction is provided on the lower surface of the semiconductor substrate 1.

  The electric field concentrating portion 8 provided in the avalanche breakdown layer 2 has a cross-sectional shape in a direction perpendicular to the substrate surface, which is rectangular or has a width on the side in contact with the semiconductor substrate 1 (hereinafter referred to as a bottom side) larger than the width of the tip portion. Also has a long taper shape. The electric field concentration portion 8 is set to have an impurity concentration that is two orders of magnitude higher than the impurity concentration of the avalanche breakdown layer 2 (n-type semiconductor layer) in order to concentrate the electric field. Further, the electric field concentration portion 8 is provided in the avalanche breakdown layer 2 with a surface density at which electric field concentration occurs. The surface density varies depending on the semiconductor material to be used, and is determined by experiments as appropriate. Even in this case, it is desirable that the aspect ratio, which is the ratio of the height of the electric field concentration portion 8 to the width of the bottom side, be 1 or more.

In the case of this semiconductor device, by setting the n-type impurity concentration of the electric field concentration portion 8 higher than that of the avalanche breakdown layer 2 (n-type semiconductor layer), the avalanche breakdown in the electric field concentration portion 8 is easily caused. At this time, n ⁺ -type lower end of the electric field concentration portion 8 carriers from (n ⁺ -type between the electric field concentrated portion 8 and the p-type semiconductor substrate 1) generated by the. In addition, the same code | symbol is attached | subjected to the component same as 1st Embodiment, and the detailed description is abbreviate | omitted.

  Since the manufacturing method and operation of the semiconductor device having such a structure are basically the same as those described in the first embodiment, detailed description thereof will be omitted. However, in the second embodiment, instead of ion implantation of p-type impurities in the ion implantation step in FIG. 3-5, the n-type semiconductor layer 21 is compared with the n-type impurity concentration of the n-type semiconductor layer. An n-type impurity having a concentration two digits higher is ion-implanted. At this time, the diameter of the upper portion of the electric field concentration portion 8 is about several tens to several hundreds of squares, and the interval is preferably several thousand squares to several μm.

In the above description, the avalanche breakdown layer 2 made of an n-type semiconductor layer is formed on the p-type semiconductor substrate 1, and the n ⁺ -type electric field concentration portion 8 is ionized on the p-type semiconductor substrate 1 side of the avalanche breakdown layer 2. Although the case of forming by injection has been described, the conductive type may be changed in the above description. That is, an avalanche breakdown layer made of a p-type semiconductor layer is formed on an n-type semiconductor substrate, and a p ⁺ -type electric field concentration portion is formed by ion implantation on the n-type semiconductor substrate side of the p-type semiconductor layer (avalanche breakdown layer). It may be formed.

  According to the second embodiment, in addition to the effects of the first embodiment, the electric field concentration portion 8 having a conductivity type different from that of the semiconductor substrate 1 is formed in the avalanche breakdown layer 2 and pn is formed on the substrate side interface. Since the junction is formed, the manufacturing process can be simplified as compared with the case of the first embodiment.

(Third embodiment)
FIG. 12 is a cross-sectional view schematically showing the configuration of the semiconductor device according to the third embodiment of the present invention. This semiconductor device includes an avalanche breakdown layer 2 made of an n-type semiconductor layer made of the same material as the semiconductor substrate 1, on a p-type semiconductor substrate 1 which is a wide band gap semiconductor having a large thermal conductivity, and the semiconductor substrate 1 and the avalanche. A drift layer 3 having an impurity concentration lower than that of the breakdown layer 2 and an ohmic contact layer 4 made of an n ⁺ type semiconductor material are sequentially stacked. The semiconductor substrate 1 on the side in contact with the avalanche breakdown layer 2 includes the avalanche breakdown layer 2. A plurality of electric field concentration portions 8 made of an n ⁺ type semiconductor material having an n type impurity concentration higher than that of the n ⁺ type semiconductor material is provided. In addition, a first electrode 5 having an ohmic junction is provided on the upper surface of the ohmic contact layer 4, and a second electrode 6 having an ohmic junction is provided on the lower surface of the semiconductor substrate 1. In addition, the same code | symbol is attached | subjected to the component same as 1st Embodiment, and the detailed description is abbreviate | omitted.

  Unlike the first and second embodiments in which the electric field concentration portion 8 is formed in the avalanche breakdown layer 2, the electric field concentration portion 8 in the third embodiment is formed in the semiconductor substrate 1. However, also in this case, the electric field concentrating portion 8 provided in the semiconductor substrate 1 has a rectangular cross section in the direction perpendicular to the substrate surface or a side on the side in contact with the avalanche breakdown layer 2 (hereinafter referred to as an upper side). Has a taper shape that is shorter than the width of the side of the lower end portion (hereinafter referred to as the bottom side). The electric field concentration portion 8 is set to have a higher impurity concentration than the impurity concentration in the avalanche breakdown layer 2 in order to concentrate the electric field. Further, the electric field concentration portion 8 is provided in the upper surface of the semiconductor substrate 1 with a surface density at which electric field concentration occurs. The surface density varies depending on the semiconductor material to be used, and is determined by experiments as appropriate. The aspect ratio, which is the ratio of the height of the electric field concentration portion 8 to the width of the base, is preferably 1 or more.

  Next, a method for manufacturing a semiconductor device having such a structure will be described. FIGS. 13-1 to 13-6 are cross-sectional views schematically showing an example of the procedure of the manufacturing method of the third embodiment of the semiconductor device according to the present invention. Hereinafter, a case where SiC is used as a semiconductor material will be described as an example. First, an Al-containing film 31 that is an Al film or an alloy film containing Al is deposited on the entire upper surface of the SiC substrate 1S into which p-type impurities have been introduced (FIG. 13-1) (FIG. 13-2). Next, as in the first embodiment, the p-type SiC substrate 1S on which the Al-containing film 31 is deposited is used as the anode, the oxide such as Pb is used as the cathode, and these are used as an anodic oxidation solution in dilute sulfuric acid. The aluminum-containing film 31 formed on the upper surface of the p-type SiC substrate 1S is anodized by dipping in the p-type SiC substrate 1S to form an alumite mask 32 as shown in FIG. 4 in which fine holes are formed (FIG. 13-). 3). The alumite mask 32 formed at this time has a diameter of the upper part of the electric field concentration portion 8 formed by using the alumite mask 32 in a later step, which is about several tens to several hundreds of centimeters, and the interval is several thousand Å. It is desirable that the micropores are formed so as to be ˜several μm.

  Next, using the alumite mask 32 formed in FIGS. 13-3 and 4 as a mask, ion implantation of P (phosphorus) or N (nitrogen) n-type impurities is performed selectively on the p-type SiC substrate 1S to selectively remove n. A type semiconductor region 8 is formed (FIG. 13-4). At this time, the depth of the n-type impurity implantation region is preferably about 0.3 to 2.5 μm. For example, when the depth of the n-type impurity implantation region is 0.6 μm, it is necessary to perform multi-stage implantation with 10 to 360 keV P ions or N ions on the p-type SiC substrate 1S. Thereafter, the alumite mask 32 is peeled off, and heat treatment is performed to activate the implanted ion species to form the electric field concentration portion 8 (FIG. 13-5). At the time of this heat treatment, Al ions implanted into the SiC substrate 1S are difficult to thermally diffuse, so that the profile formed by the ion implantation does not collapse greatly.

  Next, an n-type SiC film 2S, a drift layer 3S made of an i-type SiC film, and an ohmic in which an n-type impurity is introduced at a higher concentration than the drift layer 3S on the SiC substrate 1S on which the electric field concentration portion 8 is formed. The contact layer 4S is epitaxially grown in order by the MOCVD method or the like (FIG. 13-6). Further, a first electrode such as Ni is formed on the ohmic contact layer 4S, and a second electrode is formed on the back side of the SiC substrate 1S using Al—Ti, for example. Thus, the semiconductor device shown in FIG. 12 is obtained.

In the above description, the avalanche breakdown layer 2 made of an n-type semiconductor layer is formed on the p-type semiconductor substrate 1 and the vicinity of the boundary with the n-type semiconductor layer (avalanche breakdown layer 2) in the p-type semiconductor substrate 1 is used. Although the case where the n ⁺ -type electric field concentration portion 8 is formed is described in FIG. 14, it may be configured such that the conductivity type is switched as described above as shown in FIG. FIG. 14 is a cross-sectional view schematically showing another example of the configuration of the semiconductor device according to the third embodiment of the present invention. As shown in FIG. 14, an avalanche breakdown layer 2 is formed by laminating a p-type semiconductor layer on an n-type semiconductor substrate 1, and a p-type semiconductor layer (avalanche breakdown layer 2) in the n-type semiconductor substrate 1 is formed. ² is a diagram illustrating an example of a cross-sectional structure of a semiconductor device in which a p ⁺ -type electric field concentration portion 8 is formed in the vicinity of the boundary between the two. In this case, it is preferable to use, for example, N or P as the dopant of the n-type semiconductor substrate 1, and it is preferable to use, for example, Al or B as the dopant of the p-type semiconductor layer.

FIG. 15 is a sectional view schematically showing another example of the structure of the semiconductor device according to the third embodiment of the present invention. In the example of FIG. 15, the semiconductor device of FIG. 12 includes a p ⁺ type semiconductor layer 11 having a predetermined thickness at a position x [μm] from the interface with the ohmic contact layer 4 in the drift layer 3. It has become. At this time, the drift layer 3a between the p-type semiconductor substrate 1 and the p ⁺ -type semiconductor layer 11 is an n ⁻ -type having an n-type impurity concentration lower than that of the electric field concentration portion 8, and the ohmic contact layer 4 and the p ⁺ -type are used. The drift layer 3b between the semiconductor layer 11 is i-type. According to such a structure, the p ⁺ type semiconductor layer 11 functions as a charge clamp. That is, since the drift layer 3 is composed of an i-type semiconductor layer, the charge is considered to be almost zero. When a reverse bias is applied between the first and second electrodes 5 and 6 of the semiconductor device, the ohmic contact layer Since the electric field drop due to electric charge is considered to be almost zero between 4 and the p ⁺ type semiconductor layer, the electric field distribution in this region can be made almost constant. As a result, since heat generation on the first electrode 5 side during operation is suppressed as compared with the case of FIG. 12, when the semiconductor device produced as described above is packaged, The soldering junction temperature can be made lower than in the case of FIG. 12, and a semiconductor device that is not easily broken can be realized. In this case, the conductivity type may be changed. Such a third embodiment also has the same effect as the first and second embodiments.

  The semiconductor device according to the present embodiment can be applied to a semiconductor device that can flow a large current and does not cause an increase in cost, weight, and reliability, and a manufacturing method thereof. In addition, by using a wide band gap semiconductor such as SiC with high thermal conductivity, it has excellent heat release properties, eliminates the need for cooling equipment, and enables downsizing and space saving of various equipment. .

  For example, the present invention can be applied to an electronic cooking device such as a microwave oven using a microwave. This is an application example to equipment using molecular vibration, but it can also be applied to other food processing / processing (heating, drying, fermentation, sterilization). The present invention can also be applied to household, industrial, and medical waste disposal (medical / garbage disposal).

  Furthermore, it is also used in equipment using plasma such as electrodeless lamp devices (ultraviolet rays and visible light), semiconductor manufacturing devices (etching devices, ashing devices, sputtering devices, cleaning devices, etc.), and radar and mobile device related amplifiers. Applicable. Further, the present invention can be applied to the field of wireless communication, and can be applied to GPS (Global Positioning System) or the like, or can be applied to a parking prohibition control terminal. In addition, it can be applied to a medical X-ray generator.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are an electronic cooking device, a garbage disposal device, an electrodeless lamp device, a semiconductor manufacturing device, a wireless communication device that can efficiently flow a large current while suppressing element destruction. Suitable for devices in the communication field, medical X-ray generators, and the like.

It is sectional drawing which shows typically the structure of the semiconductor device concerning the 1st Embodiment of this invention. It is sectional drawing which shows typically an example of the cross-sectional shape of an electric field concentration part. It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 1st Embodiment of the semiconductor device by this invention (the 1). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 1st Embodiment of the semiconductor device by this invention (the 2). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 1st Embodiment of the semiconductor device by this invention (the 3). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 1st Embodiment of the semiconductor device by this invention (the 4). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 1st Embodiment of the semiconductor device by this invention (the 5). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 1st Embodiment of the semiconductor device by this invention (the 6). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 1st Embodiment of the semiconductor device by this invention (the 7). It is a figure which shows an example of the top view of an alumite mask. It is a figure which shows typically the mode of the cross section into which ion implantation was carried out. It is a figure which shows typically the operation state of a semiconductor device. It is a figure which shows typically the operation state of a semiconductor device. It is a figure which shows typically the operation state of a semiconductor device. It is a figure which shows the mode of the electric potential in case the pn junction is formed flat. It is a figure which shows the mode of the electric potential of the electric field concentration part vicinity whose aspect ratio is less than one. It is a figure which shows the mode of the electric potential of the electric field concentration part vicinity whose aspect ratio is 1 or more. It is a figure which shows an example of the formation method of the electric field concentration part in which the aspect ratio generally known is less than one. It is a figure which shows an example which selects the cross section in the electric field concentration part of a regular quadrangular pyramid. It is a figure which shows the cross section of the regular quadrangular pyramid of FIGS. 8-2. It is a figure which shows an example which selects the cross section in the electric field concentration part of a regular quadrangular pyramid. It is a figure which shows the cross section of the regular quadrangular pyramid of FIGS. 8-4. It is sectional drawing which shows typically the other example of a structure of the semiconductor device concerning the 1st Embodiment of this invention. It is sectional drawing which shows typically the other example of the structure of 1st Embodiment of the semiconductor device concerning this invention. It is sectional drawing which shows typically the other example of the structure of 1st Embodiment of the semiconductor device concerning this invention. It is sectional drawing which shows typically the structure of the semiconductor device concerning the 2nd Embodiment of this invention. It is sectional drawing which shows typically the structure of the semiconductor device concerning the 3rd Embodiment of this invention. It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 3rd Embodiment of the semiconductor device by this invention (the 1). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 3rd Embodiment of the semiconductor device by this invention (the 2). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 3rd Embodiment of the semiconductor device by this invention (the 3). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 3rd Embodiment of the semiconductor device by this invention (the 4). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 3rd Embodiment of the semiconductor device by this invention (the 5). It is sectional drawing which shows typically an example of the procedure of the manufacturing method of 3rd Embodiment of the semiconductor device by this invention (the 6). It is sectional drawing which shows typically the other example of a structure of the semiconductor device concerning the 3rd Embodiment of this invention. It is sectional drawing which shows typically the other example of the structure of 3rd Embodiment of the semiconductor device concerning this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Avalanche breakdown layer 3 Drift layer 4 Ohmic contact layer 5 1st electrode 6 2nd electrode 8 Electric field concentration part

Claims (10)

A second conductivity type semiconductor layer, a drift layer, and an ohmic contact layer of the second conductivity type semiconductor, which are epitaxially formed in order by a wide band gap semiconductor of the same type as the semiconductor substrate on the first conductivity type semiconductor substrate;
First and second electrodes respectively formed on the lower surface of the semiconductor substrate and the upper surface of the ohmic contact layer;
A plurality of electric field concentration portions of a first conductivity type semiconductor formed in a convex shape upward from the semiconductor substrate side interface in the second conductivity type semiconductor layer;
And a reverse bias voltage is applied between the first and second electrodes to cause avalanche breakdown at a pn junction portion between the plurality of electric field concentration portions and the second conductivity type semiconductor layer. Semiconductor device.   The second conductivity type semiconductor layer includes a first layer and a second layer provided on the first layer, and the plurality of electric field concentration portions are formed in the first layer. The semiconductor device according to claim 1. A second conductivity type semiconductor layer, a drift layer, and an ohmic contact layer of the second conductivity type semiconductor, which are epitaxially formed in order by a wide band gap semiconductor of the same type as the semiconductor substrate on the first conductivity type semiconductor substrate;
First and second electrodes respectively formed on the lower surface of the semiconductor substrate and the upper surface of the ohmic contact layer;
A plurality of electric field concentration portions formed in the second conductive type semiconductor layer in contact with the semiconductor substrate side interface and formed by a second conductive type impurity having a concentration higher than that of the second conductive type semiconductor layer;
And a reverse bias voltage is applied between the first and second electrodes to cause avalanche breakdown at a pn junction portion between the semiconductor substrate and the plurality of electric field concentration portions. A second conductivity type semiconductor layer, a drift layer, and an ohmic contact layer of the second conductivity type semiconductor, which are epitaxially formed in order by a wide band gap semiconductor of the same type as the semiconductor substrate on the first conductivity type semiconductor substrate;
First and second electrodes respectively formed on the lower surface of the semiconductor substrate and the upper surface of the ohmic contact layer;
A plurality of electric field concentration portions formed in the semiconductor substrate in contact with the second conductivity type semiconductor layer side interface and formed by a second conductivity type impurity having a higher concentration than the second conductivity type semiconductor layer;
And a reverse bias voltage is applied between the first and second electrodes to cause avalanche breakdown at a pn junction portion between the semiconductor substrate and the plurality of electric field concentration portions.   The semiconductor device according to claim 1, wherein the wide band gap semiconductor is made of any one of SiC, diamond, and BN.   The semiconductor device according to claim 1, wherein the electric field concentration portion has a ratio with respect to a lower side of a height in a cross section perpendicular to the substrate surface of 1 or more. A method of manufacturing a semiconductor device in which an avalanche breakdown is caused in a pn junction by applying a reverse bias voltage,
Forming a first second conductivity type semiconductor layer epitaxially on a first conductivity type semiconductor substrate with a wide bandgap semiconductor of the same type as the semiconductor substrate;
A first conductivity type impurity is ion-implanted into the first second conductivity type semiconductor layer using a mask in which holes having a predetermined diameter are formed at a predetermined surface density, and the implanted first conductivity type impurities are activated. Then, an electric field concentration portion is formed in the first second conductivity type semiconductor layer so as to protrude upward from the interface on the semiconductor substrate side, whereby the electric field concentration portion and the first second conductivity type semiconductor are formed. Forming the pn junction portion between the layers;
A step of epitaxially forming a drift layer and an ohmic contact layer of a second conductivity type semiconductor in order on the first second conductivity type semiconductor layer by a wide band gap semiconductor of the same type as the semiconductor substrate;
Forming a first electrode and a second electrode for applying the reverse bias voltage to the lower surface of the semiconductor substrate and the upper surface of the ohmic contact layer, respectively.   By forming a second second conductivity type semiconductor layer between the first second conductivity type semiconductor layer and the drift layer, between the second second conductivity type semiconductor layer and the electric field concentration portion. The method of manufacturing a semiconductor device according to claim 7, wherein the pn junction portion is formed. A method of manufacturing a semiconductor device in which an avalanche breakdown is caused in a pn junction by applying a reverse bias voltage,
Forming a second conductivity type semiconductor layer epitaxially on the first conductivity type semiconductor substrate with a wide band gap semiconductor of the same type as the semiconductor substrate;
Using a mask in which a hole having a predetermined aperture is formed with a predetermined surface density, a second conductivity type impurity is ion-implanted into the second conductivity type semiconductor layer, and the implanted second conductivity type impurity is activated, Forming a plurality of electric field concentration portions in the second conductivity type semiconductor layer in contact with the semiconductor substrate side interface and containing a second conductivity type impurity having a higher concentration than the second conductivity type semiconductor layer; Forming the pn junction between the semiconductor substrate and the semiconductor substrate;
A step of epitaxially forming a drift layer and an ohmic contact layer of a second conductivity type semiconductor in order on the second conductivity type semiconductor layer by a wide band gap semiconductor of the same type as the semiconductor substrate;
Forming a first electrode and a second electrode for applying the reverse bias voltage to the lower surface of the semiconductor substrate and the upper surface of the ohmic contact layer, respectively. A method of manufacturing a semiconductor device in which an avalanche breakdown is caused in a pn junction by applying a reverse bias voltage,
A second conductivity type impurity is ion-implanted into the surface region of the first conductivity type semiconductor substrate using a mask in which holes of a predetermined diameter are formed with a predetermined surface density, and the implanted second conductivity type impurities are activated. Forming a pn junction portion between the electric field concentration portion and the semiconductor substrate by forming a plurality of electric field concentration portions of a second conductivity type semiconductor in the surface region of the semiconductor substrate;
A second conductive type semiconductor layer, a drift layer, and a second layer including a second conductive type impurity having a lower concentration than the plurality of electric field concentration portions on the semiconductor substrate by the same type of wide band gap semiconductor as the semiconductor substrate. A step of epitaxially forming ohmic contact layers of a conductive semiconductor in sequence;
Forming a first electrode and a second electrode for applying the reverse bias voltage to the lower surface of the semiconductor substrate and the upper surface of the ohmic contact layer, respectively.

Images