JP4950957B2 - NRZ signal amplifier - Google Patents

Description

  The present invention relates to an NRZ signal amplifying apparatus for amplifying a NRZ (Non Return Zero) signal used for data communication to a desired level and supplying it to a succeeding apparatus for correctly holding and outputting the waveform of the NRZ signal. Regarding technology.

  In the NRZ signal used in digital signal transmission, for example, a high level voltage is assigned to data 1 and a low level voltage is assigned to data 0, but the direct current component varies greatly depending on the mark rate of the data.

  A device or the like that receives this NRZ signal amplifies the input NRZ signal to a level at which data can be determined, and identifies 0 and 1 at an appropriate phase timing.

  In the case of this type of device, a differential amplifier is generally used for signal amplification. However, if the DC average voltage fluctuates due to a change in the mark ratio of the input NRZ signal, an appropriate input operating point of the amplifier. Therefore, there is a problem that a sufficient amplitude cannot be obtained as an output signal of the amplifier.

  As a technique for solving this problem, conventionally, there has been a system in which an offset voltage is added to an input NRZ signal and the NRZ signal to which the offset voltage is added is input to a main amplifier.

FIG. 6 shows an example of a conventional apparatus 10 having such a configuration.
Here, the offset circuit 11 includes a capacitor 11a for passing the AC component of the input NRZ signal S, a coil 11b and a resistor 11c for passing the DC component, an adder 11d for adding the offset voltage Voffset to the passed DC component, and an adder 11d. The resistor 11e and the coil 11f are combined with the alternating current component that has passed through the capacitor 11a.

  According to this offset circuit 11, a desired DC voltage component can be given to the input NRZ signal S, and the signal S 'input from the offset circuit 11 to the main amplifier 12 is variably controlled by the offset voltage Voffset. It is possible to maintain the input range of the main amplifier 12 within an appropriate range.

  For this control, the high-level voltage VH and low-level voltage VL of the signal S ′ are detected by a detection type voltage detection circuit 13 comprising diodes 13a and 13b and capacitors 13c and 13d, and these are detected by an A / D converter. 14 and 15, the center voltage Vcent = (VH + VL) / 2 is obtained by the center voltage calculation means 16, and the center voltage Vcent is substantially the center value of the proper input range of the main amplifier 12. The offset voltage Voffset necessary for the calculation is obtained by the offset voltage setting means 17 and supplied to the offset circuit 11.

  By this feedback control, the center voltage Vcent of the high level voltage VH and the low level voltage VL of the signal S ′ is constantly maintained at substantially the center value of the proper input range of the main amplifier 12, and the output from the main amplifier 12 The amplitude of the signal S ″ is the maximum amplitude that the main amplifier 12 can originally output, and no amplitude reduction occurs.

  A technique for variably controlling the offset voltage by detecting a high-level voltage and a low-level voltage of a digital signal with a diode detection circuit as described above is disclosed, for example, in Patent Document 1 below.

Japanese Patent Laid-Open No. 5-7135

  However, as described above, in the case where the high level voltage and the low level voltage of the signal S ′ input to the main amplifier 12 are detected by diode detection, when the signal frequency is as high as several tens GHz, for example, the capacitance of the diode, etc. As a result, the input impedance changes greatly to generate waveform distortion and lower the detection accuracy. Therefore, the input signal exceeds the proper input range of the main amplifier and the amplitude of the output signal is reduced.

  The present invention solves this problem and can detect the high level voltage and low level voltage of the signal with high accuracy even when the signal frequency is as high as several tens of GHz, for example. An object of the present invention is to provide an NRZ signal amplifying device that is stably held in an appropriate input range of a main amplifier and does not cause a decrease in amplitude of an output signal.

To achieve the above object, the NRZ signal amplifying apparatus of the present invention comprises:
An offset circuit (21) for adding an offset voltage to the input NRZ signal and outputting it;
A main amplifier (22) for receiving and amplifying the output signal of the offset circuit;
Voltage detection means (30) for detecting a high level voltage and a low level voltage of an input signal to the main amplifier;
Center voltage calculating means (40) for calculating center voltages of the high level voltage and the low level voltage detected by the voltage detecting means;
In an NRZ signal amplifying apparatus comprising offset voltage setting means (50) for obtaining an offset voltage for the calculated center voltage to be approximately the center of an appropriate input range of the main amplifier and giving the offset voltage to the offset circuit,
The voltage detection means includes
A first comparator (31) for comparing an input signal to the main amplifier and a first reference voltage;
A second comparator (32) for comparing an input signal to the main amplifier and a second reference voltage;
A first filter (33) for extracting a DC component from the output signal of the first comparator;
A second filter (34) for extracting a DC component from the output signal of the second comparator;
A first filter that receives an output signal of the first filter and a first reference voltage equal to an output upper limit voltage of the first comparator, and provides a difference output to the first comparator as the first reference voltage; Operational amplifier (35),
A second filter that receives an output signal of the second filter and a second reference voltage equal to an output lower limit voltage of the second comparator, and supplies a difference output to the second comparator as the second reference voltage; And an operational amplifier (36).
Feedback control is performed so that the first reference voltage and the second reference voltage match the high level voltage and the low level voltage of the signal input to the main amplifier, respectively, and the first and second reference voltages are changed. The high level voltage and the low level voltage are supplied to the center voltage calculation means.

An NRZ signal amplifying device according to claim 2 of the present invention is the NRZ signal amplifying device according to claim 1,
The main amplifier, the first comparator, and the second comparator are integrally configured by the same semiconductor process.

  In the NRZ signal amplifying apparatus of the present invention, since the voltage detecting means is configured as described above, even when the signal frequency is as high as several tens of GHz, the high level voltage and low level voltage of the signal can be obtained with high accuracy. It can be detected, and the input signal is stably held in the proper input range of the main amplifier, and the amplitude of the output signal is not reduced.

  In the present invention, the influence on the input impedance can be minimized by using a comparator having both high impedance and low capacitance.

  Further, since the main amplifier, the first comparator, and the second comparator are on the same semiconductor process, the main amplifier can be formed with the same characteristics (transistor operation). Therefore, it is possible to perform feedback control with little error.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows a configuration of an NRZ signal amplifying apparatus 20 to which the present invention is applied. Although the case where the input NRZ signal is a single phase will be described here, the present invention can also be applied to a case where an inverted two-phase NRZ signal is amplified as will be described later.

  The input NRZ signal S is input to the offset circuit 21, and a DC offset voltage Voffset is added to the main amplifier 22.

  Here, similarly to the above, the offset circuit 21 includes a capacitor 21a for passing the AC component of the input NRZ signal S, a coil 21b and a resistor 21c for passing the DC component, and an adder for adding the offset voltage Voffset to the passed DC component. The resistor 21e and the coil 21f are combined with the AC component that has passed through the capacitor 21a through the output of the adder 21d.

  According to the offset circuit 21, a desired direct current component can be given to the input NRZ signal S, and the signal S 'input from the offset circuit 21 to the main amplifier 22 is variably controlled by the offset voltage Voffset. It is possible to maintain the input range of the amplifier 22 within a proper range.

  In order to perform this variable control, a voltage detection means 30, A / D converters 38 and 39, a center voltage calculation means 40, and an offset voltage setting means 50 are provided.

  The voltage detection means 30 is for detecting the high level voltage VH and the low level voltage VL of the signal S ′ input to the main amplifier 22, and the configuration thereof will be described later.

  These detected voltages VH and VL are converted into digital values by A / D converters 38 and 39, respectively, and input to the center voltage calculation means 40, and the center voltage Vcent = (high level voltage VH and low level voltage VL). VH + VL) / 2 is calculated.

  Then, the offset voltage setting means 50 obtains an offset voltage Voffset for the calculated center voltage Vcent to be approximately the center Vaa of the proper input range of the main amplifier 22 and gives it to the offset circuit 21, thereby giving the main amplifier 22 On the other hand, the state in which the NRZ signal is input in the proper input range is maintained.

Next, the configuration and operation of the voltage detection means 30 of this embodiment will be described.
The voltage detection means 30 includes a first comparator 31 that compares the input signal S ′ to the main amplifier and the first reference voltage Vs1, and a second comparator that compares the input signal S ′ and the second reference voltage Vs2. The first low-pass filter 33 that extracts the DC component DC1 from the comparator 32, the output signal C1 of the first comparator 31, and the first low-pass filter that extracts the DC component DC2 from the output signal C2 of the second comparator 32. 2, the output signal DC 1 of the first filter 33, and the first reference voltage Vr 1 equal to the output upper limit voltage of the first comparator 31. The difference is amplified by a predetermined gain A and the first The first operational amplifier 35 to be supplied to the first comparator 31 as the first reference voltage Vs1, the output signal DC2 of the second filter 34, and the output lower limit voltage of the second comparator Receiving equal and a second reference voltage Vr2, and a second operational amplifier 36 to provide the difference as predetermined gain A partial amplified and the second reference voltage Vs2 to a second comparator 32.

  According to the voltage detection means 30 of this feedback configuration, the first reference voltage Vs1 substantially coincides with the low level voltage of the signal S ′ input to the main amplifier 22, and the second reference voltage Vs2 is the signal S ′. Feedback control is performed so as to substantially match the high level voltage.

  Therefore, by supplying the first and second reference voltages Vs1 and Vs2 as the high level voltage and the low level voltage to the center voltage calculation means 40, the center voltage Vcent of the signal S is set to the center voltage within the proper input range of the main amplifier 22. It can be matched with Vaa.

  FIG. 2 shows an example of the operation. In the initial period T1, as shown in FIG. 2A, the high level voltage VH (for example, positive) and the low level voltage VL (for example, negative) of the signal S ′ are shown. ) Between the first reference voltage Vs1 (for example, the initial value 0), the output C1 of the first comparator 31 is the signal S ′ first as shown in FIG. Is higher than the output upper limit voltage (Vr1) of the first comparator 31, and when the signal S 'is lower than the first reference voltage Vs1, the output lower limit voltage ( Vr2) is a low-level rectangular wave.

  Therefore, the output voltage DC1 of the first filter 33 is a value between the first reference voltage Vr1 and the second reference voltage Vr2.

  Then, the first operational amplifier 35 supplies the first comparator 31 with a voltage of A (DC1-Vr1) proportional to the difference between the first reference voltage Vr1 and the output voltage DC1 as the first reference voltage Vs1.

  If A is positive here, A (DC1-Vr1) is negative, so the first reference voltage Vs1 in the next period T2 is negative, which is lower than the initial value.

  Thus, in the period T2 in which the first reference voltage Vs1 is low, the high level period of the output C1 of the first comparator 31 is long as shown in FIG. The voltage DC1 becomes high and becomes close to the first reference voltage Vr1.

  Therefore, A (Vr1-DC1) proportional to the difference between the first reference voltage Vr1 and the output voltage DC1, that is, the first reference voltage Vs1 further decreases.

  The above operation is continuously performed, and in a period T3, the first reference voltage Vs1 substantially coincides with the low level voltage VH of the signal S ′ (strictly, slightly lower than the low level voltage). At this time, the output C1 of the first comparator 33 is at a high level (may be instantaneously at a low level due to noise) for most of the period, and the voltage of the output DC1 of the first filter 33 is the output upper limit voltage of the comparator 33. It becomes substantially equal to (Vr1), and this state is maintained by automatic control of the loop.

  In the above operation, the first reference voltage Vs1 is made to substantially coincide with the low level voltage VL of the signal S ′ by the loop control including the first comparator 31, the first filter 33, and the first operational amplifier 35. The same applies to the loop control by the second comparator 32, the second filter 34, and the second operational amplifier 36. In this case, the second reference voltage Vs2 is substantially equal to the high level voltage VH of the signal S '. I am letting.

  That is, as shown in FIG. 3, in the initial period T1, the second reference voltage Vs2 (eg, 0) is between the high level voltage VH (eg, positive) and the low level voltage VL (eg, negative) of the signal S ′. If it exists, as shown in FIG. 3B, the output C2 of the second comparator 32 is the output upper limit of the second comparator 32 during the period in which the signal S ′ is higher than the second reference voltage Vs2. When the voltage (Vr1) is at a high level and the signal S ′ is lower than the first reference voltage Vs2, the output lower limit voltage (Vr2) of the second comparator 32 is a low-level rectangular wave.

  Therefore, the output voltage DC2 of the second filter 34 is between the first reference voltage Vr1 and the second reference voltage Vr2.

  Then, a voltage of A (DC2-Vr2) proportional to the difference between the second reference voltage Vr2 and the output voltage DC2 is given to the second comparator 32 as the second reference voltage Vs2.

  In this case, if A is positive as described above, A (DC2-Vr2) is also positive. Therefore, the second reference voltage Vs2 in the next period T2 is positive and changes high.

  Thus, in the period T2 in which the second reference voltage Vs2 is high, the high level period of the output C2 of the second comparator 32 is shortened as shown in FIG. The voltage DC2 becomes low and becomes close to the second reference voltage Vr2.

  Therefore, A (Vr2-DC2) proportional to the difference between the second reference voltage Vr2 and the output voltage DC2, that is, the second reference voltage Vs2 is further increased.

  The above operation is continuously performed, and the second reference voltage Vs2 substantially coincides with the high level voltage VH of the signal S ′ (strictly, slightly higher than the high level voltage) as in the period T3. At this time, the output C2 of the second comparator 32 is at a low level (may be instantaneously at a high level due to noise) for most of the period, and the voltage of the output DC2 of the second filter 34 is the output lower limit voltage of the comparator ( Vr2), and this state is maintained by automatic loop control.

  In this way, the reference voltages Vs1 and Vs2 that approximately match the high level voltage and the low level voltage of the signal S ′ are converted into digital values by the A / D converters 38 and 39 as described above, and the center voltage is calculated. The center voltage Vcent = (VH + VL) / 2 of the high level voltage VH and the low level voltage VL is input to the means 40.

  Here, the offset voltage setting means 50 determines whether or not the center voltage Vcent is within an appropriate input center voltage range of the main amplifier 22, and if so, holds the offset voltage Voffset at the current value.

  Further, as shown in FIG. 4, when the center voltage Vcent of the signal S ′ deviates from the proper input center voltage range Vaa ± α of the main amplifier 22, the difference (Vaa−Vcent) with the center voltage Vaa. ), The offset voltage Voffset with respect to the offset circuit 21 is changed so that the center voltage Vcent becomes substantially the center Vaa of the proper input range of the main amplifier 22. As a result, it is possible to maintain the state in which the NRZ signal is input to the main amplifier 22 in its proper input range.

  Further, by using the comparators 31 and 32 having both high impedance and low capacity without using the diode detection method as in the conventional apparatus, even if the signal is several tens of GH, waveform change due to disturbance of impedance can be generated. Therefore, highly accurate voltage detection processing can be performed.

  In the above-described embodiment, an element in which a circuit including the main amplifier 22, the first comparator 31, and the second comparator 32 is integrally configured by the same semiconductor process (for example, InP) is used. For this reason, the first comparator 31 and the second comparator 32 can be formed with the same characteristics (transistor operation) as the main amplifier 22, and a comparison process capable of handling high-speed signals processed by the main amplifier 22 is possible. Thus, the voltage detection process described above can be performed with higher accuracy. Therefore, it is possible to perform feedback control with little error on the main amplifier 22.

  In the above embodiment, the main amplifier 22 is a single operation with a single-phase input. However, as in the NRZ signal amplifying apparatus 20 ′ of FIG. 5, two-phase NRZ signals S and Sinv that are inverted with respect to each other are differentially converted. The present invention can also be applied to the case of amplification by the main amplifier 22 '.

  That is, both NRZ signals S and Sinv are input to the main amplifier 22 ′ through offset circuits 21 A and 21 B configured in the same manner as the offset circuit 21.

  Then, with respect to the signals S ′ and Sinv ′ output from the offset circuits 21A and 21B, the voltage detection means 30A and 30B configured in the same manner as the voltage detection means 30 are used for the low level voltage and the high level voltage of each signal. , And the voltage value is converted into a digital value by the A / D converters 38 and 39 configured in the same manner as described above, and the central voltage is calculated by the central voltage calculating means 40A and 40B configured similarly to the central voltage calculating means 40. Vcent1 and Vcent2 are obtained. Then, the offset voltages Voffset1 and Voffset2 are controlled by the offset voltage setting means 50A and 50B so that the center voltages Vcent1 and Vcent2 of each signal fall within the input appropriate center voltage range of the main amplifier 22 '.

  Even in the case of performing such differential amplification processing, the main amplifier 22 'and the circuit including the comparators 31 and 33 of the voltage detection means 30A and 30B are integrally formed by the same semiconductor process (for example, InP). By using the configured element, it is possible to perform a comparison process compatible with a high-speed signal processed by the main amplifier 22 ', and the above-described voltage detection process can be performed with higher accuracy.

Configuration diagram of an embodiment of the present invention Operation explanatory diagram of the embodiment Operation explanatory diagram of the embodiment Operation explanatory diagram of the embodiment Configuration diagram of differential type embodiment Configuration diagram of conventional equipment

Explanation of symbols

  20, 20 '... NRZ signal amplifying device, 21, 21A, 21B... Offset circuit, 22, 22'... Main amplifier, 30, 30A, 30B... Voltage detection means, 31. ...... Second comparator, 33 ...... first filter, 34 ...... second filter, 35 ...... first operational amplifier, 36 ...... second operational amplifier, 38, 39 ...... A / D conversion , 40, 40A, 40B ... center voltage calculating means, 50, 50A, 50B ... offset voltage setting means

Claims (2)

An offset circuit (21) for adding an offset voltage to the input NRZ signal and outputting it;
A main amplifier (22) for receiving and amplifying the output signal of the offset circuit;
Voltage detection means (30) for detecting a high level voltage and a low level voltage of an input signal to the main amplifier;
Center voltage calculating means (40) for calculating center voltages of the high level voltage and the low level voltage detected by the voltage detecting means;
In an NRZ signal amplifying apparatus comprising offset voltage setting means (50) for obtaining an offset voltage for the calculated center voltage to be approximately the center of an appropriate input range of the main amplifier and giving the offset voltage to the offset circuit,
The voltage detection means includes
A first comparator (31) for comparing an input signal to the main amplifier and a first reference voltage;
A second comparator (32) for comparing an input signal to the main amplifier and a second reference voltage;
A first filter (33) for extracting a DC component from the output signal of the first comparator;
A second filter (34) for extracting a DC component from the output signal of the second comparator;
A first filter that receives an output signal of the first filter and a first reference voltage equal to an output upper limit voltage of the first comparator, and provides a difference output to the first comparator as the first reference voltage; Operational amplifier (35),
A second filter that receives an output signal of the second filter and a second reference voltage equal to an output lower limit voltage of the second comparator, and supplies a difference output to the second comparator as the second reference voltage; And an operational amplifier (36).
Feedback control is performed so that the first reference voltage and the second reference voltage match the high level voltage and the low level voltage of the signal input to the main amplifier, respectively, and the first and second reference voltages are changed. An NRZ signal amplifying apparatus characterized in that the high-level voltage and the low-level voltage are supplied to the center voltage calculation means.   2. The NRZ signal amplifying apparatus according to claim 1, wherein the main amplifier, the first comparator, and the second comparator are integrally configured by the same semiconductor process.

Images