JPH0661863A - Dc dither input type deltasigma modulation type a/d converter - Google Patents

Abstract

PURPOSE:To facilitate the setting and adjustment of a DC dither input level by providing a digital signal processing function and a DC dither supply function to the A/D converter. CONSTITUTION:A digital signal processing section 70 calculates a power of a digital signal outputted from an LPF 60 to detect a signal level and to decide a DC digital voltage based on the result. A DC dither supply section 80 receiving the digital control signal deciding the DC dither level supplies the relevant DC dither level to an adder 10. Thus, even when there takes place any difference between a noninverting voltage level and an inverting voltage level being outputs of a D/A converter 50, a power arithmetic operation means of the signal processing section 70 detects a signal level equivalent to the difference between the noninverting voltage level and the inverting voltage level to decide the DC dither level based on the detected signal level. Thus, a differential amplifier 20 is used to be acted like absorbing the difference between the noninverting voltage level and the inverting voltage level of the D/A converter 50.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ΔΣ modulation type A for inputting a DC dither to convert an analog signal into a digital signal.
It relates to a D converter.

Recently, a method of inputting a DC dither into a ΔΣ modulation type AD converter for converting an analog signal into a digital signal to reduce the quantization noise has been studied, but there is a strong demand for early practical use.

[0003]

2. Description of the Related Art A conventional example will be described with reference to FIGS. FIG. 7 shows a first conventional example, which is an example of a ΔΣ modulation type AD converter, and FIG. 8 shows a second conventional example which is an improvement of FIG.
FIG. 9 is a diagram showing an example of a DC dither input type ΔΣ modulation type AD converter, and FIG. 9 is a diagram showing changes in the output voltage level of the integrator.

Conventionally, in converting an analog signal into a digital signal, if the resolution of the digital portion is increased, the quantization noise can be reduced, but the ΔΣ modulation type AD converter outputs one bit at a time. Therefore, since the number of quantization bits is small, quantization noise increases. Therefore, a method of reducing the quantization noise by dispersing the noise component in a wide band by increasing the frequency of the main clock to be input several hundred times higher than that of the analog input signal is usually used.

In the first conventional example of FIG. 7, in order to simplify the explanation, the comparator 40 has a threshold value Vc of +
Input 0.5V, 1-bit DA converter 5
The dynamic range of 0 is +1 V and -1 V, and the analog input signal Ain is input to the + terminal of the differential amplifier 20, but the analog signal Ain will be described as a state in which 0 V is input.

First, when the initial clock for operating the circuit is not input, the output V1 of the differential amplifier 20 becomes indefinite and the output V2 of the integrator 30 becomes 0V. In the next comparator 40, the threshold value +0.5 V and the integrator 30
The output of the comparator 40 becomes "L" because the negative side becomes larger.

When "L" is output to the output of the comparator 40, the -1V side is turned on in the 1-bit DA converter (hereinafter referred to as "DA converter") 50, and D
The output V3 of the -A converter 50 becomes -1V.

Next, when the first clock (first clock) is input to the integrator 30, the comparator 40, the DA converter 50, etc., the output -1V of the DA converter 50 is -1V. −1V is output to the output V1 of the differential amplifier 20 as it is input to the negative terminal.

The output V of the integrator 30 to which this + 1V is input
In the case of 2, the value at the immediately preceding clock was 0V, so + 1V is added to 0V, and + 1V is output.

Next, in the comparator 40, this input + 1V is compared with the threshold value 0.5V, which is higher than the threshold value 0.5V, so "H" is output to the output of the comparator 40. To be done.

When "H" is output, the + 1V side of the DA converter 50 is turned on, and the DA converter 5
The output V3 of 0 becomes + 1V. The next second clock is the integrator 30, the comparator 40, and the DA converter 50.
, The output V3 of the DA converter 50 is +
Since 1V is input to the-terminal of the differential amplifier 20, -1V is output to the output V1 of the differential amplifier 20.

The output V of the integrator 30 to which this -1V is input
In the case of 2, the value at the previous clock was + 1V, so -1V is added to + 1V, and 0V is output.

Thereafter, similarly, the output V2 of the integrator 30 is obtained.
Outputs + 1V and 0V alternately, and the output V3 of the comparator 40 outputs digital signals "L" and "H" alternately. Therefore, a filter 60 for averaging the digital signal level is used. By passing it, the digital signal output Dout can be obtained at the output of the filter 60.

The S / N value is obtained by converting the digital signal output into an FFT (Fast Fourier transform).
m: fast Fourier transform) Obtained by analysis. When FFT analysis is performed, the DC component and the clock frequency f = 1 / T [H
A spectral component equal to z] can be obtained. FIG. 9 (1) shows the voltage level of the output V2 of the integrator 30 obtained in this way, which is 0V and + 1V each time one clock is input. This is an ideal representation of alternating output voltage levels.

However, in reality, the DA converter 5
When an error occurs between + 1V and -1V of the output voltage V3 of 0,
The voltage level change does not change as shown in FIG. 9 (1), and the voltage level changes with T1 as a cycle, for example, as shown in FIG. 9 (2).

FIG. 9B shows the DA converter 5 of FIG.
0 of the dynamic range on both sides of 0.
Error of 2V (Normally, an error of about several tens of mV occurs when integrated into an LSI, but for convenience of explanation, the error is expanded to 0.2V.
FIG. 7 is a diagram showing a change in the output voltage level of the integrator 30 when V decreases and +0.8 V is assumed to be sent to the differential amplifier 20).

Unlike the ideal operation shown in FIG. 9A, D-
Since the output error of 0.2 A of the A converter 50 continues to influence the addition (integration) of the input signals in the integrator 30, the output voltage level value of the integrator 20 is newly set to T1 (as shown in FIG. 9B). A frequency component having a cycle of frequency = f ₁ appears (see FIG. 3).

When the spectrum of the frequency f ₁ exists within the input signal band, the output voltage level V of the integrator 30
Even if 2 passes through the comparator 40 and the filter 60, it is included in the digital signal output Dout.

In order to solve this problem, as shown in FIG. 8, a small offset potential called DC dither is added to the input signal Ain, and the positive and negative voltage values of the dynamic range output from the DA converter 50. The method of absorbing the difference of is taken.

Normally, the DC dither input is set to a value of about 10 mV within a range where it does not affect the input signal, but for convenience of explanation, it is assumed that the value is set to 80 mV. First, when there is no clock input, the output V2 of the integrator 30 is 0V and the output of the comparator 40 is "L" because the operation without clock input is before, and thus the output V3 of the DA converter 50 is -1V. Become.

Next, when the first clock is input, it is assumed that there is no analog signal input Ain (0V), and the result of adding 80 mV of DC dither VD to the analog signal input by the adder 10 is output from the differential amplifier 20. To + input, D-
The output V3 "-1V" of the A converter 50 is used as the differential amplifier 2
When input to each of the-inputs of 0, the output V1 of the differential amplifier 20 is + 1.08V, and the output of the comparator 30 is "
The output V3 of the H ″, DA converter 50 is 0.8V.

Next, at the second clock input,
0.08V to + input of differential amplifier 20, 0.8 to-input
V is input, and the output V1 of the differential amplifier 20 is -0.72.
It becomes V. In the integrator 30, the value V one clock before
-0.72V is added to 1.08V which is 2, the output V2 of the integrator 30 becomes 0.36V, and the comparator 4
The output of 0 becomes "L".

In this way, the same operation is performed after the third clock. FIG. 9C shows this operation with respect to the output voltage level of the integrator 30. In the normal operation of the circuit of FIG. 7, the frequency component of the period T1 generated as shown in FIG. 9 (2) is input by the DC dither, so that the frequency component having the period T2 as shown in FIG. 9 (3). You can see that it changes to.

FIG. 3 shows a spectrum display of these signal components. Here, if 1 / T2 [Hz] = f ₂ is a high frequency compared to the input signal band (DC to f ′), then f ₂
Goes out of band, so S in the input signal band
The / N characteristic will be improved.

[0025]

However, although this method is an existing technique, at present, it is a situation in which an attempt is made to arbitrarily set a dither input value each time in a simulation or the like, and it is practically used. Is scarce.

An object of the present invention is to solve the above problems and to provide a DC dither input type ΔΣ modulation type AD converter capable of easily setting and adjusting the DC dither input value.

[0027]

FIG. 1 is a diagram showing the principle configuration of a DC dither input type ΔΣ modulation type AD converter according to the present invention. In the figure, the same reference numerals as those in FIG. 8 indicate the same components, 70 is a digital signal processing unit, and 80 is a DC dither supply unit.

The present invention adds an analog signal input obtained by adding a DC dither to an analog signal input by the adder 10, and
The differential amplifier 20 amplifies the difference between the digitized data one clock before returned to the analog input signal side by the 1-bit DA converter 50, and further the integrator 30.
Comparing the value with and comparing it with the threshold value with the comparator 40
A filter 60 for converting the digital value to either the H "level or the" L "level and averaging the digital value.
DC dither input type Δ that extracts digital signal via
In the Σ modulation type AD converter, the low-pass filter 60
A digital signal processing unit 70 having a power calculation means for calculating the power of the digital signal output from the device and detecting the signal level, a DC dither setting means for determining the DC dither voltage value based on the result, and the digital signal processing The object can be achieved by providing the adder 10 with the DC dither supply means 80 for supplying the corresponding DC dither value in response to the digital control signal for determining the DC dither value from the section 70.

Here, the DC dither supply section 80 can be constructed by using an analog switch, a resistor, and a serial / parallel converter. Further, the low-pass filter 82 can be added to the output section of the DC dither supply section 80.

[0030]

According to the present invention, there is provided a digital circuit having a power calculating means for calculating the power of the digital signal output from the low-pass filter 60 to detect the signal level, and a DC dither determining means for determining the DC dither voltage value based on the result. The signal processing section 70 and the DC dither supply means 80 for supplying the corresponding DC dither value to the adder 10 in response to the digital control signal for determining the DC dither value from the digital signal processing section 70 are provided. Even if a difference occurs between the + side voltage level and the − side voltage level of the output of the A converter 50, the power calculation means of the digital signal processing unit 70 causes the + side voltage level of the output of the DA converter 50 and −.
The signal level corresponding to the difference in the side voltage level is detected, and the DC dither value is determined by the detected signal level.

Then, the DC dither supply section 80 which has received the digital control signal for determining the DC dither value supplies the DC dither voltage value corresponding to this digital control signal to the adder 10, so that the differential amplifier 20 , D
It is possible to act so as to absorb the difference between the + side voltage level and the − side voltage level of the output of the −A converter 50.

By doing so, noise generated due to the difference between the + side voltage level and the + side voltage level of the output of the DA converter 50 can be further reduced. Here, the DC dither supply unit 80 can be easily configured by using an analog switch, a resistor, and a serial / parallel converter.

Further, by adding a low-pass filter 82 to the output section of the DC dither supply section 80, noise accompanying the operation of the analog switches S1 to S5 can be cut off.

[0034]

EXAMPLES Next, examples will be described with reference to FIGS. FIG. 2 is a DC dither input type ΔΣ according to the present invention.
FIG. 3 is an output signal spectrum relationship diagram, and FIG. 4 is an example of a DC dither setting flowchart in the present invention, which is an embodiment of a modulation type AD converter. 5 is a specific example of the selector circuit in FIG. 2, and FIG. 6 is a specific example of the DC dither supply section in FIG.

In the figure, the same reference numerals as those in FIGS. 1 and 8 indicate the same elements, 11 is a selector, 12 is an INV circuit, 71 is a power calculation section, 72 is a DC dither input value setting section, and 73 is a training operation switching section. , 81 is a serial / parallel converter, 13 and 82 are low-pass filters, C is a capacitor,
R, R0 to R5 are resistors, and S1 to S5 are analog switches.

In this embodiment, a training function for confirming circuit operation is provided before converting an analog signal into a digital signal. A specific example of the selector circuit necessary for training is shown in FIG. 5. Before the analog signal is converted into the digital signal, the training operation switching section 73 of the digital processing section 70 sends a control signal to the selector 11. Opening S1 and closing S2 to raise the ground level instead of the analog input signal is the state of the analog signal input.

The low-pass filter 13 is provided to cut off noise generated by the operation of the analog switches S1 and S2. Embodiments of the present invention are based on digital signal processing (Digital signal processes).
The digitalized output signal Dout (i) is

[0038]

[Equation 1] A power calculation is performed based on the following equation, and the resulting power calculation value P is compared with a predicted power calculation value Pc which is the result of the power calculation of the analog input signal Ain predicted in advance.

As a result, if a large difference occurs between P and Pc, there is an error in the output voltage of the DA converter 50,
It is assumed that the spectrum of f ₁ = 1 / T1 [Hz] shown in FIG. 9B appears and the noise component has increased.

Next, according to the difference between P and Pc, the adder 10
The DC dither to be input to is set by R2 divided by resistance. If the DC dither is too large, the analog signal input Ai
Since n may not be equal to the digital signal output Dout, the DC dither should be kept to the minimum necessary each time and fixed should be avoided.

Now, FIG. 4 will be described with reference to FIGS. 2 and 3. In addition, the following ○ numbers are shown in Fig. 4.
Match the number. Training operation switching unit 7 of digital processing unit 70
In 1, the selector 11 is switched to the training mode. As an initial setting, the DC dither DV is set to 0V in the state without dither input. Clear the power calculation result (P = 0). The circuit of the embodiment of FIG. 2 is operated in the same manner as described in the explanation of the operation of the second conventional example, and the digital output Dout is addressed to the digital signal processing unit 70 N times or more sampling operations.

[0042]

[Equation 2] According to the equation, power calculation is performed by the digital signal output Dout. Depending on the analog input signal, the average value of the digital signals to be output can be 0, so in the present invention, the average value of the sum of squares is calculated. An expected power calculation result Pc of the analog input signal is obtained in advance, a target range defined by the upper limit value Pov and the lower limit value Pun is set, and the result is compared with the result obtained in the section. If the result obtained by the term is within the target range obtained by the term, the DC dither VD is determined, and if the result obtained by the term is outside the target range obtained by the term, the DC dither VD is reset. When the result obtained by the term is within the target range obtained by the term, the DC dither VD at that time is finally determined as the DC dither value. Training operation switching unit 7 of digital processing unit 70
3, the selector 11 is switched to the normal operation mode.

As described above, the DC dither value is determined. 6 is a diagram showing a specific example of the DC dither supply unit 80, a digital control signal for determining the DC dither value sent from the DC dither input value setting unit 72 of the digital signal processing unit 70, That is, a digital control signal, which is serial data having the number of bits corresponding to the number of analog switches, is input to the serial / parallel converter 81,
The analog switches S1 to S5 of the corresponding bits converted into the parallel signal are closed to generate the DC dither value.

The low-pass filter 82 is for preventing noise generated during the operation of the analog switches S1 to S5. In addition, the pass band is a DC component. By increasing the number of bits of the serial / parallel converter 81, it is possible to increase the generated DC dither value.

[0045]

As described above, according to the present invention,
By providing a digital signal processing function and a DC dither supply function, it can be put into practical use, and the ΔΣ modulation type A
Since the main noise that is likely to occur in the D converter can be easily moved to the high frequency band, the S / N characteristic can be improved.

[Brief description of drawings]

FIG. 1 is a DC dither input type ΔΣ modulation type A according to the present invention.
It is a principle block diagram of a D converter.

FIG. 2 is a DC dither input type ΔΣ modulation type A according to the present invention.
It is an example of a D converter.

FIG. 3 is a relational diagram of an output signal spectrum according to the present invention.

FIG. 4 is an example of a DC dither setting flowchart in the present invention.

5 is a diagram showing a specific example of a selector circuit in FIG.

FIG. 6 is a diagram showing a specific example of a DC dither supply unit in FIG.

FIG. 7 is a diagram showing an example of a ΔΣ modulation type AD converter in the first conventional example.

FIG. 8 is a DC dither input type ΔΣ modulation type A in the second conventional example.
It is a figure which shows an example of a D converter.

FIG. 9 is a diagram showing changes in the output voltage level of the integrator.

[Explanation of symbols]

 10 adder 11 selector 12 INV circuit 20 differential amplifier 30 integrator 40 comparator 50 1-bit D / A converter 13, 60, 82 low-pass filter 70 digital signal processing unit 71 power operation unit 72 DC dither input value setting unit 73 training operation Switching unit 80 DC dither supply unit 81 Serial / parallel converter C Capacitor R, R0 to R5 Resistance S1 to S5 Analog switch

Claims (3)

[Claims] 1. An analog signal input obtained by adding a DC dither to an analog signal input by an adder (10) and a 1-bit D / A converter (50) to re-analog digitized data one clock before. The difference from that returned to the input signal side is amplified by the differential amplifier (20), and the value integrated by the integrator (30) is compared with the threshold value by the comparator (40) to be converted into a digital value, In a DC dither input type ΔΣ modulation type AD converter for extracting a digital signal through a filter (60) for averaging the digital value, the power of the digital signal output from the filter (60) is calculated to detect the signal level. Power calculation means for
A digital signal processing unit (70) having direct current dither setting means for determining a direct current dither voltage value based on the result.
And a digital control signal for determining a DC dither value from the digital signal processing unit (70), the adder (1
0) is provided with a DC dither supply means (80) for supplying the corresponding DC dither value. A DC dither input type ΔΣ modulation AD converter. 2. The DC dither input type ΔΣ modulation type AD converter according to claim 1, wherein the DC dither supply section (80) comprises an analog switch, a resistor, and a serial / parallel converter. 3. The DC dither input type ΔΣ modulation type AD according to claim 2, wherein a low pass filter (82) is added to the output section of the DC dither supply section (80).
converter.