JP4950710B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly to a semiconductor device using a metal oxide film or a metal silicate film as a gate insulating film and a method for manufacturing the semiconductor device.

  With the miniaturization of MISFETs, thinning of the gate insulating film is required. However, in the conventional silicon oxide film and silicon oxynitride film, the limit of thinning is about 2 nm due to the increase of direct tunnel current. Will reach.

  Therefore, by using a metal oxide film or metal silicate film (metal silicate film) whose dielectric constant is higher than that of silicon oxide film as the gate insulating film, the actual film thickness (physical film thickness) is maintained while maintaining the effective film thickness. ) Is made thick to suppress leakage current.

  However, when a metal oxide film is used for the gate insulating film, there is a problem that it is difficult to obtain a good interface with the silicon substrate. In addition, when a metal silicate film is used as a gate insulating film, a good interface can be obtained to some extent, but there is a problem that a dielectric constant is smaller than that of a metal oxide film.

  Although a method of forming a silicon oxynitride film at the interface between the silicon substrate and the metal oxide film is also conceivable, it is difficult to reduce the thickness of the silicon oxynitride film to 1 nm or less. The film thickness cannot be reduced.

  Another possible method is to form a metal oxide film on the silicon substrate, and then form a metal silicate film at the interface between the silicon substrate and the metal oxide film by heat treatment to form a laminated structure of the two. However, in this case, both constituent metals are necessarily the same, and there is a problem that it is difficult to obtain an optimal combination of a metal oxide film and a metal silicate film. In addition, since the metal oxide film has a crystal structure, there is a problem that the local effective film thickness varies due to the dependency of the dielectric constant on the crystal plane orientation.

As described above, a proposal has been made to use a metal oxide film or a metal silicate film as an insulating film having a dielectric constant higher than that of a silicon oxide film in order to limit the thinning of the gate insulating film . In that respect, many problems to be solved remain.

The present invention has been made to solve the above-described conventional problems, and in a semiconductor device using a metal oxide film or a metal silicate film as a gate insulating film, the semiconductor device capable of improving characteristics and its manufacture It aims to provide a method.

  A first invention is a semiconductor device using an insulating film containing metal, silicon and oxygen as at least a part of a gate insulating film, wherein the insulating film containing metal, silicon and oxygen contains at least one of fluorine and nitrogen. It is included.

  A second invention is a semiconductor device using a metal oxide film as at least a part of a gate insulating film, wherein an insulating film containing metal, silicon, and oxygen is provided between a semiconductor substrate and the metal oxide film. The formed insulating film containing metal, silicon, and oxygen contains at least one of fluorine and nitrogen.

  According to the first and second inventions, by including fluorine in the metal silicate film, the tangling bond existing at the interface between silicon and the metal silicate film constituting the semiconductor substrate is terminated with fluorine. Can do. Therefore, the interface state density can be made lower than that of a normal metal silicate film, and good interface characteristics can be obtained.

  Further, according to the first and second inventions, by including nitrogen in the metal silicate film, the dielectric constant of the metal silicate film can be increased and the effective film thickness can be reduced. Further, for example, in the annealing in an oxidizing atmosphere for compensating oxygen vacancies in the metal oxide film, the oxidation reaction at the interface between silicon and the metal silicate film constituting the semiconductor substrate can be suppressed, and the effective film It is possible to reduce the thickness and obtain good interface characteristics with a low interface state density.

  Thus, by forming an insulating film containing metal, silicon and oxygen containing at least one of fluorine and nitrogen between the semiconductor substrate and the metal oxide film, the metal oxide film and the metal silicate film It is possible not only to reduce the effective film thickness of the gate insulating film made of and to reduce leakage current, but also to realize a high-performance transistor having good interface characteristics.

  A third invention is a semiconductor device using a metal oxide film as at least a part of a gate insulating film, wherein an insulating film containing metal, silicon and oxygen is provided between a semiconductor substrate and the metal oxide film. The formed metal oxide film and the insulating film containing metal, silicon, and oxygen are amorphous films.

  A fourth invention is a semiconductor device using a metal oxide film as at least a part of a gate insulating film, wherein an insulating film containing metal, silicon and oxygen is provided between a semiconductor substrate and the metal oxide film. The main metal element formed and constituting the metal oxide film is different from the main metal element constituting the metal, silicon and oxygen insulating film.

  A fifth invention is a method of manufacturing a semiconductor device using a metal oxide film as at least a part of a gate insulating film, the step of forming an insulating film containing metal, silicon and oxygen on a semiconductor substrate; And a step of forming a metal oxide film over the insulating film containing metal, silicon, and oxygen.

  5th invention WHEREIN: After the process of forming the said insulating film containing a metal, silicon, and oxygen, before the process of forming the said metal oxide film, the crystallization temperature of the said insulating film containing a metal, silicon, and oxygen It is preferable to perform the heat treatment at a temperature lower than that and higher than the crystallization temperature of the metal oxide film.

  According to the third aspect of the invention, the basic effect that the effective film thickness of the gate insulating film made of the metal oxide film and the metal silicate film can be reduced and the leakage current can be reduced is obtained. Since the material film and the insulating film containing metal, silicon, and oxygen are non-crystalline films, variations in local effective film thickness due to the dependence of the dielectric constant on the crystal plane orientation are reduced, and variations in threshold voltage, etc. A transistor with less reliability and excellent reliability can be obtained.

  According to the fourth aspect of the invention, the basic effect that the effective thickness of the gate insulating film made of the metal oxide film and the metal silicate film can be reduced and the leakage current can be reduced is obtained. Since the main metal element constituting the material film is different from the main metal element constituting the insulating film containing metal, silicon and oxygen, a suitable metal element can be selected for each, and a stable metal silicate film can be obtained. Interface characteristics can be obtained, and a metal oxide film having a high dielectric constant can be used, so that a transistor having excellent characteristics can be obtained.

  According to the fifth invention, instead of forming an insulating film containing metal, silicon and oxygen by heat treatment after forming a metal oxide film as in the prior art, an insulating film containing metal, silicon and oxygen is formed. Then, since the metal oxide film is formed, the main constituent metal element of the metal oxide film and the main constituent metal element of the insulating film containing metal, silicon, and oxygen can be easily made different. In addition, after the step of forming the insulating film containing metal, silicon, and oxygen, and before the step of forming the metal oxide film, the temperature is lower than the crystallization temperature of the insulating film containing metal, silicon, and oxygen and the metal oxide By performing heat treatment at a temperature higher than the crystallization temperature of the film, an insulating film containing metal, silicon, and oxygen and an amorphous film of a metal oxide film can be easily obtained.

  A sixth invention is a method of manufacturing a semiconductor device using a metal oxide film as at least a part of a gate insulating film, and after forming a metal oxide film on a semiconductor substrate, a plurality of types having different oxidizing powers Heat treatment is performed in an atmosphere containing gas.

  6th invention WHEREIN: The said heat processing is performed on the conditions that the silicon | silicone of the boundary area | region of the said semiconductor substrate and the said metal oxide film is not oxidized, but the metal contained in the said metal oxide film is oxidized. Is preferred.

  A seventh invention is a method of manufacturing a semiconductor device using an insulating film containing metal, silicon and oxygen as at least a part of a gate insulating film, and forming an insulating film containing metal, silicon and oxygen on a semiconductor substrate Then, heat treatment is performed in an atmosphere containing a plurality of types of gases having different oxidizing powers.

  In a seventh aspect of the invention, the heat treatment does not oxidize silicon in a boundary region between the semiconductor substrate and the insulating film containing the metal, silicon, and oxygen, and the metal contained in the insulating film containing the metal, silicon, and oxygen. It is preferable that the reaction be performed under conditions that allow oxidation.

  According to the sixth and seventh inventions, by performing heat treatment in an atmosphere containing a plurality of types of gases having different oxidizing powers, the interface region between the semiconductor substrate and the metal oxide film or the semiconductor substrate and the metal, silicon, and oxygen A metal oxide film or an insulating film containing metal, silicon and oxygen can be brought close to a stoichiometric composition without forming a silicon oxide film in an interface region with the insulating film containing the dense metal oxide. A film or an insulating film containing metal, silicon, and oxygen can be obtained. Therefore, the effective thickness of the gate insulating film and the leakage current can be reduced, and a transistor having excellent characteristics can be obtained.

  An eighth invention is a method of manufacturing a semiconductor device using an insulating film containing metal, silicon, and oxygen as at least a part of a gate insulating film, the step of forming a silicon oxide insulating film on a semiconductor substrate; Forming a metal film on the silicon oxide insulating film; and reacting the silicon oxide insulating film with the metal film by heat treatment to form an insulating film containing metal, silicon, and oxygen. It is characterized by having.

  In the eighth invention, when the insulating film containing metal, silicon and oxygen is formed, a part of the metal film may be left on the insulating film containing metal, silicon and oxygen.

  According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a silicon oxide insulating film on a semiconductor substrate; forming a first metal film on the silicon oxide insulating film; A step of reacting the silicon oxide insulating film with the first metal film to form an insulating film containing a metal element, silicon and oxygen constituting the first metal film, and during the heat treatment, Removing a part of the first metal film left without reacting with the silicon oxide insulating film; and applying the first metal film to a region where the part of the first metal film is removed. Forming a second metal film composed of a metal element different from the constituent metal elements.

  A method of manufacturing a semiconductor device according to a tenth aspect of the invention includes a step of forming a silicon oxide film-based insulating film on a semiconductor substrate, a step of forming a first metal film on the silicon oxide film-based insulating film, A step of removing a part of the first metal film, and a region made of a metal element different from the metal element constituting the first metal film in a region where the part of the first metal film is removed. A first metal element containing silicon and oxygen, which forms the first metal film by reacting the silicon oxide insulating film and the first metal film by a step of forming a second metal film and a heat treatment. And forming a second insulating film containing a metal element, silicon, and oxygen constituting the second metal film by reacting the silicon oxide film-based insulating film with the second metal film. And a step of performing.

  According to the eighth to tenth inventions, the silicon oxide film-based insulating film and the metal film are reacted by heat treatment to form the insulating film containing metal, silicon, and oxygen, so that the film quality is excellent and the dielectric constant is high. An insulating film can be obtained. In addition, by leaving a part of the metal film on the insulating film containing metal, silicon, and oxygen during the heat treatment, the remaining metal film can be used as a gate electrode, thereby simplifying the manufacturing process and productivity. Can be improved. Further, according to the ninth and tenth aspects, a dual metal transistor using different metals for the gate electrode can be easily manufactured.

  A semiconductor device according to an eleventh aspect of the invention includes first and second regions using an insulating film containing metal, silicon, and oxygen as at least a part of a gate insulating film. The metal elements constituting the insulating film containing metal, silicon, and oxygen are the same, and the composition ratio of the metal elements of the insulating film containing the metal, silicon, and oxygen, silicon, and oxygen in the first and second regions is the same. It is different from each other.

  According to a twelfth aspect of the present invention, there is provided a semiconductor device including: a first region using a metal oxide film as at least part of a gate insulating film; and an insulating film containing metal, silicon, and oxygen as at least part of the gate insulating film. The metal element constituting the metal oxide film in the first region and the metal element constituting the insulating film containing metal, silicon and oxygen in the second region are the same. It is characterized by that.

  A thirteenth aspect of the invention is a method of manufacturing a semiconductor device having first and second regions having different gate insulating films, and a step of forming a silicon oxide insulating film on the semiconductor substrate of the first region Forming a metal oxide film on the silicon oxide insulating film in the first region and on the semiconductor substrate in the second region, the metal oxide film in the second region, and the semiconductor substrate And a step of forming an insulating film containing metal, silicon and oxygen by reacting with silicon by heat treatment.

  A fourteenth aspect of the invention is a method of manufacturing a semiconductor device having first and second regions in which gate insulating films are different from each other, wherein a metal is formed on a semiconductor substrate or a silicon oxide-based insulating film formed on the semiconductor substrate. A step of forming an oxide film, a step of selectively introducing silicon into the metal oxide film formed in the second region, and a heat treatment of the metal oxide film into which silicon has been introduced by heat treatment. And a step of converting into an insulating film containing oxygen.

  A fifteenth aspect of the invention is a method of manufacturing a semiconductor device having first and second regions having different gate insulating films, the step of forming a silicon oxide insulating film on a semiconductor substrate, and the silicon oxide film Forming a metal oxide film on the base insulating film; selectively damaging the silicon oxide insulating film formed in the second region; and damaging the silicon oxide film And a step of reacting the insulating film with the metal oxide film by heat treatment to form an insulating film containing metal, silicon, and oxygen.

  According to the eleventh and twelfth inventions, the first region and the second region have different composition ratios of metal, silicon, and oxygen (in the twelfth invention, the metal oxide in the first region). The composition ratio of silicon in the film is substantially zero), and a gate insulating film structure having different effective film thicknesses in the first region and the second region can be obtained. In addition, according to the thirteenth to fifteenth inventions, such gate insulating film structures having different effective film thicknesses can be easily manufactured with high productivity.

  In each of the above inventions, the insulating film containing metal, silicon, and oxygen substantially refers to a metal silicate film (metal silicate film). In addition, the metal silicate film has a mode in which the metal oxide and the silicon oxide are present as a mixture by phase separation, and a mode in which the metal, silicon and oxygen are uniformly present as a compound. And

  According to the present invention, it is possible to improve characteristics, reliability, productivity, and the like in a semiconductor device using a metal oxide film or a metal silicate film as a gate insulating film.

(Embodiment 1)
A first embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1 (A))
FIG. 1 is a cross-sectional view illustrating a configuration example of a semiconductor device according to Embodiment 1A of the present invention.

  A metal silicate film (metal silicate film, here, zirconium silicate film) 6 and a metal oxide film 3 (here, zirconium oxide film) are formed on the silicon substrate 1 as a gate insulating film. On the material film 3, a titanium nitride film 4 and a tungsten film 5 are formed as gate electrodes.

  The thickness of the zirconium silicate film 6 is about 1.5 nm, the thickness of the zirconium oxide film 3 is about 3 nm, and the equivalent silicon oxide film thickness is about 0.5 nm. The film thickness is about 1 nm. A small amount of fluorine is contained in the zirconium silicate film 6 between the gate electrode and the silicon substrate 1. The width of the gate electrode is about 50 nm.

The amount of fluorine contained in the zirconium silicate film 6 is preferably 1 × 10 ¹⁹ cm ⁻³ to 1 × 10 ²¹ cm ⁻³ in terms of the number of atoms per unit volume. In particular, it is desirable to have a concentration peak of 5 × 10 ¹⁹ cm ^{−3 to} 5 × 10 ²⁰ cm ^{−3 in} the vicinity of the interface with the silicon substrate 1.

  The metal silicate film 6 may be a zirconium silicate film, a hafnium silicate film, a lanthanium silicate film, a gadolinium silicate film, an yttrium silicate film, an aluminum silicate film, or a titanium silicate film. Good. Alternatively, a metal silicate film containing two or more of these metal elements (Zr, Hf, La, Gd, Y, Al, Ti) may be used.

  In addition to the zirconium oxide film, the metal oxide film 3 includes a tantalum oxide film, a titanium oxide film, a lanthanum oxide film, a hafnium oxide film, a gadolinium oxide film, an yttrium oxide film, and an aluminum oxide. A membrane may be used. Alternatively, a metal oxide film containing two or more of these metal elements (Zr, Ta, Ti, La, Hf, Gd, Y, Al) may be used.

  Next, with reference to FIGS. 2A to 4I, a method for manufacturing a semiconductor device according to the present embodiment will be described.

  First, as shown in FIG. 2A, a silicon oxide film 7 having a thickness of 3 nm is formed by thermal oxidation on the surface of the silicon substrate 1 on which an element isolation region (not shown) is formed by the STI technique. Subsequently, a polysilicon film 8 having a thickness of 50 nm and a silicon nitride film 9 having a thickness of 30 nm are deposited using the LPCVD method.

  Next, as shown in FIG. 2B, the silicon nitride film 9 and the polysilicon film 8 are selectively removed using a lithography technique and an RIE method, and a dummy gate pattern 10 is formed in a region where a gate electrode is to be formed. Form.

Next, as shown in FIG. 2C, a silicon oxide film 11 is formed on the sidewalls of the polysilicon film 8 by thermal oxidation at 1000.degree. Thereafter, for example, As ions are implanted under the conditions of an acceleration voltage of 15 keV and a dose of 5 × 10 ¹⁴ cm ⁻² to form the source / drain extension regions 12 in a self-aligned manner with respect to the gate electrode.

  Next, as shown in FIG. 3D, after performing RTA at 800 ° C. for 10 seconds, for example, a silicon nitride film 13 having a thickness of 10 nm and a silicon oxide film 14 having a thickness of 50 nm are formed on the entire surface by LPCVD. Use to deposit. Thereafter, etch back is performed to form sidewalls of the silicon oxide film 14.

Next, as shown in FIG. 3E, for example, As ions are implanted under the conditions of an acceleration voltage of 35 keV and a dose of 5 × 10 ¹⁵ cm ⁻² , and subsequently, RTA is performed at 1035 ° C. for 10 seconds. Then, the source / drain diffusion layer 15 is formed.

  Next, as shown in FIG. 3F, a 100 nm-thickness silicon oxide film 16 is deposited on the entire surface, followed by planarization using a CMP method to expose the upper portion of the dummy gate pattern 10. .

  Next, as shown in FIG. 4G, the silicon nitride film 9 is removed using hot phosphoric acid, and then the polysilicon film 8 is removed using dry etching. Further, channel ion implantation and activation annealing for threshold adjustment are performed. Thereafter, the silicon oxide film 7 is removed using a dilute hydrofluoric acid solution to expose the surface of the silicon substrate 1 serving as a channel region.

Next, as shown in FIG. 4 (h), zirconium chloride (ZrCl ₄ ), tetraethoxysilane (TEOS, Si (OC ₂ H ₅ ) ₄ ) and oxidizing agents O _2, N ₂ O, NO or A zirconium silicate film 6 having a thickness of about 1.5 nm is deposited by LPCVD using H ₂ O. Subsequently, after annealing at 800 ° C. for 30 seconds, the film thickness is about 3 nm by LPCVD using zirconium chloride (ZrCl ₄ ) and oxidizing agents O _2, N ₂ O, NO or H ₂ O. A zirconium oxide film 3 is deposited.

Next, as shown in FIG. 4I, a 10 nm thick titanium nitride film 4 and a 100 nm thick tungsten film 5 are deposited on the entire surface. Thereafter, fluorine ions are implanted under the conditions of an acceleration voltage of 30 keV and a dose of 1 × 10 ¹⁵ cm ⁻² to introduce fluorine into the tungsten film 5.

  Thereafter, planarization is performed using a CMP method. Furthermore, annealing is performed at a temperature of about 500 ° C. to 650 ° C. in a non-oxidizing atmosphere (for example, nitrogen or argon atmosphere). By this annealing treatment, fluorine introduced into the tungsten film 5 is diffused, and fluorine is segregated in the zirconium silicate film 6 formed at the interface with the silicon substrate 1.

  As described above, the structure as shown in FIG. 1 is manufactured. Thereafter, the transistor is completed through a normal wiring process and the like.

  Thus, in this embodiment, the dielectric constant of the interface region between the metal oxide film, which is a high dielectric film, and the silicon substrate, which is the channel region, is higher than that of the silicon oxide film and the silicon oxynitride film (SiON film). By forming a high metal silicate film, the equivalent silicon oxide film thickness in the interface region can be reduced to 1 nm or less.

  In addition, by adding fluorine in the metal silicate film, the tangling bond existing at the interface with the silicon substrate can be terminated, so the interface state density is lower than that of a normal metal silicate film, Good interface characteristics can be realized.

  Therefore, the effective film thickness of the gate insulating film made of the metal oxide film and the metal silicate film can be made extremely thin, and a high-performance transistor with less leakage current and suppressed short channel effect can be realized. can do.

  In this embodiment, an example using a damascene gate process without a high-temperature heat process after the formation of the gate insulating film is shown. However, a normal transistor forming process in which a polycrystalline silicon film is used as the gate electrode instead of the metal gate electrode. Even if is used, the same effect can be obtained.

  Further, in this embodiment, a stacked structure of a metal oxide film and a metal silicate film is used for the gate insulating film. However, a single layer film of a metal silicate film is used, and fluorine is contained in the metal silicate film. You may do it.

(Embodiment 1 (B))
FIG. 5 is a cross-sectional view showing a configuration example of the semiconductor device according to Embodiment 1 (B) of the present invention. The basic structure is similar to that of Embodiment 1 (A) shown in FIG. 1, and the same reference numerals are assigned to the components corresponding to the components shown in FIG.

  The thickness of the zirconium silicate film 6 is about 1.5 nm, the thickness of the zirconium oxide film 3 is about 3 nm, and the equivalent silicon oxide film thickness is about 0.5 nm. The film thickness is about 1 nm. A very small amount of nitrogen is contained in the zirconium silicate film 6 between the gate electrode and the silicon substrate 1. The width of the gate electrode is about 50 nm.

The amount of nitrogen contained in the zirconium silicate film 6 is preferably 1 × 10 ¹⁴ cm ⁻² to 1 × 10 ¹⁵ cm ⁻² when the total number of atoms is converted into the surface density. In particular, it is desirable to have a concentration peak near the interface with the silicon substrate 1.

  Instead of the zirconium silicate film 6 and the zirconium oxide film 3, various metal silicate films and metal oxide films can be used as in the first embodiment (A).

  Next, with reference to FIGS. 6A to 7D, a method for manufacturing a semiconductor device according to the present embodiment will be described. In addition, since it is the same as that of Embodiment 1 (A) until the middle process (process to FIG.4 (g)), the subsequent process is demonstrated here.

  After the step shown in FIG. 4G, a silicon oxynitride film 18 having a thickness of about 0.7 nm is formed on the exposed surface of the silicon substrate 1 as shown in FIG. 6A.

Next, as shown in FIG. 6B, a zirconium oxide film 19 having a thickness of about 1 nm is deposited by LPCVD using zirconium chloride (ZrCl ₄ ) and O ₂ or H ₂ O.

  Subsequently, as shown in FIG. 7C, the zirconium silicate film 6 containing nitrogen having a thickness of about 1.5 nm is formed only on the bottom surface of the groove by annealing at 800 ° C. for 30 seconds. It is formed.

Next, as shown in FIG. 7 (d), zirconium having a film thickness of about 3 nm is formed by LPCVD using zirconium chloride (ZrCl ₄ ) and oxidizing agents O _2, N ₂ O, NO or H ₂ O. An oxide film 3 is deposited. Subsequently, annealing is performed in an ozone atmosphere at 400 ° C. for 3 minutes to compensate for oxygen defects in the zirconium oxide film 3 existing immediately after the film formation.

  Thereafter, a titanium nitride film 4 having a thickness of 10 nm and a tungsten film 5 having a thickness of 100 nm are deposited on the entire surface, and further planarized using a CMP method. In this way, a structure as shown in FIG. 5 is produced. Thereafter, the transistor is completed through a normal wiring process and the like.

  As described above, in this embodiment as well, in the same manner as in the first embodiment (A), by forming the metal silicate film in the interface region between the metal oxide film and the silicon substrate, the silicon oxide film equivalent in the interface region is converted. The film thickness can be made 1 nm or less.

  Moreover, the dielectric constant of the metal silicate film itself can be increased by adding nitrogen to the metal silicate film. As a result, the effective thickness of the gate insulating film is reduced, and the performance of the transistor can be improved. In addition, by adding nitrogen to the metal silicate film, an oxidation reaction at the metal silicate film / silicon interface by an oxidant is performed in annealing in an oxidizing atmosphere to compensate for oxygen vacancies in the metal oxide film. Can be suppressed. As a result, the effective thickness of the gate insulating film can be reduced, and an increase in the interface state in the low-temperature oxidation process can be suppressed to a low level, so that favorable interface characteristics can be realized.

  Therefore, the effective film thickness of the gate insulating film made of the metal oxide film and the metal silicate film can be made extremely thin, and a high-performance transistor with less leakage current and suppressed short channel effect can be realized. can do.

  In this embodiment, a stacked structure of a metal oxide film and a metal silicate film is used for the gate insulating film. However, a single layer film of a metal silicate film is used, and nitrogen is contained in the metal silicate film. You may do it. Further, the present invention is not limited to the damascene gate process, and can be used for a normal transistor formation process.

(Embodiment 2)
Hereinafter, a second embodiment of the present invention will be described with reference to the drawings. In addition, about drawing, since what was used for description of 1st Embodiment can be used, it demonstrates using those drawings.

(Embodiment 2 (A))
FIG. 1 is a cross-sectional view illustrating a configuration example of a semiconductor device according to Embodiment 2A of the present invention.

  A metal silicate film (metal silicate film, here a zirconium silicate film) 6 and a metal oxide film 3 (here a tantalum oxide film) are formed on the silicon substrate 1 as a gate insulating film. On the material film 3, a titanium nitride film 4 and a tungsten film 5 are formed as gate electrodes.

  The film thickness of the zirconium silicate film 6 is about 1.5 nm, the film thickness of the tantalum oxide film 3 is about 3 nm, and the equivalent silicon oxide film thickness is about 0.5 nm. The film thickness is about 1 nm. The width of the gate electrode is about 50 nm.

  The metal silicate film 6 may be a zirconium silicate film, a hafnium silicate film, a lanthanium silicate film, a gadolinium silicate film, an yttrium silicate film, an aluminum silicate film, or a titanium silicate film. Good. Alternatively, a metal silicate film containing two or more of these metal elements may be used.

  In addition to the tantalum oxide film, the metal oxide film 3 includes a titanium oxide film, a lanthanum oxide film, a hafnium oxide film, a zirconium oxide film, a gadolinium oxide film, an yttrium oxide film, and an aluminum oxide. A membrane may be used. Alternatively, a metal oxide film containing two or more of these metal elements may be used.

  Next, with reference to FIGS. 2A to 4H, a method for manufacturing the semiconductor device according to the present embodiment will be described.

  First, as shown in FIG. 2A, a silicon oxide film 7 having a thickness of 3 nm is formed by thermal oxidation on the surface of the silicon substrate 1 on which an element isolation region (not shown) is formed by the STI technique. Subsequently, a polysilicon film 8 having a thickness of 50 nm and a silicon nitride film 9 having a thickness of 30 nm are deposited using the LPCVD method.

  Next, as shown in FIG. 2B, the silicon nitride film 9 and the polysilicon film 8 are selectively removed using a lithography technique and an RIE method, and a dummy gate pattern 10 is formed in a region where a gate electrode is to be formed. Form.

Next, as shown in FIG. 2C, a silicon oxide film 11 is formed on the sidewalls of the polysilicon film 8 by thermal oxidation at 1000.degree. Thereafter, for example, As ions are implanted under the conditions of an acceleration voltage of 15 keV and a dose of 5 × 10 ¹⁴ cm ⁻² to form the source / drain extension regions 12 in a self-aligned manner with respect to the gate electrode.

  Next, as shown in FIG. 3D, after performing RTA at 800 ° C. for 10 seconds, for example, a silicon nitride film 13 having a thickness of 10 nm and a silicon oxide film 14 having a thickness of 50 nm are formed on the entire surface by LPCVD. Use to deposit. Thereafter, etch back is performed to form sidewalls of the silicon oxide film 14.

Next, as shown in FIG. 3E, for example, As ions are implanted under the conditions of an acceleration voltage of 35 keV and a dose of 5 × 10 ¹⁵ cm ⁻² , and subsequently, RTA is performed at 1035 ° C. for 10 seconds. Then, the source / drain diffusion layer 15 is formed.

  Next, as shown in FIG. 3F, a 100 nm-thickness silicon oxide film 16 is deposited on the entire surface, followed by planarization using a CMP method to expose the upper portion of the dummy gate pattern 10. .

  Next, as shown in FIG. 4G, the silicon nitride film 9 is removed using hot phosphoric acid, and then the polysilicon film 8 is removed using dry etching. Further, channel ion implantation and activation annealing for threshold adjustment are performed. Thereafter, the silicon oxide film 7 is removed using a dilute hydrofluoric acid solution to expose the surface of the silicon substrate 1 serving as a channel region.

Next, as shown in FIG. 4 (h), tetra-tertiary-butoxy zirconium _{(Zr (t-OC 4 H} 9) 4), tetraethoxysilane _{(TEOS, Si (OC 2 H} 5) 4) and, O ₂ Alternatively, a zirconium silicate film 6 having a thickness of about 1.5 nm is deposited by LPCVD using H ₂ O. Subsequently, after annealing at 800 ° C. for 30 seconds, tantalum having a film thickness of about 3 nm at a temperature of 600 ° C. by LPCVD using pentaethoxy tantalum (Ta (OC ₂ H ₅ ) ₅ ) and O _2. An oxide film 3 is deposited.

  Next, as shown in FIG. 4I, a titanium nitride film 4 having a thickness of 10 nm and a tungsten film 5 having a thickness of 100 nm are deposited on the entire surface, and further planarized using a CMP method.

  As described above, the structure as shown in FIG. 1 is manufactured. Thereafter, the transistor is completed through a normal wiring process and the like. Since the wiring process is usually performed at 500 ° C. or lower, the tantalum oxide film 3 maintains an amorphous state.

  Thus, in this embodiment, the dielectric constant of the interface region between the metal oxide film, which is a high dielectric film, and the silicon substrate, which is the channel region, is higher than that of the silicon oxide film and the silicon oxynitride film (SiON film). By forming a metal silicate film having a high thickness, the equivalent silicon oxide film thickness in the interface region can be reduced to 1 nm or less, and good interface characteristics can be realized.

  Therefore, the effective film thickness of the gate insulating film made of the metal oxide film and the metal silicate film can be made extremely thin, and a high-performance transistor with less leakage current and suppressed short channel effect can be realized. can do.

  Further, instead of forming a metal silicate film at the interface between the silicon substrate and the metal oxide film by heat treatment after forming the metal oxide film as in the prior art, in this embodiment, the metal silicate film is deposited. Then, since the metal oxide film is deposited, the main constituent metal element of the metal oxide film can be made different from the main constituent metal element of the metal silicate film. Therefore, it is possible to obtain good interface characteristics with a stable metal silicate film and to form a metal oxide film having a high dielectric constant on the metal silicate film.

  In addition, after depositing the metal silicate film, heat treatment is performed at a temperature lower than the crystallization temperature of the metal silicate film and higher than the crystallization temperature of the metal oxide film, and then depositing the metal oxide film. Thus, both the metal oxide film and the metal silicate film can be made amorphous. Therefore, local variation in effective film thickness due to the dependence of dielectric constant on crystal plane orientation is reduced, and a transistor with excellent reliability with little variation in threshold voltage and the like can be obtained.

  Also in this embodiment, as in the first embodiment, at least one of fluorine and nitrogen may be added to the metal silicate film. Further, the present invention is not limited to the damascene gate process, and can be used for a normal transistor formation process. However, in this case, the metal oxide film may be crystallized.

(Embodiment 2 (B))
FIG. 5 is a cross-sectional view showing a configuration example of a semiconductor device according to Embodiment 2 (B) of the present invention. The basic structure is similar to that of Embodiment 2 (A) shown in FIG. 1, and the same reference numerals are assigned to the components corresponding to the components shown in FIG.

  In this embodiment, a zirconium oxide film is used as the metal oxide film 3, and a zirconium silicate film is used as the metal silicate film 6. The thickness of the zirconium silicate film 6 is about 1.5 nm, the thickness of the zirconium oxide film 3 is about 3 nm, and the equivalent silicon oxide film thickness is about 0.5 nm. The film thickness is about 1 nm. The width of the gate electrode is about 50 nm.

  Instead of the zirconium silicate film 6 and the zirconium oxide film 3, various metal silicate films and metal oxide films can be used as in the second embodiment (A).

  Next, with reference to FIGS. 6A to 7D, a method for manufacturing a semiconductor device according to the present embodiment will be described. In addition, since it is the same as that of Embodiment 2 (A) until the process on the way (process to FIG.4 (g)), the subsequent process is demonstrated here.

  After the step shown in FIG. 4G, a silicon oxynitride film 18 having a thickness of about 0.7 nm is formed on the exposed surface of the silicon substrate 1 as shown in FIG. 6A.

Next, as shown in FIG. 6B, the film thickness of about 1 nm is obtained by LPCVD using tetratertiarybutoxyzirconium (Zr (t-OC ₄ H ₉ ) ₄ ) and O ₂ or H ₂ O. A zirconium oxide film 19 is deposited.

  Subsequently, as shown in FIG. 7C, annealing is performed under the conditions of 800 ° C. and 30 seconds to form a zirconium silicate film 6 having a thickness of about 1.5 nm only on the bottom surface of the groove.

Next, as shown in FIG. 7D, a film having a thickness of about 3 nm is formed by LPCVD using tetratertiarybutoxyzirconium (Zr (t-OC ₄ H ₉ ) ₄ ) and O ₂ or H ₂ O. A zirconium oxide film 3 is deposited.

  Thereafter, a titanium nitride film 4 having a thickness of 10 nm and a tungsten film 5 having a thickness of 100 nm are deposited on the entire surface, and further planarized using a CMP method. In this way, a structure as shown in FIG. 5 is produced. Thereafter, the transistor is completed through a normal wiring process and the like. Since the wiring process is normally performed at 500 ° C. or lower, the zirconium oxide film 3 maintains an amorphous state.

  Thus, also in this embodiment, as in Embodiment 2 (A), by forming a metal silicate film in the interface region between the metal oxide film and the silicon substrate, conversion to a silicon oxide film in the interface region The film thickness can be reduced to 1 nm or less, and good interface characteristics can be realized.

  Therefore, the effective film thickness of the gate insulating film made of the metal oxide film and the metal silicate film can be made extremely thin, and a high-performance transistor with less leakage current and suppressed short channel effect can be realized. can do.

  In addition, since both the metal oxide film and the metal silicate film can be made amorphous, variation in local effective film thickness due to the crystal plane orientation dependence of the dielectric constant is reduced, and the threshold voltage is reduced. Thus, it is possible to obtain a transistor with excellent reliability with little variation.

  Also in this embodiment, as in the first embodiment, at least one of fluorine and nitrogen may be added to the metal silicate film. Further, the present invention is not limited to the damascene gate process, and can be used for a normal transistor formation process. However, in this case, the metal oxide film may be crystallized.

(Embodiment 3)
Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

(Embodiment 3 (A))
8A to 10H are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 3A of the present invention.

  First, as shown in FIG. 8A, As ions are implanted into the silicon substrate 101, followed by thermal diffusion, thereby forming an N-type region 102 having a depth of about 1 μm.

  Next, as shown in FIG. 8B, a silicon oxide film having a thickness of about 600 nm is buried in a predetermined region, thereby forming an element isolation region 103 having an STI structure.

  Next, as shown in FIG. 8C, a protective oxide film 104 having a thickness of about 10 nm is formed. Subsequently, impurity ions 105 for adjusting the threshold voltage of the transistor are implanted.

Next, after removing the protective oxide film 104, a silicon oxynitride film (SiON film) 106 having a thickness of about 1 nm is formed as shown in FIG. Subsequently, a metal oxide film (high dielectric film) 107 made of GdO _x with a film thickness of several nm is formed by CVD or the like. A metal oxide film formed by a CVD method or the like is generally a sparse film having a different stoichiometric composition. Therefore, an oxidation treatment (heat treatment) is performed to bring the metal oxide film 107 close to the stoichiometric composition. In this oxidation treatment, silicon on the surface of the silicon substrate 101 is not oxidized, and only the metal oxide film 107 is selectively oxidized. Therefore, heat treatment is performed in an atmosphere containing two kinds of gases having different oxidizing powers. Specifically, heat treatment is performed in an atmosphere containing water vapor (H ₂ O) as an oxidizing agent and hydrogen (H ₂ ) as a reducing agent.

  FIG. 11 is an equilibrium hydrogen / water vapor partial pressure curve in the oxidation of silicon and gadolinium. Since the standard free energy of the silicon oxide film and the metal oxide film is different, by appropriately selecting the partial pressure ratio of hydrogen and water vapor, it is oxidizing to the metal oxide film and to the silicon oxide film A reducing atmosphere can be formed. According to the thermodynamic calculation based on Gibbs free energy, silicon is not oxidized but only gadolinium can be oxidized by performing heat treatment in the region shown by hatching in FIG.

By performing the heat treatment under the conditions as described above, only GdO _x can be brought close to the stoichiometric composition without forming a silicon oxide film in the interface region, and a dense metal oxide film 107 can be obtained. Is possible. Therefore, it is possible to obtain a gate insulating film having excellent characteristics with little leakage current without increasing the physical thickness of the gate insulating film. When silicon oxide is formed on the surface of the silicon substrate, this silicon oxide can be reduced by the above heat treatment.

  Next, as shown in FIG. 9E, a polycrystalline silicon film 108 having a film thickness of 150 nm is deposited by using a CVD method or the like. Subsequently, the polycrystalline silicon film 108 is etched using the photoresist as a mask to obtain a desired gate shape.

Next, as shown in FIG. 9F, ion implantation of BF ₂ is performed with an acceleration voltage of 10 keV and a dose of 5 × 10 ¹⁴ cm ^{−2 using} the gate electrode (polycrystalline silicon film 108) as a mask. A drain extension region 109 (LDD region) is formed. The extension region 109 has an effect of relaxing the pn junction electric field and suppressing the generation of hot electrons.

Next, as shown in FIG. 10G, a silicon oxide film (SiO ₂ film) having a film thickness of about 10 nm to be the liner layer 110 is deposited by LP-CVD or the like. Subsequently, a silicon nitride film (SiN film) 111 having a thickness of about 50 nm is deposited by LP-CVD or the like.

Next, as shown in FIG. 10H, the SiN film 111 is etched by the RIE method, leaving the SiN film 111 only on the gate sidewall. The liner layer 110 serves as an etching stopper when performing RIE. Thereafter, B ions are implanted at an acceleration voltage of 5 keV and a dose of 5 × 10 ¹⁵ cm ⁻² in order to form a source / drain high-concentration diffusion layer. Further, activation annealing is performed at 1000 ° C. for about 10 seconds. Thereafter, an interlayer insulating film, a contact, an upper wiring, and the like are formed.

(Embodiment 3 (B))
12A to 13F are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 3B of the present invention.

  First, as in Embodiment Mode 3 (A), the element isolation region 122 is formed in the silicon substrate 121. Thereafter, as shown in FIG. 12A, a dummy gate 123 is formed in a region where a gate is to be formed in the future. The dummy gate 123 may have any structure as long as the etching selectivity with respect to the interlayer insulating film can be obtained. In this embodiment, the dummy gate 123 is formed as follows. First, a thermal oxide film 124 (silicon oxide film) having a film thickness of several nm is formed, and a polycrystalline silicon film 125 and a silicon nitride film (SiN film) 126 are formed by CVD. Subsequently, the SiN film 126 is processed into a desired shape using the photoresist as a mask. After removing the photoresist, the polysilicon film 125 and the thermal oxide film 124 are etched using the SiN film 126 as a mask to form a dummy gate 123.

Next, as shown in FIG. 12B, ion implantation of B is performed with an acceleration voltage of 5 keV and a dose of 5 × 10 ¹⁵ cm ^{−2 using} the dummy gate 123 as a mask, and a high-concentration source / drain diffusion layer 127. Form.

  Next, as shown in FIG. 12C, an interlayer insulating film 128 is deposited by the CVD method. Further, planarization is performed by CMP to expose the upper surface of the dummy gate 123.

  Next, as shown in FIG. 13D, the exposed dummy gate 123 is removed by wet etching or dry etching.

Next, after pretreatment such as dilute hydrofluoric acid treatment, as shown in FIG. 13E, a silicon oxynitride film 129 having a thickness of about 1 nm is formed by oxynitridation or the like. Further, a metal oxide film 130 made of GdO _x with a film thickness of several nm is formed by CVD or the like. Subsequently, similarly to Embodiment 3 (A), heat treatment is performed in an atmosphere containing two kinds of gases having different oxidizing powers, specifically, an atmosphere containing water vapor and hydrogen. As a result, as in Embodiment 3A, the silicon on the surface of the silicon substrate 121 is not oxidized, and only the metal oxide film 130 is selectively oxidized. As a result, only the GdO _x can be brought close to the stoichiometric composition without forming a silicon oxide film in the interface region, and a dense metal oxide film 130 can be obtained. Therefore, it is possible to obtain a gate insulating film having excellent characteristics with little leakage current without increasing the physical thickness of the gate insulating film.

  Next, as shown in FIG. 13F, a gate electrode 131 is formed by depositing a gate electrode material such as aluminum by a CVD method and then performing planarization by a CMP method. Thereafter, contacts, upper wirings and the like are formed.

  Although the third embodiment has been described above, the following modifications are possible in this embodiment.

  In the above-described embodiment, an atmosphere containing water vapor and hydrogen has been described as an example of an atmosphere containing two kinds of gases having different oxidizing powers. However, an atmosphere containing carbon monoxide (CO) and carbon dioxide (CO) is used. May be used for heat treatment. In this case, carbon dioxide functions as an oxidizing agent, and carbon monoxide functions as a reducing agent.

  In the above-described embodiment, the laminated structure of the silicon oxynitride film and the metal oxide film is described as an example of the gate insulating film, but a metal silicate film may be used instead of the metal oxide film. Alternatively, a single layer film of a metal oxide film or a metal silicate film may be used as the gate insulating film. Furthermore, a laminated structure in which a metal oxide film is formed on the metal silicate film may be used. Also in these cases, a dense metal oxide film or metal silicate film can be obtained by performing heat treatment in an atmosphere containing two types of gases having different oxidizing powers.

  In the above-described embodiment, gadolinium is described as an example of the metal element contained in the metal oxide film. However, in the metal oxide film or the metal silicate film, zirconium, gadolinium, hafnium, lanthanum, yttrium, aluminum, It is sufficient that at least one metal element in titanium is contained.

(Embodiment 4)
Hereinafter, a fourth embodiment of the present invention will be described with reference to the drawings.

(Embodiment 4 (A))
14A to 14C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 4A of the present invention.

First, as shown in FIG. 14A, an element isolation region 202 is formed in a silicon substrate 201. Subsequently, a silicon oxide film 203 having a thickness of about 2 nm is formed by a dry oxidation method or a wet oxidation method. Further, a zirconium film having a thickness of about 100 nm is formed as the metal film 204 by plating or sputtering. When the plating method is used, after forming a zirconium seed layer, the zirconium film 204 is formed by performing electrolysis in an aqueous solution of zirconium sulfate (Zr (SO ₄ ) ₂ .4H ₂ O). By using the plating method, the zirconium film 204 can be formed with good controllability and productivity.

  Next, as shown in FIG. 14B, heat treatment is performed in an inert atmosphere under conditions that do not cause crystallization. By performing the heat treatment, a redox reaction and interdiffusion occur at the interface between the silicon oxide film 203 and the zirconium film 204, and a zirconium silicate film 205 having a thickness of about 4 nm (about 1 nm equivalent to a silicon oxide film thickness) is formed. The Zirconium is known to have an oxidation film formed on the surface by a slight amount of oxygen and exhibit strong oxidation resistance (for example, the first ionization potential ΔE of copper is about 7.73 (eV), whereas Zirconium is about 6.84 (eV)). Therefore, the surface of the zirconium film 204 is easily oxidized in the air, and a zirconium oxide film 206 is formed.

  When the surface of the zirconium film 204 is oxidized to some extent, the oxidation does not proceed any more, and the inside of the zirconium film 204 is kept in a metallic state in the heat treatment under a mild condition. Therefore, zirconium remaining inside may be used as an electrode as it is. Alternatively, the zirconium oxide film 206 may be removed with sulfuric acid or hydrofluoric acid, the zirconium film 204 may be further removed with hydrogen peroxide solution, and a new metal film may be formed on the remaining zirconium silicate film 205. In the present embodiment, a case where the zirconium film 204 is used as it is without peeling off will be described.

  After the zirconium silicate film 205 is formed, as shown in FIG. 14C, a silicon nitride film (SiN film) 207 which is a cap insulating film having a thickness of about 200 nm is formed on the entire surface. Thereafter, the silicon nitride film 207, the zirconium film 204, and the like are patterned into the shape of the gate electrode. Subsequently, impurities are ion-implanted using the gate electrode as a mask, and the implanted impurities are activated to form the source / drain diffusion layer 211.

  Thereafter, a SiN film 208 serving as a spacer is formed, and the substrate surface is exposed by RIE. Subsequently, a liner SiN film 209 serving as a barrier during BPSG film formation and a stopper during RIE is formed to a thickness of about 15 nm. Subsequently, a BPSG film 210 is formed, and the BPSG film 210 is further densified in a wet oxidation atmosphere at 800 ° C. for 30 minutes. Thereafter, the BPSG film 210 is planarized by the CMP method using the SiN films 207 to 209 as stoppers, thereby completing the transistor.

  As described above, according to the present embodiment, a zirconium film is formed on a silicon oxide film, and a silicon silicate film is formed by reacting the silicon oxide film and the zirconium film by heat treatment, so that the dielectric constant having excellent film quality is achieved. High zirconium silicate film can be used as the gate insulating film, and the zirconium film remaining after the heat treatment can be used as the gate electrode as it is, so that the manufacturing process can be simplified and the productivity can be improved.

(Embodiment 4 (B))
FIGS. 15A to 16E are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 4B of the present invention. In this embodiment, the method described in Embodiment 4 (A) is applied to form a dual metal transistor using different kinds of metals for the gate electrode. In addition, the same reference number is attached | subjected about the component corresponding to the component of Embodiment 4 (A) shown to Fig.14 (a)-FIG.14 (c).

  First, a zirconium film 204 is formed on a silicon oxide film (not shown) by a process similar to that in Embodiment 4 (A), and further, the silicon oxide film and the zirconium film 204 are reacted by heat treatment, whereby FIG. As shown in (a), a zirconium silicate film 205 is formed.

  Next, as shown in FIG. 15B, a part of the zirconium film 204 is removed. Specifically, a resist pattern is formed on a region where the zirconium film 204 is left, and the zirconium oxide film 206 is removed with sulfuric acid or hydrofluoric acid using the resist pattern as a mask. 204 is removed. Thereafter, an yttrium film 212 having a thickness of 100 nm is formed on the entire surface as a metal film other than zirconium.

  Next, as shown in FIG. 15C, planarization is performed by a CMP method. By taking out the substrate into the atmosphere, a zirconium oxide film 206 is formed on the surface of the zirconium film 204, and an yttrium oxide film 213 is formed on the surface of the yttrium film 212. The first ionization potential ΔE of yttrium is about 6.38, and is easily oxidized in the air like zirconium.

  Next, as shown in FIG. 16D, a silicon nitride film 207 as a cap insulating film is formed to a thickness of 200 nm. Thereafter, the silicon nitride film 207, the zirconium film 204, the yttrium film 212, and the like are patterned into the shape of the gate electrode.

  Thereafter, in the same manner as in the embodiment 4 (A), the source / drain diffusion layer 211, the spacer SiN film 208, the liner SiN film 209, the BPSG film 210, and the like are formed. A transistor having a structure as shown in FIG. Complete.

  In this embodiment, when manufacturing a dual metal transistor, a metal silicate film having excellent film quality and high dielectric constant can be used as a gate insulating film, as in Embodiment 4 (A), and the manufacturing process can be simplified. Productivity can be improved.

(Embodiment 4 (C))
FIGS. 17A to 17E are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 4C of the present invention. In this embodiment, the method described in Embodiment 4 (A) is applied to form a dual metal transistor using different kinds of metals for the gate electrode. In addition, the same reference number is attached | subjected about the component corresponding to the component of Embodiment 4 (A) shown to Fig.14 (a)-FIG.14 (c).

  First, as shown in FIG. 17A, the zirconium film 204 is formed on the silicon oxide film 203 and the zirconium oxide film 206 is formed on the zirconium film 204 by the same process as that in Embodiment 4A. To do.

  Next, as shown in FIG. 17B, a part of the zirconium film 204 is removed. Specifically, a resist pattern is formed on a region where the zirconium film 204 is left, and the zirconium oxide film 206 is removed with sulfuric acid or hydrofluoric acid using the resist pattern as a mask. 204 is removed. Thereafter, an yttrium film 212 having a thickness of 100 nm is formed on the entire surface as a metal film other than zirconium.

  Next, as shown in FIG. 17C, planarization is performed by a CMP method. Thereafter, heat treatment is performed in an inert atmosphere under conditions that do not cause crystallization. By performing the heat treatment, an oxidation-reduction reaction and mutual diffusion occur at the interface between the silicon oxide film 203 and the zirconium film 204 and the interface between the silicon oxide film 203 and the yttrium film 212, and each has a thickness of about 4 nm (silicon oxide film A zirconium silicate film 205 and an yttrium silicate film 214 having a conversion film thickness of about 1 nm are formed. Further, by removing the substrate into the atmosphere, a zirconium oxide film 206 is formed on the surface of the zirconium film 204, and an yttrium oxide film 213 is formed on the surface of the yttrium film 212.

  Next, as shown in FIG. 18D, a silicon nitride film 207 as a cap insulating film is formed to a thickness of 200 nm. Thereafter, the silicon nitride film 207, the zirconium film 204, the yttrium film 212, and the like are patterned into the shape of the gate electrode.

  Thereafter, in the same manner as in the embodiment 4 (A), the source / drain diffusion layer 211, the spacer SiN film 208, the liner SiN film 209, the BPSG film 210, and the like are formed. A transistor having a structure as shown in FIG. Complete.

  Also in this embodiment, in manufacturing a dual metal transistor, a metal silicate film having excellent film quality and high dielectric constant can be used as a gate insulating film as in the case of Embodiment 4 (A) and Embodiment 4 (B). It is possible to simplify the manufacturing process and improve productivity.

  In Embodiments 4 (A) to 4 (C) described above, zirconium and yttrium have been described as examples of the metal element contained in the metal silicate film. However, the metal silicate film includes zirconium, gadolinium, It is sufficient that at least one metal element selected from hafnium, lanthanum, yttrium, aluminum, and titanium is included.

  In the above-described Embodiments 4 (A) to 4 (C), an example in which a single-layer silicon metal silicate film is used as the gate insulating film has been described. However, a metal oxide film is formed on the metal silicate film. The formed laminated structure may be sufficient. In this case, after the metal silicate film is formed by heat treatment, the unreacted metal film on the metal silicate film is removed, and then the metal oxide film is formed. The metal oxide film may be a film containing at least one of the various metal elements described above, a tantalum oxide film, a bismuth / strontium / titanium oxide film (BSTO), or the like.

  In the above-described Embodiments 4 (A) to 4 (C), the metal film is formed on the silicon oxide film. However, the present invention is not limited to the silicon oxide film, and any silicon oxide-based insulating film may be used. A metal film may be formed on the silicon oxynitride film (SiON film).

  Furthermore, the metal used for the gate electrode can be variously modified. For example, a tungsten film may be used, and a laminated structure of a TiN film and a tungsten film as a barrier metal may be used.

(Embodiment 5)
Hereinafter, a fifth embodiment of the present invention will be described with reference to the drawings.

(Embodiment 5 (A))
FIG. 19A to FIG. 19C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 5A of the present invention.

First, as shown in FIG. 19A, an extremely thin silicon oxide film (SiO ₂ film) 302 having a thickness of 1 nm or less is formed on a silicon substrate 301. Subsequently, part of the silicon oxide film 302 is selectively removed to form a region where the silicon oxide film 302 exists and a region where the silicon oxide film 302 does not exist on the silicon substrate 301. Thereafter, a metal oxide film 303 containing a metal such as La, Hf, Zr, or Gd is deposited on the entire surface.

  Next, as shown in FIG. 19B, heat treatment is performed on the substrate having the above-described structure. By appropriately selecting the conditions for this heat treatment, the metal oxide film 303 reacts with the silicon of the silicon substrate 301 in the region where the silicon oxide film 302 is removed, and a metal silicate film 304 is formed. In the region not removed, the laminated film of the metal oxide film 303 and the silicon oxide film 302 remains.

  Next, as shown in FIG. 19C, an electrode film 305 for a gate electrode made of TiN or the like is formed on the entire surface, and further a silicon oxide film 302, a metal oxide film 303, a metal silicate film 304, and an electrode film. 305 is patterned. In this way, gate electrode structures having different effective film thicknesses of the gate insulating film are formed.

(Embodiment 5 (B))
20A to 20C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 5B of the present invention.

  First, as shown in FIG. 20A, a silicon oxide film 302 and a metal oxide film 303 are formed on a silicon substrate 301 in the same manner as in the embodiment 5A.

  Next, as shown in FIG. 20B, heat treatment is performed on the substrate having the above-described structure. By appropriately selecting the conditions for this heat treatment, for example, by performing heat treatment at a temperature higher than the temperature of the heat treatment performed in Embodiment 5 (A), a region where the silicon oxide film 302 is removed and a region where the silicon oxide film 302 is not removed are obtained. Metal silicate films 306 and 307 having different composition ratios of metal element, oxygen, and silicon can be formed. In the formed metal silicate film, the oxygen concentration of the metal silicate film 307 is higher than that of the metal silicate film 306, and the silicon concentration of the metal silicate film 306 is higher than that of the metal silicate film 307.

  Next, as shown in FIG. 20C, an electrode film 305 is formed in the same manner as in Embodiment 5A, and the metal silicate films 306 and 307 and the electrode film 305 are patterned. In this way, gate electrode structures having different effective film thicknesses of the gate insulating film are formed.

(Embodiment 5 (C))
FIG. 21A to FIG. 21C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 5C of the present invention.

  First, as shown in FIG. 21A, a silicon oxide film 302 and a metal oxide film 303 are formed on a silicon substrate 301 in the same manner as in Embodiment 5A. At this time, the oxygen concentration in the metal oxide film 303 is set lower than the stoichiometric ratio.

  Next, as shown in FIG. 21B, heat treatment is performed on the substrate having the above-described structure. By appropriately selecting the conditions of the heat treatment (heating temperature, heating time), the thickness of the silicon oxide film, the composition ratio of the metal oxide film, etc., the region where the silicon oxide film 302 is removed and the region where it is not removed Different insulating film structures can be obtained. In the region where the silicon oxide film 302 is removed, the metal oxide film 303 reacts with the silicon of the silicon substrate 301 to form a metal silicate film 308 near the surface of the silicon substrate 301. A laminated structure with the material film 303 is formed. In a region where the silicon oxide film 302 is not removed, the metal oxide film 303 and the silicon oxide film 302 react to form a metal oxide film 309 having a composition close to the stoichiometric ratio.

  Next, as shown in FIG. 21C, an electrode film 305 is formed in the same manner as in Embodiment 5A, and the metal silicate film 308, the metal oxide films 303 and 309, and the electrode film 305 are patterned. To do. In this way, gate electrode structures having different effective film thicknesses of the gate insulating film are formed.

(Embodiment 5 (D))
FIG. 22A to FIG. 22C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 5D of the present invention.

  First, as shown in FIG. 22A, a silicon oxide film 302 and a metal oxide film 303 are formed on a silicon substrate 301 in the same manner as in the embodiment 5A. At this time, the oxygen concentration in the metal oxide film 303 is set lower than the stoichiometric ratio.

  Next, as shown in FIG. 22B, heat treatment is performed on the substrate having the above-described structure. By appropriately selecting the conditions of the heat treatment (heating temperature, heating time), the thickness of the silicon oxide film, the composition ratio of the metal oxide film, etc., the region where the silicon oxide film 302 is removed and the region where it is not removed Different insulating film structures can be obtained. In the region where the silicon oxide film 302 is removed, a metal silicate film 310 having a higher silicon composition ratio is formed closer to the surface of the silicon substrate 301. In the region where the silicon oxide film 302 is not removed, a metal oxide film 312 having a composition close to the stoichiometric ratio is formed, and a metal silicate film 311 is formed near the surface of the silicon substrate 301. .

  Next, as shown in FIG. 21C, an electrode film 305 is formed in the same manner as in Embodiment 5A, and the metal silicate films 310 and 311, the metal oxide film 312 and the electrode film 305 are patterned. To do. In this way, gate electrode structures having different effective film thicknesses of the gate insulating film are formed.

(Embodiment 5 (E))
FIG. 23A to FIG. 23C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 5E of the present invention.

  First, as shown in FIG. 23A, a metal oxide film 313 containing a metal such as La, Hf, Zr, or Gd is deposited on the silicon substrate 301. Subsequently, silicon ions are introduced into the metal oxide film 313 by ion implantation using the photoresist 314 as a mask. The ion implantation conditions are such that the range of ions is in the metal oxide film 313. For example, when the thickness of the metal oxide film 313 is about 3 to 5 nm, the acceleration voltage is 0.5 to 5. Set to about 1 keV.

Next, as shown in FIG. 23B, after the photoresist 314 is removed by plasma ashing and wet processing using an oxidizing chemical solution, heat treatment is performed. By this heat treatment, the metal oxide film 313 is converted into a metal silicate film 315 (La ₂ SiO ₅ or the like) in a region where silicon is introduced into the metal oxide film 313. In the region where silicon is not introduced, the metal oxide film 313 is left as it is. Thus, by introducing silicon ions into the metal oxide film 313 in advance, the metal silicate film 315 is formed even if the temperature of the heat treatment is lower than the temperature of the heat treatment performed in Embodiment 5A. Is possible.

  Next, as shown in FIG. 23C, an electrode film 305 is formed in the same manner as in Embodiment 5A, and the metal silicate film 315, the metal oxide film 313, and the electrode film 305 are patterned. In this way, gate electrode structures having different effective film thicknesses of the gate insulating film are formed.

  In the above example, the metal oxide film 313 is directly deposited on the silicon substrate 301. However, a thin silicon oxide film is formed on the silicon substrate 301, and the metal oxide film 313 is formed on the silicon oxide film. It may be deposited. In this case, the structure of the gate insulating film finally obtained is a laminated film of the silicon oxide film and the metal oxide film 313 or the metal silicate film 315 in both the region where the ion implantation is performed and the region where the ion implantation is not performed.

(Embodiment 5 (F))
24A to 24C are process cross-sectional views illustrating a method for manufacturing a semiconductor device according to Embodiment 5F of the present invention.

  First, as shown in FIG. 24A, an extremely thin silicon oxide film 316 having a thickness of 1 nm or less is formed on a silicon substrate 301. Subsequently, a metal oxide film 317 containing a metal such as La, Hf, Zr, or Gd is deposited on the silicon oxide film 316. Subsequently, ion implantation of ions such as Ar and Si is performed using the photoresist 318 as a mask. The ion implantation conditions are such that the ion range is in the silicon oxide film 316. By this ion implantation, the silicon oxide film 316 is intentionally damaged.

  Next, as shown in FIG. 24B, after the photoresist 318 is removed, heat treatment is performed. In the region where the silicon oxide film 316 is damaged by this heat treatment, the metal oxide film 317 and the silicon oxide film 316 react to form a metal silicate film 319, and the silicon oxide film 316 is damaged. In a region that is not, the stacked film of the silicon oxide film 316 and the metal oxide film 317 remains. By damaging the silicon oxide film 316 in advance, the bond between silicon and oxygen is weakened. Therefore, even if the temperature of the heat treatment is lower than the temperature of the heat treatment performed in Embodiment 5A, the metal A silica film 319 can be formed.

  Next, as shown in FIG. 24C, an electrode film 305 is formed in the same manner as in Embodiment 5A, and a metal silicate film 319, a metal oxide film 317, a silicon oxide film 316, and an electrode film are formed. 305 is patterned. In this way, gate electrode structures having different effective film thicknesses of the gate insulating film are formed.

  Thus, according to the fifth embodiment, by using a metal oxide film or a metal silicate film for the gate insulating film, the effective thickness of the gate insulating film can be reduced, and the gate insulating film By varying the structure in a plurality of regions, the effective thickness of the gate insulating film in each region can be varied.

  In the fifth embodiment, the metal oxide film or the metal silicate film includes at least one metal of Al, Sn, Sc, Ti, Sr, Y, Zr, Ba, La, Gd, Hf, and Ta. It only needs to contain an element. However, in an example in which a metal oxide film or a metal silicate film is formed by reaction with a silicon oxide film, Sn and Ta are less reducible than Si, so among the above-described metal elements, metal elements other than Sn and Ta Is preferably used.

  In the fifth embodiment, a silicon oxide film is described as an example of a silicon oxide film-based insulating film formed on a silicon substrate. However, a silicon oxynitride film may be used as the silicon oxide film-based insulating film. .

  As mentioned above, although Embodiment 1-5 of this invention was demonstrated, this invention is not limited to said each embodiment. For example, the structures and manufacturing methods shown in the above embodiments can be appropriately combined. In addition, the present invention can be implemented with various modifications without departing from the spirit of the present invention.

Sectional drawing which showed the 1st example of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 1st example of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 1st example of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 1st example of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention. Sectional drawing which showed the 2nd example of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 2nd example of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 2nd example of the semiconductor device which concerns on the 1st and 2nd embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 1st example of the semiconductor device which concerns on the 3rd Embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 1st example of the semiconductor device which concerns on the 3rd Embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 1st example of the semiconductor device which concerns on the 3rd Embodiment of this invention. The figure which showed the equilibrium hydrogen and water vapor partial pressure curve in the oxidation of silicon and gadolinium concerning the 3rd Embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 2nd example of the semiconductor device which concerns on the 3rd Embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 2nd example of the semiconductor device which concerns on the 3rd Embodiment of this invention. Process sectional drawing which showed the manufacturing process about the 1st example of the semiconductor device which concerns on the 4th Embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 2nd example of the semiconductor device which concerns on the 4th Embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 2nd example of the semiconductor device which concerns on the 4th Embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 3rd example of the semiconductor device which concerns on the 4th Embodiment of this invention. Process sectional drawing which showed a part of the manufacturing process about the 3rd example of the semiconductor device which concerns on the 4th Embodiment of this invention. Process sectional drawing which showed the manufacturing process about the 1st example of the semiconductor device which concerns on the 5th Embodiment of this invention. Process sectional drawing which showed the manufacturing process about the 2nd example of the semiconductor device which concerns on the 5th Embodiment of this invention. Process sectional drawing which showed the manufacturing process about the 3rd example of the semiconductor device which concerns on the 5th Embodiment of this invention. Process sectional drawing which showed the manufacturing process about the 4th example of the semiconductor device which concerns on the 5th Embodiment of this invention. Process sectional drawing which showed the manufacturing process about the 5th example of the semiconductor device which concerns on the 5th Embodiment of this invention. Process sectional drawing which showed the manufacturing process about the 6th example of the semiconductor device which concerns on the 5th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 3, 19 ... Metal oxide film, 4 ... Titanium nitride film, 5 ... Tungsten film, 6 ... Metal silicate film, 7, 11, 14, 16 ... Silicon oxide film, 8 ... Polysilicon film, DESCRIPTION OF SYMBOLS 9, 13 ... Silicon nitride film, 10 ... Dummy gate pattern, 12 ... Extension area | region, 15 ... Source-drain diffused layer, 18 ... Silicon oxynitride film 101, 121 ... Silicon substrate, 102 ... N-type area | region, 103, 122 ... Element isolation region, 104 ... protective oxide film, 105 ... impurity ions, 106, 129 ... silicon oxynitride film, 107, 130 ... metal oxide film, 108, 125 ... polycrystalline silicon film, 109 ... extension region, 110 ... liner Layers 111, 126 ... Silicon nitride film, 123 ... Dummy gate, 124 ... Thermal oxide film, 127 ... High concentration expansion of source / drain Spread layer, 128 ... interlayer insulating film, 131 ... gate electrode 201 ... silicon substrate, 202 ... element isolation region, 203 ... silicon oxide film, 204, 212 ... metal film, 205, 214 ... metal silicate film, 206, 213 ... Metal oxide film, 207, 208, 209 ... Silicon nitride film, 210 ... BPSG film, 211 ... Source / drain diffusion layer 301 ... Silicon substrate, 302, 316 ... Silicon oxide film, 303, 309, 312, 313, 317 ... Metal oxide film, 304, 306, 307, 308, 310, 311, 315, 319 ... Metal silicate film, 305 ... Electrode film, 314, 318 ... Photoresist

Claims (5)

A semiconductor device using a metal oxide film as at least a part of a gate insulating film, wherein an insulating film containing metal, silicon and oxygen is formed between a semiconductor substrate and the metal oxide film, and the metal oxide film things film and the metal, the insulating film is an amorphous film der containing silicon and oxygen is, the a main metal element forming the metal oxide film a metal, and a main metal element constituting the insulating film containing silicon and oxygen A semiconductor device characterized by different . The semiconductor device according to claim 1, wherein at least one of fluorine and nitrogen is added to the insulating film containing metal, silicon, and oxygen. The insulating film containing metal, silicon, and oxygen is a zirconium silicate film, a hafnium silicate film, a lanthanium silicate film, a gadolinium silicate film, an yttrium silicate film, an aluminum silicate film, or a titanium silicate film. The semiconductor device according to claim 1. The metal oxide film is a tantalum oxide film, a titanium oxide film, a lanthanum oxide film, a hafnium oxide film, a zirconium oxide film, a gadolinium oxide film, an yttrium oxide film, or an aluminum oxide film. The semiconductor device according to claim 1.   A method of manufacturing a semiconductor device using a metal oxide film as at least a part of a gate insulating film, comprising: forming an insulating film containing metal, silicon and oxygen on a semiconductor substrate; and Forming a metal oxide film over the insulating film including, after the step of forming the insulating film containing the metal, silicon and oxygen, before the step of forming the metal oxide film, A method for manufacturing a semiconductor device, wherein heat treatment is performed at a temperature lower than a crystallization temperature of an insulating film containing metal, silicon, and oxygen and higher than a crystallization temperature of the metal oxide film.

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