JP4932268B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  2. Description of the Related Art In recent years, attention has been focused on an individual recognition technique in which an ID (individual identification number) is given to an individual object to clarify information such as a history of the object and to be useful for production and management. Among them, development of semiconductor devices capable of transmitting and receiving data without contact is underway. As such a semiconductor device, RFID (Radio Frequency Identification) (ID tag, IC tag, IC chip, RF tag (Radio Frequency), wireless tag, electronic tag, wireless chip), etc. are especially used in the company, market, etc. Has begun to be introduced.

Many of these semiconductor devices have a circuit using a semiconductor substrate such as silicon (Si) (hereinafter also referred to as an IC (Integrated Circuit) chip) and an antenna, and the IC chip is a memory circuit (hereinafter also referred to as a memory). And a control circuit. In addition, organic thin film transistors (hereinafter also referred to as TFTs) using organic compounds for control circuits, memory circuits, and the like, organic memories, and the like have been actively developed (for example, Patent Document 1).
Japanese Unexamined Patent Publication No. 7-22669

However, in a memory circuit using an organic compound in which a memory element is formed by providing an organic compound between a pair of electrodes, current does not flow easily and the drive voltage increases depending on the film thickness of the organic compound layer and the size of the memory circuit. There is a problem of end up.

Therefore, an object of the present invention is to provide a technique capable of manufacturing a memory device and a semiconductor device with higher performance and higher reliability at low cost and with high yield.

    A substance containing an insulating material becomes fluid when the temperature rises to the glass transition temperature of the material. Therefore, an insulating layer made of a substance containing an insulating material becomes a composition having fluidity that does not maintain a certain shape at a temperature equal to or higher than the glass transition temperature, and exhibits a behavior close to a liquid state. When it comes to fluidity, the wettability of the surface of the formation region, which was not significantly affected in the solid state, will affect its shape, which is greatly related to the direction and speed of flow of the composition. .

    The wettability of the solid surface, which is the formation material, is influenced by the chemical properties of the surface. If the material has low wettability with respect to the composition having fluidity, the surface thereof becomes a region having low wettability with respect to the composition having fluidity (hereinafter also referred to as low wettability region), and the flow is reversed. When the substance has high wettability with respect to the composition having the property, the surface thereof becomes a region with high wettability with respect to the composition having the fluidity (hereinafter also referred to as the high wettability region). In the present invention, the wettability of the surface of the region to be formed is formed so that the insulating layer is formed over regions having different wettability when the insulating layer becomes a glass transition temperature or higher after voltage application and changes to a fluid composition. Are controlled by materials and processing.

    A region having different wettability is a region having a difference in wettability with respect to a composition having fluidity, and a contact angle of the composition having fluidity is different. A region with a large contact angle of a composition having fluidity is a region with lower wettability (hereinafter also referred to as a low wettability region), and a region with a small contact angle is a region with high wettability (hereinafter referred to as a high wettability region). Say). When the contact angle is large, the composition having fluidity does not spread on the surface of the region and repels the composition, so that the surface is not wetted, but when the contact angle is small, the composition having fluidity spreads on the surface. This is because the surface is often wetted. Therefore, regions having different wettability also have different surface energies. The surface energy of the surface in the region with low wettability is small, and the surface energy at the surface of the region with high wettability is large.

    In the present invention, an insulating layer (also referred to as a memory layer) included in a memory element included in a memory device is formed so as to cover or be in contact with the first conductive layer and an end portion of the first conductive layer. In contact with a partition wall (insulating layer). When a voltage is applied between the first conductive layer and the second conductive layer, current flows through the insulating layer to generate heat. Then, when the temperature of the insulating layer rises to the glass transition temperature and becomes a composition having fluidity, the wettability to the composition having fluidity is higher than the partition wall (insulating layer) from the surface of the first conductive layer. ) Make sure that the surface is higher. Since the composition having fluidity moves to the higher wettability, the composition having fluidity flows to the partition wall (insulating layer) having high wettability without maintaining the solid state shape. Therefore, the thickness of the insulating layer becomes nonuniform, the insulating layer is deformed, and the first conductive layer and the second conductive layer are short-circuited. In some cases, the electric field concentrates on a thin region of the insulating layer, causing a dielectric breakdown to cause a short circuit between the first conductive layer and the second conductive layer. Therefore, the conductivity of the memory element before and after voltage application changes.

Note that in this specification, a memory layer included in a memory element called an insulating layer shows insulating properties in a bulk state, but a small amount of current flows in a thin film state. In this specification, a memory layer having a slight conductivity depending on the shape is called an insulating layer instead of such a complete insulator.

  Note that in this specification, a semiconductor device refers to a device that can function by utilizing semiconductor characteristics. A semiconductor device such as a chip having a processor circuit (hereinafter also referred to as a processor chip) can be manufactured by using the present invention.

    According to one embodiment of the semiconductor device of the present invention, a first conductive layer, a first insulating layer in contact with a side end portion of the first conductive layer, a second conductive layer on the first conductive layer and the first insulating layer The second insulating layer has an insulating layer and a second conductive layer on the second insulating layer, and the second insulating layer is formed of an insulating material, and wettability to a fluidized material when the insulating material is fluidized. Is higher in the first insulating layer than in the first conductive layer.

    In one embodiment of the method for manufacturing a semiconductor device of the present invention, a first conductive layer is formed, a first insulating layer is formed in contact with a side end portion of the first conductive layer, and the first conductive layer and the first conductive layer are formed. A second insulating layer is formed on the insulating layer, a second conductive layer is formed on the second insulating layer, the second insulating layer is formed of an insulating material, and the insulating material is The wettability to the fluidized material when fluidized is higher in the first insulating layer than in the first conductive layer.

    According to one method for manufacturing a semiconductor device of the present invention, a first conductive layer having a liquid repellent layer is formed, a first insulating layer is formed in contact with a side end portion of the first conductive layer, A second insulating layer is formed over the conductive layer and the first insulating layer, and a second conductive layer is formed over the second insulating layer.

According to the present invention, a semiconductor device with higher performance and higher reliability, and the semiconductor device can be manufactured at low cost with high yield.

  Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in structures of the present invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

(Embodiment 1)
In this embodiment, an example of a structure of a memory element included in the memory device of the present invention will be described with reference to drawings. More specifically, the case where the structure of the memory device is a passive matrix type will be described.

    The memory element and its operation mechanism of the present invention will be described with reference to FIG. In FIG. 1, a partition wall (insulating layer) 51 a and a partition wall (insulating layer) 51 b are provided so as to cover an end portion of the first conductive layer 50. The partition wall (insulating layer) 51a and the partition wall (insulating layer) 51b also function as partition walls that separate other memory elements. An insulating layer 52 that is an insulating layer is formed over the partition wall (insulating layer) 51 a, the partition wall (insulating layer) 51 b, and the first conductive layer 50, and the second conductive layer 53 is formed over the insulating layer 52.

    For the material of the first conductive layer 50 and the second conductive layer 53, a highly conductive element or compound is used. In this embodiment, a material whose crystal state, conductivity, and shape are changed by an electric action or an optical action is used as the material of the insulating layer 52. Since the conductivity of the memory element having the above configuration changes before and after voltage application, two values corresponding to “initial state” and “after conductivity change” can be stored. A change in conductivity of the memory element before and after voltage application will be described.

    A substance including an insulating material forming the insulating layer has fluidity when the temperature rises to the glass transition temperature of the material. Therefore, the insulating layer becomes a composition having fluidity that does not maintain a certain shape above the glass transition temperature, and behaves close to a liquid state. When it comes to fluidity, the wettability of the surface of the formation region, which was not significantly affected in the solid state, will affect its shape, which is greatly related to the direction and speed of flow of the composition. .

    The wettability of the solid surface, which is the formation material, is influenced by the chemical properties of the surface. If the material has low wettability with respect to the composition having fluidity, the surface becomes a low wettability region with respect to the composition having fluidity, and conversely, the wettability with respect to the composition having fluidity. If the substance is a high-concentration substance, the surface thereof becomes a highly wettable region with respect to the composition having fluidity. In the present invention, the wettability of the surface of the region to be formed is formed so that the insulating layer is formed over regions having different wettability when the insulating layer becomes a glass transition temperature or higher after voltage application and changes to a fluid composition. Are controlled by materials and processing.

    A region having different wettability is a region having a difference in wettability with respect to a composition having fluidity, and a contact angle of the composition having fluidity is different. A region where the contact angle of the composition having fluidity is large is a region with low wettability, and a region with a small contact angle is a region with high wettability. When the contact angle is large, the composition having fluidity does not spread on the surface of the region and repels the composition, so that the surface is not wetted, but when the contact angle is small, the composition having fluidity spreads on the surface. This is because the surface is often wetted. Therefore, regions having different wettability also have different surface energies. The surface energy of the surface in the region with low wettability is small, and the surface energy at the surface of the region with high wettability is large.

    In the present embodiment, the insulating layer 52 is formed in contact with the first conductive layer 50, the partition wall (insulating layer) 51a and the partition wall (insulating layer) 51b that cover the edge of the first conductive layer. When a voltage is applied between the first conductive layer 50 and the second conductive layer 53, a current flows through the insulating layer 52 and heat such as Joule heat is generated. When the temperature of the insulating layer 52 rises to the glass transition temperature and becomes a composition having fluidity, the wettability with respect to the composition having fluidity is increased from the surface of the first conductive layer 50 by the partition wall ( The surfaces of the insulating layer 51a and the partition wall (insulating layer) 51b are made higher. The difference in contact angle with respect to the composition in which the insulating material forming the insulating layer between the surface of the first conductive layer 50 and the surfaces of the partition wall (insulating layer) 51a and partition wall (insulating layer) 51b is fluidized is 30 degrees or more. Preferably, it is more preferably 40 degrees or more. Further, since the material for forming the insulating layer moves on the first conductive layer 50 and the film thickness of the insulating layer on the first conductive layer 50 is not uniform, the partition wall (insulating layer) 51a, It is only necessary that the wettability of one surface of the partition wall (insulating layer) 51b is higher than that of the surface of the first conductive layer 50.

  Since the composition having fluidity moves to a higher wettability, the composition having fluidity does not maintain the solid state shape, and the wettability is shown as shown in the directions of the arrows 54a and 54b. Flow to the partition walls (insulating layer) 51a and the partition walls (insulating layer) 51b. Accordingly, the thickness of the insulating layer 52 is not uniform, the insulating layer 52 is deformed, and partly contacts the first conductive layer 50 and the second conductive layer 53 as in a region 55 illustrated in FIG. As a result, the first conductive layer 50 and the second conductive layer 53 are short-circuited. In some cases, the electric field concentrates on the thin region of the insulating layer 52, causing dielectric breakdown, causing a short circuit between the first conductive layer and the second conductive layer. Therefore, the conductivity of the memory element before and after voltage application changes.

As a result, writing can be performed with low power consumption.

  FIG. 3 shows a structural example of the memory device of the present invention. A memory cell array 722 in which memory cells 721 are provided in a matrix, a circuit 726 having a reading circuit and a writing circuit, a decoder 724, and a decoder 723 are provided. Have. Note that the structure of the memory device 716 shown here is merely an example, and may include other circuits such as a sense amplifier, an output circuit, a buffer, and an interface for external communication.

  The memory cell 721 includes a first conductive layer connected to the bit line Bx (1 ≦ x ≦ m), a second conductive layer connected to the word line Wy (1 ≦ y ≦ n), an insulating layer, Have The insulating layer is provided as a single layer or a stacked layer between the first conductive layer and the second conductive layer.

  2A is a top view of the memory cell array 722, and FIGS. 2B and 2C are cross-sectional views taken along line AB in FIG. 2A. In FIG. 2A, the insulating layer 752 and the insulating layer 754 are omitted and not shown, but are provided as shown in FIG.

  The memory cell array 722 includes a first conductive layer 751a, a first conductive layer 751b, and a first conductive layer 751c extending in the first direction, a first conductive layer 751a, a first conductive layer 751b, and a first conductive layer 751b. An insulating layer 752 provided to cover the conductive layer 751c, a second conductive layer 753a, a second conductive layer 753b, and a second conductive layer 753c extending in a second direction perpendicular to the first direction; (See FIG. 2A). An insulating layer 752 is provided between the first conductive layer 751a, the first conductive layer 751b, the first conductive layer 751c, the second conductive layer 753a, the second conductive layer 753b, and the second conductive layer 753c. It has been. In addition, an insulating layer 754 serving as a protective film is provided so as to cover the second conductive layer 753a, the second conductive layer 753b, and the second conductive layer 753c (see FIG. 2B). Note that the insulating layer 752 provided in each memory cell may be separated when there is a concern about the influence of a horizontal electric field between adjacent memory cells.

  FIG. 2C is a modification example of FIG. 2B, in which a first conductive layer 761a, a first conductive layer 761b, a first conductive layer 761c, and a partition wall (insulating layer) 765 are formed over a substrate 760. , An insulating layer 762, a second conductive layer 763b, and an insulating layer 764 which is a protective layer. As in the first conductive layer 761a, the first conductive layer 761b, and the first conductive layer 761c in FIG. 2C, the first conductive layer may have a tapered shape, and a partition wall ( The insulating layer 765 may have a shape in which the radius of curvature continuously changes. A shape such as the partition wall (insulating layer) 765 can be formed by a droplet discharge method or the like. When the partition wall 765 is a curved surface having such a curvature, the insulating layer and the conductive layer to be stacked have good coverage.

  If the wettability difference between the surface of the first conductive layer and the surface of the partition wall (insulating layer) is large with respect to the composition in which the insulating material forming the insulating layer is fluidized, the insulating layer is formed. The fluidized composition becomes easier to move. Since the composition having fluidity is repelled by the surface of the first conductive layer which is a low wettability region, it does not stay on the surface, and thus a force attracted toward the partition wall (insulating layer) side which is a high wettability region works strongly. Because.

  In this way, in order to increase the difference in wettability, the surface of the first conductive layer can be processed to become a lower wettability region. A substance with low wettability is formed on the first conductive layer to form a low wettability region that is more liquid repellent. In FIG. 15A, a liquid repellent layer 776a, a liquid repellent layer 776b, and a liquid repellent layer 776c made of a material with low wettability are formed over the first conductive layer 771a, the first conductive layer 771b, and the first conductive layer 771c. An example formed is shown below. In this embodiment, the partition wall (insulating layer) 775 to be a partition wall is solidified by attaching a liquid composition containing an insulating material and baking, drying, or the like. Therefore, the first conductive layer 771a, Instead of covering the end portions of the first conductive layer 771b and the first conductive layer 771c, they are formed in contact with the side end portions of the first conductive layer 771a, the first conductive layer 771b, and the first conductive layer 771c. Yes. With such a structure, a liquid repellent layer 776a, a liquid repellent layer 776b, and a liquid repellent layer are formed over the first conductive layer 771a, the first conductive layer 771b, and the first conductive layer 771c as illustrated in FIG. Even when the layer 776c is formed, the partition wall (insulating layer) and the liquid repellent layer are not in contact with each other, so that the partition wall (insulating layer) can be formed stably. However, when the partition wall (insulating layer) is formed using a dry process such as a vapor deposition method, the partition wall (insulating layer) is the first conductive layer even if the partition wall (insulating layer) is the first conductive layer having the liquid repellent layer on the entire surface. The shape which covers the edge part of this may be sufficient. An insulating layer 772, a second conductive layer 773b, and a protective layer (insulating layer) 774 are formed over the liquid repellent layer 776a, the liquid repellent layer 776b, and the liquid repellent layer 776c by a dry process such as an evaporation method. The liquid repellent layer may be a thin film having a thickness of several nanometers, and may not have continuity as a film depending on the formation method.

  As a substance having low wettability, a substance containing a fluorocarbon group (fluorocarbon chain) or a substance containing a silane coupling agent can be used. Since the silane coupling agent can form a monomolecular film, it can be efficiently decomposed and modified, and the wettability can be changed in a short time. The monomolecular film can also be said to be a self-assembled film. Silane coupling agents can be used because they exhibit low wettability by arranging not only those having a fluorocarbon group (fluorocarbon chain) but also those having an alkyl group on the substrate. is there. Moreover, since the functional group contained in the silane coupling agent differs depending on the fluorocarbon group or the alkyl group in reducing the wettability, it can be appropriately set depending on the material so as to obtain the required wettability.

As a substance having low wettability, a substance containing a fluorocarbon group (fluorocarbon chain) or a substance containing a silane coupling agent can be used. The silane coupling agent is represented by a chemical formula of Rn—Si—X _(4-n) (n = 1, 2, 3). Here, R is a substance containing a relatively inert group such as an alkyl group. X is a hydrolyzable group such as halogen, methoxy group, ethoxy group or acetoxy group, which can be bonded by condensation with a hydroxyl group on the substrate surface or adsorbed water.

    As a substance having low wettability, alkoxysilane which is a substance having an alkyl group can be used for R of the silane coupling agent. For example, octadecyltrimethoxysilane or the like can be used as an organic silane. As alkoxysilane, C2-C30 alkoxysilane is preferable. Typically, decyltrimethoxysilane, ethyltriethoxysilane, propyltriethoxysilane, octyltriethoxysilane, decyltriethoxysilane, dodecyltriethoxysilane, octadecyltriethoxysilane (ODS), eicosyltriethoxysilane, tria An example is contitriethoxysilane. A silane compound having a long-chain alkyl group is particularly preferable because it can reduce wettability. Further, decyltrichlorosilane, tetradecyltrichlorosilane, octadecyltrichlorosilane, eicosyltrichlorosilane, docosyltrichlorosilane, and the like can also be used.

Further, as a representative example of the silane coupling agent, wettability can be further reduced by using a fluorine-based silane coupling agent (fluoroalkylsilane (FAS)) having a fluoroalkyl group in R. R of FAS has a structure represented by (CF ₃ ) (CF ₂ ) _x (CH ₂ ) _y (x: an integer from 0 to 10 and y: an integer from 0 to 4), and a plurality of R Alternatively, when X is bonded to Si, R and X may all be the same or different. As typical FAS, fluoroalkyl such as heptadecafluorotetrahydrodecyltriethoxysilane, hepadecafluorotetrahydrodecyltrichlorosilane, tridecafluorotetrahydrooctyltrichlorosilane, trifluoropropyltrimethoxysilane, tridecafluorooctyltrimethoxysilane, etc. Examples include silane. In addition, a coupling agent such as tridecafluorooctyltrichlorosilane whose hydrolyzable group is halogen can also be used. Of course, the compounds are not limited to the exemplified compounds.

  Moreover, you may use a titanate coupling agent and an aluminate coupling agent as a substance with low wettability. For example, isopropyl triisooctanoyl titanate, isopropyl (dioctyl pyrophosphate) titanate, isopropyl tristearoyl titanate, isopropyl tris (dioctyl phosphate) titanate, isopropyl dimethacrylisostearoyl titanate, acetoalkoxy aluminum diisopropylate and the like can be mentioned.

  In order to form the low wettability substance as a film in the formation region, a vapor deposition method in which a liquid substance is evaporated and formed in the formation region (for example, a substrate) can be used. . A substance with low wettability can be formed by a spin coating method, a dip method, a droplet discharge method, a printing method (screen printing, offset printing, or the like), or a solution dissolved in a solvent.

As a solvent of a solution containing a substance having low wettability, water, alcohol, ketone, hydrocarbon solvent (aliphatic hydrocarbon, aromatic hydrocarbon, halogenated hydrocarbon, etc.), ether compound, and a mixture thereof Can be used. For example, methanol, ethanol, propanol, acetone, butanone, n-pentane, n-hexane, n-heptane, n-octane, n-decane, dicyclopentane, benzene, toluene, xylene, durene, indene, tetrahydronaphthalene, deca Hydronaphthalene, squalane, carbon tetrachloride, chloroform, methylene chloride, trichloroethane, diethyl ether, dioxane, dimethoxyethane, tetrahydrofuran, or the like is used. The concentration of the solution is not particularly limited, but may be in the range of 0.001 to 20 wt%.

  In addition, amines such as pyridine, triethylamine, dimethylaniline may be mixed with the substance having low wettability. Further, a carboxylic acid such as formic acid or acetic acid may be added as a catalyst.

  As described above, the processing temperature when forming a monomolecular film by using a spin coat method or the like in which a low wettability substance is attached to a formation region in a liquid state is from room temperature (about 25 ° C.) to 200 ° C. The processing time may be several minutes to 12 hours. The treatment conditions may be appropriately set depending on the nature of the substance having low wettability, the concentration of the solution, the treatment temperature, and the treatment time.

  In addition, when a thin film to be formed (regardless of a formation method) is washed with a solvent that can be used when a solution containing a substance with low wettability is prepared, an unreacted substance with low wettability can be removed. In this case, an ultrasonic cleaner or the like may be used.

  The film containing a substance with low wettability that can be used in the present invention may be a thin film with a thickness of 0.3 nm to 10 nm. Note that a thin film of a material with low wettability formed using a spin coating method or the like in which a substance with low wettability is attached to a formation region in a liquid state is very thin, and the thickness is in a range of 0.3 nm to 10 nm. It can be a monomolecular film.

  In addition, as an example of a composition that is controlled to reduce wettability and forms a low wettability region, a material having a fluorocarbon (fluorocarbon) group (fluorocarbon chain) (fluorine-based resin) can be used. . Examples of fluorine resins include polytetrafluoroethylene (PTFE; tetrafluoroethylene resin), perfluoroalkoxyalkane (PFA; tetrafluoroethylene perfluoroalkyl vinyl ether copolymer resin), and perfluoroethylene propene copolymer (PFEP; four fluoropolymer). Ethylene-hexafluoropropylene copolymer resin), ethylene-tetrafluoroethylene copolymer (ETFE; tetrafluoroethylene-ethylene copolymer resin), polyvinylidene fluoride (PVDF; vinylidene fluoride resin), polychlorotrifluoroethylene (PCTFE; trifluoroethylene chloride resin), ethylene-chlorotrifluoroethylene copolymer (ECTFE; trifluoroethylene chloride-ethylene copolymer resin), polytetrafluoroethylene-perfluorodioxide Rukoporima (TFE / PDD), polyvinyl fluoride (PVF; a vinyl fluoride resin), or the like can be used.

Further, when plasma treatment is performed in a gas (for example, CHF ₃ ) atmosphere containing fluorine and carbon in the conductive layer, wettability can be reduced. As shown in FIG. 15B, plasma treatment is performed on the first conductive layer 781a, the first conductive layer 781b, and the first conductive layer 781c in a gas atmosphere containing fluorine, and the surface is subjected to a liquid-repellent region. 786a, a liquid repellent area 786b, and a liquid repellent area 786c. This treatment may be performed after a partition wall (insulating layer) 785 is formed so as to cover end portions of the first conductive layer 781a, the first conductive layer 781b, and the first conductive layer 781c. An insulating layer 782, a second conductive layer 783b, and an insulating layer 784 are formed over the liquid repellent region 786a, the liquid repellent region 786b, and the liquid repellent region 786c by a dry process such as an evaporation method.

As a method of processing the liquid repellent layer on the first conductive layer into a desired shape, back exposure can be performed from the back side of the substrate using the first conductive layer as a mask. A first conductive layer 601a, a first conductive layer 601b, and a first conductive layer 601c are formed over a substrate 600, and a liquid repellent layer 602 made of a substance with low wettability is formed by a spin coating method or the like (FIG. 16 (A).) The light 606 emitted from the light source 603 passes through the substrate 600, and the first conductive layer 601a, the first conductive layer 601b, and the first conductive layer 601c serve as masks and the regions 607a and 607b of the liquid repellent layer 602 that are not blocked. , 607c, the liquid repellent layer is decomposed, and the regions 607a, 607b, and 607c are modified (see FIG. 16B). Therefore, the liquid-repellent layer 608a, the liquid-repellent layer 608b, and the liquid-repellent layer 608c are processed and formed into desired shapes over the first conductive layer 601a, the first conductive layer 601b, and the first conductive layer 601c (FIG. 16). (See (C).)

    In order to improve the processing efficiency by light irradiation, a light absorber having an absorption region in the wavelength region of the light may be mixed in the liquid repellent layer. A light absorber having an absorption region in the wavelength region of light absorbs irradiated light and radiates (radiates) energy such as heat to the surroundings. The radiant energy acts on surrounding materials, and as a result, changes the physical properties of the materials and modifies them. When the present invention is used, a light absorber may be selected in accordance with the wavelength of light, so that the range of light selection is widened. Therefore, the wavelength of the region where the substrate does not absorb much can be selected, and light irradiation for performing surface modification with good controllability can be performed. In addition, since the light irradiation efficiency can be improved, sufficient processing can be performed even if the light itself has low energy. Therefore, since the apparatus and the process are simplified, cost and time can be reduced and productivity can be improved.

    As the light absorber, an organic material, an inorganic material, a substance containing an inorganic material, an organic material, or the like can be used. A material having an absorption region at the wavelength may be selected depending on the wavelength of light used. It may be a conductive material such as metal or an insulating material such as an organic resin. As the inorganic material, iron, gold, copper, silicon or germanium can be used, and as the organic material, plastic or pigment such as polyimide or acrylic can be used. For example, rhodamine can be used as the pigment corresponding to a light wavelength of 532 nm. Examples of pigments corresponding to light wavelengths of 300 nm to 400 nm such as B, eosin Y, methyl orange, and rose bengal include coumarins (coumarin 6H, coumarin 30, coumarin 102, coumarin 152, coumarin 153, coumarin 545T, etc.), Bis. MSB (l, 4-bis (abbreviation for o-methylstyryl) benzene) can be used. Further, as the coloring matter, black carbon black or a pigment-based black resin can be used. As other dyes, rhodamine 6G, dicyanomethylenepyran derivative (DCM), and the like can also be used.

    As the light absorber, a substance having a photocatalytic function (hereinafter simply referred to as a photocatalytic substance) can be used. Since the photocatalytic substance has photocatalytic activity, it can be activated by light irradiation and the substance surface can be modified by the energy.

    An example of forming a photocatalytic substance as a light absorber is shown in FIG. In FIG. 17, the light absorber layer 614 made of a photocatalytic substance is in contact with the first conductive layer 611a, the first conductive layer 611b, the first conductive layer 611c, and the liquid repellent layer 612 provided over the substrate 610. Is formed. Similarly, the light 616 irradiated from the light source 613 passes through the substrate 610 and is irradiated to the light absorber layer 614. A light absorber having an absorption region in the wavelength region of light absorbs irradiated light and radiates (radiates) energy such as heat to the surroundings. The radiant energy acts on the liquid repellent layer 612. As a result, the liquid repellent layer 612 is decomposed and the regions 617a, 617b, and 617c are modified (see FIG. 17B). Therefore, the liquid repellent layer 618a, the liquid repellent layer 618b, and the liquid repellent layer 618c are processed and formed into desired shapes over the first conductive layer 611a, the first conductive layer 611b, and the first conductive layer 611c (FIG. 17). (See (C).) The light absorber layer 614 may be removed after the liquid repellent layer is processed.

Photocatalytic materials include titanium oxide (TiO _x ), strontium titanate (SrTiO ₃ ), cadmium selenide (CdSe), potassium tantalate (KTaO ₃ ), cadmium sulfide (CdS), zirconium oxide (ZrO ₂ ), niobium oxide ( Nb ₂ O ₅ ), zinc oxide (ZnO), iron oxide (Fe ₂ O ₃ ), tungsten oxide (WO ₃ ) and the like are preferable. These photocatalytic substances may be irradiated with light in the ultraviolet region (wavelength 400 nm or less, preferably 380 nm or less) to cause photocatalytic activity.

    The light used for the modification treatment is not particularly limited, and any one of infrared light, visible light, ultraviolet light, or a combination thereof can be used. For example, light emitted from an ultraviolet lamp, black light, halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp may be used. In that case, the lamp light source may be lit and irradiated for a necessary time, or may be irradiated multiple times.

Laser light may also be used, and as the laser oscillator, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. Examples of laser oscillators include excimer laser oscillators such as KrF, ArF, XeCl, and Xe, gas laser oscillators such as He, He—Cd, Ar, He—Ne, and HF, YAG, GdVO ₄ , YVO ₄ , YLF, and YAlO _3. A solid-state laser oscillator using a crystal doped with Cr, Nd, Er, Ho, Ce, Co, Ti, or Tm, and a semiconductor laser oscillator such as GaN, GaAs, GaAlAs, or InGaAsP can be used. In the solid-state laser oscillator, it is preferable to apply a fundamental wave, a second harmonic, and a third harmonic. In order to adjust the shape of the laser light emitted from the laser oscillator and the path of the laser light, an optical system including a reflector such as a shutter, a mirror, or a half mirror, a cylindrical lens, or a convex lens may be installed.

In the structure of the memory cell, as the substrate 750, the substrate 760, the substrate 770, and the substrate 780, a glass substrate, a flexible substrate, a quartz substrate, a silicon substrate, a metal substrate, a stainless steel substrate, or the like can be used. The flexible substrate is a substrate that can be bent (flexible), and examples thereof include a plastic substrate made of polycarbonate, polyarylate, polyethersulfone, or the like. It is also possible to use films (made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, etc.), paper made of fibrous materials, substrate films (polyester, polyamide, inorganic vapor deposition film, papers, etc.), etc. it can. In addition, a memory cell array 722 may be provided above a field effect transistor (FET) formed on a semiconductor substrate such as Si or above a thin film transistor (TFT) formed on a substrate such as glass. it can.

  In addition, the first conductive layers 751a to 751c, the first conductive layers 761a to 761c, the first conductive layers 771a to 771c, the first conductive layers 781a to 781c, the second conductive layers 753a to 753c, the second For the conductive layer 763b, the second conductive layer 773b, and the second conductive layer 783b, an element, a compound, or the like with high conductivity is used. Typically, gold (Au), silver (Ag), platinum (Pt), nickel (Ni), tungsten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co), From one element selected from copper (Cu), palladium (Pd), carbon (C), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), etc. or an alloy containing a plurality of such elements A single layer or a laminated structure can be used. Examples of the alloy containing a plurality of the above elements include an alloy Al containing Al and Ti, an alloy containing Ti and C, an alloy containing Al and Ni, an alloy containing Al and C, and Al, Ni and C. An alloy containing Al or an alloy containing Al and Mo can be used.

First conductive layers 751a to 751c, first conductive layers 761a to 761c, first conductive layers 771a to 771c, first conductive layers 781a to 781c, second conductive layers 753a to 753c, second conductive layers The 763b, the second conductive layer 773b, and the second conductive layer 783b can be formed by an evaporation method, a sputtering method, a CVD method, a printing method, a dispenser method, or a droplet discharge method.

  In this embodiment mode, data is written to the memory cell by applying an electric action or an optical action. When data is written by an optical action, the first conductive layers 751a to 751c, Conductive layers 761a to 761c, first conductive layers 771a to 771c, first conductive layers 781a to 781c, second conductive layers 753a to 753c, second conductive layers 763b, second conductive layers 773b, second One or both of the conductive layers 783b are provided so as to transmit light. The light-transmitting conductive layer is formed using a transparent conductive material, or is formed with a thickness that allows light to pass even if it is not a transparent conductive material. As the transparent conductive material, other light-transmitting oxide conductive materials such as indium tin oxide (ITO), zinc oxide (ZnO), indium zinc oxide (IZO), gallium-doped zinc oxide (GZO), and the like are used. Is possible. Oxide conductivity formed using a target in which indium tin oxide containing ITO and silicon oxide (hereinafter referred to as ITSO) or indium oxide containing silicon oxide is mixed with 2 to 20 wt% zinc oxide (ZnO). A material may be used.

The insulating layer 752, the insulating layer 762, the insulating layer 772, and the insulating layer 782, which are memory layers, are an organic insulator, an organic compound whose conductivity is changed by an electric action or an optical action, an inorganic insulator, or an organic compound and an inorganic substance. It is formed of a layer formed by mixing with a compound. The insulating layer 752, the insulating layer 762, the insulating layer 772, and the insulating layer 782 may be provided as a single layer or a plurality of stacked layers. Alternatively, a mixed layer of an organic compound and an inorganic compound and a layer formed of an organic compound whose conductivity is changed by another electric action or optical action may be provided.

Note that in this specification, a memory layer included in a memory element called an insulating layer shows insulating properties in a bulk state, but a small amount of current flows in a thin film state. In this specification, a memory layer having a slight conductivity depending on the shape is called an insulating layer instead of such a complete insulator.

As the inorganic insulator that can form the insulating layer 752, the insulating layer 762, the insulating layer 772, and the insulating layer 782, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or the like can be used.

As an organic insulator that can form the insulating layer 752, the insulating layer 762, the insulating layer 772, and the insulating layer 782, an organic resin typified by polyimide, acrylic, polyamide, benzocyclobutene, epoxy, or the like is used. it can.

Further, as an organic compound which can form the insulating layer 752, the insulating layer 762, the insulating layer 772, and the insulating layer 782 and whose conductivity is changed by an electric action or an optical action, an organic compound having a high hole-transport property is used. A compound material or an organic compound material having a high electron transporting property can be used.

As an organic compound material having a high hole-transport property, 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (abbreviation: α-NPD), 4,4′-bis [ N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (abbreviation: TPD) or 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (abbreviation: TDATA) ), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) -N-phenyl-amino] -triphenylamine (abbreviation: MTDATA) and 4,4′-bis (N- (4- (N, N-di-m-tolylamino) phenyl) -N-phenylamino) biphenyl (abbreviation: DNTPD) and other aromatic amine-based compounds (that is, having a benzene ring-nitrogen bond) and phthalocyanines (abbreviation: H ₂ Pc), copper phthalo Phthalocyanine compounds such as cyanine (abbreviation: CuPc) and vanadyl phthalocyanine (abbreviation: VOPc) can be used. The substances described here are mainly substances having a hole mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that other than the above substances, any substance that has a property of transporting more holes than electrons may be used.

Note that in the case of providing a mixed layer of an organic compound and an inorganic compound, it is preferable to mix an organic compound material having a high hole-transport property and an inorganic compound material that easily receives electrons. By adopting such a configuration, many hole carriers are generated in an organic compound which has essentially no inherent carrier, and exhibits extremely excellent hole injection / transport properties. As a result, the organic compound layer can obtain excellent conductivity.

  As an inorganic compound material that easily receives electrons, a metal oxide, metal nitride, or metal oxynitride of a transition metal in any of Groups 4 to 12 of the periodic table can be used. Specifically, titanium oxide (TiOx), zirconium oxide (ZrOx), vanadium oxide (VOx), molybdenum oxide (MoOx), tungsten oxide (WOx), tantalum oxide (TaOx), hafnium oxide (HfOx), niobium oxide (NbOx), cobalt oxide (Cox), rhenium oxide (ReOx), ruthenium oxide (RuOx), zinc oxide (ZnO), nickel oxide (NiOx), copper oxide ( CuOx) or the like can be used. Further, although oxides are given as specific examples here, these nitrides and oxynitrides may of course be used.

As an organic compound material having a high electron-transport property, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), tris (4-methyl-8-quinolinolato) aluminum (abbreviation: Almq ₃ ), bis (10-hydroxybenzo [ h] -quinolinato) beryllium (abbreviation: BeBq ₂ ), bis (2-methyl-8-quinolinolato) -4-phenylphenolato-aluminum (abbreviation: BAlq), etc., and a metal complex having a quinoline skeleton or a benzoquinoline skeleton Materials can be used. In addition, bis [2- (2-hydroxyphenyl) benzoxazolate] zinc (abbreviation: Zn (BOX) ₂ ), bis [2- (2-hydroxyphenyl) benzothiazolate] zinc (abbreviation: Zn (BTZ) A material such as a metal complex having an oxazole-based or thiazole-based ligand such as ₂ ) can also be used. In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (abbreviation: PBD), 1,3-bis [5- (P-tert-butylphenyl) -1,3,4-oxadiazol-2-yl] benzene (abbreviation: OXD-7), 3- (4-tert-butylphenyl) -4-phenyl-5- ( 4-biphenylyl) -1,2,4-triazole (abbreviation: TAZ), 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2, 4-triazole (abbreviation: p-EtTAZ), bathophenanthroline (abbreviation: BPhen), bathocuproin (abbreviation: BCP), and the like can be used. The substances mentioned here are mainly substances having an electron mobility of 10 ⁻⁶ cm ² / Vs or higher. Note that other than the above substances, any substance that has a property of transporting more electrons than holes may be used.

Note that in the case of providing a mixed layer of an organic compound and an inorganic compound, it is preferable to mix an organic compound material having a high electron-transport property and an inorganic compound material that easily gives electrons. By adopting such a structure, many electron carriers are generated in an organic compound that has essentially no intrinsic carrier, and exhibits extremely excellent electron injecting and transporting properties. As a result, the organic compound layer can obtain excellent conductivity.

  As the inorganic compound material that easily gives electrons, alkali metal oxides, alkaline earth metal oxides, rare earth metal oxides, alkali metal nitrides, alkaline earth metal nitrides, and rare earth metal nitrides can be used. Specifically, lithium oxide (LiOx), strontium oxide (SrOx), barium oxide (BaOx), erbium oxide (ErOx), sodium oxide (NaOx), lithium nitride (LiNx), magnesium nitride (MgNx), calcium nitride, yttrium nitride (YNx), lanthanum nitride (LaNx), or the like can be used.

  Furthermore, as the inorganic compound material, any inorganic compound material that easily receives electrons from an organic compound or inorganic compound material that easily gives electrons to an organic compound may be used. Aluminum oxide (AlOx), gallium oxide (GaOx), silicon In addition to oxide (SiOx), germanium oxide (GeOx), indium tin oxide (ITO), and the like, various metal oxides, metal nitrides, or metal oxynitrides can be used.

  In the case where the insulating layer 752, the insulating layer 762, the insulating layer 772, and the insulating layer 782 are formed of a compound selected from metal oxides or metal nitrides and a compound having a high hole-transport property, further steric hindrance is performed. It is good also as a structure which added the compound (having a (three-dimensional) structure which has a spatial extension unlike a plane structure). As the compound having a large steric hindrance, 5,6,11,12-tetraphenyltetracene (abbreviation: rubrene) is preferable. However, besides this, hexaphenylbenzene, t-butylperylene, 9,10-di (phenyl) anthracene, coumarin 545T, and the like can also be used. In addition, dendrimers and the like are also effective.

Furthermore, 4-dicyanomethylene-2-methyl-6- [2- (1,1) is formed between a layer formed of an organic compound material having a high electron-transport property and an organic compound material layer having a high hole-transport property. 1,7,7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran (abbreviation: DCJT), 4-dicyanomethylene-2-tert-butyl-6- [2- (1,1,7, 7-tetramethyljulolidin-9-yl) ethenyl] -4H-pyran, periflanthene, 2,5-dicyano-1,4-bis [2- (10-methoxy-1,1,7,7-tetramethyljuro) Lysine-9-yl) ethenyl] benzene, N, N′-dimethylquinacridone (abbreviation: DMQd), coumarin 6, coumarin 545T, tris (8-quinolinolato) aluminum (abbreviation: Alq ₃ ), 9,9′-biant Ril, 9,10-diphenylanthracene (abbreviation: DPA), 9,10-bis (2-naphthyl) anthracene (abbreviation: DNA), 2,5,8,11-tetra-t-butylperylene (abbreviation: TBP) A luminescent material such as may be provided.

The insulating layer 752, the insulating layer 762, the insulating layer 772, and the insulating layer 782 can be formed using a material whose electrical resistance changes by an optical action. For example, a conjugated polymer doped with a compound that generates an acid by absorbing light (a photoacid generator) can be used. As the conjugated polymer, polyacetylenes, polyphenylene vinylenes, polythiophenes, polyanilines, polyphenylene ethynylenes, and the like can be used. As the photoacid generator, arylsulfonium salts, aryliodonium salts, o-nitrobenzyl tosylate, arylsulfonic acid p-nitrobenzyl esters, sulfonylacetophenones, Fe-allene complex PF ₆ salts, and the like can be used. .

  The insulating layer 752, the insulating layer 762, the insulating layer 772, and the insulating layer 782 can be formed by an evaporation method, an electron beam evaporation method, a sputtering method, a CVD method, or the like. Moreover, the mixed layer containing an organic compound and an inorganic compound can be formed by simultaneously forming the respective materials. The co-evaporation method using resistance heating evaporation, the co-evaporation method using electron beam evaporation, and resistance heating. It can be formed by a combination of the same or different methods such as co-evaporation by vapor deposition and electron beam vapor deposition, film formation by resistance heating vapor deposition and sputtering, and film formation by electron beam vapor deposition and sputtering.

Note that the insulating layer 752, the insulating layer 762, the insulating layer 772, and the insulating layer 782 are formed to have thicknesses at which the conductivity of the memory element is changed by an electric action or an optical action.

    As the partition wall (insulating layer) 755, the partition wall (insulating layer) 765, the partition wall (insulating layer) 775, and the partition wall (insulating layer) 785, silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, and others Alternatively, an inorganic insulating material, acrylic acid, methacrylic acid and derivatives thereof, heat-resistant polymers such as polyimide, aromatic polyamide, polybenzimidazole, or siloxane materials may be used. Note that the siloxane material corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Further, a resin material such as a vinyl resin such as polyvinyl alcohol or polyvinyl butyral, an epoxy resin, a phenol resin, a novolac resin, an acrylic resin, a melamine resin, or a urethane resin is used. Alternatively, an organic material such as benzocyclobutene, parylene, or polyimide, a compound material formed by polymerization of a polymer, a composition material containing a water-soluble homopolymer and a water-soluble copolymer, or the like may be used. As a manufacturing method, a vapor deposition method such as a plasma CVD method or a thermal CVD method, or a sputtering method can be used. Alternatively, a droplet discharge method, a dispenser method, or a printing method (a method for forming a pattern such as screen printing or offset printing) can be used. A thin film obtained by a spin coating method can also be used.

    Further, after a conductive layer, an insulating layer, or the like is formed by discharging a composition by a droplet discharge method, the surface may be flattened by pressing with a pressure in order to improve the flatness. As a pressing method, unevenness may be reduced by scanning a roller-shaped object on the surface, or the surface may be pressed vertically with a flat plate-like object. A heating step may be performed when pressing. Alternatively, the surface may be softened or dissolved with a solvent or the like, and the surface irregularities may be removed with an air knife. Further, polishing may be performed using a CMP method. This step can be applied when the surface is flattened when unevenness is generated by the droplet discharge method.

  In this embodiment, in the above structure, the first conductive layers 751a to 751c, the first conductive layers 761a to 761c, the first conductive layers 771a to 771c, and the first conductive layers 781a to 781c are insulated from each other. An element having a rectifying property may be provided between the layer 752, the insulating layer 762, the insulating layer 772, and the insulating layer 782. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. Thus, by providing a diode having a rectifying property, current flows only in one direction, so that an error is reduced and a read margin is improved. Note that the rectifying element includes the insulating layer 752, the insulating layer 762, the insulating layer 772, the insulating layer 782, the second conductive layers 753a to 753c, the second conductive layer 763b, the second conductive layer 773b, and the second The conductive layer 783b may be provided.

    With the memory element of the present invention, the driving voltage at the time of data writing can be reduced. As a result, a memory device and a semiconductor device with low power consumption can be provided at low cost with high yield.

(Embodiment 2)
In this embodiment, a memory device having a structure different from that in Embodiment 1 is described. Specifically, a case where the structure of the memory device is an active matrix type will be described.

  FIG. 5 shows an example of a structure of the memory device described in this embodiment. A bit line including a memory cell array 232 in which memory cells 231 are provided in a matrix, a column decoder 226a, a read circuit 226b, and a selector 226c. It has a driver circuit 226, a word line driver circuit 224 having a row decoder 224a and a level shifter 224b, an interface 223 having a write circuit and the like for performing exchanges with the outside. Note that the structure of the memory device 216 shown here is merely an example, and other circuits such as a sense amplifier, an output circuit, and a buffer may be included, and a writing circuit may be provided in the bit line driver circuit.

  The memory cell array 232 includes a first wiring configuring the word line Wy (1 ≦ y ≦ n), a second wiring configuring the bit line Bx (1 ≦ x ≦ m), a transistor 210a, and a storage element 215b. And have. The memory element 215b has a structure in which an insulating layer is sandwiched between a pair of conductive layers.

  4A is a top view of the memory cell array 232, and FIG. 4B is a cross-sectional view taken along line EF in FIG. 4A. In FIG. 4A, the insulating layer 212 and the insulating layer 214 are omitted and not shown, but are provided as shown in FIG. 4B.

  The memory cell array 232 includes a first wiring 205a and a first wiring 205b extending in a first direction and a second wiring 202 extending in a second direction perpendicular to the first direction in a matrix. It has been. The first wiring is connected to the source electrode or the drain electrode of the transistors 210a and 210b, and the second wiring is connected to the gate electrodes of the transistors 210a and 210b. Further, the first conductive layer 206a and the first conductive layer 206b are connected to the source or drain electrodes of the transistor 210a and the transistor 210b which are not connected to the first wiring, respectively. A memory element 215a and a memory element 215b are provided by a stacked structure of one conductive layer 206b, an insulating layer 212, and a second conductive layer 213. A partition wall (insulating layer) 207 is provided between each adjacent memory cell 231, and an insulating layer 212 and a second conductive layer 213 are stacked over the first conductive layer and the partition wall (insulating layer) 207. Yes. An insulating layer 214 serving as a protective layer is provided over the second conductive layer 213. Thin film transistors are used as the transistors 210a and 210b (see FIG. 4B). The memory device in FIG. 4B is provided over a substrate 200, and includes an insulating layer 201a, an insulating layer 201b, an insulating layer 208, an insulating layer 209, an insulating layer 211, a semiconductor layer 204a included in the transistor 210a, and a gate electrode layer. 202a, a first wiring 205a also serving as a source electrode layer or a drain electrode layer, a semiconductor layer 204b included in the transistor 210b, a gate electrode layer 202b, and a wiring 205b also serving as a source electrode layer or a drain electrode layer.

    In this embodiment, the insulating layer 212 is formed in contact with the first conductive layer 206a and a partition wall (insulating layer) 207 that covers an end portion of the first conductive layer. When a voltage is applied between the first conductive layer 206a and the second conductive layer 213, a current flows through the insulating layer 212 and heat such as Joule heat is generated. Also in this embodiment mode, when the temperature of the insulating layer 212 rises to the glass transition temperature and becomes a fluid composition, the wettability with respect to the fluid composition is reduced by the surface of the first conductive layer 206a. Thus, the surface of the partition wall (insulating layer) 207 is higher.

  Since the composition having fluidity moves toward the higher wettability, the composition having fluidity flows to the partition wall (insulating layer) 207 having high wettability without maintaining the solid state shape. Accordingly, the thickness of the insulating layer is not uniform, the insulating layer is deformed, and the first conductive layer 206a and the second conductive layer 213 are short-circuited. In some cases, the electric field concentrates on a thin region of the insulating layer, causing a dielectric breakdown to cause a short circuit between the first conductive layer and the second conductive layer. Therefore, the conductivity of the memory element before and after voltage application changes. The memory element 215b including the first conductive layer 206b, the partition wall (insulating layer) 207, the insulating layer 212, and the second conductive layer 213 is similar to the memory element 215a.

As a result, writing can be performed with low power consumption.

  Further, as illustrated in FIG. 6, a memory element 265 a and a memory element 265 b may be connected to the field effect transistor 260 a and the field effect transistor 260 b provided over the single crystal semiconductor substrate 250. Here, an insulating layer 270 is provided so as to cover the source or drain electrode layers 255a to 255d of the field effect transistor 260a and the field effect transistor 260b, and the first conductive layer 256a and the first conductive layer are provided over the insulating layer 270. The memory element 265a and the memory element 265b are formed by 256b, the partition wall (insulating layer) 267, the insulating layer 262a, the insulating layer 262b, and the second conductive layer 263. An insulating layer such as the insulating layers 262a and 262b may be selectively provided only in each memory cell using a mask or the like. In addition, the memory device illustrated in FIG. 6 also includes an element isolation region 268, an insulating layer 269, an insulating layer 261, and an insulating layer 264.

  In the memory elements 265a and 265b, the surfaces of the first conductive layer 256a and the first conductive layer 256b are controlled to be a liquid-repellent region by plasma treatment using a gas containing fluorine, as indicated by a dotted line. Layer) 267 has lower wettability than the surface of the composition having fluidity of the material forming the insulating layers 262a and 262b. Therefore, the fluid composition of the material forming the insulating layers 262a and 262b moves toward the partition wall (insulating layer) 267, and the memory elements 265a and 265b are short-circuited.

  In this manner, by providing the insulating layer 270 and forming the memory element, the first conductive layer can be freely arranged. In other words, in the structure in FIG. 4B, the memory element 215a and the memory element 215b need to be provided in a region where the source electrode layer or the drain electrode layer of the transistor 210a and the transistor 210b are avoided. For example, the memory element 215a and the memory element 215b can be formed above the transistors 210a and 210b. As a result, the storage device 216 can be more highly integrated.

  Further, the transistor 210a and the transistor 210b may have any structure as long as they can function as switching elements. As the semiconductor layer, various semiconductors such as an amorphous semiconductor, a crystalline semiconductor, a polycrystalline semiconductor, and a microcrystalline semiconductor can be used, and an organic transistor may be formed using an organic compound. FIG. 4A illustrates an example in which a planar thin film transistor is provided over an insulating substrate; however, a transistor can be formed with a staggered structure, an inverted staggered structure, or the like.

    FIG. 7 shows an example using a thin film transistor having an inverted staggered structure. Over the substrate 280, transistors 290a and 290b which are thin film transistors having an inverted staggered structure are provided. The transistor 290a includes an insulating layer 288, a gate electrode layer 281, an amorphous semiconductor layer 282, a semiconductor layer 283a having one conductivity type, a semiconductor layer 283b having one conductivity type, a source or drain electrode layer 285, The source electrode layer or the drain electrode layer is the first conductive layer 286a included in the memory element. A partition wall (insulating layer) 287 is stacked so as to cover end portions of the first conductive layer 286a and the first conductive layer 286b, and the first conductive layer 286a, the first conductive layer 286b, and the partition wall (insulating layer) 287 are stacked. An insulating layer 292, a second conductive layer 293, and an insulating layer 294 which is a protective layer are formed over the memory element 295a and the memory element 295b. In the memory device illustrated in FIG. 7, the gate electrode layer 281, the source or drain electrode layer 285, the first conductive layer 286a, the first conductive layer 286b, and the partition wall (insulating layer) 287 are formed by a droplet discharge method. Form. The droplet discharge method is a method in which a composition containing a composition forming material that is a fluid is discharged (jetted) as droplets to form a desired pattern shape. A droplet containing a component forming material is discharged onto a region where the component is to be formed, and fixed by firing, drying, or the like to form a component having a desired pattern.

  Further, any structure of a semiconductor layer included in the transistor may be used. For example, an impurity region (including a source region, a drain region, and an LDD region) may be formed, or a p-channel type or an n-channel may be formed. You may form with either type | mold. Further, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed on one or both of the source and drain regions and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  The materials and formation methods of the first conductive layers 206a, 206b, 256a, 256b, 286a, and 286b and the second conductive layers 213, 263, and 293 described in this embodiment are the same as those described in Embodiment 1. And any of the formation methods.

  The insulating layers 212, 262a, 262b, and 292 can be provided using a material and a formation method similar to those of the insulating layer 752 described in Embodiment 1.

  Further, a rectifying element may be provided between the first conductive layers 206a, 206b, 256a, 256b, 286a, 286b and the insulating layers 212, 262a, 262b, 292. The element having a rectifying property is a transistor or a diode in which a gate electrode and a drain electrode are connected. For example, a PN junction diode provided by stacking an N-type semiconductor layer and a P-type semiconductor layer can be used. Thus, by providing a diode having a rectifying property, current flows only in one direction, so that an error is reduced and a read margin is improved. Note that when a diode is provided, a diode having another structure such as a diode having a PIN junction or an avalanche diode may be used instead of a diode having a PN junction. Note that a rectifying element may be provided between the insulating layers 212, 262 a, 262 b, and 292 and the second conductive layers 213, 263, and 293.

    With the memory element of the present invention, the driving voltage at the time of data writing can be reduced. As a result, a memory device and a semiconductor device with low power consumption can be provided at low cost with high yield.

(Embodiment 3)
In this embodiment, an example of a semiconductor device including the memory device described in the above embodiment will be described with reference to drawings.

  The semiconductor device described in this embodiment is characterized in that data can be read and written in a non-contact manner. A data transmission format is an electromagnetic which performs communication by mutual induction with a pair of coils arranged opposite to each other. There are roughly divided into a coupling system, an electromagnetic induction system that communicates using an induction electromagnetic field, and a radio system that communicates using radio waves, but any system may be used. In addition, there are two types of antennas used for data transmission. When one antenna is provided on a substrate on which a plurality of elements and memory elements are provided, the other is provided with a plurality of elements and memory elements. In some cases, a terminal portion is provided over the substrate, and an antenna provided over another substrate is connected to the terminal portion.

  First, a structure example of a semiconductor device in the case where an antenna is provided over a substrate provided with a plurality of elements and memory elements will be described with reference to FIGS.

  FIG. 10 illustrates a semiconductor device having a memory device formed of an active matrix type. A transistor portion 330 including transistors 310a and 310b over a substrate 300, a transistor portion 340 including transistors 320a and 320b, an insulating layer 301a, An element formation layer 335 including 301b, 308, 309, 311, 316, and 314 is provided, and a storage element portion 325 and a conductive layer 343 functioning as an antenna are provided above the element formation layer 335.

  Note that here, the case where the memory element portion 325 or the conductive layer 343 functioning as an antenna is provided above the element formation layer 335 is shown; however, the structure is not limited thereto, and the memory element portion 325 or the conductive layer 343 functioning as an antenna is provided. Can be provided below the element formation layer 335 or in the same layer.

  The memory element portion 325 includes memory elements 315a and 315b. The memory element 315a has a partition wall (insulating layer) 307a, a partition wall (insulating layer) 307b, an insulating layer 312 and a second conductive layer on the first conductive layer 306a. The memory element 315b includes a partition wall (insulating layer) 307b, a partition wall (insulating layer) 307c, an insulating layer 312 and a second conductive layer 313 which are stacked over the first conductive layer 306b. Is provided. In addition, an insulating layer 314 that covers the second conductive layer 313 and functions as a protective film is formed. In addition, the first conductive layer 306a and the first conductive layer 306b in which the plurality of memory elements 315a and 315b are formed are electrically connected to the source electrode layer or the drain electrode layer of the transistors 310a and 310b, respectively. Yes. That is, each memory element is electrically connected to one transistor. In addition, although the insulating layer 312 is formed over the entire surface so as to cover the first conductive layers 306a and 306b and the partition walls (insulating layers) 307a, 307b, and 307c, the insulating layer 312 may be selectively formed in each memory cell. . Note that the memory elements 315a and 315b can be formed using any of the materials and manufacturing methods described in the above embodiment modes.

  In the memory elements 315a and 315b, the surface of the first conductive layer 306a and the first conductive layer 306b has fluidity of the material forming the insulating layer 312 from the surfaces of the partition walls (insulating layers) 307a, 307b, and 307c. Low wettability. Accordingly, the composition having fluidity of the material forming the insulating layer 312 moves toward the partition walls (insulating layers) 307a, 307b, and 307c, and the memory elements 315a and 315b are short-circuited.

  In addition, as shown in the above embodiment mode, the memory element 315a has a rectifying property between the first conductive layer 306a and the insulating layer 312 or between the insulating layer 312 and the second conductive layer 313. An element may be provided. The above-described elements having a rectifying property can also be used. The same applies to the memory element 315b.

  Here, the conductive layer 343 functioning as an antenna is formed over the conductive layer 341 formed using the same layer as the first conductive layers 306 a and 306 b and the conductive layer 342 formed using the same layer as the second conductive layer 313. Is provided. Note that a conductive layer functioning as an antenna may be formed using the same layer as the second conductive layer 313. The conductive layer 341 is connected to the source electrode layer or the drain electrode layer of the transistor 320a.

  As a material of the conductive layer 343 functioning as an antenna, gold (Au), platinum (Pt), nickel (Ni), tungsten (W), molybdenum (Mo), cobalt (Co), copper (Cu), aluminum (Al ), Manganese (Mn), titanium (Ti), or the like, or an alloy containing a plurality of such elements can be used. As a method for forming the conductive layer 343 functioning as an antenna, vapor deposition, sputtering, a CVD method, a dispenser method, various printing methods such as screen printing and gravure printing, a droplet discharge method, and the like can be used.

  The transistors 310a, 310b, 320a, and 320b included in the element formation layer 335 can be provided using a p-channel TFT, an n-channel TFT, or a CMOS in which these are combined. Further, any structure of the semiconductor layer included in the transistors 310a, 310b, 320a, and 320b may be used, and for example, an impurity region (including a source region, a drain region, and an LDD region) may be formed. The p channel type or the n channel type may be used. Further, an insulating layer (side wall) may be formed so as to be in contact with the side surface of the gate electrode, or a silicide layer may be formed on one or both of the source and drain regions and the gate electrode. As a material for the silicide layer, nickel, tungsten, molybdenum, cobalt, platinum, or the like can be used.

  Alternatively, the transistors 310a, 310b, 320a, and 320b included in the element formation layer 335 may be organic transistors in which a semiconductor layer included in the transistor is formed using an organic compound. In this case, the element formation layer 335 including an organic transistor can be formed using a direct printing method, a droplet discharge method, or the like on a flexible substrate such as plastic as the substrate 300. By using a printing method, a droplet discharge method, or the like, a semiconductor device can be manufactured at lower cost.

  The element formation layer 335, the memory elements 315a and 315b, and the conductive layer 343 functioning as an antenna are formed by vapor deposition, sputtering, CVD, printing, dispenser, droplet discharge, or the like as described above. be able to. Note that a different method may be used depending on each place. For example, a transistor that requires high-speed operation is provided by forming a semiconductor layer made of Si or the like on a substrate and then crystallizing it by heat treatment, and then forming a transistor that functions as a switching element above the element formation layer by printing or An organic transistor can be provided by a droplet discharge method.

Note that a sensor connected to the transistor may be provided. Examples of the sensor include an element that detects temperature, humidity, illuminance, gas (gas), gravity, pressure, sound (vibration), acceleration, and other characteristics by physical or chemical means. The sensor is typically formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode.

  Next, a structure example of a semiconductor device in the case where a terminal portion is provided over a substrate provided with a plurality of elements and memory elements and an antenna provided over another terminal is connected to the terminal portion is described with reference to FIG. I will explain.

  FIG. 11 illustrates a semiconductor device having a passive matrix memory device, in which an element formation layer 385 is provided over a substrate 350, a memory element portion 375 is provided above the element formation layer 385, and the substrate 396 is provided. A conductive layer 393 functioning as an antenna is provided so as to be electrically connected through the element formation layer 385 and the conductive layers 391 and 392. Note that here, the case where the memory element portion 375 or the conductive layer 393 functioning as an antenna is provided above the element formation layer 385 is shown; however, the present invention is not limited to this structure, and the memory element portion 375 is provided below the element formation layer 385. A conductive layer 393 functioning as an antenna can be provided below the element formation layer 385 in the same layer.

  In FIG. 11, a transistor portion 380 including transistors 360a and 360b over a substrate 350, a transistor portion 390 including transistors 370a and 370b, an insulating layer 351a, an insulating layer 351b, an insulating layer 358, an insulating layer 359, an insulating layer 361, an insulating layer An element formation layer 385 including a layer 366 and an insulating layer 364 is provided.

  The memory element portion 375 includes memory elements 365a and 365b. In the memory element 365a, partition walls (insulating layers) 357a and 357b, an insulating layer 362a, and a second conductive layer 363a are stacked over the first conductive layer 356. In the memory element 365b, partition walls (insulating layers) 357b and 357c, an insulating layer 362b, and a second conductive layer 363b are stacked over the first conductive layer 356. In addition, an insulating layer 364 that functions as a protective film is formed so as to cover the second conductive layers 363a and 363b. In addition, the first conductive layer 356 in which the plurality of memory elements 365a and 365b are formed is connected to one source electrode layer or drain electrode layer of the transistor 360b. That is, the plurality of memory elements are connected to the same transistor. In addition, although the insulating layers 362a and 362b are provided with partition walls (insulating layers) 357a, 357b, and 357c for separating the insulating layers for each memory cell, the influence of the electric field in the lateral direction is exerted on the adjacent memory cells. If there is no concern, an insulating layer may be formed over the entire surface. Note that the memory elements 365a and 365b can be formed using the material or the manufacturing method described in the above embodiment modes.

  In the memory elements 365a and 365b, the surface of the first conductive layer 356 has wettability to the composition having fluidity of the material forming the insulating layers 362a and 362b from the surfaces of the partition walls (insulating layers) 357a, 357b, and 357c. Is low. Therefore, the fluid composition of the material forming the insulating layers 362a and 362b moves toward the partition walls (insulating layers) 357a, 357b, and 357c, and the memory elements 315a and 315b are short-circuited.

  A substrate including the element formation layer 385 and the memory element portion 375 and a substrate 396 provided with a conductive layer 393 functioning as an antenna are attached to each other with a resin 395 having adhesiveness. The conductive layer 393 is provided over the conductive layer 391 formed using the same layer as the first conductive layer 356 and the conductive layer 392 formed using the same layer as the second conductive layers 363a and 363b. The conductive layer 391 is connected to the source electrode layer or the drain electrode layer of the transistor 370a. The element formation layer 385 and the conductive layer 393 are electrically connected through conductive fine particles 394 contained in the resin 395. In addition, a conductive layer such as a silver paste, a copper paste, or a carbon paste or a method of performing solder bonding is used to provide a substrate including the element formation layer 385 and the memory element portion 375, and a conductive layer 393 that functions as an antenna. The substrate 396 may be attached.

  In this manner, a semiconductor device including a memory device and an antenna can be formed. In this embodiment mode, an element formation layer can be provided by forming a thin film transistor over a substrate, or by forming a field effect transistor over a substrate using a semiconductor substrate such as Si as the substrate. A layer may be provided. Alternatively, an SOI substrate may be used as a substrate, and an element formation layer may be provided thereover. In this case, the SOI substrate may be formed by using a method of bonding wafers or a method called SIMOX in which an insulating layer is formed inside by implanting oxygen ions into the Si substrate.

Further, the memory element portion may be provided on a substrate provided with a conductive layer functioning as an antenna. A sensor connected to the transistor may be provided.

Note that this embodiment can be freely combined with the above embodiment. In addition, the semiconductor device manufactured in this embodiment can be provided over a flexible substrate by being separated from the substrate by a separation process and bonded onto a flexible substrate, so that a flexible semiconductor device can be obtained. Can do. Flexible substrate means film made of polypropylene, polyester, vinyl, polyvinyl fluoride, vinyl chloride, paper made of fibrous material, substrate film (polyester, polyamide, inorganic vapor deposition film, paper, etc.) and adhesiveness It corresponds to a laminated film with a synthetic resin film (acrylic synthetic resin, epoxy synthetic resin, etc.). The film is subjected to heat treatment and pressure treatment by thermocompression bonding. When the heat treatment and pressure treatment are performed, the film is either an adhesive layer provided on the outermost surface of the film or the A layer (not an adhesive layer) provided in the outer layer is melted by heat treatment and bonded by pressure. Further, an adhesive layer may be provided on the substrate, or an adhesive layer may not be provided. The adhesive layer corresponds to a layer containing an adhesive such as a thermosetting resin, an ultraviolet curable resin, an epoxy resin adhesive, or a resin additive.

    With the memory element of the present invention, the driving voltage at the time of data writing can be reduced. As a result, a memory device and a semiconductor device with low power consumption can be provided at low cost with high yield.

(Embodiment 4)
In this embodiment mode, reading or writing of data in the semiconductor device having the above structure is described.

  Data writing to the semiconductor device having the above structure can be performed by applying an optical action or an electrical action. First, a case of writing data by applying an electrical action will be described (see FIG. 3).

  In the case where data is written by applying an electrical action, one memory cell 721 is selected by the row decoder 724a, the column decoder 726a, and the selector 726c, and then data is stored in the memory cell 721 using a writing circuit. Write. Specifically, a large voltage is selectively applied to the desired portion of the insulating layer 752 to flow a large current, thereby short-circuiting the first conductive layer 751b and the second conductive layer 753b.

  The shorted portion has a significantly lower electrical resistance than the other portions. In this manner, data is written by utilizing the change in the electrical resistance between the two conductive layers by applying an electrical action. For example, in a case where an insulating layer to which no electrical action is applied is set to “0” data, when writing “1” data, a large voltage is selectively applied to a desired portion of the insulating layer to generate a large current. By flowing, the electrical resistance is reduced by short-circuiting.

  Next, a case where data is written by applying an optical action will be described (FIGS. 8A to 8C).

  In the case where data is written by applying an optical action, the insulating layer 752 is irradiated with laser light from the light-transmitting conductive layer side (here, second conductive layers 753a, 753b, and 753c). Here, the insulating layer 752 is destroyed by selectively irradiating a desired portion of the insulating layer 752 with laser light. Since the destroyed insulating layer is carbonized and insulated, the electric resistance is significantly increased as compared with other portions. In this manner, data is written by utilizing the change in electrical resistance of the insulating layer 752 due to laser light irradiation. For example, in the case where an insulating layer not irradiated with laser light is set to “0” data, when writing “1” data, the insulating layer in a desired portion is selectively irradiated with laser light to be destroyed. Increase the electrical resistance.

  In order to perform writing, the resistance value of the memory element has only to be changed before and after writing. Therefore, the resistance value of the memory element may be changed by an optical action or an electrical action. For example, the shape of the first conductive layer or the second conductive layer in the memory element changes due to energy (heat, etc.) due to light irradiation, and the first conductive layer and the second conductive layer approach, and the change Accordingly, the insulating layer may be deformed.

In the case of laser light irradiation, the change in the electrical resistance of the insulating layer 752 depends on the size of the memory cell 721, but by irradiation of the laser light with a beam spot diameter reduced to μm or nm using an optical system such as a lens. Realize. For example, when a laser beam having a diameter of 1 μm passes at a linear velocity of 10 m / sec, the time during which the insulating layer included in one memory cell 721 is irradiated with laser light is 100 nsec. In order to change the phase within a short time of 100 nsec, the laser power is preferably 10 mW and the power density is 10 kW / mm ² . In the case of selectively irradiating laser light, it is preferable to use a pulsed laser irradiation apparatus.

  Here, an example of a laser irradiation apparatus will be briefly described with reference to FIG. A laser irradiation apparatus 1001 includes a computer (hereinafter, referred to as a PC) 1002 that executes various controls when irradiating laser light, a laser oscillator 1003 that outputs laser light, a power source 1004 of the laser oscillator 1003, and laser light. An optical system (ND filter) 1005 for attenuating light, an acousto-optic modulator (AOM) 1006 for modulating the intensity of the laser light, and a lens and an optical path for reducing the cross section of the laser light An optical system 1007 composed of a mirror for changing the angle, a moving mechanism 1009 having an X-axis stage and a Y-axis stage, a D / A conversion unit 1010 for digital-analog conversion of control data output from the PC, Acousto-optic modulator 10 according to the analog voltage output from the D / A converter A driver 1011 for controlling the 6, a driver 1012 for outputting a driving signal for driving the movement mechanism 1009 is provided with an auto-focus mechanism 1013 for focusing the laser beam on the irradiated object.

As the laser oscillator 1003, a laser oscillator that can oscillate ultraviolet light, visible light, or infrared light can be used. Laser oscillators include excimer laser oscillators such as KrF, ArF, KrF, XeCl, and Xe, gas laser oscillators such as He, He—Cd, Ar, He—Ne, and HF, YAG, GdVO ₄ , YVO ₄ , YLF, and YAlO. Cr crystal such as _{3, Nd, Er, Ho,} Ce, Co, solid-state laser oscillator using a crystal doped with Ti or Tm, can be used GaN, GaAs, GaAlAs, a semiconductor laser oscillator of InGaAsP or the like. In the solid-state laser oscillator, it is preferable to apply the fundamental wave or the second to fifth harmonics.

  Next, an irradiation method using a laser irradiation apparatus will be described. When the substrate 750 provided with the insulating layer 752 is attached to the moving mechanism 1009, the PC 1002 detects the position of the insulating layer 752 to be irradiated with laser light by a camera (not shown). Next, the PC 1002 generates movement data for moving the movement mechanism 1009 based on the detected position data.

  Thereafter, the PC 1002 controls the output light amount of the acousto-optic modulator 1006 via the driver 1011, so that the laser light output from the laser oscillator 1003 is attenuated by the optical system 1005 and then the acousto-optic modulator 1006. The light amount is controlled so as to be a predetermined light amount. On the other hand, the laser light output from the acousto-optic modulator 1006 is changed in optical path and beam spot shape by the optical system 1007, condensed by a lens, and then irradiated onto the substrate 750.

  At this time, according to the movement data generated by the PC 1002, the movement mechanism 1009 is controlled to move in the X direction and the Y direction. As a result, laser light is irradiated to a predetermined place, the light energy density of the laser light is converted into thermal energy, and the insulating layer provided over the substrate 750 can be selectively irradiated with the laser light. Note that, here, an example in which the moving mechanism 1009 is moved and laser light irradiation is performed is shown; however, the laser light may be moved in the X direction and the Y direction by adjusting the optical system 1007.

  Next, an operation for reading data from the storage device will be described (see FIG. 9). Here, the reading circuit 726 b includes a resistance element 746 and a sense amplifier 747. Note that the structure of the reading circuit 726b is not limited to the above structure, and may have any structure.

  Data is read by applying voltage between the first conductive layer 751b and the second conductive layers 753a, 753b, and 753c to read the electrical resistance of the insulating layer 752. For example, as described above, when data is written by applying an electrical action, the resistance value Ra1 when no electrical action is applied, and when the two conductive films are short-circuited by applying an electrical action. The resistance value Rb1 satisfies Ra1> Rb1. Data is read by electrically reading such a difference in resistance value.

  In addition, as described above, when data is written by irradiating the insulating layer with laser light, the resistance value Ra2 when the laser light is not irradiated and when the insulating layer is destroyed by irradiating the laser light Resistance value Rb2 satisfies Ra2 <Rb2. Data is read by electrically reading such a difference in resistance value.

  For example, when data is read from a plurality of memory cells 721 included in the memory cell array 722 to the memory cell 721 arranged in the xth column and the yth row, first, the row decoder 724a, the column decoder 726a, and the selector 726c The bit line Bx in the column and the word line Wy in the y row are selected. Then, the insulating layer included in the memory cell 721 and the resistance element 746 are connected in series. Thus, when a voltage is applied across the two resistance elements connected in series, the potential of the node α becomes a resistance-divided potential according to the resistance value Ra or Rb of the insulating layer 752. The potential of the node α is supplied to the sense amplifier 747, and the sense amplifier 747 determines whether it has information “0” or “1”. Thereafter, a signal including information of “0” and “1” determined by the sense amplifier 747 is supplied to the outside.

  According to the above method, the state of the electrical resistance of the insulating layer is read as a voltage value using the difference in resistance value and resistance division. However, a method of comparing current values may be used. This is because, for example, the current value Ia1 when no electrical action is applied to the insulating layer and the resistance value Ib1 when the electrical action is applied to short-circuit the two conductive films satisfy Ia1 <Ib1. It is what you use. Further, when data is written by irradiating the insulating layer with laser light, the current value Ia2 when the laser light is not irradiated and the current value Ib2 when the insulating layer is destroyed by irradiating the laser light are: , Ia2> Ib2. In this way, data may be read by electrically reading the difference in current value.

  Since the memory element having the above structure and the semiconductor device including the memory element are nonvolatile memories, a battery for holding data may not be mounted. A small, thin, and lightweight semiconductor device can be provided. In addition, data can be written (added) by using the insulating material used in the above embodiment as an insulating layer, but data cannot be rewritten. Therefore, it is possible to provide a semiconductor device that prevents forgery and ensures security.

  Note that in this embodiment, a passive matrix memory element with a simple structure of a memory circuit and a semiconductor device including the memory element are described as examples; however, an active matrix memory circuit is provided. Even in this case, data can be written or read in the same manner.

  Here, in the case of the active matrix type, a case where data in the memory element portion is read by an electrical action will be described with reference to FIG.

  FIG. 14 shows a current-voltage characteristic 951 of a memory element unit in which data “0” is written to the memory element unit, a current-voltage characteristic 952 of memory element unit in which data “1” is written, and a resistance element 246. In this example, a transistor is used as the resistance element 246. Further, a case where 3 V is applied between the first conductive layer and the second conductive layer as an operation voltage when reading data will be described.

  In FIG. 14, in a memory cell having a memory element portion in which data of “0” is written, an intersection 954 between the current-voltage characteristic 951 of the memory element part and the current-voltage characteristic 953 of the transistor serves as an operating point. The potential of the node α is V2 (V). The potential of the node α is supplied to the sense amplifier 247. In the sense amplifier 247, the data stored in the memory cell is determined as “0”.

  On the other hand, in a memory cell having a memory element portion in which data of “1” is written, an intersection 955 between the current-voltage characteristic 952 of the memory element part and the current-voltage characteristic 953 of the transistor serves as an operating point. The potential of α is V1 (V) (V1 <V2). The potential of the node α is supplied to the sense amplifier 247. In the sense amplifier 247, the data stored in the memory cell is determined as “1”.

  As described above, the data stored in the memory cell can be determined by reading the resistance-divided potential in accordance with the resistance value of the memory element portion 241.

Note that this embodiment can be freely combined with the structures of the memory element and the semiconductor device including the memory element described in the above embodiment.
(Embodiment 5)

The configuration of the semiconductor device of this embodiment will be described with reference to FIG. As shown in FIG. 12, the semiconductor device 20 of the present invention has a function of communicating data without contact, and controls the power supply circuit 11, the clock generation circuit 12, the data demodulation / modulation circuit 13, and other circuits. A circuit 14, an interface circuit 15, a memory circuit 16, a data bus 17, an antenna (antenna coil) 18, a sensor 21, and a sensor circuit 22 are included.

The power supply circuit 11 is a circuit that generates various power supplies to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The clock generation circuit 12 is a circuit that generates various clock signals to be supplied to each circuit inside the semiconductor device 20 based on the AC signal input from the antenna 18. The data demodulation / modulation circuit 13 has a function of demodulating / modulating data communicated with the reader / writer 19. The control circuit 14 has a function of controlling the memory circuit 16. The antenna 18 has a function of transmitting and receiving an electromagnetic field or a radio wave. The reader / writer 19 controls communication and control with the semiconductor device and processing related to the data. The semiconductor device is not limited to the above-described configuration, and may be a configuration in which other elements such as a power supply voltage limiter circuit and hardware dedicated to cryptographic processing are added.

The memory circuit 16 includes a memory element in which an insulating layer or a phase change layer is sandwiched between a pair of conductive layers. Note that the memory circuit 16 may include only a memory element in which an insulating layer or a phase change layer is interposed between a pair of conductive layers, or may include a memory circuit having another structure. The memory circuit having another configuration corresponds to, for example, one or more selected from DRAM, SRAM, FeRAM, mask ROM, PROM, EPROM, EEPROM, and flash memory.

The sensor 21 is formed of a semiconductor element such as a resistance element, a capacitive coupling element, an inductive coupling element, a photovoltaic element, a photoelectric conversion element, a thermoelectric element, a transistor, a thermistor, or a diode. The sensor circuit 22 detects a change in impedance, reactance, inductance, voltage or current, performs analog / digital conversion (A / D conversion), and outputs a signal to the control circuit 14.
(Embodiment 6)

According to the present invention, a semiconductor device that functions as a processor chip (also referred to as a wireless chip, a wireless processor, a wireless memory, or a wireless tag) can be formed. The semiconductor device of the present invention has a wide range of uses, such as banknotes, coins, securities, certificates, bearer bonds, packaging containers, books, recording media, personal items, vehicles, foods, clothing It can be used in health supplies, daily necessities, medicines and electronic devices.

Banknotes and coins are money that circulates in the market, and include those that are used in the same way as money in a specific area (cash vouchers), commemorative coins, and the like. Securities refer to checks, securities, promissory notes, and the like, and can be provided with a processor chip 90 (see FIG. 13A). The certificate refers to a driver's license, a resident's card, and the like, and can be provided with a processor chip 91 (see FIG. 13B). Personal belongings refer to bags, glasses, and the like, and can be provided with a processor chip 97 (see FIG. 13C). Bearer bonds refer to stamps, gift cards, and various gift certificates. Packaging containers refer to wrapping paper such as lunch boxes, plastic bottles, and the like, and can be provided with a processor chip 93 (see FIG. 13D). Books refer to books, books, and the like, and can be provided with a processor chip 94 (see FIG. 13E). The recording medium refers to DVD software, a video tape, or the like, and can be provided with a processor chip 95 (see FIG. 13F). The vehicles refer to vehicles such as bicycles, ships, and the like, and can be provided with a processor chip 96 (see FIG. 13G). Foods refer to food products, beverages, and the like. Clothing refers to clothing, footwear, and the like. Health supplies refer to medical equipment, health equipment, and the like. Livingware refers to furniture, lighting equipment, and the like. Chemicals refer to pharmaceuticals, agricultural chemicals, and the like. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (TV receivers, flat-screen TV receivers), mobile phones, and the like.

The semiconductor device of the present invention is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin, and is fixed to each article. Since the semiconductor device of the present invention realizes a small size, a thin shape, and a light weight, the design of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device of the present invention in bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, counterfeiting can be prevented. it can. In addition, by providing the semiconductor device of the present invention in packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

Next, one mode of an electronic device in which the semiconductor device of the present invention is mounted will be described with reference to the drawings. An electronic device illustrated here is a mobile phone, which includes housings 2700 and 2706, a panel 2701, a housing 2702, a printed wiring board 2703, operation buttons 2704, and a battery 2705 (see FIG. 12B). The panel 2701 is detachably incorporated in the housing 2702, and the housing 2702 is fitted on the printed wiring board 2703. The shape and dimensions of the housing 2702 are changed as appropriate in accordance with the electronic device in which the panel 2701 is incorporated. A plurality of packaged semiconductor devices are mounted on the printed wiring board 2703, and the semiconductor device of the present invention can be used as one of them. The plurality of semiconductor devices mounted on the printed wiring board 2703 have any one function of a controller, a central processing unit (CPU), a memory, a power supply circuit, a sound processing circuit, a transmission / reception circuit, and the like.

The panel 2701 is connected to the printed wiring board 2703 through the connection film 2708. The panel 2701, the housing 2702, and the printed wiring board 2703 are housed in the housings 2700 and 2706 together with the operation buttons 2704 and the battery 2705. A pixel region 2709 included in the panel 2701 is arranged so as to be visible from an opening window provided in the housing 2700.

As described above, the semiconductor device of the present invention is characterized in that it is small, thin, and lightweight, and the limited space inside the housings 2700 and 2706 of the electronic device can be effectively used due to the above characteristics. .

In addition, since the semiconductor device of the present invention includes a memory element having a simple structure in which an insulating layer is sandwiched between a pair of conductive layers, an electronic device using an inexpensive semiconductor device can be provided. In addition, since the semiconductor device of the present invention can be easily integrated, an electronic device using the semiconductor device including a large-capacity memory circuit can be provided.

In addition, a memory device included in the semiconductor device of the present invention writes data by an optical action or an electrical action, is nonvolatile, and can additionally write data. With the above feature, forgery due to rewriting can be prevented, and new data can be added and written. Therefore, an electronic device using a semiconductor device that achieves high functionality and high added value can be provided.

Note that the housings 2700 and 2706 are examples of the appearance of a mobile phone, and the electronic device according to this embodiment can be modified into various modes depending on functions and uses.

(Embodiment 7)
In this embodiment mode, data reading or writing is described in the storage device having the above structure.

  18 shows a structural example of the memory device of the present invention. A memory cell array 1722 in which memory cells 1721 are provided in a matrix, a circuit 726 having a reading circuit and a writing circuit, a decoder 724, and a decoder 723 are provided. Have. Note that the structure of the memory device 1716 shown here is just an example, and other circuits such as a sense amplifier, an output circuit, a buffer, and an interface for exchanging with the outside may be included.

  The memory cell 1721 includes a first conductive layer connected to the bit line Bx (1 ≦ x ≦ m), a second conductive layer connected to the word line Wy (1 ≦ y ≦ n), an insulating layer, Have The insulating layer is provided as a single layer or a stacked layer between the first conductive layer and the second conductive layer.

  First, operation performed when data is written to a memory element in a passive matrix memory device will be described with reference to FIGS. Data writing is performed by optical action or electrical action. First, the case of writing data by electrical action will be described. Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

  When writing data “1” to the memory cell 1721, first, the memory cell 1721 is selected by the decoders 1723 and 1724 and the selector 1725. Specifically, the decoder 1724 applies a predetermined voltage V2 to the word line W3 connected to the memory cell 1721. In addition, the bit line B 3 connected to the memory cell 1721 is connected to the circuit 1726 by the decoder 1723 and the selector 1725. Then, the write voltage V1 is output from the circuit 1726 to the bit line B3. Thus, the potential (voltage) Vw = V1−V2 is applied between the first conductive layer and the second conductive layer included in the memory cell 1721. By appropriately selecting the potential Vw, the insulating layer provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It is good to change as follows. For example, it may be appropriately selected from the range of (V1, V2) = (0V, 5-15V), or (3-5V, -12--2V). The voltage Vw may be 5 to 15V, or -5 to -15V.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. For example, unselected word lines and unselected bit lines may be set in a floating state. The first conductive layer and the second conductive layer constituting the memory cell must have characteristics such as diode characteristics that can ensure selectivity.

  On the other hand, when data “0” is written to the memory cell 1721, it is not necessary to apply an electrical action to the memory cell 1721. In the circuit operation, for example, as in the case of writing “1”, the memory cells 1721 are selected by the decoders 1723 and 1724 and the selector 1725, but the output potential from the circuit 1726 to the bit line B3 is changed to the selected word line. The voltage is set to the same level as the potential of W3 or the potential of the non-selected word line and does not change the electrical characteristics of the memory cell 1721 between the first conductive layer and the second conductive layer constituting the memory cell 1721 (for example, −5 to 5 V) may be applied.

  Next, a case where data is written by optical action will be described. In this case, the second conductive layer needs to transmit laser light. The insulating layer is irradiated with laser light from the light-transmitting conductive layer side. Here, the insulating layer is destroyed by selectively irradiating a desired portion of the insulating layer with laser light. Since the destroyed insulating layer is insulated, the electric resistance is significantly increased as compared with other portions. In this manner, data is written by utilizing the change in electrical resistance between two conductive films provided with an insulating layer interposed therebetween by laser light irradiation. For example, in the case where an insulating layer not irradiated with laser light is set to “0” data, when writing “1” data, the insulating layer in a desired portion is selectively irradiated with laser light to be destroyed. Increase the electrical resistance.

  In addition, when a conjugated polymer doped with a compound that generates acid by absorbing light (photoacid generator) is used as the insulating layer, when irradiated with laser light, only the irradiated portion increases conductivity. However, the unirradiated part does not have conductivity. Therefore, data is written by utilizing the change in the electrical resistance of the insulating layer by selectively irradiating a desired portion of the insulating layer with laser light. For example, in the case where an insulating layer not irradiated with laser light is set to “0” data, when writing “1” data, a desired portion of the insulating layer is selectively irradiated with laser light to make conductivity. increase.

  With the structure of the present invention in which data is written by laser light irradiation, a large number of memory devices can be easily manufactured. Therefore, an inexpensive memory device and semiconductor device can be provided.

  Next, an operation of reading data from a memory element in a passive matrix memory device will be described (see FIG. 18). In reading data, the electrical characteristics between the first conductive layer and the second conductive layer constituting the memory cell are different between the memory cell having data “0” and the memory cell having data “1”. Use it. For example, the effective electrical resistance between the first conductive layer and the second conductive layer constituting the memory cell having data “0” (hereinafter simply referred to as the electrical resistance of the memory cell) is R0 at the read voltage. A method of reading data by using the difference in electric resistance when the electric resistance of the memory cell having data “1” is R1 in the read voltage will be described. Note that R1 << R0. As the structure of the reading / writing circuit, for example, a circuit 1726 using a resistance element 1746 and a differential amplifier 1747 shown in FIG. 18B can be considered. The resistance element 1746 has a resistance value Rr, and R1 <Rr <R0. A transistor 1748 may be used instead of the resistance element 1746, and a clocked inverter 1749 may be used instead of the differential amplifier (FIG. 18C). The clocked inverter 1749 receives a signal φ or an inverted signal φ that becomes Hi when reading is performed and becomes Lo when it is not performed. Of course, the circuit configuration is not limited to FIG.

  When data is read from the memory cell 1721, first, the memory cell 1721 is selected by the decoders 1723 and 1724 and the selector 1725. Specifically, a predetermined voltage Vy is applied to the word line Wy connected to the memory cell 1721 by the decoder 1724. In addition, the bit line Bx connected to the memory cell 1721 is connected to the terminal P of the circuit 1726 by the decoder 1723 and the selector 1725. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 1746 (resistance value Rr) and the memory cell 1721 (resistance value R0 or R1). Therefore, when the memory cell 1721 has data “0”, Vp0 = Vy + (V0−Vy) × R0 / (R0 + Rr). When the memory cell 1721 has data “1”, Vp1 = Vy + (V0−Vy) × R1 / (R1 + Rr). As a result, in FIG. 18B, Vref is selected to be between Vp0 and Vp1, and in FIG. 18C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Lo / Hi (or Hi / Lo) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier is operated at Vdd = 3V, and Vy = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9, when the memory cell data is “0”, Vp0 = 2.7 V and Vout is Hi, and when the memory cell data is “1”, Vp1 = 0.3V and Lo is output as Vout. Thus, the memory cell can be read.

  According to the above method, the state of the electrical resistance of the insulating layer is read as a voltage value using the difference in resistance value and resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  Next, an operation when data is written to the memory element in the active matrix memory device is described (see FIG. 19).

  FIG. 19 illustrates an example of a structure of the memory device described in this embodiment, which includes a memory cell array 1232 in which memory cells 1231 are provided in a matrix, a circuit 1226, a decoder 1224, and a decoder 1223. The circuit 1226 includes a reading circuit and a writing circuit. Note that the structure of the memory device 1216 shown here is merely an example, and may include other circuits such as a sense amplifier, an output circuit, a buffer, and an interface for external communication.

  The memory cell array 1232 includes a first wiring connected to the bit line Bx (1 ≦ x ≦ m), a second wiring connected to the word line Wy (1 ≦ y ≦ n), a transistor 1210a, and a memory element 1215b. And a memory cell 1231. The memory element 1215b has a structure in which an insulating layer is sandwiched between a pair of conductive layers. The gate electrode of the transistor is connected to the word line, either the source electrode or the drain electrode is connected to the bit line, and the other is connected to one of the two terminals of the memory element. The remaining one terminal of the memory element is connected to a common electrode (potential Vcom).

  First, an operation when data is written by electrical action will be described. Writing is performed by changing the electrical characteristics of the memory cell. The initial state of the memory cell (the state where no electrical action is applied) is data “0”, and the state where the electrical characteristic is changed is “1”. To do.

  Here, a case where data is written to the memory cell 1231 in the nth row and the mth column will be described. When data “1” is written to the memory cell 1231, first, the memory cell 1231 is selected by the decoders 1223 and 1224 and the selector 1225. Specifically, the decoder 1224 applies a predetermined voltage V22 to the word line Wn connected to the memory cell 1231. In addition, the bit line Bm connected to the memory cell 1231 is connected to the circuit 1226 having a reading circuit and a writing circuit by the decoder 1223 and the selector 1225. Then, the write voltage V21 is output from the circuit 1226 to the bit line B3.

  Thus, the transistor 1210a included in the memory cell is turned on, the bit line is electrically connected to the memory element 1215b, and a voltage of approximately Vw = Vcom−V21 is applied. Note that one electrode of the memory element 1215b is connected to a common electrode of the potential Vcom. By appropriately selecting the potential Vw, the insulating layer provided between the conductive layers is changed physically or electrically, and data “1” is written. Specifically, at the read operation voltage, the electrical resistance between the first conductive layer and the second conductive layer in the data “1” state is significantly smaller than that in the data “0” state. It may be changed as described above, or it may be simply short-circuited. The potential may be appropriately selected from the range of (V21, V22, Vcom) = (5-15V, 5-15V, 0V), or (-12 to 0V, -12 to 0V, 3 to 5V). The voltage Vw may be 5 to 15V, or -5 to -15V.

  Note that data “1” is controlled not to be written in the memory cell connected to the non-selected word line and the non-selected bit line. Specifically, a potential (for example, 0 V) for turning off the transistor of the memory cell to be connected is applied to the non-selected word line, and the non-selected bit line is in a floating state or approximately equal to Vcom. A potential may be applied.

  On the other hand, when data “0” is written in the memory cell 1231, it is not necessary to apply an electrical action to the memory cell 1231. In the circuit operation, for example, as in the case of writing “1”, the memory cells 1231 are selected by the decoders 1223 and 1224 and the selector 1225, but the output potential from the circuit 1226 to the bit line B3 is set to the same level as Vcom. Alternatively, the bit line B3 is brought into a floating state. As a result, a small voltage (for example, −5 to 5 V) is applied to the memory element 1215b or no voltage is applied, so that electrical characteristics do not change and data “0” writing is realized.

  Next, a case where data is written by optical action will be described. In this case, the insulating layer is irradiated with laser light from the light-transmitting conductive layer side with a laser irradiation apparatus. As the laser irradiation device, a passive matrix storage device similar to that described with reference to FIG. 8 may be used.

  In the case where an organic compound material is used for the insulating layer, the insulating layer is oxidized or carbonized and insulated by laser light irradiation. Then, the resistance value of the memory element irradiated with the laser light increases, and the resistance value of the memory element not irradiated with the laser light does not change. Further, when a conjugated polymer material doped with a photoacid generator is used, conductivity is imparted to the insulating layer by laser light irradiation. That is, conductivity is given to the memory element irradiated with the laser beam, and conductivity is not given to the memory element not irradiated with the laser beam.

  Next, an operation when data is read by electrical action will be described. Here, the circuit 1226 includes a resistance element 1246 and a differential amplifier 1247. Note that the structure of the circuit 1226 is not limited to the above structure, and may have any structure.

  Next, an operation when data is read by an electrical action in an active matrix memory device will be described. Data is read by utilizing the fact that the electrical characteristics of the memory element 1215b are different between the memory cell having the data “0” and the memory cell having the data “1”. For example, the electrical resistance of the memory element constituting the memory cell having data “0” is R0 at the read voltage, and the electrical resistance of the memory element constituting the memory cell having data “1” is R1 at the read voltage. A method of reading using the difference will be described. Note that R1 << R0. As the reading / writing circuit, for example, a circuit 1226 using a resistance element 1246 and a differential amplifier 1247 shown in FIG. The resistance element has a resistance value Rr, and R1 <Rr <R0. A transistor 1249 may be used instead of the resistance element 1246, and a clocked inverter 1248 may be used instead of the differential amplifier (FIG. 19C). Of course, the circuit configuration is not limited to FIG.

  When data is read from the memory cell 1231 in the xth row and the yth column, first, the memory cell 1231 is selected by the decoders 1223 and 1224 and the selector 1225. Specifically, the decoder 1224 applies a predetermined voltage V24 to the word line Wy connected to the memory cell 1231 to turn on the transistor 1210a. In addition, the bit line Bx connected to the memory cell 1231 is connected to the terminal P of the circuit 1226 by the decoder 1223 and the selector 1225. As a result, the potential Vp of the terminal P becomes a value determined by resistance division by the resistance element 1246 (resistance value Rr) and the memory element 1215b (resistance value R0 or R1) of Vcom and V0. Therefore, when the memory cell 1231 has data “0”, Vp0 = Vcom + (V0−Vcom) × R0 / (R0 + Rr). When the memory cell 1231 has data “1”, Vp1 = Vcom + (V0−Vcom) × R1 / (R1 + Rr). As a result, in FIG. 19B, Vref is selected to be between Vp0 and Vp1, and in FIG. 19C, the change point of the clocked inverter is selected to be between Vp0 and Vp1. Thus, Lo / Hi (or Hi / Lo) is output as the output potential Vout according to the data “0” / “1”, and reading can be performed.

  For example, the differential amplifier is operated at Vdd = 3V, and Vcom = 0V, V0 = 3V, and Vref = 1.5V. Assuming that R0 / Rr = Rr / R1 = 9 and the on-resistance of the transistor 1210a can be ignored, when the data in the memory cell is “0”, Vp0 = 2.7V and Vout is output as Hi. When the data of “1” is “1”, Vp1 = 0.3 V and Lo is output as Vout. Thus, the memory cell can be read.

  According to the above method, the voltage value is read by utilizing the difference in resistance value of the memory element 1215b and the resistance division. Of course, the reading method is not limited to this method. For example, in addition to using the difference in electrical resistance, reading may be performed using the difference in current value. In addition, when the electrical characteristics of the memory cell have data “0” and “1” and diode characteristics with different threshold voltages, reading may be performed using the threshold voltage difference.

  Since the memory element having the above structure and the memory device and the semiconductor device including the memory element are nonvolatile memories, it is not necessary to incorporate a battery for holding data, and a small, thin, and lightweight semiconductor device Can be provided. In addition, data can be written (added) by using the insulating material used in the above embodiment as an insulating layer, but data cannot be rewritten. Therefore, it is possible to provide a storage device and a semiconductor device that prevent forgery and ensure security.

  Note that this embodiment mode can be freely combined with the structures of the memory element, the memory device including the memory element, and the semiconductor device described in the above embodiment modes.

The conceptual diagram explaining this invention. 3A and 3B illustrate a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 8A to 8D illustrate a method for manufacturing a semiconductor device of the present invention. 6A and 6B illustrate a semiconductor device of the present invention. 3A and 3B illustrate a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 8A and 8B illustrate a method for manufacturing a memory device of the present invention. 8A and 8B illustrate a method for manufacturing a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention. 3A and 3B illustrate a memory device of the present invention.

Claims (14)

A first conductive layer;
A first insulating layer in contact with a side edge of the first conductive layer;
A second insulating layer provided on and in contact with the first conductive layer and the first insulating layer;
A second conductive layer provided on the second insulating layer,
The second insulating layer is made of an insulating material that fluidizes above the glass transition temperature ,
The semiconductor device according to claim 1, wherein the first insulating layer has higher wettability with respect to the composition in which the insulating material is fluidized than the first conductive layer.   2. The semiconductor device according to claim 1, further comprising a liquid repellent layer between the first conductive layer and the second insulating layer.   3. The semiconductor device according to claim 2, wherein the liquid repellent layer includes a substance having a fluorocarbon group.   3. The semiconductor device according to claim 2, wherein the liquid repellent layer includes a substance containing a silane coupling agent.   5. The semiconductor device according to claim 4, wherein the silane coupling agent has an alkyl group.   6. The semiconductor device according to claim 1, wherein the second insulating layer includes an organic material. 7. The device according to claim 1, wherein after applying a voltage between the first conductive layer and the second conductive layer, the first conductive layer and the second conductive layer are A semiconductor device characterized by being in partial contact. 8. The film thickness of the second insulating layer is changed according to claim 1, after a voltage is applied between the first conductive layer and the second conductive layer. 9. A semiconductor device. Forming a first conductive layer;
Forming a first insulating layer in contact with a side edge of the first conductive layer;
A second insulating layer formed in contact with the first conductive layer and the first insulating layer,
Forming a second conductive layer on the second insulating layer;
The second insulating layer is made of an insulating material that fluidizes above the glass transition temperature ,
The method for manufacturing a semiconductor device, wherein the first insulating layer has higher wettability to the composition in which the insulating material is fluidized than the first conductive layer. Forming a first conductive layer having a liquid repellent layer;
Forming a first insulating layer in contact with a side edge of the first conductive layer;
A second insulating layer formed in contact with the first conductive layer and the first insulating layer,
The second conductive layer is formed on the second insulating layer,
The second insulating layer is made of an insulating material that fluidizes above the glass transition temperature,
The method for manufacturing a semiconductor device, wherein the first insulating layer has higher wettability to the composition in which the insulating material is fluidized than the first conductive layer .   The method for manufacturing a semiconductor device according to claim 10, wherein the liquid repellent layer includes a substance having a fluorocarbon group.   11. The method for manufacturing a semiconductor device according to claim 10, wherein the liquid repellent layer includes a substance containing a silane coupling agent.   The method for manufacturing a semiconductor device according to claim 12, wherein the silane coupling agent includes an alkyl group.   14. The method for manufacturing a semiconductor device according to claim 9, wherein the second insulating layer includes an organic material.

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