JP4930500B2 - Semiconductor device and oscillator - Google Patents

Description

The present invention relates to a semiconductor device and an oscillator, and more specifically, a semiconductor device in which a resin layer is formed on a semiconductor substrate including an integrated circuit, and a passive element including a Cu wiring layer is formed on the surface of the resin layer;
The present invention relates to an oscillator formed by this passive element in a semiconductor device.

Conventionally, in a voltage controlled oscillator formed in a semiconductor device having a semiconductor substrate and a multilayer wiring layer provided on the semiconductor substrate, an output terminal and a spiral inductor provided in the multilayer wiring layer and connected to the output terminal And a variable capacitor that includes a region directly under the spiral inductor, is formed in a region that does not include the central axis of the spiral inductor, and is connected in parallel to the spiral inductor to form a resonance circuit together with the spiral inductor,
There is known a voltage-controlled oscillator configured to include (for example, see Patent Document 1).

Japanese Patent Laying-Open No. 2005-6153 (5th page, FIGS. 1 and 2)

In Patent Document 1, such a resonant circuit is configured by a spiral inductor formed on the surface of a multilayer wiring layer provided on a semiconductor substrate and a variable capacitor provided in a semiconductor integrated circuit including the semiconductor substrate and the multilayer wiring layer. Has been. In general, since such a spiral inductor is formed of Al wiring, for example, the specific resistance is about 30% as compared with Cu wiring.
There is a problem that the phase noise characteristic cannot be improved because the Q value of the inductor is low to a large extent.

In addition, since the above-described variable capacitor is formed in a semiconductor integrated circuit, the capacitance and the variable range can be reduced due to restrictions on the materials that can be used for the dielectric forming the capacitor and restrictions on the size of the counter electrode. There is a limit, and there are problems such as realizing an oscillator having a frequency in a low frequency region and being unable to widen the frequency selection range.

SUMMARY OF THE INVENTION The object of the present invention is to solve the above-mentioned problems, an oscillator having a passive element having a high Q value, having excellent phase noise characteristics and capable of widening the frequency selection range, and an oscillator including the oscillator. A semiconductor device capable of forming a chip size package is provided.

The semiconductor device of the present invention includes a semiconductor substrate including an integrated circuit as an active element and a plurality of connection electrodes electrically connected to the integrated circuit, and a surface of the semiconductor substrate on which the connection electrodes are formed. A first resin layer formed avoiding the connection electrode; a connection wiring layer formed between the semiconductor substrate and the first resin layer and connected to one of the plurality of connection electrodes; A Cu wiring layer having one end connected to the connection wiring layer and formed on the surface of the first resin layer; a passive element comprising the connection wiring layer and the Cu wiring layer; and a surface of the Cu wiring layer. And a second resin layer electrically connected to some of the plurality of connection electrodes and partly protruding from the second resin layer.

According to this invention, the connection wiring layer formed between the semiconductor substrate and the first resin layer and connected to one of the plurality of connection electrodes, and formed on the surface of the first resin layer A passive element is constituted by the Cu wiring layer. Since Cu has a specific resistance of about 30% smaller than that of a conventionally used Al wiring, when a passive element is configured using a Cu wiring,
It is possible to increase the value, and from this, it is possible to improve the phase noise characteristics if it is used in a resonance circuit such as an oscillator.

Further, in the case where the semiconductor substrate is a semiconductor chip that is scribe-isolated from the wafer, the passive element is formed by a Cu wiring layer on the surface of the first resin layer formed on the semiconductor substrate. Since the chip can be formed over most of the planar shape (planar area) of the chip, the planar area can be increased, the Cu wiring width can be increased, and the wiring resistance can be further reduced.

Further, since the uppermost Cu wiring layer is covered with the second resin layer except for a part of the external terminals, it is possible to protect passive elements including active elements.

Further, the present invention is characterized in that the passive element is a spiral inductor made of a Cu wiring layer formed on the surface of the first resin layer.

Thus, by forming the spiral inductor with the Cu wiring layer, as described above, the specific resistance can be made smaller than that of the spiral inductor formed by the conventional Al wiring. Since it can be formed by plating, the thickness can be increased, so that the wiring resistance can be further reduced. As is well known, the Q value is
Since it is proportional to the reactance and inversely proportional to the resistance value, the Q value can be increased by lowering the resistance value of the spiral inductor.

Further, since the spiral inductor pattern is formed by Cu wiring on the surface of the first resin layer formed on the semiconductor substrate, it can be spaced from the semiconductor substrate. As a result, the loss due to the parasitic capacitance component generated between the spiral inductor pattern and the semiconductor substrate can be reduced, and as a result, the Q value can be increased.

Further, suppose that the above-described spiral inductor is used for an oscillator. It is known that the phase noise characteristic of an oscillator is inversely proportional to the square of the Q value, and the phase noise (phase noise) can be significantly reduced by increasing the Q value. The Q value used when considering the phase noise characteristic is a value representing the loss of the entire oscillation circuit called a load Q. However, in the LC resonance circuit using the spiral inductor of the present invention, the Q value of the spiral inductor portion is dominant. Become.
Therefore, the phase noise can be greatly reduced by increasing the Q value of the spiral inductor section.

The passive element is a capacitor including the connection wiring layer, the Cu wiring layer, and a first resin layer sandwiched between regions where the connection wiring layer and the Cu wiring layer intersect, A capacitor is connected in parallel with a variable capacitor provided in the integrated circuit.
Here, the first resin layer constituting the capacitor is a dielectric in the multilayer capacitor, and the Cu wiring layer and the connection wiring layer correspond to electrodes sandwiching the dielectric.

As described above, by providing the capacitor outside the integrated circuit, the capacitance can be increased. It is known that the oscillation frequency decreases as the capacitance increases. As a result, an oscillator in a low frequency region can be realized.

In addition, the variable capacitor formed inside the integrated circuit is limited in size and dielectric constant, which limits the capacitance. However, the frequency selection range can be expanded by providing the capacitor according to the present invention. In addition, since the area of the Cu wiring layer formed on the upper surface of the semiconductor substrate can be increased, the capacitance can be increased.

Furthermore, in addition to the variable capacitor, a capacitor composed of a Cu wiring layer can be provided in parallel, so that the setting range of the capacitance of the capacitor can be expanded. There is an effect that can be.

The passive element includes a spiral inductor made of a first Cu wiring layer formed on the surface of the first resin layer, and a second Cu wiring layer formed on the surface of the first resin layer. ,
The capacitor includes: a connection wiring layer; and a capacitor including a first resin layer sandwiched between regions where the second Cu wiring layer and the connection wiring layer intersect.

Thus, by forming the spiral inductor and the capacitor by the Cu wiring layer, it is possible to have both the effect of forming the spiral inductor and the effect of forming the capacitor.

In addition, since the first Cu wiring layer forming the spiral inductor and the second Cu wiring layer forming the capacitor are formed on substantially the same plane of the first resin layer, the two passive elements are formed. While provided, these Cu wiring layers can be formed in the same process, and the manufacturing efficiency can be increased.

Furthermore, it is preferable that the semiconductor device is sealed by the second resin layer except for a part of the external terminals.

According to such a structure, the semiconductor device includes the Cu wiring layer constituting the passive element and includes the second wiring layer.
Therefore, the second resin layer can be packaged without being packaged again, and a small and thin semiconductor device packaged in the size of a semiconductor chip is provided. be able to.

The oscillator according to the present invention includes a semiconductor substrate including an integrated circuit as an active element and a plurality of connection electrodes electrically connected to the integrated circuit, and a surface of the semiconductor substrate on which the connection electrodes are formed. The first resin layer formed avoiding the connection electrode, and the spiral resin on the surface of the first resin layer, the spiral inductor constituting the resonance circuit, or the capacitor described above,
Alternatively, a passive element configured by connecting both in parallel and an external terminal connected to some of the plurality of connection electrodes are provided.

According to the present invention, by providing a spiral inductor or a capacitor as a passive element composed of the above-described Cu wiring outside the integrated circuit, the passive element having a high Q value is provided, the phase noise characteristic is excellent, and the frequency selection range. Can be realized.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
1 to 3 show a semiconductor device according to the first embodiment of the present invention, and FIGS. 4 to 6 show the second embodiment.
It is a semiconductor device concerning.
(Embodiment 1)

FIG. 1 is a plan view of the semiconductor device according to the first embodiment, and FIG. 2 is a cross-sectional view taken along the line AA of FIG. Here, FIG. 1 shows a state seen through the resist layer 75 and the coating film 76 as the second resin layer shown in FIG. 1 and 2 illustrate a voltage controlled oscillator as an example of the embodiment of the present invention.

1 and 2, a semiconductor device 1 has an integrated circuit 1 as an active element as a basic configuration.
2 and an Al wiring for connecting a circuit element group (not shown) constituting the integrated circuit 12, and a plurality of connection electrodes connected to the Al wiring and exposed on the surface (connection electrodes 14 and 15 are shown in FIG. 2) In order to connect the spiral inductors 40 and 50 as passive elements formed on the upper surface of the passivation film (SiN) 16 that opens the connection electrodes and covers the integrated circuit 12, and the integrated circuit 12 or the spiral inductor 40 and an external circuit. External terminals 81-86.

The semiconductor device 1 is formed by arranging a plurality of wafers (not shown).
Each semiconductor chip is separated by scribing. Here, the configuration in the form of a semiconductor chip is described.

The integrated circuit 12 includes a group of circuit elements for controlling the semiconductor device 1 such as a transistor, a variable capacitor, and a constant current circuit (not shown). The entire surface of the semiconductor substrate 10 including the integrated circuit 12 is covered with a passivation film 16, but connection electrodes (for example, the integrated circuit 12, the external terminals 81 to 86, and the spiral inductors 40 and 50 are connected to each other). (In FIG. 2, only the connection electrodes 14 and 15 are illustrated, and the connection electrode will be described as a representative of the plurality of connection electrodes).
The passivation film 16 is made of SiN, SiO ₂ , MgO, or the like, and has connection terminals (
14 and 15) are made of Al.

On the upper surface of the semiconductor substrate 10, that is, on the surface of the passivation film 16, there is a connection wiring layer 25.
, 26 are formed. The connection wiring layers 25 and 26 are formed of the passivation layer 16 and Cu.
For example, nickel (Ni), tungsten (W), chromium (Cr), titanium (Ti), vanadium (Pd), or a single metal or a plurality of these are provided. Sputtered with the alloy used.

A Cu connection wiring layer 55 is formed on the upper surface of the connection wiring layer 26. The Cu connection wiring layer 55 is formed by a film forming means such as electrolytic Cu plating, and is preferably formed with a thickness of about 6 μm. In a range covering the upper surface of the Cu connection wiring layer 55 from the upper surface of the passivation film 16, the first
The resin layer 70 (hereinafter, simply referred to as the resin layer 70) is formed.

The resin layer 70 has a stress relaxation function, and a polyimide resin is preferably used. In addition, a silicon-modified polyimide resin, an epoxy resin, a silicon-modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (POB) It is also possible to employ a resin such as
The resin layer 70 preferably has a thickness of 20 μm or more.

The spiral inductors 40 and 50 are formed on the surface of the first resin layer 70 to have the spiral shape shown in FIG.
It is symmetrical with respect to the center line g of each interval. Therefore, the spiral inductor 40 will be described as an example.

The outer end portion 41 of the spiral inductor 40 is in a range covered by the resin layer 70 and is connected to the connection electrode 14 via the lower Cu wiring layer 30 and has a rising portion toward the inside of the spiral shape. The surface of the resin layer 70 is extended. A spiral inductor 40 having a spiral shape is formed on the surface of the resin layer 70.
An inner end 42 of the spiral inductor 40 is connected to a rising portion from the Cu connection wiring layer 55.

On the other hand, one end of the Cu connection wiring layer 55 is bifurcated into a spiral inductor 4.
0 and the spiral inductor 50 are connected to the inner end portions 42 and 52 of the spiral inductor 50 (see FIG. 1), and the other end portion extends to the surface of the resin layer 70 to form a connection portion 61 with the external terminal 81. To do. The outer end portion 51 of the spiral inductor 50 is connected to another connection electrode (14) formed on the semiconductor substrate 10.

On the surface of the resin layer 70, a resist layer 75 as a second resin layer covering the spiral inductors 40 and 50 is formed. The resist layer 75 is a solder resist layer, and only the region where the external terminal 81 is formed is opened, and the other region is sealed. By providing the resist layer 75, corrosion of the Cu wiring layer including the spiral inductors 40 and 50 and the connecting portion 61 is prevented, and electrical failure is prevented.

The semiconductor device 1 is provided with a plurality of external terminals. In the present embodiment, six external terminals 81 are provided.
To 86 are provided (see FIG. 1). The external terminals 81 to 86 are connected to connection electrodes corresponding to each of a plurality of connection electrodes provided on the semiconductor substrate 10, the external terminal 81 is a Vdd terminal, the external terminal 82 is an output terminal OUT2, and the external terminal 83 is GND. Terminal, external terminal 8
4 is a Vc terminal, an external terminal 85 is a GND terminal, and an external terminal 86 is an output terminal OUT1 (see also FIG. 3).

Since the basic structures of the external terminals 81 to 86 and the periphery are the same, the external terminal 81 will be described as an example. The resist layer 75 is provided with an opening for forming the external terminal 81, and the connection portion 61 exposed in the opening is a land 62. This land 62
An external terminal 81 is formed inside.

The external terminal 81 is a metal having conductivity, and is, for example, solder for melting and making an electrical connection. In addition to the solder, it is possible to form either a soft solder or a hard solder. In this embodiment,
The external terminal 81 has a spherical shape and employs solder balls.

A coating film 76 is formed on the surface of the resist layer 75. The coating film 76 is formed of external terminals 81-8.
6 is covered (the lower part of the external terminal in FIG. 2). The covering film 76 has a portion formed on the surface of the resist layer 75 and a portion that rises from this portion and covers the base portion of the external terminals 81 to 86, and reinforces the external terminals 81 to 86. Furthermore, after the semiconductor device 1 is mounted on a circuit board or the like, the stress concentration on the external terminals can be dispersed by the coating film 76.

The semiconductor device 1 according to this embodiment is configured as described above, and the manufacturing method thereof will be briefly described below with reference to FIG. In addition, about each component mentioned above, what was illustrated is demonstrated on behalf of it.
First, connection wiring layers 25 and 26 are formed by sputtering on the surface of the semiconductor substrate 10 on which the passivation film 16 and the connection electrodes 14 and 15 are formed. The connection electrodes 14 and 15 and the connection wiring layers 25 and 26 are in an electrically connected state. At this time, the connection wiring layers 25 and 26 are formed on the entire continuous surface.

Subsequently, a Cu plating resist is applied to the surfaces of the connection wiring layers 25 and 26, patterned into a predetermined shape of the lower Cu wiring layers 41 and 55 by an exposure process, and the lower Cu wiring layers 41 and 55 are formed by electrolytic Cu plating. Form. Then, the Cu plating resist is removed, unnecessary portions of the connection wiring layers 25 and 26 having the same planar shape as the Cu wiring layers 41 and 55 are removed, and the Cu wiring layer 41 is removed.
, 55 are formed in the same plane shape as the connection wiring layers 25, 26.
Subsequently, a first resin layer 70 (polyimide resin) is applied to the entire surface.

Here, the first resin layer 70 is once formed to a thickness up to the end 41 of the spiral inductor 40 and the surface of the Cu connection wiring layer 55 (this resin layer is referred to as a first layer). Subsequently, the first resin layer 70 is opened by exposure processing or the like in the shape of a portion where the end portion 41 and the Cu connection wiring layer 55 are not raised. Then, the connection wiring layers 25 and 26 are formed on the entire surface of the opened portion and the uppermost layer of the first layer by sputtering, and a plating resist is applied on the upper surface thereof, followed by patterning, and the surfaces of the connection wiring layers 25 and 26 are formed. Then, electrolytic Cu plating forms a portion of the Cu wiring layer where the end portion 41 and the Cu connection wiring layer 55 are not raised. And these C
A second layer having the remaining thickness of the first resin layer 70 including the upper surfaces of the u wiring layer and the Cu connection wiring layer 55 is applied to the entire surface. Through this step, the total thickness of the first resin layer 70 is formed.

Next, the first resin layer 70 (corresponding to the second layer) is opened at the rising portion of the spiral inductor 40 and the rising portion of the Cu connection wiring layer 55, and the first resin layer 70 is After the wiring layer is sputtered again on the upper layer, a plating resist is applied and patterned into the spiral shape (including the rising portion) of the spiral inductor 40 and the shape of the rising portion and the connecting portion 61 of the Cu connection wiring layer 55, and electrolytic Cu The spiral inductor 40 and the connecting portion 61 are formed by plating. Then, unnecessary portions of the plating resist and the sputter wiring layer are removed.

Subsequently, a resist (solder resist) is applied to the surface of the first resin layer 70 including the surfaces of the spiral inductor 40 and the connection portion 61 to form a resist layer 75. A land 62 is opened in the resist layer 75. After the external terminals 81 made of solder balls are formed on the lands 62, a coating film 76 as a fundamental reinforcing layer is formed on the surface of the resist layer 75. The covering film 76 is preferably formed of a polyimide resin.

Next, a circuit configuration of the semiconductor device 1 manufactured by the above-described structure and method will be described with reference to FIG. The semiconductor device 1 described in the present embodiment is characterized in that the spiral inductors 40 and 50 are formed of the Cu wiring layer, and can be applied to various circuits. The spiral inductors 40 and 50 are used. Since it is suitable for a voltage controlled oscillator, a voltage controlled oscillator will be described as a representative example.

FIG. 3 is a circuit diagram showing a basic circuit configuration of the voltage controlled oscillator 90 formed in the semiconductor device 1 according to the first embodiment. In FIG. 3, the voltage controlled oscillator 90 includes a pair of Cu wirings in which the monolithic circuit region 92 in the integrated circuit 12 and the spiral inductors 40 and 50 formed on the upper surface of the integrated circuit 12 are formed as described above. Layer region 91 (passive device region)
It is composed of.

The voltage controlled oscillator 90 is connected to a power supply potential terminal Vdd (hereinafter referred to as Vdd terminal), a variable potential terminal Vc (hereinafter referred to as Vc terminal) and a ground potential terminal GND (hereinafter simply referred to as GND terminal). Yes. The voltage-controlled oscillator 90 includes spiral inductors 40 and 50, two variable capacitors 96, N-channel transistors 93 and 94 as negative resistance units, and a current adjustment unit 95 from the Vdd terminal to the GND terminal. Are connected in this order.

One end of the spiral inductors 40 and 50 is connected to the Vdd terminal, and the other end is connected to one end of the variable capacitor 96.
In the negative resistance portion, the drain of the N-channel transistor 93 is connected to the output terminal OUT1, and the gate is connected to the output terminal OUT2. N channel transistor 94
The drain is connected to the output terminal OUT2, and the gate is connected to the output terminal OUT1. Further, a buffer amplifier 97 that amplifies the output signal immediately before the output terminals OUT1 and OUT2.
98.

The voltage controlled oscillator 90 having the circuit configuration as described above is connected to the Vdd terminal and the GND terminal so that when a voltage is applied to the LC resonance circuit including the spiral inductors 40 and 50 and the two variable capacitors 96, the LC Resonance circuit complementary resonance signal to output terminal OUT
1 and the output terminal OUT2. However, the oscillation attenuates in this state.

For this purpose, a positive variable potential is applied to the Vc terminal, a ground potential is applied to the GND terminal to supply current, and a negative resistance portion is provided to oscillate a resonance signal permanently in the LC resonance circuit. be able to.

Therefore, according to the first embodiment described above, the first resin layer 70 formed on the semiconductor substrate 10.
Spiral inductors 40 and 50 as passive elements are formed by Cu wiring layers on the surface. The Cu wiring layer has a specific resistance of about 30% smaller than that of a conventionally used Al wiring layer, and since this Cu wiring layer is formed by electrolytic Cu plating, it can be made thicker. The wiring resistance can be further reduced.

Further, when the semiconductor substrate 10 is a semiconductor chip that is scribe-separated from the wafer, the spiral inductors 40 and 50 are configured by a Cu wiring layer on the surface of the first resin layer 70 formed on the semiconductor substrate 10. Therefore, the planar shape of the semiconductor chip (
Therefore, the width of the Cu wiring layer constituting the spiral inductors 40 and 50 can be increased, and the wiring resistance can be further reduced.

As is well known, since the Q value is proportional to the reactance and inversely proportional to the resistance value, the Q value can be increased by reducing the wiring resistance of the spiral inductors 40 and 50.
Further, it is known that the phase noise characteristic in the resonance circuit of the voltage controlled oscillator 90 of the present embodiment is inversely proportional to the square of the Q value. However, the Q value used in the phase noise characteristic of the oscillation circuit is a value representing the loss of the entire circuit called the load Q, but in this embodiment, the contribution of the spiral inductor portion is the largest, so the Q value of the spiral inductor is You may discuss it. Therefore, the phase noise characteristic (phase noise) can be reduced by increasing the Q value of the spiral inductor section.

In addition, according to such a structure, the semiconductor device 1 is further packaged because the spiral inductors 40 and 50 are sealed with the resist layer 75 except for a part of the external terminals 81 to 86. In addition, sealing characteristics equivalent to those of packaging mounting can be obtained, corrosion of the internal wiring layer can be prevented, and a semiconductor chip-sized resin-sealed small semiconductor device can be provided. .

Furthermore, since the coating film 76 is formed on the surface of the resist layer 75, still better sealing characteristics can be obtained, and the external terminals 81 to 86 can be fundamentally reinforced.
In addition to increasing the fixing strength (connection strength) of 86, the connection stress can be dispersed during mounting on the circuit board.
(Embodiment 2)

Subsequently, a semiconductor device according to Embodiment 2 of the present invention will be described with reference to the drawings. The second embodiment has a feature in that a capacitor is provided in addition to a spiral inductor as a passive element using a Cu wiring layer as compared with the first embodiment described above. The formation method is the same as that of the first embodiment (see FIGS. 1 and 2) or the range of application, and detailed description thereof is omitted, and parts having the same configuration are denoted by the same reference numerals.

4 and 5 show the semiconductor device 100 according to the second embodiment. FIG. 4 is a plan view thereof, and FIG.
These are sectional drawings which show the BB cut surface represented by FIG. 4 and 5, the semiconductor substrate 1
A passivation film 16 and a connection electrode 17 are formed on the uppermost layer of 0, connection wiring layers 125 and 126 are formed on the upper surface, and a lower Cu wiring layer 141 and lower layer are formed on the upper surface. 156 is formed.

On the upper surface of the connection wiring layer 126, lower electrode portions 156 of the capacitors C1 and C2 that are continuous with the Cu connection wiring layer 155 made of Cu plating are formed. As shown in FIG. 4, the Cu connection wiring layer 155 is bifurcated from the middle of the extension of the lower electrode portion 156, and one end portion is connected to the end portion 142 of the spiral inductor 140. The other end is connected to the end 152 of the spiral inductor 150.

The other end 141, 151 of each of the spiral inductors 140, 150 is
It is connected to the GND terminal in the same structure as the connection structure of the end portion 41 of the spiral inductor 40 and the connection electrode 14 according to the first embodiment (see FIG. 2) (see also FIG. 6).
A first resin layer 70 is formed on the upper surface of the passivation film 16, and spiral inductors 140 and 150 made of a first Cu wiring layer and capacitors C1 and C2 made of a second Cu wiring layer are formed on the uppermost layer. The upper electrode part 165 which comprises is formed.

The planar configuration of the spiral inductors 140 and 150 is the same as that of the first embodiment (see FIG. 1). The upper electrode portion 165 constituting the capacitors C1 and C2 is formed by extending a Cu wiring layer 164. In this embodiment, the capacitors C1 and C2 are formed with the same size.

Here, the configuration of the capacitors C1 and C2 will be described. Since the capacitors C1 and C2 have the same configuration, the capacitor C1 will be described as an example. A part of the lower Cu connection wiring layer 155 and a part of the upper Cu wiring layer 164 are formed so as to intersect in the plane direction. In this intersection, the upper layer is the upper electrode portion 165 of the capacitor, and the lower layer is the lower electrode portion 156. The first resin layer 70 in the region sandwiched between the upper electrode portion 165 and the lower electrode portion 156 is the capacitor. The capacitors C1 and C2 are formed.

The upper surfaces of the spiral inductors 140 and 150 and the upper electrode portion 165 described above are covered with a second resin layer (resist layer) 75. An external terminal 83 and a coating film 76 are formed. The external terminals 81 to 86 are the external terminal 83 shown in the figure and the first embodiment described above (
It is formed with the same structure as the external terminal 81 of FIG.

Next, the circuit configuration of the semiconductor device 100 having the structure according to the second embodiment will be described with reference to FIG. The semiconductor device 100 described in the present embodiment is characterized in that the spiral inductors 140 and 150 and the capacitors C1 and C2 are formed using a Cu wiring layer, and the first embodiment (see FIG. 3). Similarly to the above, a voltage controlled oscillator will be described as an example.

FIG. 6 is a circuit diagram showing a basic circuit configuration of the voltage controlled oscillator 190 in the semiconductor device 100 according to the second embodiment. Reference is also made to FIG. 4 and 6, the voltage controlled oscillator 1
Reference numeral 90 denotes a monolithic circuit area (active element area) 9 in the integrated circuit 12 as described above.
2 and spiral inductors 140 and 150 stacked on the upper surface of the integrated circuit 12 and a Cu wiring layer region (passive element region) 91 in which the capacitors C1 and C2 are formed.

The voltage controlled oscillator 190 includes a power supply potential terminal Vdd (hereinafter referred to as Vdd terminal), a variable potential terminal Vc (hereinafter referred to as Vc terminal), and a ground potential terminal GND1 (hereinafter simply referred to as GND1).
Terminal). The voltage controlled oscillator 190 includes spiral inductors 140 and 150, capacitors C1 and C2, two variable capacitors 96, and N-channel transistors 93 and 94 serving as negative resistance units from the Vdd terminal to the GND1 terminal. ,
The current adjustment unit 95 is connected in this order.

One end of the spiral inductors 140 and 150 is connected to the Vdd terminal, the other end is connected to one end of each of the capacitors C1 and C2, and one end of each of the capacitors C1 and C2 is connected to the Gdd terminal.
The other end of the variable capacitor 96 is connected to the ND2 terminal. Therefore, the capacitors C1 and C2 and the variable capacitor 96 are electrically connected in parallel.

In the negative resistance portion, the drain of the N-channel transistor 93 is connected to the output terminal OUT1, and the gate is connected to the output terminal OUT2. N channel transistor 94
The drain is connected to the output terminal OUT2, and the gate is connected to the output terminal OUT1.

The operation of the voltage controlled oscillator 190 is basically the same as that of the first embodiment described above, but is different from the first embodiment in that capacitors C1 and C2 are added, and an additional capacitor is formed in the LC resonance circuit. It will be done.

Therefore, according to the second embodiment described above, by providing the capacitors C1 and C2 in parallel to the variable capacitor 96 outside the integrated circuit 12, it is possible to increase the capacitance. It is known that the oscillation frequency decreases as the capacitance increases. As a result, an oscillator in a low frequency region can be realized.

The variable capacitor 96 formed in the integrated circuit 12 is limited in size and dielectric constant and has a limited capacitance. However, by providing the capacitors C1 and C2 according to the present embodiment, a frequency selection range is provided. In addition, since the upper electrode 165 and the lower electrode portion 156 formed on the semiconductor substrate 10 can easily be increased in area, the capacitances of the capacitors C1 and C2 can be increased.

Further, by adding the capacitors C1 and C2 in addition to the variable capacitor 96, the setting range of the capacitance of the capacitor can be expanded, so that the frequency band of the voltage controlled oscillator 190 can be expanded.

In addition, according to such a structure, as in the first embodiment, it is possible to obtain a sealing characteristic equivalent to that of packaging mounting without re-packaging and prevent corrosion of the internal wiring layer. In addition, a semiconductor chip-sized resin-sealed small semiconductor device can be provided.

Furthermore, the spiral inductors 140 and 150 and the upper electrode portion 1 of the capacitors C1 and C2
Since 65 is formed on the same surface of the first resin layer 70, it can be formed in the same process when the upper Cu wiring layer is formed. Therefore, even if two passive elements are formed, they can be manufactured without increasing the manufacturing process.

It should be noted that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.
That is, although the present invention has been illustrated and described with particular reference to particular embodiments, it is not intended to depart from the technical spirit and scope of the invention. Various modifications can be made by those skilled in the art in terms of materials, combinations thereof, and other detailed configurations.

Therefore, the description limited to the shape, material, process order and the like disclosed above is an example for easy understanding of the present invention, and does not limit the present invention. Descriptions in the names of members from which some or all of the limitations, such as materials, combinations, and order of steps, are removed, are included in the present invention.

For example, in Embodiment 2 described above, the spiral inductor 1 is formed on the surface of the first resin layer 70.
40 and 150 and capacitors C1 and C2 are disposed, but only capacitors C1 and C2 may be disposed.

In the first and second embodiments, the spiral inductors 40, 50 and 140, 15 are used.
Although 0 is used as an inductor of an LC resonator, it can be used as a spiral planar antenna and applied as a semiconductor device for communication.

Furthermore, in addition to the spiral inductor and capacitor described above, it is possible to form other passive elements made of a Cu wiring layer and to combine circuit elements connected to these elements.

Therefore, according to the first and second embodiments described above, an oscillator having a passive element having a high Q value and excellent phase noise characteristics and capable of widening the frequency selection range, and this oscillator are provided. A semiconductor device capable of forming the package can be provided.

1 is a plan view of a semiconductor device according to Embodiment 1 of the present invention. 1 is a cross-sectional view of a semiconductor device according to Embodiment 1 of the present invention. 1 is a circuit diagram showing a basic circuit configuration of a voltage controlled oscillator in a semiconductor device according to Embodiment 1 of the present invention. The top view of the semiconductor device which concerns on Embodiment 2 of this invention. Sectional drawing of the semiconductor device which concerns on Embodiment 2 of this invention. The circuit diagram which shows the basic circuit structure of the voltage controlled oscillator in the semiconductor device which concerns on Embodiment 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device, 10 ... Semiconductor substrate, 12 ... Integrated circuit, 14, 15 ... Connection electrode, 25,
26 ... Connection wiring layer, 40, 50 ... Spiral inductor as a passive element, 70 ... First resin layer, 75 ... Second resin layer, 81-86 ... External terminal.

Claims (3)

A semiconductor substrate including an integrated circuit as an active element and a plurality of connection electrodes electrically connected to the integrated circuit;
A first resin layer formed on the surface of the semiconductor substrate on which the connection electrode is formed, avoiding the connection electrode;
A connection wiring layer formed between the semiconductor substrate and the first resin layer;
One end connected to the connection wiring layer connected to one of the plurality of connection electrodes, a first Cu wiring layer formed on the surface of the first resin layer, the connection wiring layer, A spiral inductor consisting of
A region where the second Cu wiring layer formed on the surface of the first resin layer, the connection wiring layer connected to the spiral inductor, and the second Cu wiring layer and the connection wiring layer intersect A capacitor comprising a first resin layer sandwiched between,
A second resin layer covering surfaces of the first Cu wiring layer and the second Cu wiring layer;
An external terminal electrically connected to some of the plurality of connection electrodes and partially protruding from the second resin layer. The semiconductor device according to claim 1,
  The semiconductor device is sealed by the second resin layer except for a part of the external terminals. A semiconductor substrate including an integrated circuit as an active element and a plurality of connection electrodes electrically connected to the integrated circuit;
  A first resin layer formed on the surface of the semiconductor substrate on which the connection electrode is formed, avoiding the connection electrode;
  A connection wiring layer formed between the semiconductor substrate and the first resin layer;
  One end connected to the connection wiring layer connected to one of the plurality of connection electrodes, a first Cu wiring layer formed on the surface of the first resin layer, the connection wiring layer, A spiral inductor consisting of
  A region where the second Cu wiring layer formed on the surface of the first resin layer, the connection wiring layer connected to the spiral inductor, and the second Cu wiring layer and the connection wiring layer intersect A capacitor comprising a first resin layer sandwiched between,
  An external terminal electrically connected to some of the plurality of connection electrodes,
  An oscillator comprising the spiral inductor and the capacitor connected in parallel.

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