JP4928577B2 - Analog signal output circuit - Google Patents

Description

  The present invention relates to an analog signal output circuit, and more particularly to an analog signal output circuit suitable for audio equipment.

Many audio signals (hereinafter referred to as audio signals) added to music and video are processed by a semiconductor integrated circuit. Many of the semiconductor integrated circuits that process audio signals include a switched capacitor circuit (hereinafter referred to as an SC circuit).
In an audio device using such a semiconductor integrated circuit, when an audio signal is output as music or the like from a speaker or headphones, the SC circuit uses a D / A converter to convert the digital signal into an analog signal or an analog signal. The signal is bass enhanced and further filtered.

  FIG. 8 is a diagram showing a general SC circuit, and shows a first-order low-pass filter that removes unnecessary high-frequency signals from audio signals. The illustrated low-pass filter includes three capacitors C1, C2, and C3, three sets of switches S1 and S2, and a differential amplifier 1. The switches S1 and S2 are alternately turned on in a non-overlapping relationship. By such an operation, the low-pass filter low-passes the input signal Vi and outputs an analog output signal Vo. Such a low-pass filter is described in Non-Patent Document 1.

Tsuji, Kikunobu et al., Analog technology for VLSI, 223 pages, Kyoritsu Publishing Co., Ltd.

By the way, an audio device may be set to a mute state by a user operation during output of music or voice from a speaker or headphones. By setting the mute state, the ground voltage is output as an output signal.
However, in the conventional technique described above, a voltage step occurs when the ground voltage is instantaneously used as an output signal in the SC circuit. The voltage step generates noise called click noise, which gives the user a sense of incongruity.
The present invention has been made in view of the above points, and when an audio device is muted during output of music or voice, the output signal can be changed gently without generating click noise. An object is to provide an analog signal output circuit.

In order to solve the above problems, an analog signal output circuit according to claim 1 of the present invention includes a differential amplifier (for example, the differential amplifier 103 shown in FIG. 1) and an input terminal of the differential amplifier (for example, FIG. And a first capacitor element (for example, the capacitor 102b illustrated in FIG. 1) connected between the inverting input terminal 103a illustrated in FIG. 1 and an output terminal (for example, the output terminal 106 illustrated in FIG. 1). And an analog signal output circuit including the first capacitive element connected in parallel and stopping the output from the output terminal of the differential amplifier, the charge held in the first capacitive element A charge discharge circuit (for example, the switch 105 and the resistor element 104 shown in FIG. 1 ) that discharges over a predetermined time, and the charge discharge circuit includes a first switch element (for example, the switch 105 shown in FIG. 1); A resistor element connected in series to the first switch element (for example, the resistor element 104 shown in FIG. 1), and for turning the first switch element on and off at least once with respect to the first switch element. The signal control means (for example, the clock control circuit 108 shown in FIG. 1) that outputs the control signal of stepwise and discharges the electric charge held in the first capacitive element in response to turning on and off of the first switch element. the equipped and wherein the Rukoto.

Analog signal output circuit according to 請 Motomeko 2 resides in that in Claim 1, the control signal for the first switching element one or more times on, is turned off, turning on the first switch element, after being off, The first switch element is a signal that stops in a state where the first switch element is turned on.

The analog signal output circuit according to claim 3 includes an analog signal including a differential amplifier and a circuit unit including a first capacitor connected between an input terminal and an output terminal of the differential amplifier. When the output circuit is connected in parallel to the first capacitor element and stops output from the output terminal of the differential amplifier, the charge held in the first capacitor element is taken over a predetermined time. A charge discharge circuit for discharging, the charge discharge circuit including a second switch element (for example, the switch 301 shown in FIG. 3) and a third switch element (for example, in FIG. 3) connected in series with the second switch element. Switch 302), the second switch element, and a second capacitance element (for example, the capacitor 303 shown in FIG. 3) connected in series to a connection point of the third switch element, and the second switch element And a control signal for alternately turning on and off the second switch element and the third switch element at least once with respect to the third switch element. Signal control means (for example, a clock control circuit 308 shown in FIG. 3) for discharging the charge held in the first capacitor element stepwise in response to on and off is provided.

The analog signal output circuit according to claim 4 is the analog signal output circuit according to claim 3 , wherein the control signal for alternately turning on and off the second switch element and the third switch element at least once is the second switch element and The signal is a signal for stopping the second switch element and the third switch element in an on state after the third switch element is turned on and off.

The analog signal output circuit according to one embodiment of the present invention can release the charge held in the first capacitor element slowly over a predetermined time when the output is stopped. The output signal can be brought close to 0 slowly without being generated.
The analog signal output circuit of one embodiment of the present invention can realize a charge discharge circuit relatively easily.
The analog signal output circuit of one embodiment of the present invention can prevent an output of the differential amplifier from becoming indefinite due to a slight leakage current of a switch of the signal input circuit.
The analog signal output circuit of one embodiment of the present invention can realize a charge discharge circuit relatively easily.
The analog signal output circuit of one embodiment of the present invention can prevent an output of the differential amplifier from becoming indefinite due to a slight leakage current of a switch of the signal input circuit.

It is a circuit diagram for demonstrating the analog output circuit of Embodiment 1 of this invention. It is a figure for demonstrating operation | movement of the clock control circuit when the mute of Embodiment 1 of this invention is set. It is a circuit diagram for demonstrating the analog output circuit of Embodiment 2 of this invention. In Embodiment 2 of this invention, it is a figure for demonstrating operation | movement of the clock control circuit when a mute is set. It is a figure for demonstrating the modification of the analog signal output circuit of Embodiment 1 of this invention. It is a figure for demonstrating the modification of the analog signal output circuit of Embodiment 2 of this invention. It is a figure for demonstrating the modification of the analog signal output circuit of Embodiment 2 of this invention. It is a figure for demonstrating the circuit equivalent to the prior art of this invention.

Hereinafter, Embodiment 1 and Embodiment 2 of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a circuit diagram for explaining an analog output circuit according to a first embodiment of the present invention. As illustrated, the analog output circuit according to the first embodiment includes a circuit unit 110 serving as a main body of the analog output circuit, and a clock control circuit 108. The signal input circuit 100 is a circuit for inputting a signal to the circuit unit 110, and includes switch units 101a and 101b and a capacitor 102a. The switch units 101a and 101b include switches S1 and S2, respectively. Then, the input signal Vi is input, and the output signal is input to the circuit unit 110.

The circuit unit 110 includes a differential amplifier 103 and capacitors 102 b and 102 c, a switch unit 101 c, a resistance element 104, and a switch unit 105 connected in parallel to the differential amplifier 103.
The switch unit 101c of the circuit unit 110 includes switches S1 and S2 like the switch units 101a and 101b. The switches S1 and S2 of the switch units 101a, 101b, and 101c are all controlled by a two-phase non-overlap clock. The switch unit 105 includes a switch S3. The analog signal output circuit 100 is operated by such switches S1, S2, and S3.

The clock control circuit 108 is configured to output a clock signal for controlling on / off of the switch to the switch units 101a, 101b, 101c, and 105. The clock signal output by the clock control circuit 108 outputs a non-overlapping clock signal that does not simultaneously turn on the switches S1 and S2 to the switch units 101a, 101b, and 101c. Furthermore, it is possible to independently output clock signals to the switches S1, S2 and the switch S3.
In the signal input circuit 100, the input signal Vi is sampled by the capacitor 102a at the timing when the switch S1 of the switch unit 101a is turned on. The sampled charge of the input signal Vi is transferred to the inverting input terminal 103a of the differential amplifier 103 at the timing when the switch S2 of the switch unit 101a is turned on.

In the circuit unit 110, the transferred charge is also sent to the capacitor 102b and integrated. A signal generated by the integrated charge is output as an analog output signal Vo from the output terminal 106 of the analog signal output circuit. The output terminal 106 is a common terminal with the output terminal of the differential amplifier 103.
The capacitor 102c is a capacitor provided for the analog signal output circuit to form a low-pass filter. The capacitor 102c is alternately connected to the inverting input terminal 103a and output terminal 106 of the differential amplifier 103 by means of switches S1 and S2 whose one terminal is controlled by a non-overlapping clock signal.

In the analog output circuit operating as described above, when the audio device is set to the mute state, the signal input circuit 100 stops the signal input. The signal input is stopped by the clock control circuit 108 stopping the non-overlapping clock signal for the signal input circuit 100. At this time, in the first embodiment, the operation of the capacitor 102c is also stopped and the operation as the low-pass filter is stopped. The differential amplifier 103 outputs a DC voltage corresponding to the electric charge held in the capacitor 102b.
The clock control circuit 108 outputs a clock signal to the switch S3 of the switch unit 105 so that the switch S3 is turned on or off at least once in a predetermined pattern at the start of the mute operation.

FIG. 2 is a diagram for explaining the operation of the clock control circuit 108 when the mute is set according to the first embodiment. In the figure, the mute setting timing, the switch S1 on / off timing, the switch S2 on / off timing, the switch S3 on / off timing, and the analog output signal Vo are respectively shown from the top.
As shown in FIG. 2, in the first embodiment, the clock control circuit 108 outputs a non-overlapping clock signal to the switches S1 and S2 during normal operation. When the mute is set, the non-overlapping clock signal output to the switches S1 and S2 is stopped, and the output of the clock signal to the switch S3 is started. In the illustrated clock signals, the switch is turned on between the rising edge and the falling edge, and the switch is turned off between the falling edge and the next rising edge.

As for the clock signal output to the switch S3, a period during which the switch S3 is turned on (hereinafter referred to as an on period), a period during which the switch S3 is turned off (hereinafter referred to as an off period), an on count, and an off count are preset. . The set ON period, OFF period, ON count, and OFF count are collectively referred to as a clock signal pattern.
In the first embodiment, the pattern of the clock signal output to the switch S3 is set so that the on period is short and the off period is long. Further, on / off is performed one or more times (the number of on-times and the number of off-times is one or more), and preferably the number of on-times and the number of off-times are each several times or tens of thousands of times. When the switch S3 is turned on, part of the electric charge held in the capacitor 102b is released through the resistance element 104. Further, when the switch S3 is turned off, the path through the resistance element 104 is blocked.
For this reason, by turning on and off the switch S3, the electric charge held in the capacitor 102b can be discharged stepwise, so that the analog output signal Vo output from the output terminal 106 is gently applied over a predetermined time. It can be converged to the signal operating point voltage.

Hereinafter, the effects obtained by the first embodiment will be described with specific examples.
In the analog output circuit, from the viewpoint of economy and the like, the capacitance of the capacitor 102b is considered to be 10 pF, and the resistance value of the resistance element 104 connected in series with the switch S3 is considered to be about 100K ohms. At this time, the time constant of the analog output signal Vo is 1 μS. In the case of such a number of stoppages, if mute is set when a relatively large signal is output, a sensitive click noise occurs when the analog output signal Vo becomes the ground potential.

  However, in the first embodiment, when the duty ratio in the ON state of the switch S3 is 1/10000, the resistance value of the resistance element is virtually equivalent to 1 Gohm. With such a resistor and a 10 pF capacitor, the time constant can be made sufficiently longer than the above example, 10 mS. For this reason, Embodiment 1 can provide an analog output circuit that can prevent the occurrence of sensitive click noise and can shift to mute without causing the user to feel uncomfortable in the audio device.

  Also, as shown in FIG. 2, in the first embodiment, the switch S3 is turned on and off in a predetermined pattern, and then the switch S3 is turned on and stopped. By stopping the switch S3, signals of different paths are output from the differential amplifier, or the operating state of the analog output circuit is not changed, so no click noise occurs. When the switch S3 is on, the differential amplifier forms a stable voltage follower circuit via the resistance element 104 shown in FIG.

Therefore, in the first embodiment, by maintaining the switch S3 in the ON state, the output of the differential amplifier does not become uncertain due to a slight leakage current of the switch of the signal input circuit. As described above, according to the analog signal output circuit of the first embodiment, when the normal signal output state is changed to the mute state, the output signal gradually changes, and the generation of click noise can be suppressed. Finally, the signal operating point voltage of zero signal can be continuously output.
Further, by changing the ratio between the ON period and the OFF period of the switch S3, a more gradual output voltage change can be realized. Specifically, for example, immediately after the start of mute, the duty ratio between the on period and the off period may be decreased and gradually increased.

  In FIG. 2, the operation is simplified for easy understanding. That is, in the section where the switch S1 and the switch S2 are alternately turned on and off alternately, the analog signal output actually has a stepped waveform, but in FIG. 2, the cycle of the switch S1 and the switch S2 shown in FIG. It shows that the analog output waveform appears as a smooth change by turning on and off at a fast cycle to form a fine stepped waveform. Similarly, in the section where the switch S3 is repeatedly turned on and off, the analog signal output actually has a stepped waveform, but in FIG. 2, the switch is turned on and off at a period much faster than the cycle of the switch S3 shown in the figure. By repeating, it becomes a fine stepped waveform, and the analog output waveform is seen as a smooth change.

  In the first embodiment, the analog signal output circuit is described by taking the SC circuit as an example, but the first embodiment is not limited to such a configuration as a matter of course. That is, a circuit added to the circuit body such as a signal input circuit may be a switched register circuit including a switch and a resistance element, or may be a circuit that operates continuously with a resistance element or a capacitor element. Furthermore, a circuit in which the SC circuit and other circuits are mixed may be used.

(Embodiment 2)
FIG. 3 is a circuit diagram for explaining an analog output circuit according to the second embodiment of the present invention. The circuit of the second embodiment includes the same configuration as the circuit of the first embodiment shown in FIG. For this reason, the same code | symbol is attached | subjected about the same code | symbol and description is partially abbreviate | omitted.
The analog output circuit according to the second embodiment includes a signal input circuit 100 as in the first embodiment. As in the first embodiment, the signal input circuit 100 is operated by switches S1 and S2 controlled by a two-phase non-overlap clock signal. The input signal Vi is sampled by the capacitor 102a while the switch S1 of the switch unit 101a is on. The charge sampled by turning on the switch S2 of the switch unit 101b is transferred to the inverting input terminal 103a of the differential amplifier.

  The second embodiment includes a circuit unit 310. The circuit unit 310 includes a switch unit 101c, a differential amplifier 103, and a capacitor 102b. Further, the circuit unit 310 includes two switch units 301 and 302. The switch unit 301 includes a switch S3, and the switch unit 302 includes a switch S4. A capacitor 303 is provided between the switches S3 and S4.

The transferred charge is also transferred to the capacitor 102b and integrated in the capacitor 102b. An analog output signal Vo corresponding to the integrated charge is output from the output terminal 106.
Also in the second embodiment, the circuit unit 310 is provided with the capacitor 102c, and the analog signal output circuit forms a low-pass filter. One terminal of the capacitor 102c is alternately connected to the output terminal 106 and the inverting input terminal 103a of the differential amplifier by switches S1 and S2.

  The clock control circuit 308 of the second embodiment outputs clock signals independently to the switches S1 and S2 of the switch units 101a, 101b, and 101c, the switch S3 of the switch unit 301, and the switch S4 of the switch unit 302, respectively. . The clock signal is a non-overlapping clock signal in which the switches S1 and S2 are not turned on at the same time. Further, the non-overlapping clock signals are such that the switch S3 and the switch S4 do not turn on at the same time.

  FIG. 4 is a diagram for explaining the operation of the clock control circuit when mute is set in the second embodiment. In the figure, the mute setting timing, the switch S1 on / off timing, the switch S2 on / off timing, the switch S3 on / off timing, the switch S4 on / off timing, and the analog output signal Vo are shown from the top in the figure. ing.

The clock control circuit 308 stops outputting the clock signal to the switches S1 and S2 when the mute is set. As a result, the function of the capacitor 102c as a low-pass filter is also stopped. The differential amplifier 103 outputs a DC voltage signal corresponding to the charge held in the capacitor 102b.
As shown in FIG. 4, the clock control circuit 308 has a predetermined pattern for the switch S3 of the switch unit 301 and the switch S4 of the switch unit 302 at the start of mute, and includes the switch S3 and the switch S3. A non-overlapping synchronization signal that does not turn on S4 at the same time is output. By turning on and off according to the synchronization signal, the switch S3 and the switch S4 are alternately turned on and off one or more times.

  When the switch S3 and the switch S4 are alternately turned on and off, a part of the electric charge held in the capacitor 102b connected between the switch S3 and the switch S4 is discharged by the capacitor 303. By taking a cycle in which the switches S3 and S4 are alternately turned on and off longer than a predetermined period, the analog output signal Vo output from the output terminal 106 is given a predetermined time to a signal operating point voltage that means a zero signal. Over time.

  Also in the second embodiment, as shown in FIG. 4, after the switches S3 and S4 are turned on and off in a predetermined pattern, the switches S3 and S4 are turned on and stopped. By stopping the switch S3, signals of different paths are output from the differential amplifier, or the operating state of the analog output circuit is not changed, so no click noise occurs. When the switches S3 and S4 are in the on state, the differential amplifier constitutes a stable voltage follower circuit.

  Therefore, in the second embodiment, by maintaining the switches S3 and S4 in the ON state, the output of the differential amplifier does not become uncertain due to a slight leakage current of the switch of the signal input circuit. As described above, according to the analog signal output circuit of the second embodiment, when the normal signal output state is changed to the mute state, the output signal gradually changes, and generation of click noise can be suppressed. Finally, the signal operating point voltage of zero signal can be continuously output.

  In FIG. 4, the operation is shown in a simplified manner so that it can be easily understood. That is, in the section where the switch S1 and the switch S2 are alternately turned on and off alternately, the analog signal output actually has a stepped waveform, but in FIG. 2, the cycle of the switch S1 and the switch S2 shown in FIG. It shows that the analog output waveform appears as a smooth change by turning on and off at a fast cycle to form a fine stepped waveform. Similarly, in the section where the switch S3 and the switch S4 are alternately turned on and off alternately, the analog signal output actually has a stepped waveform, but in FIG. 4, the cycle of the switches S3 and S4 shown in the figure is much longer. It shows that the analog output waveform appears as a smooth change by turning on and off at a fast cycle to form a fine stepped waveform.

  Further, Embodiment 2 of the present invention is not limited to the configuration described above. That is, in the second embodiment, it has been described that the switches S1 and S2 and the capacitor 102c constituting the low-pass filter are different from the switches S3 and S4 that operate to start mute and the capacitor 303. However, the switches S1 and S2, the capacitor 102c, the switches S3 and S4, and the capacitor 303 can have a common configuration, and can be operated in the same manner as in the second embodiment by a clock signal output from the clock control circuit.

Further, the capacitor 303 may be a capacitor formed intentionally, or may be a capacitor that is parasitic on the terminal capacity of the switch or the wiring.
Furthermore, also in the second embodiment, a more gradual change in output voltage can be realized by changing the ratio of the on period and the off period of the switches S3 and S4. Specifically, for example, immediately after the start of mute, it is conceivable to shorten the cycle of the on period and the off period and gradually increase the period.

(Modification)
Next, a modified example of the analog signal output circuit of Embodiment 1 and Embodiment 2 described above will be described.
FIG. 5 is a diagram for explaining a modification of the analog signal output circuit according to the first embodiment of the present invention, and shows a circuit when the analog signal output circuit according to the first embodiment is realized by a fully differential circuit. ing. 6 and 7 each show a circuit when the analog signal output circuit of the second embodiment is realized by a fully differential circuit. 5-7, the same code | symbol is attached | subjected and shown about the structure similar to the structure demonstrated in FIG. 1, FIG.
In any of the first embodiment, the second embodiment, and the modification, the analog signal output circuit is preferably formed as a circuit on a semiconductor integrated circuit.

  The present invention described above can be applied to any configuration as long as it is desired to gently change the output signal when the output signal is stopped. In particular, when applied to audio equipment, it is possible to suppress the occurrence of click noise when the equipment is muted.

DESCRIPTION OF SYMBOLS 100 Signal input circuit 101a, 101b, 101c, 105, 301, 302 Switch part 102a, 102b, 102c, 303 Capacitor 103 Differential amplifier 103a Inversion input terminal 104 Resistance element 106 Output terminal 108, 308 Clock control circuit 110, 310 Circuit part

Claims (4)

An analog signal output circuit including a circuit unit including a differential amplifier and a first capacitor connected between an input terminal and an output terminal of the differential amplifier,
It is connected in parallel to said first capacitive element, the differential case to stop the output from the output terminal of the amplifier, the charge emission circuits to release electric charges held in the first capacitive element over a predetermined time With
The charge discharge circuit includes:
Including a first switch element and a resistance element connected in series to the first switch element;
A control signal for turning the first switch element on and off at least once is output to the first switch element, and the first switch element is held by the first capacitor element according to the on / off state of the first switch element. An analog signal output circuit comprising signal control means for discharging charges in a stepwise manner . The control signal for turning on and off the first switch element at least once is a signal for turning on and off the first switch element and then stopping the first switch element with the first switch element turned on. The analog signal output circuit according to claim 1 . An analog signal output circuit including a circuit unit including a differential amplifier and a first capacitor connected between an input terminal and an output terminal of the differential amplifier,
A charge discharge circuit connected in parallel to the first capacitive element and configured to discharge the charge held in the first capacitive element over a predetermined time when the output from the output terminal of the differential amplifier is stopped; Prepared,
The charge discharge circuit includes:
A second switch element, a third switch element connected in series with the second switch element, the second switch element, and a second capacitor element connected in series with a connection point of the third switch element, Including
A control signal for alternately turning on and off the second switch element and the third switch element at least once is output to the second switch element and the third switch element, and the second switch element and the third switch element on the third switch element, wherein the to luer analog signal output circuit further comprising a signal control means for stepwise release a charge held in the first capacitive element in response to off. A control signal for alternately turning on and off the second switch element and the third switch element is turned on and off after the second switch element and the third switch element are turned on and off. The analog signal output circuit according to claim 3 , wherein the signal is a signal to be stopped in a state where the element and the third switch element are turned on.

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