JP3872613B2 - Noise reduction device during mute - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a noise reduction device during mute, and more particularly to a noise reduction device during mute for reducing noise during mute of an audio device.
[0002]
[Prior art]
The sound device is provided with a mute device (silencer). In the mute apparatus shown in FIG. 11, as shown in FIG. 12, when the mute signal μ is turned on, the pulse density modulation signal (PDM signal) output from the noise shaper NSSP has a pulse waveform with a duty of 50% (see FIG. 12 (indicated by reference numeral 101 in FIG. 12), the pulse waveform 101 is input to the analog filter, and is output based on the control signals of the signal φ1 (positive) and the signal φ2 (negative) shown in FIG. It is a circuit device that prevents the volume output from being output by integrating and neutralizing the output.
[0003]
The analog filter of the mute device that is forced so that the output of 50% duty output from the ΔΣ modulator at mute becomes zero output has a circuit as shown in FIG. 13 and generates signals by control signals φ1 and φ2. Since this is digital, abnormal sounds such as “bottom” and “buchi” occur at the moment when the reference voltage before mute is changed to zero voltage at the time of mute. Such abnormal noise is particularly disliked when the user uses headphones.
[0004]
A technique for preventing the occurrence of such abnormal noise is known from Japanese Patent Application Laid-Open No. 61-264920. This technology discloses a device that can reduce shock noise and residual noise during mute by sufficiently increasing the frequency of the output with a duty of 50%. This known technique cannot suppress the generation of a shock sound (noise indicated by symbol A in FIG. 6) at the time of switching to mute. Furthermore, when simulating the volume at the time of mute of this known technique, generation of high frequency noise cannot be suppressed (noise indicated by reference numeral 31 in FIG. 6).
[0005]
In order to reduce noise, it is desirable to use an analog signal generation circuit that is originally provided. Furthermore, it is desirable to reduce noise during transition to mute. Furthermore, it is desirable to eliminate and reduce noise after transition to mute.
[0006]
[Problems to be solved by the invention]
SUMMARY OF THE INVENTION An object of the present invention is to provide a noise reduction device at the time of mute that can effectively reduce the noise by effectively utilizing an analog signal generation circuit originally provided for noise reduction.
Another object of the present invention is to provide a mute noise reduction device capable of reducing noise during transition to mute.
Still another object of the present invention is to provide a mute noise reduction device capable of reducing noise during transition to mute and erasing / reducing noise after transition to mute.
[0007]
[Means for Solving the Problems]
Means for solving the problem is expressed as follows. The technical matters corresponding to the claims in the expression are appended with numbers, symbols, etc. in parentheses (). The number, symbol, etc. clarify the correspondence / correspondence between the technical matters corresponding to the claims and the technical matters of at least one of the forms / implementations. It is not intended to show that the technical matter is limited to the technical matter of the embodiment.
[0008]
The mute noise reduction apparatus according to the present invention includes an analog circuit for outputting an analog signal. The analog circuit includes a signal generation unit (1) for generating an analog signal, and a signal generation unit (1). A control unit (2) for inputting a control signal for controlling the output to the signal generation unit (1), and signals φ1 and φ2, a mute signal, and a PDM signal for generating the control signal are supplied to the control unit (2). Is input. As an output, the mute signal μ is input into the analog circuit, and the analog signal generation capability of the analog circuit can be effectively utilized.
[0009]
The control unit (2) includes a switch group including a plurality of switches. The switch group performs a switching operation by signals φ1, φ2, a mute signal μ, and a PDM signal, and a control signal is generated by the operation of the switch group. The mute signal μ can be effectively used by the control unit.
[0010]
The control unit further includes a capacitor, and a control signal is output from the capacitor to the signal generation unit via one switch (26) of the switch group. The original switch and capacitor (23) can be used effectively. The other two switches (21, 22) of the switch group operate by a combination of the signals φ1, φ2, the mute signal μ, and the PDM signal. During the period when the mute signal μ is input, the capacitor (23) is positively connected. Or a negative charge is charged. Such a charge is smooth, and the control signal can be smooth and constant, not steep. As a result, noise immediately after the mute signal μ is input can be reduced, and further, residual noise can be reduced and persistent noise can be removed.
[0011]
One of the other two switches (21) is preferably operated by a signal φ1 · PDM, and the other one (22) of the other two switches is preferably operated by a signal φ1 · (PDM + μ). As a result, the output signal from the capacitor (23) can be a signal having a constant value or a gentle slope.
[0012]
The other three switches in the switch group operate in combination with the signals φ1, φ2, the mute signal μ, and the PDM signal. During the period when the mute signal mu is input, the capacitor (23) has a negative charge. No charge is charged. As a result, the noise immediately after the mute signal μ is input can be further reduced, and further, the residual noise can be reduced and the continuous noise can be removed substantially completely. This means that one of the other three switches is operated by the signal φ1 · PDM, the other one of the other three switches is operated by the signal φ1 · PDM, and the other three switches One can be realized by operating with a signal (φ1 · μ + φ2). Such an implementation is possible by using a known circuit as it is.
[0013]
It is preferable that the control unit (2) is formed as one-to-two, and the two control units (2) are symmetrically designed by the concept of reverse polarity. The noise reduction effect is further enhanced. Two control signals are input to the signal generation unit (1) from the two control units (2), respectively. It is preferable that the signal generation unit (1) is also formed as one-to-two, and the two control units (2) are designed symmetrically based on the reverse polarity concept.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Corresponding to FIG. 1, the mute noise reduction apparatus according to the embodiment of the present invention includes a mute circuit in the analog signal generation circuit. An analog filter 1 and a mute circuit 2 are connected to the analog signal generation circuit (SCF). The mute circuit 2 receives the mute signal μ from the mute signal generation terminal 3. When the mute signal μ is input to the mute circuit 2, the mute control signal 4 output from the mute circuit 2 and input to the analog filter 1 is an analog signal that changes slowly.
[0015]
A noise shaper (NNSP) 5 generates a PDM signal 6. The PDM signal 6 is input to the SCF. When the mute signal μ is input based on the PDM signal 6, the SCF outputs an analog output signal 7 from the output terminal 8 based on the PDM signal 6 and the mute signal μ. An input signal 11 generated at the input terminal 9 passes through the digital filter 12 and is input to the noise shaper 5, and the mute control signal 4 outputs the PDM signal 6 based on the input.
[0016]
FIG. 2 shows details of the SCF. The mute circuit 2 receives four types of signals shown in FIG. The first signal is the PDM signal 6. The second signal is the first pulse waveform signal φ1. The third signal is the second pulse waveform φ2. The fourth signal is the mute signal μ. The first pulse waveform signal φ1 and the second pulse waveform φ2 are opposite in phase. In principle, when they are added, they become zero signals. Its antiphase relationship is not perfect.
[0017]
As shown in FIG. 2, the mute circuit 2 is provided with a first switch 21 and a second switch 22. A common terminal common to the first switch 21 and the second switch 22 is provided on the output side of these switches. The input side of the first switch 21 is connected to a constant voltage power source (not shown) having a positive voltage VR (+). The input side of the second switch 22 is connected to a constant voltage power supply (not shown) having a negative voltage (−) VR.
[0018]
The first capacitor 23 is directly connected to the common terminal. A third switch 24 and a fourth switch 25 are connected to both sides of the first capacitor 23, respectively. The third switch 24 and the fourth switch 25 are connected to the reference voltage GND. A fifth switch 26 is connected to the output side of the first capacitor 23. The fifth switch 26 is connected to the fourth switch 25 in series with the GND. The first capacitor 23 is connected to the third switch 24 in series with the GND.
[0019]
A second capacitor 27 for forming the analog filter 1 is interposed between the fifth switch 26 and the output terminal 8. The auxiliary circuit 30 including the switch group 28 and the third capacitor 29 constitutes a known analog signal circuit 1 together with the second capacitor 27.
[0020]
Each switch 2221, 24, 25, 26 operates when a corresponding signal is turned on as described below.
First switch 21: φ1, PDM
Second switch 22: φ1 · (PDM * + μ)
Third switch 24: φ2
Fourth switch 25: φ1
Fifth switch 26: φ2
Here, PDM * represents inversion of PDM (in the figure, * corresponds to the upper line). “·” in “φ1 · PDM” means AND. As shown in FIG. 3, φ1 and φ2 are in an antiphase relationship with each other.
[0021]
If the mu signal μ is zero, the signals φ1 · PDM and φ1 · PDM * that operate the first switch 21 and the second switch 22 respectively are inverted signals (because their phases are shifted by 180 degrees). Any one of the first switch 21 and the second switch 22 is turned ON. When either the first switch 21 or the second switch 22 is turned ON, φ2 is a zero signal, and the third switch 24 and the fifth switch 26 are non-conductive.
[0022]
When the first switch 21 is ON, the first capacitor 23 is charged by the voltage VR (+). When the second switch 22 is ON, the first capacitor 23 is charged by the voltage VR (−). In this way, the voltage / charge charged to the first capacitor 23 becomes positive in the opposite phase φ2 while φ1 becomes a zero signal and the first switch 21 and the second switch 22 are OFF. The fifth switch 26 is turned on (opened) and discharged toward the analog filter 1. The voltage thus discharged is charged in the second capacitor 27. When the duty of the PDM becomes 50%, the voltage of the second capacitor 27 is offset and added and discharged from the output terminal 8.
[0023]
If exactly as mute signal mu is shown in Figure 3, even PDM is either state, the second switch 22 based on the mute signal mu are added φ1 · (PDM * + μ) is turned ON that Do not.
[0024]
While the mute signal μ is not zero, the voltage VR (−) is charged to the first capacitor 23. The charge is a slow charge of negative charges. Regardless of whether the PDM is positive or negative, the first capacitor 23 is connected to the VR (−) side via the second switch 22, the charge amount is maintained constant, and a constant voltage (GND) is maintained when the fifth switch 26 is turned on. Is output.
[0025]
FIG. 4 shows other details of the analog filter 1. The circuit of FIG. 4 is apparently exactly the same as the circuit of FIG. Each switch 21, 22, 24, 25, 26 operates when a corresponding signal is turned on as follows.
First switch 21: φ1 · (PDM + μ)
Second switch 22: φ1, PDM *
Third switch 24: φ2
Fourth switch 25: φ1
As described above, with respect to the mute circuit 2, the signals entering the first switch 21 and the second switch 22 are reversed in FIGS. 2 and 4, and only in this respect, the circuit of FIG. 2 and the circuit of FIG. Is different.
[0026]
If the mu signal μ becomes positive as shown in FIG. 3, the φ1 · (PDM + μ) to which the mute signal μ is added has priority over the φ1 · PDM, regardless of the state of the PDM. 21 is turned ON, and the second switch 22 is not turned ON. While the mute signal μ is not zero, the voltage VR (+) is charged in the first capacitor 23. The charge is a slow charge of positive charges. Regardless of whether the PDM is positive or negative, the first capacitor 23 is connected to the VR (+) side via the first switch 21, the charge amount is maintained constant, and the constant voltage (GND) is maintained even when the fifth switch 26 is turned on. ) Is output.
[0027]
FIG. 5 shows further details of the analog filter 1. The circuit of FIG. 5 is apparently exactly the same as the circuit of FIG. Each switch 21, 22, 24, 25, 26 operates when a corresponding signal is turned on as follows.
First switch 21: φ1, PDM
Second switch 22: φ1, PDM *
Third switch 24: φ1 · μ + φ2
Fourth switch 25: φ1
Thus, with respect to the mute circuit 2, the signals entering the first switch 21 and the second switch 22 are different between FIG. 2 and FIG. 5, and the circuit of FIG. 2 and the circuit of FIG. ing.
[0028]
If the mu signal μ becomes positive as shown in FIG. 3, the third switch 24 becomes conductive regardless of the state of the PDM and the phase of φ1 and φ2. The first capacitor 23 is not charged with either positive or negative charge. The output of the first capacitor 23 is maintained at a constant value.
[0029]
FIG. 6 shows the above-described three embodiments according to the present invention and the silencing effect of the conventional apparatus. The vertical axis indicates the voltage value output from the output terminal 8. The conventional value (A) suddenly rises immediately after the mute signal μ rises, and an unusual noise “buchi” is generated greatly. In contrast, the inventive value (B) of the embodiment shown in FIGS. 2 and 4 suddenly rises immediately after the mute signal μ rises, but the rise value is kept small.
[0030]
The present invention value (c) shown in FIG. 6 falls suddenly immediately after the mute signal μ rises, but the absolute value of the fall value is kept small. Inventive values (B) and (C) have a shorter time to settle to a constant value (zero) than the conventional value (A).
[0031]
The simulation results also show other different phenomena between the conventional values and the present invention values. The conventional value (A) generates a vibration 31 having a constantly large amplitude even after the average value has settled to zero. On the other hand, all three values of the present invention converge to substantially zero values.
[0032]
Usually, the analog filter 1 is constituted by a differential circuit. In general, all of the three embodiments described above use an AAF (Anchorius filter) for each of their output stages. The simulation results when the filter is used are shown in FIG. As shown in FIG. 7, the present invention values (B) and (C) show similar results, and further, their signal values are gradually changed. Since the signal value (B) has settled down to a constant value, vibration with a slight amplitude has occurred, but such vibration does not appear in the signal value (C), and practically complete. The mute function has been achieved. It should be noted that the conventional value is far from the range of FIG. 7 and cannot be illustrated.
[0033]
FIG. 8 shows a further different form of implementation according to the invention. The analog signal generation circuit of this embodiment is formed of an analog filter 1 ′ and a mute circuit 2 ′. The analog filter 1 ′ is a symmetrical combination of the two analog filters 1 of FIG. 2, and has a positive output terminal 8 ′ and a negative output terminal 8 ″. The mute circuit 2 ′ is the same as 2 in FIG. Two mute circuits 2 are combined symmetrically, and the two mute circuits 2 are connected to the two analog filters 1 respectively by the same connection as shown in FIG.
[0034]
The symmetry means that the signals output from the output terminal 8 ′ and the output terminal 8 ″ have opposite polarities. For example, the two first switches 21 in a pair are shown in FIG. Are indicated by 21 (+) and 21 (-), and the paired first capacitor 23 is indicated by 23 (+) and 23 (-). It does not mean that the charges charged simultaneously to the first capacitor 23 (+) and the first capacitor 23 (-) have opposite polarities, and the first capacitors 23 (+) and 23 (-) are charged simultaneously. If the electric charges have the same polarity, a circuit configuration in which the voltages output from the output terminal 8 ′ and the output terminal 8 ″ have opposite polarities is realized in the analog filter 1 ′ by a conventional technique. The signal input in FIG. 8 corresponds to the signal input in FIG. 2 as follows.
[0035]
First switch 21 (+): φ1, PDM
Second switch 22 (+): φ1 · (PDM * + μ)
Third switch 24 (+): φ2
Fourth switch 25 (+): φ1
First switch 21 (-): φ1, PDM *
Second switch 22 (−): φ1 · (PDM + μ)
Third switch 24 (-): φ2
Fourth switch 25 (-): φ1
[0036]
FIG. 9 shows yet another form of implementation according to the present invention. The circuit in FIG. 8 has the same correspondence as that in FIG. 2, and the circuit in FIG. 9 corresponds to the circuit in FIG. The point that the symmetry has a reverse polarity in terms of functional concept is exactly the same as that of FIG. That is, the signal input is as follows.
[0037]
First switch 21 (+): φ1 · (PDM + μ)
Second switch 22 (+): φ1, PDM *
Third switch 24 (+): φ2
Fourth switch 25 (+): φ1
First switch 21 (−): φ1 · (PDM * + μ)
Second switch 22 (-): φ1 · PDM
Third switch 24 (-): φ2
Fourth switch 25 (-): φ1
[0038]
FIG. 10 shows yet another form of implementation according to the present invention. The circuit in FIG. 8 has the same correspondence as that in FIG. 2, and the circuit in FIG. 10 corresponds to the circuit in FIG. The point that the symmetry exhibits a reverse polarity in terms of functional concept is exactly the same as those in FIGS. That is, the signal input is as follows.
[0039]
First switch 21 (+): φ1, PDM
Second switch 22 (+): φ1, PDM *
Third switch 24 (+): φ1 · μ + φ2
Fourth switch 25 (+): φ1
First switch 21 (-): φ1, PDM *
Second switch 22 (-): φ1 · PDM
Third switch 24 (−): φ1 · μ + φ2
Fourth switch 25 (-): φ1
[0040]
In such a reverse polarity symmetric (mirror symmetry) pair mute circuit 2 ′, the two outputs of the analog filter 1 ′ have opposite polarities and the absolute values of the positive and negative values are equal. , 7 can change the present invention values (B) and (C) more gently, and more quickly shift to a zero value with a narrower vibration width more strictly.
[0041]
Since the mute signal is directly introduced into the analog circuit in this way, the MPX of the known device shown in FIG. 11 is not required in each embodiment of the present invention.
[0042]
【The invention's effect】
The noise reduction device at the time of mute according to the present invention can suppress the generation of abnormal noise at the time of mute, and can substantially completely eliminate the continuous noise during the mute period. Such an effect is further improved by providing reverse polarity symmetry.
[Brief description of the drawings]
FIG. 1 is a circuit block diagram showing an embodiment of a noise reduction apparatus at mute according to the present invention.
FIG. 2 is a circuit diagram showing an embodiment of an analog generation circuit.
FIG. 3 is a timing chart showing signal generation.
FIG. 4 is a circuit diagram showing another embodiment of the analog generation circuit.
FIG. 5 is a circuit diagram showing still another embodiment of the analog generation circuit.
FIG. 6 is a graph showing simulation results.
FIG. 7 is another graph showing simulation results.
FIG. 8 is a circuit diagram showing still another embodiment of the analog generation circuit.
FIG. 9 is a circuit diagram showing still another embodiment of the analog generation circuit.
FIG. 10 is a circuit diagram showing still another embodiment of the analog generation circuit.
FIG. 11 is a circuit diagram showing a known device.
FIG. 12 is a time chart of known signals.
FIG. 13 is a circuit diagram showing a part of a known device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Signal generation part 2 ... Control part 21, 22, 24, 25, 26 ... Switch 23 ... Capacitor φ1 ... Signal φ2 ... Signal μ ... Mute signal

Claims (3)

It consists of an analog circuit for outputting analog signals,
The analog circuit is:
A signal generation unit for generating the analog signal;
A control unit for inputting a control signal for controlling the output of the signal generation unit to the signal generation unit,
A signal φ1 for generating the control signal, a signal φ2, a phase φ2 having the opposite phase and the same amplitude, a mute signal, and a PDM signal are input to the control unit ;
The control unit includes a capacitor, a first switch that opens and closes a connection between a positive voltage constant voltage source and one end of the capacitor by a logical product signal of the signal φ1 and the PDM signal, and a negative voltage constant voltage source. A second switch that opens and closes a connection between the capacitor and one end of the capacitor, a third switch that opens and closes a connection between the one end of the capacitor and a reference voltage GND by the signal φ2, and the other end of the capacitor and the reference A fourth switch that opens and closes a connection with a voltage GND by the signal φ1; and a fifth switch that opens and closes a connection between the other end of the capacitor and the signal generator by the signal φ2. The switch No. 2 is a switch that opens and closes in response to a signal obtained by taking the logical product of the signal φ1 to the signal obtained by logically summing the inversion of the PDM signal and the mute signal. A mute noise reduction device characterized by the above . It consists of an analog circuit for outputting analog signals,
The analog circuit is:
A signal generation unit for generating the analog signal;
A control unit for inputting a control signal for controlling the output of the signal generation unit to the signal generation unit,
A signal φ1 for generating the control signal, a signal φ2, a phase φ2 having the opposite phase and the same amplitude, a mute signal, and a PDM signal are input to the control unit;
The control unit connects the signal φ1 and the PDM with a capacitor, a first switch that opens and closes a connection between a positive voltage constant voltage source and one end of the capacitor, and a negative voltage constant voltage source and a common terminal. A second switch that opens and closes by an AND signal with an inverted signal of the signal, a third switch that opens and closes a connection between one end of the capacitor and a reference voltage GND by the signal φ2, the other end of the capacitor, and the A fourth switch that opens and closes a connection with a reference voltage GND by the signal φ1; and a fifth switch that opens and closes a connection between the other end of the capacitor and the signal generator by the signal φ2. The first switch is a switch that opens and closes in response to a signal obtained by taking a logical product of the signal φ1 to a signal obtained by logically summing the PDM signal and the mute signal. Noise reduction device mute to. A second control unit having the same circuit configuration as that of the control unit, wherein the PDM signal and the inverted signal of the PDM signal are input interchangeably, and the second control unit outputs the inverted signal of the control signal to the signal generation unit when not muted; 3. The mute noise reduction apparatus according to claim 1, wherein an output of the signal generation unit is controlled by the control unit and the second control unit .

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