JP4927220B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing an SOI structure semiconductor device in which element isolation is performed by an isolation insulating film such as a partial insulating film that leaves a part of an SOI layer.

  A conventional SOI structure in which element isolation is performed by an isolation insulating film such as a partial insulating film that leaves a part of the SOI layer, and the potential of the body region is fixed (hereinafter may be abbreviated as “partial isolation body fixed SOI structure”) Such semiconductor devices are disclosed in, for example, Non-Patent Document 1, Patent Document 1, and Patent Document 2.

Japanese Patent Laid-Open No. 2000-24397 JP 2000-39484 A

Y.Hirano et al., IEEE 1999 SOI conf., P131

  In a semiconductor device having a partially isolated body-fixed SOI structure, it is difficult to produce a semiconductor element such as a MOSFET by accurately controlling the body resistance. The reason will be described in detail below.

  FIG. 33 is a cross-sectional view for explaining the problems of the conventional partially separated body-fixed SOI structure. As shown in the figure, an SOI layer 3 is formed on a buried oxide film 2 existing on a silicon substrate (not shown), and the SOI layer 3 is element-isolated by a partial oxide film 31. The partial oxide film 31 is formed below the well region 11, which is the lower layer portion of the SOI layer 3.

  A channel formation region 7 is formed in the transistor formation region of the SOI layer 3, and a gate oxide film 8 and a gate electrode 9 are sequentially formed on the channel formation region 7.

  On the other hand, body region 10 is provided on the opposite side of channel formation region 7 with partial oxide film 31 interposed therebetween, and well region 11 is in contact with body region 10 and channel formation region 7 respectively. The channel formation region 7 is electrically connected through the well region 11 below the channel 31.

  In order to form the source / drain regions of the MOS transistor, as shown in FIG. 33, S / D impurity ions 19 are implanted using the gate electrode 9 and the like as a mask, but the partial oxide film 31 is not masked at this time. In general, the resist is not formed.

  Therefore, part of the S / D impurity ions 19 is also implanted into the well region 11 below the partial oxide film 31 when the source / drain regions are formed, and the resistance of the well region 11 from the body region 10 to the channel formation region 7 is increased. There is a risk that the resistance value of a certain body resistance becomes high and the high-speed operation of the MOS transistor becomes unstable.

The implantation conditions of the impurity ions 19 for S / D at the time of forming the source / drain regions are, for example, As (arsenic) 50 keV (implantation energy), 4 × 10 ¹⁵ / cm ² (dose amount).

  FIG. 34 is a graph showing an impurity profile of As. The injection conditions are as described above. As shown in the figure, the impurity profile has a standard deviation σ (= 8.5 nm) around 26 nm, and the range is 51.5 nm (= 26 + 3σ (nm)).

  Therefore, when the thickness of the partial oxide film 31 is reduced to about 50 nm, the As impurity reliably reaches the well region 11. Further, even when the partial oxide film 31 is formed to be slightly thicker than 50 nm, as shown in FIG. 34, the tail portion of the impurity profile is deeper than 51.5 nm, so that As is implanted into the partial oxide film 31. There is still a risk of being lost.

Further, P (phosphorus) is implanted at about 30 to 50 keV and 1 × 10 ¹³ / cm ^{2 in} order to reduce leakage current from a silicide region such as CoSi ₂ (cobalt silicide), but P has a larger range than As. Therefore, the risk of reaching the well region 11 is higher than As.

  When the partial oxide film 31 is obtained by trench isolation, the film thickness of the partial oxide film 31 varies greatly depending on the pattern density, the position in the wafer surface, etc. Scatters about ± 30 nm.

  Therefore, when forming the partial oxide film 31, it is necessary to set a margin in consideration of the above-mentioned variation, but As ions at the time of forming the source / drain regions are surely implanted into the well region 11 below the partial oxide film 31. If the thickness of the partial oxide film 31 is set so as not to occur, the separation step 32 that is the formation height of the partial oxide film 31 from the surface of the SOI layer 3 that is the surface of the SOI substrate cannot be ignored as shown in FIG. It becomes height.

  As a result, when the gate electrode 9 is formed, as shown in FIG. 35, if the etching time for forming the gate is increased so that the residue 33 is not formed on the side surface of the partial oxide film 31 or the residue 33 is not generated, There is a problem that the reliability of the gate oxide film 8 is lowered due to damage to the film 8.

FIG. 36 is a plan view of a conventional semiconductor device having a partially separated body-fixed SOI structure. FIG. 33 is a cross-sectional view taken along the line CC of FIG. At the time of N-type impurity implantation when forming the source / drain regions, the N ⁺ block region 40 covering the entire body region 10 is masked with a resist or the like so that the N-type impurity is not implanted into the P-type body region 10.

As shown in FIG. 36, the N ⁺ block region 40 has a minimum necessary size so as to reliably cover the body region 10 so that the gate oxide film 8 is not charged and electrostatically broken by charge-up. It was common to form.

On the other hand, when the P-type impurity is implanted into the body region 10, the P ⁺ block region 39 covering the entire drain region 5 and the source region 6 is formed so that the P-type impurity is not implanted into the N-type drain region 5 and the source region 6. Masked with resist or the like.

For the same reason as the N ⁺ block region 40, the P ⁺ block region 39 is generally formed in the minimum necessary size so as to reliably cover the drain region 5 and the source region 6, as shown in FIG. Met.

As described above, since the formation of the source / drain regions and the formation of the body region are performed while masking the N ⁺ block region 40 and the P ⁺ block region 39, respectively, other than the P ⁺ block region 39 and the N ⁺ block region 40 In this region, both N-type and P-type impurities are implanted.

  As a result, as described above, the well that electrically connects the body region 10 and the channel formation region 7 (not shown in FIG. 36, but present in the SOI layer 3 below the gate electrode 9 as shown in FIG. 33). Impurities are implanted into the region 11 to cause a problem such as an increase in the resistance value of the body resistor R1, which is the resistance of the well region 11 from the body region 10 to the channel formation region 7, and variations. The problem that it becomes difficult to control well arises.

  When the resistance value of the body resistance R1 is increased, there is a problem that the operation becomes unstable due to fluctuations in the threshold voltage of the transistor. This problem is disclosed in, for example, “S. Maeda et al., IEEE TRANSACTION ON ELACTRON DEVICES vol. 45, no. 7 pp. 1479-1486 (1998)”.

  In addition, since the body resistance becomes a noise source and increases the noise of the transistor, when a circuit such as PLL (Phase Locked Loop) is configured using a transistor whose body resistance is unstable, phase noise is reduced. Problems such as an increase occur.

  As described above, the stable control by lowering the body resistance is an important matter for a semiconductor device having a partially isolated body-fixed SOI structure.

  The present invention has been made to solve the above problems, and an object of the present invention is to obtain a method of manufacturing a semiconductor device having a partially isolated body-fixed SOI structure in which body resistance is reduced.

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: (a) a substrate, an insulating layer on the substrate, and a silicon layer on the insulating layer, wherein the silicon layer includes a transistor formation region and a partial isolation. Providing an SOI substrate having a first conductivity type in the formation region and the body region formation region; and (b) insulating the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region. Forming a partial oxide film having a thickness that does not reach the layer, and the step (b) includes (b-0) depositing an oxide film and a nitride film for forming a trench on the SOI substrate. (B-1) forming a trench that does not reach the insulating layer on the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region ; (b-2) oxidizing the trench Fill with membrane Degree, and (b-3) has a step of forming the polished oxide film partially oxidized film, (c) in the transistor formation region, a gate oxide film on the silicon layer surface, the partial isolation formation region Forming a gate electrode extending on the partial oxide film, and (d) using a first mask layer that covers the body region formation region and exposes the transistor formation region, and has both ends of the gate electrode in the transistor formation region using a step of a first impurity of the second conductivity type is introduced to form the source and drain regions in parts, the second mask layer to expose the (e) covers the transistor formation region, the body region forming region, body region further comprising a second impurity of the first conductivity type is introduced into the forming region and forming a body region, said first mask layer, the body region forming region and the partial isolation type Region, and covers a portion of the gate electrode in the partial isolation formation region.

The method according to claim 2, wherein according to the present invention, (a) a substrate, an insulating layer on the substrate, a silicon layer on said insulating layer, said silicon layer transistor forming region, partial isolation Providing an SOI substrate having a first conductivity type in the formation region and the body region formation region; and (b) insulating the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region. Forming a partial oxide film having a thickness that does not reach the layer, and the step (b) includes (b-0) depositing an oxide film and a nitride film for forming a trench on the SOI substrate. (B-1) forming a trench that does not reach the insulating layer on the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region ; (b-2) oxidizing the trench Fill with membrane Degree, and (b-3) has a step of forming the polished oxide film partially oxidized film, (c) in the transistor formation region, a gate oxide film on the silicon layer surface, the partial isolation formation region Forming a gate electrode extending on the partial oxide film, and (d) using a first mask layer that covers the body region formation region and exposes the transistor formation region, and has both ends of the gate electrode in the transistor formation region using a step of a first impurity of the second conductivity type is introduced to form the source and drain regions in parts, the second mask layer to expose the (e) covers the transistor formation region, the body region forming region, body region And a step of introducing a second impurity of the first conductivity type into the formation region to form a body region, wherein the first mask layer is formed from the body region formation region to the partial isolation formation region. And partially covering the gate electrode in the partial isolation formation region .

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising: (a) a substrate, an insulating layer on the substrate, and a silicon layer on the insulating layer, wherein the silicon layer includes a transistor formation region and a partial isolation. Providing an SOI substrate having a first conductivity type in the formation region and the body region formation region; and (b) insulating the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region. Forming a partial oxide film having a thickness that does not reach the layer, and the step (b) includes (b-0) depositing an oxide film and a nitride film for forming a trench on the SOI substrate. (B-1) forming a trench that does not reach the insulating layer on the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region ; (b-2) oxidizing the trench Filling with film , And (b-3) has a step of forming the oxide film polishing partial oxidation film, in (c) the transistor formation region, a gate oxide film on the silicon layer surface, of the partial isolation formation region Forming a gate electrode extending on the partial oxide film; and (d) both ends of the gate electrode in the transistor formation region using a first mask layer that covers the body region formation region and exposes the transistor formation region. Forming a source and drain region by introducing a first impurity of a second conductivity type into (e) forming a body region using a second mask layer covering the transistor forming region and exposing the body region forming region; further comprising the step of forming the introducing a second impurity of the first conductivity type in the region body region, said first mask layer, in the partial isolation formation region, and the partial oxidation film It will covering a portion of the gate electrode.

A fourth aspect of the present invention is the method for manufacturing a semiconductor device according to any one of the first to third aspects, wherein the silicon layer includes the transistor formation region , the partial isolation formation region , and the body region formation. A second body region forming region of a second conductivity type different from the region , and in the step (d), the first mask layer exposes the second body region forming region and the first impurity Is also introduced into the second body region forming region , and in the step (e), the second mask layer covers the second body region forming region .

  In a first aspect of the method for manufacturing a semiconductor device according to the present invention, a block region including a body region and a partial region in an isolation insulating film is set as a region that prevents the introduction of impurities of the second conductivity type. Since the active region is formed by introducing the second conductivity type impurity, the implantation of the second conductivity type impurity into the semiconductor region under the block region can be reliably avoided, so that at least one element formation region is formed from the body region. It is possible to reduce the resistance value of the body resistance, which is the resistance of the semiconductor region leading to.

  The second aspect of the method for manufacturing a semiconductor device can avoid the implantation of the second conductivity type impurity into the semiconductor region under the block region by the first resist.

  The third aspect of the semiconductor device manufacturing method can avoid the implantation of the second conductivity type impurity into the semiconductor region under the block region and under the gate electrode by the first resist and the gate electrode.

  According to a fourth aspect of the method for manufacturing a semiconductor device, the first resist and the gate electrode are continuously formed in a region extending from the body region to at least one element formation region. Further reduction can be achieved.

  The fifth aspect of the semiconductor device manufacturing method can avoid the implantation of the second conductivity type impurity into the semiconductor region under the gate electrode by the gate electrode.

  In the sixth aspect of the method for manufacturing a semiconductor device, since the gate electrode is formed in a region extending from the body region to at least one element formation region, the resistance value of the body resistance can be further reduced. it can.

  According to a seventh aspect of the method for manufacturing a semiconductor device, the first and second aperture priority mask methods have first and second openings in regions where introduction of impurities of the second and first conductivity types is desired, respectively. By using this resist, it is possible to avoid the introduction of the second and first conductivity type impurities into the semiconductor region when the second and first conductivity type impurities are introduced, thereby reducing the resistance value of the body resistance. Can be achieved.

  Since the second opening of the second resist in the eighth aspect of the method for manufacturing a semiconductor device includes an opening provided substantially only on the body region, isolation insulation is performed when the impurity of the first conductivity type is introduced. Impurities of the first conductivity type are not introduced in most regions of the film.

  Since the second opening of the second resist in the ninth aspect of the method for manufacturing a semiconductor device includes an opening provided on a part of the body region and the isolation insulating film, By introducing the first conductivity type impurity into the semiconductor region under the second opening at the time of introduction, the resistance value of the body resistance can be reduced. This effect is sufficiently greater than the problem that the first conductivity type impurity is introduced into the isolation insulating film below the second opening.

  According to a tenth aspect of the semiconductor device manufacturing method, since the first conductivity type impurity is implanted from the second opening into a region extending from the body region to at least one element formation region in the semiconductor region, the body resistance The resistance value can be further reduced.

  In the eleventh aspect of the semiconductor device manufacturing method, the first and second resists are provided with the first and second dummy openings, so that the formation areas of the first and second resists can be reduced. .

  In a twelfth aspect of the semiconductor device manufacturing method, the first and second dummy openings are formed in the same position and shape, so that the dummy pattern having the first (second) dummy openings is formed in the first pattern. And can be commonly used for the second resist.

  According to a thirteenth aspect of the semiconductor device manufacturing method, the first and second resist formation areas are formed by providing the first and second dummy openings in the first and second dummy regions, respectively. Can be reduced.

  Furthermore, the first and second dummy regions formed by introducing the first and second conductivity type impurities through the first and second dummy openings are only introduced with one conductivity type impurity, respectively. Therefore, there is no problem associated with the implantation of both the first and second conductivity type impurities.

It is sectional drawing (the 1) which shows the semiconductor device of the partial isolation body fixed SOI structure used as the basis of this invention. It is sectional drawing (the 2) which shows the semiconductor device of the partial isolation body fixed SOI structure used as the basis of this invention. It is a top view which shows the semiconductor device of the partial isolation body fixed SOI structure used as the basis of this invention. It is sectional drawing which shows the basic manufacturing method of the semiconductor device of a partial isolation body fixed SOI structure. It is sectional drawing which shows the basic manufacturing method of the semiconductor device of a partial isolation body fixed SOI structure. It is sectional drawing which shows the basic manufacturing method of the semiconductor device of a partial isolation body fixed SOI structure. It is sectional drawing which shows the basic manufacturing method of the semiconductor device of a partial isolation body fixed SOI structure. It is sectional drawing which shows the basic manufacturing method of the semiconductor device of a partial isolation body fixed SOI structure. It is sectional drawing which shows the basic manufacturing method of the semiconductor device of a partial isolation body fixed SOI structure. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 1 of this invention. FIG. 3 is a cross-sectional view showing a cross-sectional structure when forming a block resist according to the first embodiment. It is sectional drawing which shows the semiconductor device of a general partial isolation body fixed SOI structure. It is explanatory drawing which shows the fall phenomenon of a partial oxide film. It is sectional drawing which shows the cross-section of the semiconductor device of the partial isolation body fixed SOI structure manufactured with the conventional manufacturing method. 3 is a cross-sectional view showing a cross-sectional structure of a semiconductor device having a partially separated body-fixed SOI structure manufactured by the manufacturing method according to the first embodiment; FIG. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 2 of this invention. 6 is a cross-sectional view showing a cross-sectional structure when forming a block resist according to Embodiment 2. FIG. FIG. 10 is a cross-sectional view showing a cross-sectional structure of a semiconductor device having a partially isolated body-fixed SOI structure manufactured by the manufacturing method of the second embodiment. FIG. 10 is a cross-sectional view showing a cross-sectional structure of a semiconductor device having a partially isolated body-fixed SOI structure manufactured by the manufacturing method of the second embodiment. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 3 of this invention. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 4 of this invention. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 5 of this invention. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 6 of this invention. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 7 of this invention. FIG. 25 is a cross sectional view showing a cross sectional structure when forming a P ⁺ implantation resist in the seventh embodiment. FIG. 24 is a cross-sectional view showing a cross-sectional structure when an N ⁺ implantation resist is formed in the seventh embodiment. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 8 of this invention. FIG. 29 is a cross sectional view showing a cross sectional structure when forming a P ⁺ implantation resist in an eighth embodiment. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 9 of this invention. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 10 of this invention. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 11 of this invention. It is a top view which shows the manufacturing method of the semiconductor device of the partial isolation body fixed SOI structure which is Embodiment 12 of this invention. It is sectional drawing for demonstrating the problem of the conventional partial isolation body fixed SOI structure. It is a graph which shows the impurity profile of As. It is sectional drawing for demonstrating the problem by the isolation | separation level | step difference of a partial oxide film. It is a top view of the semiconductor device of a partial isolation body fixed SOI structure.

<Basic structure>
1 to 3 are views showing the configuration of a semiconductor device having a partially separated body-fixed SOI structure which is the basis of the present invention. 1 and 2 are sectional views, and FIG. 3 is a plan view. The AA and BB sections in FIG. 3 are respectively FIG. 1 and FIG.

  As shown in these figures, each transistor formation region of the SOI layer 3 in the SOI structure semiconductor device including the silicon substrate 1, the buried oxide film 2, and the SOI layer has a well region (11, 12) formed in the lower layer portion. Separated by the partial oxide film 31. That is, a p-type well region 11 is formed below the partial oxide film 31 separating the NMOS transistors, and an n-type well region 12 is formed below the partial oxide film 31 separating the PMOS transistors. The p-type well region 11 (NMOS transistor formation region side) and the n-type well region 12 (PMOS transistor formation region side) are formed below the partial oxide film 31 (isolation insulating film) separating the PMOS transistors. .

  As shown in FIG. 3, the well region 11 is formed so as to surround the drain region 5 and the source region 6 of the NMOS transistor group, and the well region 12 is formed so as to surround the drain region 5 and the source region 6 of the PMOS transistor group. The In this basic structure, the SOI layer 3 is covered with an interlayer insulating film 4.

  In this basic structure, one unit of MOS transistor separated from other transistors by the partial oxide film 31 includes a drain region 5, a source region 6, a channel formation region 7, and a channel formation region 7 formed in the SOI layer 3. And a gate electrode 9 formed on the gate oxide film 8. In addition, the wiring layer 22 formed on the interlayer insulating film 4 is electrically connected to the drain region 5 or the source region 6 through a contact 21 provided in the interlayer insulating film 4. Although the contact 21 is drawn large, the contact may be made by opening a plurality of small holes.

  As shown in FIGS. 2 and 3, a body region 10 is formed between the well regions 11 in the SOI layer 3, and the body region 10 is in contact with the adjacent well region 11. The wiring layer 25 formed on the interlayer insulating film 4 is electrically connected to the body region 10 via the body contact 23 provided in the interlayer insulating film 4. Further, the wiring layer 26 formed on the interlayer insulating film 4 is electrically connected to the gate electrode 9 through the gate contact 24 provided in the interlayer insulating film 4.

  As described above, in the semiconductor device having this basic structure, as shown in FIGS. 1 to 3, the partial oxide film 31 in the element isolation region does not reach the lower part of the SOI layer 3, and the channel formation of the transistor to be isolated is performed. Well regions 11 and 12 into which impurities of the same conductivity type as the region are introduced are provided under the partial oxide film 31.

  Therefore, the substrate potential of each transistor can be fixed from the outside through the wiring layer 25, the body contact 23, the high-concentration body region 10 and the well region 11. Similarly, the substrate potential of each transistor can be fixed via the body region on the PMOS transistor side.

Hereinafter, the details will be described with reference to FIGS. The thickness of the buried oxide film 2 is, for example, about 100 to 500 nm, and the thickness of the SOI layer 3 is about 30 to 200 nm. The channel forming region 7 is formed by introducing a first conductivity type impurity (p-type impurity for NMOS, n-type impurity for PMOS) of about 10 ¹⁷ to 10 ¹⁸ / cm ³ , for example. The drain region 5 and the source region 6 are adjacent to the channel forming region 7 and are introduced by introducing a second conductivity type impurity (for example, an n-type impurity in NMOS and a p-type impurity in PMOS) of about 10 ¹⁹ to 10 ²¹ / cm ³ . It is formed.

  The partial oxide film 31 that separates adjacent transistors is formed by leaving the lower layer portion of the SOI layer 3 for, for example, about 10 to 100 nm for forming a well region.

The well regions 11 and 12 having the same conductivity type as the channel formation region (for example, an impurity concentration of 10 ^{17 to} 5 × 10 ¹⁸ / cm ³ , the impurity concentration is the channel formation region) Or higher, the higher the concentration, the more the punch-through can be prevented and the separation performance improved).

Further, as shown in FIG. 2, the body region 10 is doped with impurities of the same conductivity type as that of the adjacent well region 11 and having a high concentration of 10 ¹⁹ to 10 ²¹ / cm ³ .

<Basic manufacturing method of MOS transistor>
4 to 9 are sectional views showing a basic manufacturing method of a semiconductor device having a partially separated body-fixed SOI structure.

  First, as shown in FIG. 4, an SOI substrate formed by a SIMOX method for forming a buried oxide film 2 by oxygen ion implantation or the like, which includes a silicon substrate 1, a buried oxide film 2, and an SOI layer 3, is used as a starting material. Normally, the SOI layer 3 has a thickness of 50 to 200 nm, and the buried oxide film 2 has a thickness of 100 to 400 nm.

  Then, as shown in FIG. 5, an oxide film 141 of about 20 nm and a nitride film 142 of about 200 nm are sequentially deposited on the SOI substrate, and then the isolation region is patterned using the patterned resist 143 as a mask. A plurality of partial trenches 144 are formed by etching the three multilayer films of the oxide film 141 and the SOI layer 3 so that the lower layer portion of the SOI layer 3 remains.

  Next, as shown in FIG. 6, an oxide film having a thickness of about 500 nm is deposited and polished halfway through the nitride film 142 by a CMP process in the same manner as in normal trench isolation, and then the nitride film 142 and the oxide film 141 are formed. By performing the removal, a structure in which the partial oxide film 31 and the SOI layer 3 (well regions 11 and 12) thereunder are formed can be obtained.

  Thereafter, the NMOS formation region of the SOI layer 3 is made an N-type region and the PMOS formation region is made a P-type region by using an existing CMOS transistor formation method such as selective impurity implantation.

  Then, as shown in FIG. 7, the gate oxide film 8 and the gate electrode 9 are selectively formed in each region in which the NMOS and PMOS regions are separated in MOS transistor units by the partial oxide film 31.

  After that, as shown in FIG. 8, a resist 15 is formed on the source / drain region formation scheduled region on the PMOS transistor formation region side and the body region formation scheduled region on the NMOS transistor side, and these regions are masked and N By implanting type impurity ions 17, a drain region 5 and a source region 6 are formed in the NMOS region and a body region (not shown) is formed in the PMOS region at the same time.

  Then, as shown in FIG. 9, after removing the resist 15, a resist 16 is formed on the drain region 5 on the NMOS transistor side and the source region 6 and on the body region (not shown) on the PMOS transistor side. By implanting P-type impurity ions 18 after masking the region, a drain region 5 and a source region 6 are simultaneously formed in the PMOS region, and a body region (not shown) is simultaneously formed in the NMOS region.

<Embodiment 1>
FIG. 10 is a plan view showing a method of manufacturing a semiconductor device having a partially isolated body fixed SOI structure according to the first embodiment of the present invention.

As shown in the figure, the P ⁺ block region 39 is formed in the minimum size necessary to reliably cover the region where the drain region 5 and the source region 6 are formed (scheduled) as in the conventional case. ⁺ Block region 41 securely covers the formation (planned) region of body region 10 and is a gate in which a partial region on the extension line in the longitudinal direction (gate width direction) of gate electrode 9 extends toward gate contact region 9c. It has the direction extension area | region 41a.

P ⁺ block region 39 indicates a resist formation region at the time of implantation of P-type impurity ions 18 in FIG. 9, and N ⁺ block region 41 indicates a resist formation region at the time of implantation of N-type impurity ions 17 in FIG. Yes.

  FIG. 11 is a cross-sectional view showing a cross-sectional structure when the block resist is formed according to the first embodiment, and corresponds to a CC cross section of FIG.

As shown in the figure, the N ⁺ block resist 51 is formed on an N ⁺ block region 41 extending in the direction of the gate electrode 9 from the conventional N ⁺ block region 40. Similarly, the P ⁺ block resist 59 is formed on the P ⁺ block region 39.

In FIG. 11, both the N ⁺ block resist 51 and the P ⁺ block resist 59 are shown for convenience, but actually, the N ⁺ block resist 51 and the P ⁺ block resist 59 are not present at the same time. 7 to 9, the N ⁺ block resist 51 is provided during the step shown in FIG. 8, and the P ⁺ block resist 59 is provided during the step shown in FIG.

As shown in FIG. 11, the gate region extension region 41 a of the N ⁺ block region 41 is a well region 11 that may be implanted with both N-type and P-type impurities on the longitudinal extension line of the gate electrode 9. The resistance forming region can be narrowed from the conventional high resistance forming region A1 to the high resistance forming region A2.

  Thus, the N-type impurity is not implanted into the well region 11 below the gate direction extension region 41a. That is, since the well region 11 under the gate direction extension region 41a becomes a P-type impurity region into which N-type impurities are not mixed, the resistance value of the body resistance can be lowered and variations can be suppressed accordingly. As a result, it is possible to obtain a semiconductor device having a partially separated body-fixed SOI structure that can be accurately controlled without increasing the resistance value of the body resistance.

In addition, by performing the manufacturing method of the first embodiment in which the N ⁺ block region 41 is changed from the conventional N ⁺ block region, the number of manufacturing steps does not increase from the conventional one.

  FIG. 12 is a cross-sectional view showing a general semiconductor device having a partially separated body-fixed SOI structure. As shown in the figure, when the thickness of the SOI layer 3 is 100 nm, the partial oxide film 31 is dug by 50 nm by trench etching, and the partial oxide film 31 is formed so that a separation step protruding 30 nm from the surface of the SOI layer 3 is provided. Assume that it is formed. In the example of FIG. 12, a structure in which the sidewall 13 is formed on the side surface of the gate electrode 9 is shown.

  In consideration of variations in the CMP process (during the process of FIG. 6), the separation step of about ± 30 nm varies. Therefore, the thickness of the partial oxide film 31 varies from 80 ± 30 nm, that is, 50 to 110 nm. In the worst case, the film thickness is 50 nm, and N-type impurities are injected into the partial oxide film 31 to reduce the body resistance. It will be a situation that ends up. However, according to the manufacturing method of the first embodiment, even in such a case, since the N-type impurity is not implanted into the well region 11 below the gate direction extension region 41a, the above problem can be improved.

  FIG. 13 is an explanatory diagram showing the phenomenon of partial oxide film dropping. In general, a region in which both N-type and P-type impurities are implanted in the partial oxide film 31 has a property of being cut faster than other regions during the wet etching process. Therefore, as shown in FIG. A phenomenon occurs. In FIG. 13, the oxide film 4 a and the silicon nitride film 4 b are layers that form the interlayer insulating film 4, and the silicon nitride film 13 b is a layer that forms the sidewall 13.

As the wet etching process, an APM that uses a mixed solution of dilute hydrofluoric acid (HF), ammonia (NH ₄ OH), hydrogen peroxide (H ₂ O ₂ ), and pure water (H ₂ O) as a cleaning solution. (Ammonia-Hydrogen Peroxide Mixture) cleaning and the like can be mentioned. For example, dilute hydrofluoric acid (HF) treatment is performed when the TEOS oxide film constituting the sidewall 13 is removed.

  As a result, since the effective film thickness of the well region 11 is reduced by the amount of the depletion layer extension 37, the body resistance is increased. Therefore, it is desirable to suppress the depression phenomenon as much as possible.

  FIG. 14 is a cross-sectional view showing a cross-sectional structure of a semiconductor device having a partially separated body-fixed SOI structure manufactured by a conventional manufacturing method. FIG. 14 corresponds to the CC cross section of FIG.

  As shown in the figure, the sidewall 13 is formed of a TEOS oxide film 13a and a silicon nitride film 13b, and the interlayer insulating film 4 is formed of an oxide film 4a, a silicon nitride film 4b and an oxide film 4c.

As shown in FIG. 14, since only the N ⁺ block region 40 is masked from the implantation of the N-type impurity, the N-type impurity is implanted in the most part of the partial oxide film 31, and the above-described depression in the regions A5 to A7. The phenomenon will occur.

  FIG. 15 is a cross-sectional view showing a cross-sectional structure of a semiconductor device having a partially isolated body-fixed SOI structure manufactured by the manufacturing method of the first embodiment. FIG. 15 corresponds to the CC cross section of FIG.

As shown in FIG. 15, since the N ⁺ block region 41 wider than the N ⁺ block region 40 by the gate direction extension region 41a is masked from the implantation of the N-type impurity, the above-described depression phenomenon occurs in the regions A5 and A7 as in the conventional case. Although it occurs, since the region A6 is masked from the N-type impurity implantation by the gate direction extension region 41a, the drop phenomenon can be avoided. That is, since the partial oxide film 31 under the N ⁺ block resist 51 becomes an N-type impurity non-entry region that does not contain an N-type impurity, no drop phenomenon occurs in the region A6.

  As described above, the manufacturing method of the first embodiment can reduce the resistance value of the body resistance as much as the drop phenomenon can be suppressed as compared with the conventional method.

FIG. 10 shows the P ⁺ block region 39 and the N ⁺ block region 41 in the NMOS region. Similarly, in the PMOS region, a P equivalent to the N ⁺ block region 41 is formed on the body (to be formed) region. ^{If a +} block region is formed and an N ⁺ block region equivalent to the P ⁺ block region 39 is formed on the source / drain (to be formed) region, the same effect can be obtained.

<Embodiment 2>
FIG. 16 is a plan view showing a method of manufacturing a semiconductor device having a partially isolated body-fixed SOI structure according to the second embodiment of the present invention.

As shown in the figure, the N ⁺ block region 42 reliably covers the formation (planned) region of the body region 10 and extends a partial region on the longitudinal extension line of the gate electrode 9 toward the gate contact region 9c. In addition, the gate direction extension region 42a partially overlaps the gate contact region 9c.

The P ⁺ block region 39 indicates a resist formation region at the time of implantation of the P-type impurity ions 18 in FIG. 9, and the N ⁺ block region 42 indicates the resist formation region at the time of implantation of the N-type impurity ions 17 in FIG. Yes. Other configurations are the same as those of the first embodiment shown in FIG.

  FIG. 17 is a cross-sectional view showing a cross-sectional structure when the block resist of the second embodiment is formed, and corresponds to the CC cross section of FIG.

As shown in the figure, the N ⁺ block resist 52 is formed on the N ⁺ block region 42 that overlaps the gate electrode 9 in the overlap region A3. The P ⁺ block resist 59 is formed on the P ⁺ block region 39.

  As shown in FIG. 17, in the well region 11, the body resistance path 36 on the longitudinal extension of the gate electrode 9 is substantially composed of a high resistance formation region in which both N-type and P-type impurities may be implanted. No longer exists. That is, on the extension line in the longitudinal direction of the gate electrode 9, the well region 11 from the body region 10 to the channel formation region 7 constituting the transistor formation region becomes a P-type impurity region into which N-type impurities are not mixed.

This is because the gate electrode 9 usually has a thickness of about 200 nm, and the gate electrode 9 can reliably block impurity implantation such as As implanted at 50 keV and P implanted at 40 keV. The well region 11 on the longitudinal extension line 9 is reliably blocked from the N-type impurity implantation by the N ⁺ block resist 52 and the gate electrode 9.

  Therefore, the N-type impurity is certainly not implanted into the well region 11 on the longitudinal extension line of the gate electrode 9, and accordingly, the resistance value of the body resistance is reduced and the variation is suppressed. it can. In addition, in the second embodiment, since the high resistance forming region does not exist in the body resistance path 36, the effect of reducing the body resistance can be obtained compared to the first embodiment.

  As a result, it is possible to obtain a semiconductor device having a partially separated body-fixed SOI structure that can be accurately controlled without increasing the resistance value of the body resistance.

In addition, by performing the manufacturing method according to the second embodiment while changing the N ⁺ block region 42 from the conventional N ⁺ block region, the number of manufacturing steps does not increase.

  FIG. 18 is a cross-sectional view showing a cross-sectional structure of a semiconductor device having a partially isolated body-fixed SOI structure manufactured by the manufacturing method of the second embodiment. 18 corresponds to the CC cross section of FIG.

As shown in FIG. 18, since the N ⁺ block region 42 wider than the N ⁺ block region 40 in the gate direction extension region 42a and the region under the gate electrode 9 are masked from the implantation of the N-type impurity, a drop phenomenon occurs in the region A5. Although generated, the regions A6 and A7 are masked from the implantation of the N-type impurity by the gate direction extension region 42a, so that a drop phenomenon can be avoided. That is, since the region of the partial oxide film 31 from the body region 10 under the N ⁺ block resist 52 and the gate electrode 9 to the channel formation region 7 becomes an N-type impurity non-entry region, the phenomenon of falling into the regions A6 and A7 occurs. Does not occur.

  As described above, the manufacturing method of the second embodiment can further reduce the resistance value of the body resistance since the depression phenomenon can be suppressed as compared with the first embodiment.

  FIG. 19 is a cross-sectional view showing a cross-sectional structure of a semiconductor device having a partially separated body-fixed SOI structure manufactured by the manufacturing method of the second embodiment. FIG. 19 corresponds to the DD cross section of FIG.

  As shown in the figure, a drop phenomenon occurs in the region A4 of the partial oxide film 31 that is not masked by the gate electrode 9 and the sidewalls 13 (13a, 13b).

FIG. 16 shows the P ⁺ block region 39 and the N ⁺ block region 42 in the NMOS region. However, as in the first embodiment, the same effect can be obtained by forming an equivalent block region in the PMOS region. Can do.

<Embodiment 3>
FIG. 20 is a plan view showing a method of manufacturing a semiconductor device having a partially separated body-fixed SOI structure according to the third embodiment of the present invention.

As shown in the figure, the N ⁺ block region 43 reliably covers the formation (planned) region of the body region 10 and extends the entire region on the gate electrode 9 side toward the gate contact region 9c. It is provided so as to partially overlap 9c.

The P ⁺ block region 39 indicates a resist formation region at the time of implantation of the P-type impurity ions 18 in FIG. 9, and the N ⁺ block region 43 indicates the resist formation region at the time of implantation of the N-type impurity ions 17 in FIG. Yes. Other configurations are the same as those of the second embodiment shown in FIG.

  In the manufacturing method of the third embodiment, as in the second embodiment, since the N-type impurity is surely not implanted into the body resistance path in the well region 11, the resistance value of the body resistance is reduced accordingly. In addition, the variation can be suppressed and the effect of reducing the body resistance can be obtained from the first embodiment or more.

  As a result, it is possible to obtain a semiconductor device having a partially separated body-fixed SOI structure that can be accurately controlled without increasing the resistance value of the body resistance.

In addition, by performing the manufacturing method according to the third embodiment while changing the N ⁺ block region 43 from the conventional N ⁺ block region, the number of manufacturing steps does not increase.

  Furthermore, the manufacturing method of the third embodiment can further reduce the resistance value of the body resistance because the sagging phenomenon can be suppressed as compared with the first embodiment for the same reason as the second embodiment. .

In FIG. 20, the P ⁺ block region 39 and the N ⁺ block region 43 in the NMOS region are shown. However, as in the first embodiment and the second embodiment, if the equivalent block region is formed in the PMOS region, it is equivalent. The effect of can be obtained.

<Embodiment 4>
FIG. 21 is a plan view showing a method for manufacturing a semiconductor device having a partially isolated body-fixed SOI structure according to the fourth embodiment of the present invention.

As shown in the figure, the N ⁺ block region 44 reliably covers the formation (planned) region of the body region 10 and extends the entire region on the gate electrode 9 side toward the gate extension region 9d. 9d is provided so as to partially overlap.

Note that the P ⁺ block region 39 indicates a resist formation region when the P-type impurity ions 18 in FIG. 9 are implanted, and the N ⁺ block region 44 indicates a resist formation region when the N-type impurity ions 17 in FIG. 8 are implanted. Yes. Other configurations are the same as those of the second embodiment shown in FIG.

  In the manufacturing method of the fourth embodiment, as in the second and third embodiments, the N-type impurity is surely not implanted into the body resistance path in the well region 11. The resistance value can be reduced and the variation can be suppressed, and the effect of reducing the body resistance can be obtained from the first embodiment or more.

  As a result, it is possible to obtain a semiconductor device having a partially separated body-fixed SOI structure that can be accurately controlled without increasing the resistance value of the body resistance.

In addition, by performing the manufacturing method according to the fourth embodiment while changing the N ⁺ block region 44 from the conventional N ⁺ block region, the number of manufacturing steps does not increase.

  Furthermore, the manufacturing method of the fourth embodiment can further reduce the resistance value of the body resistance because the sagging phenomenon can be suppressed as compared with the first embodiment for the same reason as the second embodiment. .

In FIG. 21, the P ⁺ block region 39 and the N ⁺ block region 44 in the NMOS region are shown. However, as in the first to third embodiments, if the equivalent block region is formed in the PMOS region, it is equivalent. The effect of can be obtained.

<Embodiment 5>
FIG. 22 is a plan view showing a method of manufacturing a semiconductor device having a partially isolated body-fixed SOI structure according to the fifth embodiment of the present invention.

  As shown in the figure, in the fifth embodiment, a gate wiring portion 14 having a function of a gate electrode and a gate wiring is provided in place of the gate electrode 9 used in the first to fourth embodiments. The wiring portion 14 extends in the direction of the body region 10 from above the channel formation region 7 (not shown) between the drain region 5 and the source region 6 and is bent in the middle.

The N ⁺ block region 45 reliably covers the formation (planned) region of the body region 10, extends the entire region on the P ⁺ block region 39 side toward the gate wiring portion 14, and partially overlaps the gate wiring portion 14 It is provided to do.

The P ⁺ block region 39 indicates a resist formation region when the P-type impurity ions 18 in FIG. 9 are implanted, and the N ⁺ block region 45 indicates the resist formation region when the N-type impurity ions 17 in FIG. 8 are implanted. Yes. Other configurations are the same as those of the second embodiment shown in FIG.

  In the manufacturing method of the fifth embodiment, as in the second to fourth embodiments, N-type impurities are not reliably implanted into the body resistance path in the well region 11, and accordingly, the body resistance is increased accordingly. The resistance value can be reduced and the variation can be suppressed, and the effect of reducing the body resistance can be obtained from the first embodiment or more.

  As a result, it is possible to obtain a semiconductor device having a partially separated body-fixed SOI structure that can be accurately controlled without increasing the resistance value of the body resistance.

In addition, by performing the manufacturing method of the fifth embodiment while changing the N ⁺ block region 45 from the conventional N ⁺ block region, the number of manufacturing steps does not increase from the conventional one.

  Furthermore, the manufacturing method of the fifth embodiment can further reduce the resistance value of the body resistance because the sagging phenomenon can be suppressed as compared with the first embodiment for the same reason as the second embodiment. .

In FIG. 22, the P ⁺ block region 39 and the N ⁺ block region 45 in the NMOS region are shown. However, as in the first to fourth embodiments, if the equivalent block region is formed in the PMOS region, it is equivalent. The effect of can be obtained.

<Embodiment 6>
FIG. 23 is a plan view showing a method of manufacturing a semiconductor device having a partially isolated body fixed SOI structure according to the sixth embodiment of the present invention.

As shown in the figure, the N ⁺ block region 40 is formed in a minimum size to cover the formation (planned) region of the body region 10.

  On the other hand, the gate electrode 9 has a gate extension region 9e formed to extend greatly in the body region 10 direction. Other configurations are the same as those of the first embodiment shown in FIG.

  In the manufacturing method of the sixth embodiment, as in the first embodiment, the N-type impurity is certainly not implanted into the well region 11 below the gate extension region 9e, and accordingly, the resistance value of the body resistance. As well as the first embodiment, the effect of reducing body resistance can be obtained.

  As a result, it is possible to obtain a semiconductor device having a partially separated body-fixed SOI structure that can be accurately controlled without increasing the resistance value of the body resistance.

In addition, since the N ⁺ block region 40 is not changed from the conventional N ⁺ block region, the number of manufacturing steps does not increase conventionally by performing the manufacturing method of the sixth embodiment.

  Further, in the manufacturing method of the sixth embodiment, as in the first embodiment, the partial oxide film 31 under the gate extension region 9e becomes an impurity non-entry region, and the resistance value of the body resistance can be suppressed by suppressing the drop phenomenon. Can be further reduced.

Further, as shown by the one-dot chain line in FIG. 23, the gate extension region 9f is formed to extend until it partially overlaps the N ⁺ block region 40, so that the well region is the same as in the second to fourth embodiments. Since the N-type impurity is surely not implanted into the body resistance path in No. 11, the effect of reducing the body resistance can be obtained from the first embodiment or more.

  In FIG. 23, the gate extension regions 9e and 9f in the NMOS region are shown. However, if a gate electrode having a gate extension region equivalent to the PMOS region is formed, the same effect can be obtained.

  In addition, since the gate extension regions 9e and 9f are present, the partial oxide film 31 under the gate extension regions 9e and 9f is not thinned by the wet etching process after the gate electrode 9 is formed, so that the body resistance path 36 is obtained. The degree to which the body resistance varies due to the influence of the gate voltage in the well region can be reduced.

<Embodiment 7>
In the first to sixth embodiments, a shielding priority mask is used in which a resist is formed on a block region mainly including a source / drain region and a body region for the purpose of preventing impurity implantation. Yes.

  The shielding priority mask has been generally used to date, mainly to minimize the resist formation area and prevent electrostatic breakdown of the gate oxide film or the like during impurity ion implantation.

  The shielding priority mask design method is classified into the following (1) and (2).

  (1) A region where impurity implantation should be blocked is designed by CAD or the like, and a positive resist is exposed using a mask (positive mask) that uses the region as a light shielding portion on the mask as it is.

  (2) The region where impurity implantation should be blocked is designed by CAD or the like, and the negative resist is exposed using a mask (anti-mask) having a region other than the region as a light shielding portion.

  However, in recent years, ion implantation techniques have improved, and the above-described electrostatic breakdown is less likely to occur by performing a process such as an electron shower to compensate for charge-up during ion implantation.

  Therefore, although the resist area is large, the manufacturing method according to the seventh embodiment employs an opening priority mask in which openings are mainly provided in regions where impurities are to be implanted.

  The design method of the aperture priority mask is classified into the following (3) and (4).

  (3) After designing the region where the impurity is to be implanted by CAD or the like, an anti-mask is created and the positive resist is exposed using it.

  (4) After designing the region where the impurity is to be implanted by CAD or the like, a positive mask is created and the negative resist is exposed using it.

  FIG. 24 is a plan view showing a method of manufacturing a semiconductor device having a partially separated body-fixed SOI structure according to the seventh embodiment of the present invention.

As shown in the figure, an N ⁺ implantation region 60 is provided in the minimum necessary region for injecting N-type impurities into the source / drain regions 5 and 6, and it is necessary to implant P-type impurities into the body region 10. A P ⁺ implantation region 46 is provided in the minimum region.

P ⁺ implantation region 46 indicates a resist opening region at the time of implantation of P-type impurity ions 18 in FIG. 9, and N ⁺ implantation region 60 indicates a resist opening region at the time of implantation of N-type impurity ions 17 in FIG. Yes.

FIG. 25 is a cross-sectional view showing a cross-sectional structure when the P ⁺ implantation resist of the seventh embodiment is formed, and corresponds to the EE cross section of FIG.

As shown in the figure, the P ⁺ implantation resist 61 is formed by opening only the P ⁺ implantation region 46.

FIG. 26 is a cross-sectional view showing a cross-sectional structure during the formation of the N ⁺ implantation resist according to the seventh embodiment, and corresponds to the EE cross section of FIG.

As shown in the figure, the N ⁺ implantation resist 62 is formed by opening only the N ⁺ implantation region 60.

The P ⁺ implantation resist 61 is provided during the step shown in FIG. 9, and the N ⁺ implantation resist 62 is provided during the step shown in FIG.

As shown in FIGS. 25 and 26, by masking with the P ⁺ implantation resist 61 and the N ⁺ implantation resist 62, most of the well region 11 is not implanted with both P-type and N-type impurities. Therefore, the resistance value of the body resistance can be lowered and variations can be suppressed. As a result, it is possible to obtain a semiconductor device having a partially separated body-fixed SOI structure that can be accurately controlled without increasing the resistance value of the body resistance.

  In addition, by performing the manufacturing method of the seventh embodiment in which the shielding priority mask is changed to the opening priority mask, the number of manufacturing steps does not increase from the conventional level.

  Further, since neither N-type nor P-type impurities are implanted into most of the partial oxide film 31 (the part corresponding to the region A12), the partial oxide film 31 hardly causes a drop phenomenon.

  Therefore, the manufacturing method of the seventh embodiment can further suppress the drop phenomenon, and can reduce the resistance value of the body resistance.

<Eighth embodiment>
27 is a plan view showing a method of manufacturing a semiconductor device having a partially isolated body-fixed SOI structure according to an eighth embodiment of the present invention.

As shown in the drawing, in addition to the minimum necessary region for injecting P-type impurities into the body region 10, a partial region on the longitudinal extension line of the gate electrode 9 is extended toward the gate contact region 9c. A P ⁺ implantation region 47 is formed.

Note that the P ⁺ implantation region 47 indicates a resist opening region when the P-type impurity ions 18 in FIG. 9 are implanted, and the N ⁺ implantation region 60 indicates a resist opening region when the N-type impurity ions 17 are implanted in FIG. Yes.

FIG. 28 is a cross-sectional view showing a cross-sectional structure during the formation of the P ⁺ implantation resist of the eighth embodiment, and corresponds to the EE cross section of FIG.

As shown in the figure, the P ⁺ implantation resist 63 is formed by opening only the P ⁺ implantation region 47. The P ⁺ implantation resist 63 is provided during the process shown in FIG. The cross-sectional structure when forming the N ⁺ implantation resist is the same as that of the seventh embodiment shown in FIG.

As shown in FIG. 28, by masking with the P ⁺ implantation resist 63, most of the well region 11 is not implanted with N-type impurities, so that the resistance value of the body resistance is lowered and the variation is suppressed. can do.

  Further, as shown in FIG. 28, P-type impurity ions 66 are positively implanted into the well region 11 under the partial oxide film 31, thereby increasing the P-type impurity concentration in the well region 11 and reducing the resistance value of the body resistance. Reduction can be actively promoted.

  As a result, it is possible to obtain a semiconductor device having a partially separated body-fixed SOI structure that can be accurately controlled without increasing the resistance value of the body resistance.

  In addition, by performing the manufacturing method according to the eighth embodiment in which the shielding priority mask is changed to the opening priority mask, the number of manufacturing steps does not increase from the conventional level.

Further, most of the partial oxide film 31 is not implanted with N-type impurities by the N ⁺ implantation resist 62. On the other hand, the P-type impurity is implanted into most of the partial oxide film 31. However, since the effect of reducing the resistance value of the body resistance due to the implantation of the P-type impurity into the well region 11 is large, the P-type impurity is Even if a drop phenomenon caused by being implanted into most of the partial oxide film 31 is taken into account, the resistance value of the body resistance can be reduced.

Further, since the P ⁺ implantation region 47 of the eighth embodiment is made larger than the P ⁺ implantation region 46 of the seventh embodiment, the resist formation area can be made smaller than that of the seventh embodiment.

Note that, as indicated by a one-dot chain line in FIG. 27, a P ⁺ implantation region 48 may be formed so as to partially overlap the gate contact region 9c. In this case, the resistance value of the body resistance can be further reduced.

<Embodiment 9>
FIG. 29 is a plan view showing a method of manufacturing a semiconductor device having a partially isolated body fixed SOI structure according to the ninth embodiment of the present invention.

As shown in the figure, in addition to the minimum necessary region for injecting P-type impurities into the body region 10, a partial region on the longitudinal extension line of the gate electrode 9 is extended toward the gate extension region 9d, A P ⁺ implantation region 49 partially overlapping with the gate extension region 9d is formed.

Note that the P ⁺ implantation region 49 indicates a resist opening region when the P-type impurity ions 18 in FIG. 9 are implanted, and the N ⁺ implantation region 60 indicates a resist opening region when the N-type impurity ions 17 are implanted in FIG. Yes.

  According to the manufacturing method of the ninth embodiment, a semiconductor device having a partially isolated body-fixed SOI structure that can be controlled with high accuracy without increasing the resistance value of the body resistance can be obtained by the same effect as in the eighth embodiment.

  In addition, as in the manufacturing method of the eighth embodiment, the number of manufacturing steps does not increase from the past.

Further, since the P ⁺ implantation region 49 of the ninth embodiment is made larger than the P ⁺ implantation region 46 of the seventh embodiment, the resist formation area can be made smaller than that of the seventh embodiment.

<Embodiment 10>
30 is a plan view showing a method of manufacturing a semiconductor device having a partially isolated body-fixed SOI structure according to the tenth embodiment of the present invention.

  As shown in the figure, in the tenth embodiment, similarly to the fifth embodiment, a gate wiring portion 14 having functions of a gate electrode and a gate wiring is provided in place of the gate electrode 9, and the gate wiring portion 14 is The channel region 7 (not shown) between the drain region 5 and the source region 6 extends in the direction of the body region 10 and is bent in the middle.

On the other hand, in addition to the minimum necessary region for injecting the P-type impurity into the body region 10, a partial region on the N ⁺ implantation region 60 side is extended toward the gate wiring portion 14, and the gate wiring portion 14 and a part thereof A P ⁺ implantation region 50 is provided so as to overlap.

P ⁺ implantation region 50 indicates a resist opening region at the time of implantation of P-type impurity ions 18 in FIG. 9, and N ⁺ implantation region 60 indicates a resist opening region at the time of implantation of N-type impurity ions 17 in FIG. Yes.

  According to the manufacturing method of the tenth embodiment, a semiconductor device having a partially isolated body-fixed SOI structure that can be controlled with high accuracy without increasing the resistance value of the body resistance can be obtained by the same effect as in the eighth embodiment.

  In addition, as in the manufacturing method of the eighth embodiment, the number of manufacturing steps does not increase from the past.

Further, since the P ⁺ implantation region 50 of the tenth embodiment is made larger than the P ⁺ implantation region 46 of the seventh embodiment, the resist formation area can be made smaller than that of the seventh embodiment.

<Embodiment 11>
FIG. 31 is a plan view showing a method of manufacturing a semiconductor device having a partially isolated body fixed SOI structure according to an eleventh embodiment of the present invention.

As shown in the figure, an N ⁺ implantation region 60 is provided in the minimum necessary region for injecting N-type impurities into the source / drain regions 5 and 6, and it is necessary to implant P-type impurities into the body region 10. A P ⁺ implantation region 46 is provided in the minimum region.

  On the other hand, the gate electrode 9 has a gate extension region 9e formed to extend greatly in the body region 10 direction. Other configurations are the same as those of the seventh embodiment shown in FIG.

  According to the manufacturing method of the eleventh embodiment, a semiconductor device having a partially isolated body-fixed SOI structure that can be controlled with high accuracy without increasing the resistance value of the body resistance can be obtained by the same effect as the seventh embodiment.

  In addition, as in the manufacturing method of the seventh embodiment, the number of manufacturing steps does not increase from the past.

Further, as shown by the one-dot chain line in FIG. 31, the gate extension region 9f may be extended to partially overlap the P ⁺ implantation region 46.

By this method, it is possible to eliminate the decrease in the thickness of the partial oxide film 31 at the overlapping portion between the gate extension region 9f and the P ⁺ implantation region 46, and to stabilize the body resistance at a low level.

  Even when the gate extension region 9e is formed, the partial oxide film 31 under the gate extension region 9e is not thinned by the wet etching process after the gate electrode 9 is formed. The degree to which the body resistance fluctuates due to the influence of voltage can be reduced.

<Embodiment 12>
FIG. 32 is a plan view showing a method of manufacturing a semiconductor device having a partially isolated body-fixed SOI structure according to the twelfth embodiment of the present invention.

As shown in the figure, an N ⁺ implantation region 60 is provided in the minimum necessary region for injecting N-type impurities into the source / drain regions 5 and 6, and it is necessary to implant P-type impurities into the body region 10. In addition to the minimum region, a P ⁺ implantation region 47 is formed by extending a partial region on the longitudinal extension line of the gate electrode 9 toward the gate contact region 9c.

Further, a dummy N ⁺ implantation region 71 is provided in a minimum necessary region for injecting an N type impurity into the P ⁺ dummy region 73, and a minimum necessary region for injecting a P type impurity into the N ⁺ dummy region 74. Are provided with a dummy P ⁺ implantation region 72.

N ⁺ implantation region 60 and dummy N ⁺ implantation region 71 indicate the opening region of the first resist during implantation of N-type impurity ions 17 in FIG. 8, and P ⁺ implantation region 47 and dummy P ⁺ implantation region 72 are illustrated. 9 shows an opening region of the second resist when 9 P-type impurity ions 18 are implanted.

  According to the manufacturing method of the twelfth embodiment, a semiconductor device having a partially isolated body-fixed SOI structure that can be controlled with high accuracy without increasing the resistance value of the body resistance can be obtained by the same effect as the seventh embodiment.

  In addition, as in the manufacturing method of the seventh embodiment, the number of manufacturing steps does not increase from the past.

Further, since the dummy N ⁺ implantation region 71 and the dummy P ⁺ implantation region 72 are provided, the resist formation area can be further reduced. The risk of electrostatic breakdown of the gate oxide film 8 and the like due to charge-up can be suppressed to those of the seventh to eleventh embodiments.

Further, the dummy N ⁺ implantation region 71 and the dummy P ⁺ implantation region 72 are defined as generation rules for the P ⁺ dummy region 73 and the N ⁺ dummy region 74 (for example, formed for uniform pattern density for CMP). Similarly, since it is sufficient to automatically generate a rectangular shape, the design can be made relatively easily.

In the example shown in FIG. 32, the dummy N ⁺ implantation region 71 and the dummy P ⁺ implantation region 72 are provided separately for the first and second resists, but the same positions are provided between the first and second resists. Alternatively, a dummy implantation region may be provided in a shape and shared as a dummy N ⁺ P ⁺ both implantation region.

However, if both N-type and P-type impurities are implanted into the dummy region, there is a possibility that a defect such as separation of the silicide region may occur, so that a dummy N ⁺ implantation region 71 and a dummy P ⁺ implantation region 72 are provided as shown in FIG. It is desirable that only one of the N-type and P-type impurities is implanted into the dummy region by providing them separately without overlapping.

1 silicon substrate, 2 buried oxide film, 3 SOI layer, 4 interlayer insulation film, 5 drain region, 6 source region, 7 channel formation region, 8 gate oxide film, 9 gate electrode, 9c gate contact region, 9e, 9f gate extension Region, 10 body region, 11 well region (P type), 12 well region (N type), 14 gate wiring portion, 15, 16 resist, 31 partial oxide film, 41-45 N ⁺ block region, 46-50 P ⁺ Implant region, 51, 52 N ⁺ block resist, 59 P ⁺ block resist, 61 P ⁺ implant resist, 62 N ⁺ implant resist, 71 dummy N ⁺ implant region, 72 dummy P ⁺ implant region.

Claims (4)

(a) An SOI substrate comprising a substrate, an insulating layer on the substrate, and a silicon layer on the insulating layer, the silicon layer having a first conductivity type in a transistor formation region , a partial isolation formation region , and a body region formation region The process of preparing
(b) forming a partial oxide film having a thickness that does not reach the insulating layer on the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region ;
The step (b)
(b-0) depositing an oxide film and a nitride film for forming a trench on an SOI substrate;
(b-1) forming a trench that does not reach the insulating layer on the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region ;
(b-2) filling the trench with an oxide film, and
(b-3) polishing the oxide film to form a partial oxide film,
(c) forming a gate electrode extending on the partial oxide film in the partial isolation formation region via a gate oxide film on the surface of the silicon layer in the transistor formation region ;
(d) covering said body region forming region, the transistor of the first mask layer used to expose the forming region, the gate electrode end portions the second conductivity type first impurity introducing the source and drain of the said transistor formation region Forming a region;
(e) the covering the transistor forming region, the body using a second mask layer to expose regions forming regions, further forming a introducing a second impurity of the first conductivity type in the body region forming region body region Prepared,
The first mask layer covers the body region formation region, the partial isolation formation region , and a part of the gate electrode in the partial isolation formation region ,
A method for manufacturing a semiconductor device. (a) An SOI substrate comprising a substrate, an insulating layer on the substrate, and a silicon layer on the insulating layer, the silicon layer having a first conductivity type in a transistor formation region , a partial isolation formation region , and a body region formation region The process of preparing
(b) forming a partial oxide film having a thickness that does not reach the insulating layer on the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region ;
The step (b)
(b-0) depositing an oxide film and a nitride film for forming a trench on an SOI substrate;
(b-1) forming a trench that does not reach the insulating layer on the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region ;
(b-2) filling the trench with an oxide film, and
(b-3) polishing the oxide film to form a partial oxide film,
(c) forming a gate electrode extending on the partial oxide film in the partial isolation formation region via a gate oxide film on the surface of the silicon layer in the transistor formation region ;
(d) covering said body region forming region, the transistor of the first mask layer used to expose the forming region, the gate electrode end portions the second conductivity type first impurity introducing the source and drain of the said transistor formation region Forming a region;
(e) the covering the transistor forming region, the body using a second mask layer to expose regions forming regions, further forming a introducing a second impurity of the first conductivity type in the body region forming region body region Prepared,
The first mask layer extends from the body region formation region to a partial isolation formation region , and covers a part of the gate electrode in the partial isolation formation region .
A method for manufacturing a semiconductor device. (a) An SOI substrate comprising a substrate, an insulating layer on the substrate, and a silicon layer on the insulating layer, the silicon layer having a first conductivity type in a transistor formation region , a partial isolation formation region , and a body region formation region The process of preparing
(b) forming a partial oxide film having a thickness that does not reach the insulating layer on the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region ;
The step (b)
(b-0) depositing an oxide film and a nitride film for forming a trench on an SOI substrate;
(b-1) forming a trench that does not reach the insulating layer on the surface of the silicon layer in the partial isolation formation region between the transistor formation region and the body region formation region ;
(b-2) filling the trench with an oxide film, and
(b-3) polishing the oxide film to form a partial oxide film,
(c) forming a gate electrode extending on the partial oxide film in the partial isolation formation region via a gate oxide film on the surface of the silicon layer in the transistor formation region ;
(d) covering said body region forming region, the transistor of the first mask layer used to expose the forming region, the gate electrode end portions the second conductivity type first impurity introducing the source and drain of the said transistor formation region Forming a region;
(e) the covering the transistor forming region, the body using a second mask layer to expose regions forming regions, further forming a introducing a second impurity of the first conductivity type in the body region forming region body region Prepared,
The first mask layer covers the partial oxide film and a part of the gate electrode in the partial isolation formation region .
A method for manufacturing a semiconductor device. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the silicon layer has a second conductivity different from the transistor formation region , the partial isolation formation region , and the body region formation region. A second body region forming region of the mold;
In the step (d), the first mask layer exposes the second body region forming region, and the first impurity is also introduced into the second body region forming region ,
In the step (e), the second mask layer covers the second body region forming region .
A method for manufacturing a semiconductor device.

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