JP2015188103A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device including a step for performing ion implantation from an oblique direction to a substrate, which satisfies both reduction in the gate electrode size and improvement of leak current characteristics.SOLUTION: A gate electrode 34n is formed on the surface of a semiconductor substrate, and a resist mask 71 is formed to cover both end faces of the gate electrode 34n in the gate width direction crossing the gate length direction. A low density impurity layer 42n overlapping the gate electrode 34n is formed on both sides of the gate electrode 34 on the surface of the semiconductor substrate, by injecting impurity ions into the semiconductor substrate, in an injecting direction having a gate length direction component and a gate width direction component. A sidewall covering the side face of the gate electrode 34n is formed, and a high concentration impurity layer, separated from the gate electrode 34n, is formed on the surface of the semiconductor substrate, on both sides of the gate electrode 34n, by injecting impurity ions, using the gate electrode 34 and sidewall as a mask.

Description

  The present invention relates to a method for manufacturing a semiconductor device.

  Reducing the size of the semiconductor element not only enables integration of more circuits per unit area, but also allows the semiconductor element to be driven at a lower voltage and current, thereby reducing power consumption. It becomes possible. However, as the size of the semiconductor element is reduced, the device characteristics deviate from the approximation in the long channel. Specific examples include a change in threshold voltage, a decrease in breakdown voltage of the source and drain, and an increase in leakage current between the source and drain in the weak inversion state. These phenomena are collectively referred to as the short channel effect. There is an LDD structure as a technique for preventing the short channel effect. The LDD structure is a structure in which a low impurity concentration region is inserted between a high impurity concentration drain region and a source region and a channel region. By adopting the LDD structure, the electric field in the vicinity of the drain and source ends is relaxed and the breakdown voltage is improved.

  Patent Document 1 discloses a semiconductor device having a low-concentration impurity layer and a high-concentration impurity layer provided so as to overlap with a gate electrode between a drain region and a source region and a channel region having a high impurity concentration, and a method for manufacturing the semiconductor device. Have been described.

Japanese Patent Laid-Open No. 10-12870

  In a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) having an LDD structure, when a low-concentration impurity layer is formed so as to overlap the gate electrode, ion implantation is performed at an inclination angle of, for example, 45 ° with respect to the substrate. Is called.

  FIG. 1A is a top view of a general MOSFET 100. MOSFET 100 includes an active region 40 including a high concentration impurity layer 44, a low concentration impurity layer 42 and a channel region 46, an element isolation film 20 extending around the active region 40, and a gate extending across the active region 40. Electrode 34. When the low-concentration impurity layer 42 is overlapped with the gate electrode 34, the ion implantation direction has an A-direction component and a B-direction component along the gate length direction (that is, the direction in which the drain, gate, and source are aligned) shown in FIG. Ion implantation is performed in such an implantation direction. Here, when another MOSFET having a gate length direction different from that of the MOSFET 100 is present in another region, further ion implantation is performed in an implantation direction having a C direction component and a D direction component. In this case, when the protrusion dimension L1 of the gate electrode 34 from the active region 40 in the direction orthogonal to the gate length direction is small, the implanted ions are gated as shown in FIGS. 1 (b) and 1 (c). A leak path may be formed by penetrating the electrode 34 and the element isolation film 20 and entering the channel region 46. In order to prevent this, it is necessary to increase the protruding dimension L1 of the gate electrode 34 to prevent ions from entering. However, when the protrusion dimension L1 of the gate electrode 34 is increased, the element size increases, and the demand for higher density and smaller size of the semiconductor device cannot be satisfied.

  FIG. 2 is a graph showing a result of comparison of leakage currents when the gate electrode protruding dimension L1 is 0.2 μm (broken line) and 0.4 μm (solid line). In FIG. 2, the horizontal axis indicates the gate voltage, and the vertical axis indicates the drain current. It can be understood that when the protruding dimension L1 of the gate electrode is 0.2 μm, the leakage current is greatly increased, and this can be avoided by increasing the protruding dimension L1 to 0.4 μm.

  The present invention has been made in view of the above points, and in a method for manufacturing a semiconductor device including a step of performing ion implantation from an oblique direction with respect to a substrate, both reduction in gate electrode size and improvement in leakage current characteristics are achieved. An object of the present invention is to provide a manufacturing method that can be used.

  The method of manufacturing a semiconductor device of the present invention includes a step of forming a gate electrode on a surface of a semiconductor substrate, a step of forming a resist mask that covers both end faces in the gate width direction intersecting the gate length direction of the gate electrode, Impurity ions are implanted into the semiconductor substrate in an implantation direction having the gate length direction component and the gate width direction component, and the low concentration impurity layer overlaps with the gate electrode on both sides of the gate electrode on the surface of the semiconductor substrate Forming a sidewall covering the side surface of the gate electrode, implanting impurity ions using the gate electrode and the sidewall as a mask, and sandwiching the gate electrode on both sides of the surface of the semiconductor substrate Forming a high-concentration impurity layer spaced from the gate electrode, and the resist mask Wherein among the formation area of the gate electrode is characterized by covering the area protruding from the active region including the low concentration impurity layer and the high concentration impurity layer.

  According to the method for manufacturing a semiconductor device of the present invention, even when ion implantation is performed at an inclination angle having a gate width direction component that intersects the gate length direction when forming a low-concentration impurity layer, the gate width direction of the gate electrode Since both end faces of are covered with a resist mask, ion implantation into the channel region directly under the gate electrode is inhibited, and formation of a leak path in the channel region can be prevented. As a result, it is possible to achieve both reduction of the gate electrode size and improvement of the leakage current characteristics.

1A and 1B are top views showing the structure of the MOSFET. FIG.1 (c) is sectional drawing along the 1c-1c line | wire of FIG.1 (b). It is a graph which shows the leakage current characteristic of MOSFET. It is sectional drawing which shows the manufacturing process of CMOS type IC which concerns on the Example of this invention. It is sectional drawing which shows the manufacturing process of CMOS type IC which concerns on the Example of this invention. FIG. 5A is a top view of the CMOS IC in the process of forming a low concentration impurity layer in the n-MOS formation region. FIGS. 5B and 5C are cross-sectional views taken along lines 5b-5b and 5c-5c in FIG. 5A, respectively. FIG. 6A is a top view of the CMOS IC in the process of forming the low concentration impurity layer in the n-MOS formation region. 6B and 6C are cross-sectional views taken along lines 5b-5b and 5c-5c in FIG. 6A, respectively. It is a graph which shows the leakage current characteristic of MOSFET.

  Embodiments of the present invention will be described below with reference to the drawings. In the drawings shown below, substantially the same or equivalent components and parts are denoted by the same reference numerals. In the following, an example in which an n-type MOSFET and a p-type MOSFET are formed in the n-MOS formation region 2 and the p-MOS formation region 3 adjacent to each other will be described. FIGS. 3A to 3E and FIGS. 4A to 4D are cross-sectional views for each process step in the CMOS type IC manufacturing method according to the embodiment of the present invention.

  A p-type silicon substrate 10 is prepared, washed with an acid solution, rinsed with ultrapure water, and then dried with a centrifugal dryer (FIG. 3A).

  Next, after forming a resist mask so as to cover the surface of the n-MOS formation region 2 of the silicon substrate 10, phosphorus ions are implanted into the exposed surface of the silicon substrate 10 that is not covered with the resist to form the p-MOS formation region 3. An n-well 12 is formed on the substrate (FIG. 3B).

Next, an element isolation film 20 for electrically isolating the n-MOS formation region 2 and the p-MOS formation region 3 is formed. The element isolation film 20 can be formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (local oxidation of silicon) method. In the case of the STI method, a groove is formed in the element isolation region of the silicon substrate 10 by reactive ion etching (RIE), and SiO ₂ is formed in this groove by a chemical vapor deposition (CVD) method or the like. Embed. Thereafter, SiO ₂ is planarized by chemical mechanical planarization (CMP) (FIG. 3C).

Next, a gate oxide film 32 made of SiO ₂ is formed on the surface of the silicon substrate 10 by thermal oxidation. Subsequently, a silane (SiH ₄ ) gas is thermally decomposed in a nitrogen (N ₂ ) gas atmosphere to form a polycrystalline silicon film 34 constituting the gate electrodes 34 n and 34 p on the gate oxide film 32. Note that an impurity such as phosphorus (P) may be added to lower the electrical resistance of the polycrystalline silicon film 34 (FIG. 3D).

  Next, the polycrystalline silicon film 34 is patterned to form gate electrodes 34n and 34p in the n-MOS formation region 2 and the p-MOS formation region 3, respectively. Subsequently, the gate oxide film 32 is partially removed using the gate electrodes 34n and 34p as a mask (FIG. 3E).

  Next, a low concentration impurity layer 42n is formed in the n-MOS formation region 2 (FIG. 4A). Here, FIG. 5A is a top view of the n-MOS formation region 2 and the p-MOS formation region 3 corresponding to FIG. 4A, and FIG. 5B and FIG. It is sectional drawing along the 5b-5b line | wire and 5c-5c line | wire in 5 (a). Resist masks 61 and 71 are formed before ion implantation for forming the low-concentration impurity layer 42n in the n-MOS formation region 2 is performed. The resist mask 61 is a mask for preventing ion implantation into the p-MOS formation region 3. The resist mask 61 covers the surface of the p-MOS formation region 3 of the silicon substrate 10 and has an opening 61 a in the n-MOS formation region 2. The resist mask 71 covers a part of the upper surface of the gate electrode 34n exposed in the opening 61a and end faces a and b in a direction perpendicular to the gate length direction of the gate electrode 34n (hereinafter referred to as the gate width direction). doing. The protruding dimension L1 of the gate electrode 34n from the active region 40n is, for example, 0.2 μm, and the coating thickness L2 of the resist mask 71 that covers the end faces a and b of the gate electrode 34n is, for example, 0.3 μm. The resist mask 61 and the resist mask 71 can be formed using the same material, and can be formed by batch processing through the same exposure / development processing. That is, it is not necessary to newly add a process for forming the resist 71 that covers the end face of the gate electrode 34n.

After the resist masks 61 and 71 are formed, phosphorus ions (31P +) are implanted into the surface of the silicon substrate 10 at a dose of 2.0 × 10 ¹³ atoms / cm ² and an implantation energy of 160 kev, and on both sides of the gate electrode 34n. An n-type low concentration impurity layer 42n is formed. The ion implantation is performed at an implantation angle of 45 ° so that the implantation direction has an A direction component and a B direction component along the gate length direction. The low-concentration impurity layer 42n is formed in the active region 40n so as to overlap with the gate electrode 34n in a self-aligned manner (so as to have a portion that enters the region directly under the gate electrode).

  Here, in the case where an n-type MOSFET having a different gate length direction is further formed in another n-MOS formation region (not shown), in this step, an implantation direction (with a C direction component and a D direction component along the gate width direction) Ion implantation is performed at an inclination angle. Since the end faces a and b of the gate electrode 34n are covered with the resist 71 having a predetermined coating thickness, even when ion implantation having a gate width direction component is performed, ions into the channel region immediately below the gate electrode 34n Injection is blocked. Therefore, no leak path is formed in the channel region. Thus, by covering the end faces a and b in the gate width direction of the gate electrode 34n with the resist 71, the same effect as that obtained when the protruding dimension L1 of the gate electrode is increased can be obtained. The coating thickness of the resist 71 that covers both end faces of the gate electrode 34n is set to a thickness that can prevent ion implantation directly under the gate electrode, and depends on the protrusion dimension L1 of the gate electrode 34n, ion implantation conditions, and the like. It can be changed as appropriate.

  Next, the low-concentration impurity layer 42p is formed in the p-MOS formation region 3 in the same procedure (FIG. 4B). 6A is a top view of the n-MOS formation region 2 and the p-MOS formation region 3 corresponding to FIG. 4B, and FIGS. 6B and 6C are diagrams respectively. It is sectional drawing along the 5b-5b line and 5c-5c line in 6 (a). Resist masks 62 and 72 are formed before ion implantation for forming the low-concentration impurity layer 42p in the p-MOS formation region 3 is performed. The resist mask 62 is a mask for preventing ion implantation into the n-MOS formation region 2. The resist mask 62 covers the surface of the n-MOS formation region 2 of the silicon substrate 10 and has an opening 62 a in the p-MOS formation region 3. The resist mask 72 covers a part of the upper surface of the gate electrode 34p exposed in the opening 62a and the end surfaces a and b of the gate electrode 34p in the gate width direction. The protruding dimension L1 of the gate electrode 34p from the active region 40p is, for example, 0.2 μm, and the coating thickness L2 of the resist mask 72 in the gate width direction that covers the end faces a and b of the gate electrode 34n is, for example, 0.3 μm. . The resist mask 62 and the resist mask 72 can be formed using the same material, and are formed by batch processing through the same exposure / development processing. That is, it is not necessary to add a process to form the resist 72 that covers the end face of the gate electrode 34p.

  After the resist masks 62 and 72 are formed, boron ions (11B +) are implanted into the p surface of the silicon substrate 10 to form n-type low-concentration impurity layers 42p on both sides of the gate electrode 34n. The ion implantation is performed at an implantation angle of 45 ° so as to have an A direction component and a B direction component along the gate length direction. The low-concentration impurity layer 42n is formed in the active region 40p so as to overlap with the gate electrode 34p in a self-aligned manner (so as to have a portion that enters the region directly under the gate electrode).

  Here, in the case where a p-type MOSFET having a different gate length direction is further formed in another p-MOS formation region (not shown), in this step, an implantation direction having a C direction component and a D direction component along the gate width direction ( Ion implantation is performed at an inclination angle. Since the end faces a and b of the gate electrode 34p are covered with a resist 72 having a predetermined thickness, even when ion implantation having a C-direction component and a D-direction component is performed, ion implantation into the channel region is performed. It is inhibited and a leak path is not formed in the channel region. Thus, by covering the end faces a and b of the gate electrode 34p with the resist 72, the same effect as that obtained when the protruding dimension L1 of the gate electrode is increased can be obtained.

Next, after removing the resists 62 and 72, an insulating film made of SiO ₂ or the like is formed on the surface of the silicon substrate 10 so as to embed the gate electrodes 34n and 34p using a CVD method or the like. Subsequently, the insulating film is etched back by reactive ion etching to form side walls 36n and 36p on the side surfaces of the gate electrodes 34n and 34p, respectively.

Next, a resist 63 is formed on the surface of the silicon substrate 10 so as to cover the p-MOS formation region 3. Next, arsenic ions (75As +) are implanted into the surface of the silicon substrate 10 at a dose of 5.0 × 10 ¹⁵ atom / cm ² and an implantation energy of 50 kev, and correspond to the drain and source on both sides of the gate electrode 34n. An n-type high concentration impurity layer 44n is formed. Ion implantation is performed at an implantation angle of 0 °. The gate electrode 34n and the sidewall 36n function as a mask, and the high-concentration impurity layer 44n is formed at a position separated from the gate electrode 34n and the channel region in the low-concentration impurity layer 42n. That is, an LDD structure in which the low concentration impurity layer 42n is interposed between the high concentration impurity layer 44n and the channel region 46n is formed (FIG. 4C).

  Next, a resist 64 is formed on the surface of the silicon substrate 10 so as to cover the n-MOS formation region 2. Next, boron ions (11B +) are implanted into the surface of the silicon substrate 10 to form p-type high-concentration impurity layers 44p corresponding to the drain and source on both sides of the gate electrode 34p. Ion implantation is performed at an implantation angle of 0 °. The gate electrode 34p and the sidewall 36p function as a mask, and the high concentration impurity layer 44p is formed in a position separated from the gate electrode 34p and the channel region 46p in the low concentration impurity layer 42p. That is, an LDD structure in which the low concentration impurity layer 42p is interposed between the high concentration impurity layer 44p and the channel region 46p is formed (FIG. 4D). Thereafter, a CMOS IC is completed through a known wiring process.

  As is clear from the above description, according to the manufacturing method according to the present embodiment, when the low concentration impurity layer is formed, ion implantation is performed at an inclination angle having a gate width direction component orthogonal to the gate length direction. However, since both end faces in the gate width direction of the gate electrode are covered with a resist mask before the ion implantation, ion implantation into the channel region immediately below the gate electrode is inhibited, and the formation of a leak path in the channel region is prevented. can do. Therefore, the dimension of the gate electrode in the gate width direction can be made smaller than before, which can contribute to the reduction in the size and density of the semiconductor element. The resist mask that covers both end faces of the gate electrode can be formed in the same process as the existing resist mask for preventing ion implantation into other regions, so that it is not necessary to add a new process. .

  FIG. 7 shows a case where both end surfaces of the gate electrode in the gate width direction are covered with a resist mask (solid line) and a case where the gate electrode is not covered when the protruding dimension L1 from the active region of the gate electrode is 0.2 μm which is shorter than the conventional one. It is a graph which shows the result of having compared the leak current of (broken line). It can be understood that leakage current is greatly reduced by covering both end faces of the gate electrode with a resist as in this embodiment to prevent ion implantation into the channel region.

2 n-MOS formation region 3 p-MOS formation region 10 Semiconductor substrate 34n, 34p Gate electrode 36n, 36p Side wall 42n, 42p Low concentration impurity layer 44n, 44p High concentration impurity layer 61-64 Resist mask 71, 72 Resist mask

Claims (2)

Forming a gate electrode on the surface of the semiconductor substrate;
Forming a resist mask covering both end faces in the gate width direction intersecting the gate length direction of the gate electrode;
Impurity ions are implanted into the semiconductor substrate in an implantation direction having the gate length direction component and the gate width direction component, and the low concentration impurity layer overlaps with the gate electrode on both sides of the gate electrode on the surface of the semiconductor substrate Forming a step;
Forming a sidewall covering a side surface of the gate electrode;
Implanting impurity ions using the gate electrode and the sidewall as a mask to form a high concentration impurity layer spaced from the gate electrode on both sides of the gate electrode on the surface of the semiconductor substrate,
The method of manufacturing a semiconductor device, wherein the resist mask covers a region protruding from an active region including the low-concentration impurity layer and the high-concentration impurity layer in the formation region of the gate electrode.   The resist mask has a coating thickness capable of preventing entry of impurity ions implanted in the implantation direction having the gate width direction component into the region immediately below the gate electrode in the step of forming the low-concentration impurity layer. The manufacturing method according to claim 1.

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