JP4911918B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for preventing deformation and breakage in a manufacturing process.

  2. Description of the Related Art Conventionally, in power semiconductor devices and the like, vertical semiconductor devices in which electrodes are provided on both main surfaces of a semiconductor substrate and current flows in the thickness direction of the substrate have been used. In a vertical semiconductor device, the loss is reduced and the characteristics are improved by forming a thin substrate. The substrate is thinly formed from about 600 μm to about 150 μm or less. If the substrate is thinly formed from the beginning of the manufacturing process, the substrate is likely to be deformed or damaged during transportation due to the influence of a thermal process or the like. Such a problem is particularly noticeable when the back surface is ground in order to obtain a desired thickness for the substrate. In order to prevent such deformation and breakage, a protective film is formed on the gate structure or electrode formed on the surface using a wafer that is somewhat thick, and then the back surface is ground with a grindstone.

  For example, Patent Document 1 discloses a method for manufacturing a semiconductor device in which backside grinding is performed after a groove portion is filled with a filler in a semiconductor substrate to make the surface flat. Patent Document 2 discloses a method for manufacturing a semiconductor device in which a film sheet for back grinding protection is formed on the surface of a semiconductor substrate.

JP 2004-140101 A (pages 14-15, FIG. 11) JP-A-5-109679

  In conventional semiconductor device manufacturing methods, when the back surface of a substrate is ground to a thickness of 150 μm or less, the boundary between a region where a protective film made of silicon nitride, polyimide, or the like is formed and a region where no protective film is formed In the vicinity of (that is, the end of the protective film), there is a problem that unevenness or cracking occurs on the back side due to the drag from the front side.

  In addition, if a protective film is formed thin in order to prevent such deformation and breakage of the substrate, it will be contaminated by external impurities and device characteristics will be deteriorated, and the effect of reducing wiring distortion will be reduced. There's a problem.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of preventing deformation and breakage in a manufacturing process.

A method of manufacturing a semiconductor device according to the present invention includes a cell region including a region to which a wire is bonded, a gate line region for applying a gate voltage to the cell region, and an outer periphery to maintain a withstand voltage. A method of manufacturing a semiconductor device having a guard ring region on a surface side of a substrate, wherein a protective film is formed entirely in the gate line region and the guard ring region, and a wire is not bonded in the cell region. A protective film forming step for partially forming a protective film, and a step of attaching a protective tape to the front surface side of the substrate and grinding the back surface side of the substrate , along the boundary line between the cell region and the guard ring region direction is consistent with the crystal cleavage direction of the substrate, the protective layer of the cell region, a polygonal shape is not a rectangle extending along the boundary line in the top view or Plurality As is well as reduce the portion matching with the crystal cleavage direction of the end portion of the protective film by taking a shape composed of curved, along the guard ring region only in the vicinity of the boundary between the cell region and a guard ring region These regions are formed side by side .

A method of manufacturing a semiconductor device according to the present invention includes a cell region including a region to which a wire is bonded, a gate line region for applying a gate voltage to the cell region, and an outer periphery to maintain a withstand voltage. A method of manufacturing a semiconductor device having a guard ring region on a surface side of a substrate, wherein a protective film is formed entirely in the gate line region and the guard ring region, and a wire is not bonded in the cell region. A protective film forming step of partially forming a protective film; and a step of attaching a protective tape to the front surface side of the substrate and grinding the back surface side of the substrate. Therefore, by reducing the stress per unit area in the back surface grinding, the deformation and breakage of the semiconductor device in the manufacturing process can be reduced.
The direction along the boundary line between the cell region and the guard ring region coincides with the crystal cleavage direction of the substrate, and the protective film of the cell region is a non-rectangular polygonal shape extending along the boundary line when viewed from above. Or since it is a shape which consists of a curve, the part which corresponds to the cleavage direction of the crystal | crystallization which comprises a board | substrate among the edge parts of a protective film can be decreased, and the failure | damage of a semiconductor device can be reduced further. Further, since the protective film of the cell region is formed by arranging a plurality of regions along the guard ring region only in the vicinity of the boundary between the cell region and the guard ring region, the semiconductor film while reducing the amount of warping of the substrate as much as possible. The deformation and breakage of the device can be reduced.

  A chip as a semiconductor device according to the present invention is characterized in that the stress per unit area applied to the protective film is reduced by forming a passivation film as a protective film even in a region where protection is not required. . Hereinafter, each embodiment of the present invention will be described.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing a configuration of a chip 100 according to the first embodiment. The chip 100 is composed of a vertical semiconductor device having a thickness of 150 μm or less, and is used as a power semiconductor device, for example.

  As shown in FIG. 1, the chip 100 includes a cell region 150, a gate line region 160, and a guard ring region 170. The cell region 150 is a region for supplying a rated current to a wire in which, for example, a switching cell is arranged and bonded to the cell. The gate line region 160 is a region where wiring for transmitting a gate voltage for turning on / off the switching cell to the cell region 150 is formed. The guard ring region 170 is a region formed along the outer periphery of the chip 100 in order to insulate the back side and the front side of the chip 100 and maintain a withstand voltage. Hereinafter, the manufacturing process of the chip 100 will be described with reference to FIG.

  First, a base region 102 is formed on the surface of a substrate 101 made of a semiconductor such as silicon by ion implantation and diffusion (annealing). Two emitter regions 103 are formed in one base region 102 apart from each other.

  Next, an oxide film 104 and an oxide film 105 as a gate insulating film are formed over the substrate 101.

  Next, a gate electrode 106 is formed on the oxide film 105.

  Next, after an interlayer insulating film 107 is formed on the gate electrode 106 and the oxide film 104, a contact hole is opened in the interlayer insulating film 107.

  Next, an electrode pattern 108 made of titanium or the like and an electrode pattern 109 made of aluminum or the like are formed in this order on the interlayer insulating film 107.

  Next, a protective film 110 made of silicon nitride or the like is formed on the electrode pattern 109. The protective film 110 is formed on the gate line region 160 and the guard ring region 170. The protective film 110 is for protecting the device from external contamination, and prevents the device characteristics from being deteriorated or short-circuited and damaged due to ionization of moisture on the device surface.

  Next, a protective film 111 made of polyimide or the like is formed on the protective film 110. When the device is packaged with a mold resin, the protective film 111 causes the electrode pattern 108 to be distorted and damaged in a heat cycle (repeated thermal action) due to a difference in thermal expansion coefficient between aluminum constituting the electrode pattern 108 and the mold resin. Is preventing. As a result, a protective film 112 (passivation film) having a two-layer structure including the protective film 110 and the protective film 111 is formed on the gate line region 160 and the guard ring region 170. The protective film 112 has a thickness of about 10 μm or more.

  In the conventional chip, the gate line region 160 and the guard ring region 170 need to be protected, so the protective film 112 is formed. However, since the cell region 150 does not need protection, no protective film is formed. It was. Therefore, as described above, there is a problem that unevenness or cracking occurs on the back side near the boundary between the gate line region 160 where the protective film is formed and the cell region 150 where the protective film is not formed. . In the chip 100 according to the present embodiment, in the cell region 150, a protective film is not formed on a region to which a wire is bonded (generally an elliptical shape), but a polyimide is not formed on a region to which a wire is not bonded. A dummy protective film 113 (passivation film) made of or the like is partially formed. In FIG. 1, a region 151 is a region where the protective film 113 is not formed, and a region 152 is a region where the protective film 113 is formed. The end portion (end surface) of the protective film 113 is formed perpendicular to the surface of the electrode pattern 109. Hereinafter, the protective film 112 and the protective film 113 are collectively referred to as a protective film 114.

  FIG. 2 is a top view showing the configuration of the chip 100. The chip 100 shown in FIG. 2 has a size of about 15 mm (horizontal direction) × 15 mm (vertical direction), for example. As shown in FIG. 2, in the chip 100, a dummy protective film is formed so that the boundary between the region 152 (second region) and the region 151 (first region) surrounded by the region 152 is a vertically long rectangle. 113 (not shown in FIG. 2) is formed. This region 151 is determined so as to include an elliptical region (region surrounded by a dotted line) to which the wire as described above is bonded. Also, as shown in FIG. 2, the region 151 is formed by 3 rows × 7 columns. A gate line region 160 extending in the vertical direction (first direction) is interposed between the columns of the region 151. A guard ring region 170 is formed along the first direction of the chip 100 and the second direction (that is, the lateral direction) perpendicular to the first direction. Further, as described above, although not shown in FIG. 2, the protective film 112 is entirely formed in the gate line region 160 and the guard ring region 170.

  Next, the substrate 101 is turned over, and a protective tape for preventing foreign matter adhesion is attached to the front surface side of the substrate 101, and then the back surface side of the substrate 101 is ground to a desired thickness. At this time, the back surface of the substrate 101 is ground while adsorbing the surface on which the protective tape is attached (the surface side of the substrate 101) with a vacuum chuck. In this grinding, a cup-shaped grindstone having a width of 2 to 4 mm is disposed so as to pass near the center of the back surface of the substrate 101, and the grindstone is lowered toward the substrate 101 while rotating the grindstone and the substrate 101, respectively. It is done by going.

  Since the region of the substrate 101 where the protective film 114 is formed is thicker than the other regions, the resistance received from the front surface side in the back surface grinding is increased. In the conventional chip, the protective film 114 is formed only in the gate line region 160 and the guard ring region 170, and the surface area of the protective film 114 is relatively small, so that the drag per unit area is relatively large. Therefore, in the region where the protective film 114 is formed, unevenness is formed by partially thinning the substrate 101, or the substrate is subjected to shear force generated when the drag received from the surface side and the pressing force by the grindstone face each other. 101 may be broken.

  In the chip 100 according to the present embodiment, by forming the dummy protective film 113 and increasing the surface area of the protective film 114, the drag per unit area received from the front surface side in the back surface grinding is reduced. Therefore, deformation and breakage can be reduced as compared with the conventional chip.

Next, the protective tape for preventing foreign matter adhesion is peeled off from the surface of the substrate 101 . Then, as shown in FIG. 1, an n + buffer layer 115 and a p + collector layer 116 are formed in this order on the back surface of the substrate 101 by ion implantation and diffusion (annealing).

  Next, a collector electrode 117 is formed on the back surface of the p + collector layer 116 by evaporating a plurality of metals such as aluminum, titanium, nickel, and gold. Thereby, the manufacturing process of the chip 100 is completed.

  As described above, in the chip 100 according to the present embodiment, in addition to the protective film 112 formed in the gate line region 160 and the guard ring region 170, dummy protection is partially applied to a region where no wire is bonded in the cell region 150. The region 152 is provided by forming the film 113. Therefore, by reducing the stress per unit area in back surface grinding, it is possible to reduce chip deformation and breakage in the manufacturing process.

  Further, since the protective film 114 is formed only on a portion that does not affect the electrical characteristics, it is not necessary to remove the protective film 114. Therefore, the number of steps can be reduced and the yield can be prevented from being reduced due to damage to the substrate 101 as compared with Patent Document 1 that requires a step of removing the filler.

  In the above description, the case where the chip 100 is a vertical semiconductor device has been described. However, the semiconductor device is not limited to the vertical semiconductor device, and may be a semiconductor device in which a protective film is partially formed. In the above description, the method of performing ion implantation and diffusion after grinding the back surface and peeling off the protective tape has been described. However, the present invention is not limited to this, and for example, metal deposition is performed after grinding the back surface and peeling off the protective tape. It may be a method.

<Embodiment 2>
In the first embodiment, as illustrated in FIG. 2, the case has been described in which the region 151 is formed in a vertically long rectangular shape (in other words, the boundary between the region 152 and the region 151 surrounded by the region 152). However, as described above, generally, a region where a wire is bonded in the cell region 150 is elliptical. Therefore, the region 151 may be formed in a vertically long elliptical shape instead of a vertically long rectangular shape.

  FIG. 3 is a top view showing the configuration of the chip 100a according to the present embodiment.

  FIG. 3 shows that the region 151 in FIG. 2 is formed to have a vertically long elliptical shape instead of a vertically long rectangular shape. Although not shown in FIG. 3, a wire is bonded to the entire area 151 over the entire surface. 3, elements similar to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted here.

  A crystalline substrate made of silicon or the like has anisotropy in the cleavage of crystals, and therefore has a direction that is easy to break and a direction that is difficult to break even when a load of the same magnitude is applied. When tensile stress acts in a direction that is easy to break, there is a high possibility of wafer cracking. On the other hand, the tensile stress acting on the wafer during back grinding is generated in the vertical direction in the surface of the substrate 101 at the end of the protective film. When the region 151 is formed in a rectangular shape, the shape of the end portion of the protective film 113 in a top view is a linear shape. However, since the crystal generally has a linear cleavage direction, Of these, the number of portions that coincide with the crystal cleavage direction increases, and the possibility of wafer cracking increases. On the other hand, in the chip 100a according to the present embodiment, since the region 151 is formed in an elliptical shape, the portion of the end portion of the protective film that matches the crystal cleavage direction can be reduced. Therefore, it is possible to reduce the possibility of wafer cracking.

  Thus, in the chip 100a according to the present embodiment, since the region 151 has an elliptical shape, there are few portions that coincide with the crystal cleavage direction in the end portion of the protective film. Therefore, in addition to the effect of the first embodiment, there is an effect that the breakage of the chip can be further reduced.

  In the above description, the region 151 has a vertically long elliptical shape. However, the region 151 is not limited to an elliptical shape, and may have a shape including a curved line (including a perfect circular shape) or a shape including only a straight line. However, if the polygonal shape has a large number of straight lines, the portion of the end portion of the protective film that coincides with the crystal cleavage direction can be reduced.

<Embodiment 3>
In the first and second embodiments, as shown in FIGS. 2 and 3, the entire area 152 except for the area 151 defined including the area where the wire is bonded is entirely included in the cell area 150. A dummy protective film 113 is formed. However, in the case where the thickness is as thin as 150 μm or less like the substrate 101, when the dummy protective film 113 is entirely formed in the region 152, the polyimide used for the protective film 113 and the protective film 111 contracts. The substrate 101 may warp due to the stress (residual stress) to be obtained.

  FIG. 4 is a top view showing the configuration of the chip 100b according to the present embodiment.

  In FIG. 4, the region 152 in FIG. 2 is composed of a region 152a where the dummy protective film 113 is formed and a region 152b where the dummy protective film 113 is not formed. In FIG. 4, the region 152b is formed in the vertical direction and the horizontal direction, respectively. 4, elements similar to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted here.

  FIG. 5 is a graph showing experimental results for determining the relationship between the area ratio of polyimide occupying the surface area of the substrate 101 and the amount of wafer warpage after back grinding in the chip 100b. In FIG. 5, the wafer warpage increases as the polyimide area ratio increases in any of the thicknesses of 80 μm, 120 μm, and 150 μm.

  On the other hand, in the chip 100b, for example, when the chip size is 15 mm × 15 mm and the width of the region 152b is 0.5 mm, the area ratio of polyimide is 10 to 15 compared to the chip 100 of FIG. 2 according to the first embodiment. % Reduced. Thereby, in the case where the thickness is 80 μm in FIG. 5, the wafer warpage amount of 0.4 mm to 0.6 mm can be reduced.

  In the above description, the case where the linear regions 152b are formed in the vertical direction and the horizontal direction has been described. However, the present invention is not limited to this, and the linear region 152b may be formed in any direction. The region 152b is not limited to a linear shape, and may be provided in a curved shape. Further, the width of the region 152b and the interval between the regions 152b are arbitrary, but need to be set smaller than a predetermined threshold value so that wafer cracking does not occur when the back surface grinding is performed. Below, this threshold value is demonstrated using FIG.

  FIG. 6 is a graph showing experimental results obtained by finite element analysis of the relationship between the width (slit width) of the region 152b and the tensile stress applied to the substrate 101 in the chip 100b. In this experiment, the maximum value of the tensile stress generated in the substrate 101 when the back surface grinding is performed in a state where the protective tape attached to the surface side of the substrate 101 is vacuum-sucked, and this maximum value accompanying the change in the slit width is obtained. Made by seeking change. In this experiment, a protective film 114 having a thickness of 10 μm was used.

  In FIG. 6, when the slit width is lowered from 7 mm, the tensile stress starts to decrease when the slit width becomes 3 mm or less. When the slit width is 1.9 mm or less, the tensile stress is less than 100 Mpa, which is a fracture tensile stress value of silicon on a general ground surface. Furthermore, when the slit width is 0.5 mm or less, the tensile stress is reduced to the same extent as when the region 152b is not formed (that is, when the slit width is 0 mm). Therefore, the slit width is preferably 3 mm or less, and in particular, by setting the slit width to about 0.5 mm, it becomes possible to reduce the amount of wafer warp while preventing wafer cracking.

  As described above, in the chip 100b according to the present embodiment, in the chip 100 according to the first embodiment, the region 152 is divided into the region 152a where the dummy protective film 113 is formed and the region 152b where the dummy protective film 113 is not formed. And the region 152b where the dummy protective film 113 is not formed, the interval between the protective films 113 is determined to be 3 mm or less. Therefore, in addition to the effect of the first embodiment, the amount of wafer warp can be reduced. Therefore, it is possible to prevent the wafer from being warped, making it difficult to carry in each step, and preventing the bubbles from entering the solder and reducing the yield when packaged. In the above description, the case has been described in which the maximum distance between the opposing sides of the protective film 114 is 3 mm or less in the chip 100 according to the first embodiment. In the chip 100a, the maximum width of the region where the protective film 114 does not exist may be determined to be 3 mm or less.

<Embodiment 4>
In the first to third embodiments, as shown in FIGS. 2 to 4, region 151 is formed to be surrounded by region 152 (that is, region 151 is formed in gate line region 160 and guard ring region 170. The case where it is formed relatively small so as not to be adjacent to each other) has been described. However, the region 151 may be formed relatively large so as to be adjacent to the gate line region 160 and the guard ring region 170.

  FIG. 7 is a top view showing the configuration of the chip 100c according to the present embodiment.

  FIG. 7 shows that the region 151 in FIG. 2 is formed relatively large so as to be adjacent to the gate line region 160 or the guard ring region 170, and the region 151 is formed in 4 rows instead of 3 rows. 7, elements similar to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted here. As shown in FIG. 7, by forming the region 151 in four rows, the area ratio of polyimide contained in the protective film can be reduced, and the amount of wafer warp as described in the third embodiment can be reduced. .

  FIG. 8 is a graph showing experimental results obtained by finite element analysis on the relationship between the width of the protective film 114 (protective film width) and the tensile stress applied to the substrate 101 in the chip 100c. In this experiment, the maximum value of the tensile stress generated in the substrate 101 is obtained when the back surface grinding is performed in a state where the protective tape attached to the front surface side of the substrate 101 is vacuum-sucked, and the change in the width of the protective film 114 is accompanied. This was done by determining the change in maximum value. In this experiment, a protective film 114 having a thickness of 10 μm was used.

  In FIG. 8, when the protective film width is lowered from 7 mm, the tensile stress starts to increase when the protective film width becomes 4.0 mm or less. When the protective film width is about 2.0 mm, the tensile stress becomes maximum and the tensile stress begins to decrease. Furthermore, when the protective film width is 0.5 mm or less, the tensile stress is reduced to the same extent as when the protective film width is 0 mm (that is, when the protective film is not formed). Therefore, the tensile stress can be reduced by setting the protective film width to 0.5 mm or less or 4.0 mm or more. Hereinafter, this phenomenon will be described.

  When the back surface is ground, a large tensile stress is generated in the substrate 101 near the end of the protective film 114. When the protective film width is 4.0 mm or more, each tensile stress generated near both ends of the protective film 114 is Independent of each other. When the protective film width is 4.0 mm or less, the tensile stresses start to overlap each other. When the protective film width is about 2.0 mm, the peak positions of the tensile stresses coincide with each other, and the tensile stress acting on the substrate 101 is maximized. When the protective film width is 2.0 mm or less, the peak positions of the tensile stresses are separated and the tensile stress acting on the substrate 101 is lowered.

  Therefore, in order to reduce the tensile stress, the protective film width is preferably set to 0.5 mm or less or 4.0 mm or more. Hereinafter, the widths of the gate line region 160 and the guard ring region 170 for satisfying this condition will be described.

  The gate line region 160 is generally formed to have a width of 0.5 mm or less. Therefore, as shown in FIG. 7, by forming the region 151 so as to be adjacent to the gate line region 160, the width of the protective film 114 around the gate line region 160 can be reduced to 0.5 mm or less.

  As for the guard ring region 170, since a plurality of chips 100c are generally formed adjacent to each other, the guard ring regions 170 are adjacent to each other in the adjacent chips 100c. Therefore, the width of the protective film 114 formed in the guard ring region 170 is considered to be doubled. At this time, a dicing line having a width of about 0.1 mm is interposed between adjacent chips 100, but as described in the third embodiment, depending on the slit having a width of 0.5 mm or less, a tensile force is applied. Since the stress does not change, the influence of this dicing line can be ignored. Therefore, in order to satisfy the above conditions, the width of the protective film 114 formed in the guard ring region 170 in one chip 100c is preferably set to 0.25 mm or less or 2.0 mm or more. In general, it is difficult to form the guard ring region 170 with a width of 0.25 mm or less from the viewpoint of protecting the wiring. Therefore, the width is preferably set to 2.0 mm or more. In addition, since the region 151 has a vertically long rectangular shape and is formed to have a relatively narrow width, if the protective film 114 is formed so as to have a width of 2.0 mm or more over the entire guard ring region 170, the guard 151 in the vertical direction is formed. The protective film 114 along the ring region 170 may make the width of the region 151 too small. Therefore, as shown in FIG. 7, the region 152 is defined by forming the protective film 113 only along the guard ring region 170 extending in the lateral direction. As a result, the width of the protective film 114 becomes 2.0 mm or more only in the vicinity of the guard ring region 170 extending in the lateral direction.

  Further, as described with reference to FIG. 6 in Embodiment 3, in order to reduce the tensile stress, the interval between the protective films 114 is preferably 3 mm or less. Therefore, a plurality of regions 152 are formed in the lateral direction so that the distance between them is 3 mm or less.

  FIG. 9 is a graph showing the results of an experiment for determining the relationship between the thickness after back grinding and the rate of occurrence of wafer cracking when the chip size is 15 mm × 15 mm in the chip 100c. As shown in FIG. 9, in the conventional chip that does not have the dummy protective film 113, a wafer crack occurs when the thickness is 150 μm or less. However, in the chip 100c, the thickness must be 70 μm or less. Wafer cracking does not occur.

  Thus, in the chip 100c according to the present embodiment, in the region 152, the width of the protective film 114 around the gate line region 160 is 0.5 mm or less, and the protective film 114 around the guard ring region 170 extending in the lateral direction. The width is determined only in the lateral direction so that the width is 2.0 mm or more. Therefore, in addition to the effect of the first embodiment, there is an effect that the deformation and breakage of the chip can be further reduced.

  Further, in the chip 100c, the region 151 is formed to be relatively large, and is formed in four rows instead of three rows. Therefore, as in the third embodiment, the area ratio of polyimide contained in the protective film can be reduced and the amount of wafer warpage can be reduced. For example, when the thickness after back grinding in FIG. 5 is 80 μm, the wafer warpage amount is reduced by about 0.8 mm in the structure of FIG. 7 compared to the structure of FIG. 2 according to the first embodiment. Is done.

<Embodiment 5>
In the first to fourth embodiments, as shown in FIGS. 2 to 4 and 7, the region 151 is formed in a plurality of rows. However, the region 151 may be formed in one row longer in the vertical direction.

  FIG. 10 is a top view showing the configuration of the chip 100d according to the present embodiment.

  FIG. 10 is a diagram in which the region 151 in FIG. 2 is formed in one row by extending in the vertical direction instead of three rows, and adjacent to the guard ring region 170 extending in the lateral direction at the upper and lower ends thereof. . In FIG. 10, similarly to the region 151, the region 152 is formed in a rectangular shape that is long in the vertical direction and is adjacent to the guard ring region 170 that extends in the horizontal direction at the upper and lower ends thereof. The region 152 is formed adjacent to the gate line region 160 and the guard ring region 170 extending in the vertical direction. 10, elements similar to those in FIG. 2 are denoted by the same reference numerals, and detailed description thereof is omitted here. As shown in FIG. 10, the area ratio of polyimide contained in the protective film is reduced by forming the region 151 in the vertical direction, and the amount of warpage of the wafer as described in the third embodiment can be reduced. it can.

  FIG. 11 is a graph showing the experimental results of determining the relationship between the thickness after back grinding and the rate of occurrence of wafer cracking when the chip size is 15 mm × 15 mm in the chip 100d. As shown in FIG. 11, in the conventional chip that does not have the dummy protective film 113, a wafer crack occurs when the thickness is 150 μm or less. However, in the chip 100d, the thickness must be 70 μm or less. Wafer cracking does not occur.

  Thus, in the chip 100d according to the present embodiment, the region 152 is defined to extend along the vertical direction and to be adjacent to the guard ring region 170. Therefore, in addition to the effect of the first embodiment, there is an effect that the area ratio of polyimide contained in the protective film can be reduced and the amount of warpage of the wafer can be reduced.

<Embodiment 6>
As described with reference to FIG. 5 in the third embodiment, when the area ratio of polyimide contained in the protective film increases, the amount of warpage of the wafer increases. Therefore, in the sixth embodiment, a structure that can reduce the deformation and breakage of the chip while reducing the amount of wafer warpage as much as possible will be described.

  For example, in the fifth embodiment, as shown in FIG. 10, the region 152 is formed in a rectangular shape that is long in the vertical direction, and is adjacent to the gate line region 160 and the guard ring region 170 extending in the vertical direction. Is formed. However, as described above in Embodiment 4, it is preferable that the lateral width of the protective film 114 around the gate line region 160 is 0.5 mm or less, so that the region 152 is formed around the gate line region 160. There is no need to Further, the width of the guard ring region 170 is generally 1.0 mm or more, but as described above, in FIG. 8, the width of the protective film is 2.0 mm (that is, the width of the guard ring region 170 is 1.0 mm). ) Is the maximum tensile stress. Therefore, in order to reduce the tensile stress, it is preferable to provide the region 152 around the guard ring region 170 and increase the width of the protective film 114 around the guard ring region 170.

  FIG. 12 is a top view showing the configuration of the chip 100e according to the present embodiment.

  FIG. 12 shows that the region 152 in FIG. 10 is not a single row of rectangles that are long in the vertical direction, but a shape in which a plurality of relatively small triangular regions are connected, and the gate line region 160 and the vertical direction. It is formed not adjacent to the extending guard ring region 170 but adjacent to the entire guard ring region 170 along the outer periphery of the chip. 12, elements similar to those in FIG. 10 are denoted by the same reference numerals, and detailed description thereof is omitted here.

  In the chip 100e, the region 151 is formed so as to be adjacent to the gate line region 160 (the region 152 is not formed around the gate line region 160), thereby protecting the periphery of the gate line region 160 as in the fourth embodiment. The width | variety of the film | membrane 114 can be 0.5 mm or less, and a tensile stress can be made small.

  Further, by forming the triangular region 152 only around the guard ring region 170, the width of the protective film 114 around the guard ring region 170 is increased while reducing the area ratio of polyimide contained in the protective film as much as possible. The tensile stress is reduced.

  In addition, since the region 152 where the dummy protective film 113 is formed is formed far away from the region where the wire is bonded (the region surrounded by the dotted line), the accuracy when bonding the wire in a later process is improved. It is possible to have a margin.

  Further, by forming the region 152 in a triangular shape instead of a rectangular shape, the chip breakage can be reduced by reducing the portion of the end portion of the protective film that coincides with the crystal cleavage direction, as in the second embodiment. Further reduction can be achieved.

  In FIG. 12, a plurality of triangular regions 152 are formed in a connected manner. By being formed in a connected manner, it is possible to reduce the tensile stress as compared with the case where a plurality are formed at intervals. Hereinafter, this phenomenon will be described with reference to FIG.

  FIG. 13 is a graph showing experimental results obtained by finite element analysis on the relationship between the spacing between the triangular regions 152 (dummy protective film spacing) and the tensile stress applied to the substrate 101 in the chip 100e.

  In FIG. 13, the tensile stress decreases monotonously as the dummy protective film interval is lowered from 7 mm, and when the dummy protective film interval is 4.0 mm or less, the tensile stress is less than that of silicon on a general grinding surface. The fracture tensile stress value is below 100 Mpa. When the dummy protective film interval is 0 mm (that is, when a plurality of triangular regions 152 are connected), the tensile stress is minimized. Therefore, a plurality of the triangular regions 152 are formed to be connected to each other, so that the tensile stress can be reduced as compared with a case where the plurality of triangular regions 152 are formed at intervals.

  FIG. 14 is a graph showing the experimental results of determining the relationship between the thickness after back grinding and the rate of occurrence of wafer cracking when the chip size is 15 mm × 15 mm in the chip 100e. As shown in FIG. 14, in the conventional chip that does not have the dummy protective film 113, a wafer crack occurs when the thickness is 150 μm or less. However, in the chip 100e, the thickness must be 110 μm or less. Wafer cracking does not occur.

  As described above, in the chip 100e, the region 152 is formed only in the vicinity of the guard ring region 170 along the outer periphery of the chip. Therefore, the area ratio of polyimide contained in the protective film can be reduced, and the amount of wafer warpage can be reduced. For example, when the thickness after back grinding in FIG. 5 is 80 μm, the amount of warpage of the wafer in the structure of FIG. 12 is reduced by about 1.3 mm compared to the structure of FIG. 2 according to the first embodiment. Is done.

  Thus, in chip 100e according to the present embodiment, region 152 is formed adjacent to guard ring region 170 and along guard ring region 170 in the vicinity of cell region 150 and guard ring region 170. Yes. Therefore, there is an effect that deformation and breakage of the chip can be reduced while reducing the amount of warpage of the wafer as much as possible.

  In the above description, the case where the region 152 has a triangular shape has been described. However, the shape is not limited to a triangular shape, and may be a polygonal shape or a curved shape.

<Embodiment 7>
In the first to sixth embodiments, as shown in FIG. 1, in the region 151, the dummy protective film 113 is formed so that the end surface thereof is perpendicular to the surface of the substrate 101. However, the angle formed between the end surface of the protective film 113 and the surface of the substrate 101 is not limited to 90 ° C., and may be an acute angle.

  FIG. 15 is a cross-sectional view showing a configuration of a chip 100f according to the seventh embodiment.

  FIG. 15 shows that the protective film 113 in FIG. 1 is formed such that the angle formed between its end face and the surface of the substrate 101 is not an angle of 90 ° C. but an acute angle. 15, elements similar to those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted here.

  In the back surface grinding, when the grindstone approaches the end of the protective film 113, a large stress acts. In the chip 100f, the end portion of the protective film 113 is tapered, so that an abrupt change in rigidity at the end portion is alleviated and wafer cracking is prevented.

  Thus, in the chip 100f according to the present embodiment, since the end portion of the protective film 113 is formed in a tapered shape, in addition to the effects of the first to sixth embodiments, a sudden change in rigidity at the end portion is achieved. This has the effect of further reducing chip deformation and breakage.

<Eighth embodiment>
In the sixth embodiment, as shown in FIG. 12, a region 152 having a shape in which a plurality of relatively small triangular regions are connected is formed adjacent to the guard ring region 170 along the outer periphery of the chip. I am letting. However, the region 152 may not be adjacent to the guard ring region 170 but may be formed near the guard ring region 170 at a predetermined distance.

  FIG. 16 is a cross-sectional view showing a configuration of a chip 100g according to the eighth embodiment.

  FIG. 16 does not show that the region 152 in FIG. 12 is adjacent to the guard ring region 170 by connecting a plurality of relatively small triangular regions, but a plurality of relatively small circular regions. They are formed in the vicinity of a predetermined distance from the guard ring region 170 apart from each other like islands. 16, elements similar to those in FIG. 12 are given the same reference numerals, and detailed description thereof is omitted here.

  As described above, in the chip 100g according to the present embodiment, the region 152 is arranged along the guard ring region 170 at a predetermined distance from the guard ring region 170 in the vicinity of the cell region 150 and the guard ring region 170. It is formed. Therefore, as in the sixth embodiment, there is an effect that chip deformation and breakage can be reduced while reducing the amount of wafer warpage as much as possible. Further, as in the seventh embodiment, it is possible to further reduce the deformation and breakage of the chip by mitigating the sudden change in rigidity at the end.

2 is a cross-sectional view showing a configuration of a chip according to Embodiment 1. FIG. 2 is a top view showing a configuration of a chip according to Embodiment 1. FIG. FIG. 6 is a top view illustrating a configuration of a chip according to a second embodiment. FIG. 6 is a top view illustrating a configuration of a chip according to a third embodiment. 12 is a graph showing experimental results for determining the relationship between the area ratio of polyimide and the amount of warpage of a chip according to the third embodiment. It is a graph which shows the experimental result which calculated | required the relationship between slit width and tensile stress in the chip | tip concerning Embodiment 3. FIG. FIG. 6 is a top view illustrating a configuration of a chip according to a fourth embodiment. 10 is a graph showing an experimental result of obtaining a relationship between a protective film width and a tensile stress in the chip according to the fourth embodiment. 10 is a graph showing an experimental result of obtaining a relationship between a thickness after back surface grinding and a wafer crack occurrence rate in the chip according to the fourth embodiment. FIG. 10 is a top view showing a configuration of a chip according to a fifth embodiment. 12 is a graph showing experimental results for determining the relationship between the thickness after back grinding and the rate of occurrence of wafer cracking in the chip according to the fifth embodiment. FIG. 10 is a top view showing a configuration of a chip according to a sixth embodiment. 14 is a graph showing an experimental result of obtaining a relationship between a dummy protective film interval and a tensile stress in the chip according to the sixth embodiment. 14 is a graph showing experimental results for determining the relationship between the thickness after back grinding and the rate of occurrence of wafer cracking in the chip according to the sixth embodiment. FIG. 10 is a cross-sectional view illustrating a configuration of a chip according to a seventh embodiment. FIG. 10 is a top view showing a configuration of a chip according to an eighth embodiment.

Explanation of symbols

  100 chip, 101 substrate, 102 base region, 103 emitter region, 104, 105 oxide film, 106 gate electrode, 107 interlayer insulating film, 108, 109 electrode pattern, 110-114 protective film, 115 n + buffer layer, 116 p + collector layer 117 collector electrode, 150 cell region, 151-152 region, 160 gate line region, 170 guard ring region.

Claims (3)

The substrate surface includes a cell region including a region to which a wire is bonded, a gate line region for applying a gate voltage to the cell region, and a guard ring region formed along the outer periphery to maintain a withstand voltage. A method of manufacturing a semiconductor device on the side,
In the gate line region and the guard ring region, a protective film is formed over the entire surface, and in the cell region, a protective film forming step of partially forming a protective film in a region where the wire is not bonded;
Attaching a protective tape to the front side of the substrate, and grinding the back side of the substrate,
The direction along the boundary line between the cell region and the guard ring region coincides with the crystal cleavage direction of the substrate,
The protective film in the cell region has a shape corresponding to the crystal cleavage direction at the end of the protective film by taking a non-rectangular polygonal shape or a shape extending along the boundary line when viewed from above. A plurality of regions are formed side by side along the guard ring region only in the vicinity of the boundary between the cell region and the guard ring region .
A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 1,
The method for manufacturing a semiconductor device, wherein the protective film in the cell region is formed away from the guard ring region. A method of manufacturing a semiconductor device according to claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the plurality of regions of the protective film in the cell region are formed apart from each other.

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