JP4911842B2 - Interrupt control circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interrupt control circuit in a microcomputer, and more particularly to an interrupt control circuit having a function of allocating a plurality of interrupt signals to two interrupt request signals.
[0002]
[Prior art]
In recent years, microcomputers have built in a plurality of timer circuits, an interface circuit for communicating with the outside, a reduced voltage detection circuit for detecting, for example, a momentary power interruption of the power supply voltage in order to improve versatility. In a microcomputer incorporating such a peripheral circuit, each peripheral circuit requests the CPU to perform processing corresponding to the respective peripheral circuit, and incorporates an interrupt control circuit for arbitrating each request signal. .
[0003]
In a conventional general interrupt control circuit, for example, a plurality of interrupt signals are assigned to a high-speed processing interrupt request signal having a high priority and a normal processing interrupt request signal having a low priority. In general, the allocation of priorities is fixed in hardware, and in order to change the allocation by the user, the setting is changed when the product of the microcomputer is manufactured. On the other hand, a selection register for allocating each interrupt signal to, for example, a high-speed processing interrupt request signal or a normal processing interrupt request signal is provided so that the priority order of the interrupt request signal with respect to each interrupt signal can be easily changed. The selection register is set by a program, and the processing priority for the same interrupt signal input can be changed according to the microcomputer application or the like, thereby improving the versatility of the microcomputer.
[0004]
FIG. 2 is a diagram showing a conventional interrupt control circuit.
[0005]
In FIG. 2, reference numeral 1 denotes an interrupt permission register circuit, which is composed of two registers for storing permission data corresponding to the first and second interrupt signals 10 and 11, respectively, from the CPU (not shown) to the bus BUS. The first and second permission signals EN1 and EN2 are set via
[0006]
Reference numeral 4 denotes a second gate circuit that passes or blocks the first and second interrupt signals 10 and 11 in accordance with the first and second enable signals EN1 and EN2.
[0007]
Reference numeral 5 denotes a selection register circuit, and first and second selection signals SL1 and SL2 are set from the CPU via the bus BUS. The first and second selection signals SL1 and SL2 are signals that determine whether the first and second interrupt signals 10 and 11 are allocated to the first and second interrupt request signals 12 and 13.
[0008]
A third gate circuit 6 passes or blocks the first and second interrupt signals 10 and 11 input via the second gate circuit 4 according to the first and second selection signals SL1 and SL2.
[0009]
A fourth gate 7 gates the first and second interrupt signals 10 and 11 that have passed through the second and third gate circuits 4 and 6 and outputs the first and second interrupt signals 10 and 11 to the CPU as a first interrupt request signal 12.
[0010]
A fifth gate circuit 8 passes or blocks the first and second interrupt signals 10 and 11 input via the second gate circuit 4 according to the first and second selection signals SL1 and SL2. The third gate circuit 6 and the fifth gate circuit 8 complementarily pass or block the first and second interrupt signals 10 and 11 input through the second gate circuit 4.
[0011]
Reference numeral 9 denotes a sixth gate which gates the first and second interrupt signals 10 and 11 that have passed through the second and fifth gate circuits 4 and 8 and outputs them to the CPU as a second interrupt request signal 13.
[0012]
The third gate circuit 6 and the fourth gate 7 constitute a first selector circuit, and the fifth gate circuit 8 and the sixth gate constitute a second selector circuit.
[0013]
Next, the operation of the conventional interrupt control circuit of FIG. 2 will be described.
[0014]
First, the setting states of the first and second enable signals EN1 and EN2 and the first and second selection signals SL1 and SL2 in FIG. 2 will be described. It is assumed that the first and second enable signals EN1 and EN2 are set to H level, the first selection signal SL1 is set to H level, and the second selection signal SL2 is set to L level. In this state, when the first interrupt signal 10 is input, the first interrupt signal 10 passes through the AND gate 4a of the second gate circuit 4 and the AND gate 6a of the third gate circuit 6, and the fourth gate. 7, the first interrupt request signal 12 is transferred to the CPU. On the other hand, since the AND gate 8a of the fifth gate circuit 8 is in the cut-off state, the first interrupt signal 10 is cut off by the AND gate 8a. Therefore, the first interrupt signal 10 is assigned to the first interrupt request signal 12.
[0015]
When the second interrupt signal 11 is input, the second interrupt signal 11 passes through the AND gate 4 b of the second gate circuit 4 and the AND gate 8 b of the fifth gate 8 and passes through the sixth gate 9. The second interrupt request signal 13 is transferred to the CPU. On the other hand, since the AND gate 6b of the third gate circuit 6 is cut off, the second interrupt signal 11 is cut off by the AND gate 6b. Therefore, the second interrupt signal 11 is assigned to the second interrupt request signal 13.
[0016]
Although the case where the first selection signal SL is at the H level and the second selection signal SL2 is at the L level has been described, for example, the first and second permission signals EN1 and EN2 are at the H level, and the first and second selection signals. When SL1 and SL2 are at the H level, the first and second interrupt signals 10 and 11 are both distributed as the first interrupt request signal 12 and transferred to the CPU.
[0017]
[Problems to be solved by the invention]
In the conventional interrupt control circuit described above, the setting of the selection register circuit 5 can be changed without any particular limitation. Therefore, when changing the setting of the first selection signal SL1 of the selection register circuit 5, for example, if the first interrupt signal 10 is at the H level requesting an interrupt, the H level of the first interrupt signal 10 is the first and second levels. There is a problem that it is not guaranteed to which of the interrupt request signals 12 and 13 the H level is output, and an erroneous interrupt request signal is generated against the intention of those skilled in the art.
[0018]
In general, since the CPU has a processing program corresponding to each of the first and second interrupt request signals 12 and 13, the CPU executes a program different from the program to be originally processed, and the microcomputer Causes a malfunction.
[0019]
Therefore, the present invention provides an interrupt control circuit that can stably perform a setting operation to a selection register circuit that stores selection signal data for allocating a plurality of interrupt signals to a first interrupt request signal or a second interrupt request signal. With the goal.
[0020]
[Means for Solving the Problems]
The present invention has been created in view of the above points, and is characterized by storing a selector that distributes an interrupt signal into two or more interrupt request signals according to a selection signal, and a prohibition signal. And a control register, wherein the selector prohibits input of the interrupt signal by the prohibition signal and enters a setting permission state of the selection signal.
[0021]
In addition, the selector includes a selection register that stores the selection signal when the prohibition signal is input, and a plurality of gates that are passed or blocked according to the selection signal of the selection register. Features.
[0022]
The selector further includes an interrupt permission register for storing a permission signal for permitting the input of the interrupt signal, and a gate circuit for permitting the interrupt signal according to the permission signal. The interrupt signal is forcibly cut off according to the above.
[0023]
According to the present invention, in the interrupt control circuit, the operation of the interrupt control circuit is stabilized by setting the selection register circuit for storing selection signal data for allocating a plurality of interrupt signals to the first interrupt request signal or the second interrupt request signal. Can be done.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a diagram for explaining the configuration of an embodiment of the present invention.
[0025]
A feature of the present embodiment is that a control register 2 and a first gate circuit 3 are further provided. In the control register 2, a prohibition signal INHX is set from a CPU (not shown) via the bus BUS, and the first gate circuit 3 passes or blocks the first and second permission signals EN1 and EN2 according to the prohibition signal INHX. . In the selection register circuit 5, the setting of the first and second selection signals SL1 and SL2 is permitted or prohibited according to the inhibition signal INHX.
[0026]
In FIG. 1, the same circuits as those in FIG. 2 are denoted by the same reference numerals and the description thereof is omitted. Since the allocation operation by the interrupt permission register circuit 1 and the selection register circuit 5 is the same as the conventional one, the description thereof is omitted.
[0027]
Next, an interrupt request signal allocation setting operation for the interrupt signal of the interrupt control circuit of FIG. 1 will be described. The first interrupt signal 10 is switched and output as the second interrupt request signal 13 from the first interrupt request signal 12, and the second interrupt signal 11 is switched and output as the first interrupt request signal 12 from the second interrupt signal 13. In this case, first, in the control register 2, the L level indicating prohibition is set for the first and second enable signals EN1 and EN2 at the same time, and simultaneously with the setting, the prohibit signal INHX is output as the L level.
[0028]
When the inhibition signal INHX is at the L level, the selection register circuit 5 permits the setting of the first and second selection signals SL1 and SL2, and the first selection signal SL1 is set to the L level via the bus BUS from the CPU. Second selection signal SL2 is set to H level.
[0029]
Further, since the inhibition signal INHX is at the L level, the first and second permission signals EN1 and EN2 are blocked by the first gate circuit 3. As a result, all output signals are output as L level from the first gate circuit 3.
[0030]
The first and second interrupt signals 10 and 11 are blocked by the second gate circuit 4 in accordance with the L level of all signals output from the first gate circuit 3. Therefore, the first and second interrupt request signals 12 and 13 are not generated and the interrupt processing request is not indicated, so that the CPU does not perform the interrupt processing.
[0031]
Next, when the setting of the selection register circuit 5 is completed, the inhibition signal INHX is set to H level from the CPU via the bus BUS, and the blocking of the first and second permission signals EN1 and EN2 is released. As a result, the first and second enable signals EN1 and EN2 pass through the first gate circuit 3.
[0032]
Therefore, the first and second interrupt signals 10 and 11 are passed or blocked by the second gate circuit 4 according to the first and second permission signals EN1 and EN2.
[0033]
When the inhibition signal INHX becomes H level, the selection register circuit 5 is prohibited from setting selection data.
[0034]
Since the first selection signal SL1 is at the L level, the first interrupt signal 10 passes through the second gate circuit 4 and the fifth gate circuit 8 and passes through the seventh gate as the second interrupt request signal 13 to the CPU. Transferred. Further, since the second selection signal SL2 is at the H level, the second interrupt signal 11 passes through the second gate circuit 4 and the third gate circuit 6 and passes through the fourth gate as the first interrupt request signal 12 to the CPU. Forwarded to
[0035]
Accordingly, since the first selection signal SL1 is at the L level, the first interrupt signal 10 is distributed to the second interrupt request signal 13, and since the second selection signal SL2 is at the H level, the second interrupt signal 11 is the first level. It is distributed to the interrupt request signal 13.
[0036]
This completes the setting of the selection register circuit 5.
[0037]
As described above, when setting and changing the selection signals SL1 and SL2 of the selection register circuit 5, the first and second interrupt signals 10 and 11 inputted in the second gate circuit 4 are cut off. The second interrupt request signals 12 and 13 are not generated, and it is possible to reliably prevent the CPU from performing erroneous interrupt processing.
[0038]
In this embodiment, the case where two interrupt signals are input has been described. However, any number of interrupt signals can be input without any limitation. When an arbitrary plurality of interrupt signals are input, the number of AND gates constituting the first, second, third and fifth gate circuits 3, 4, 6 and 8 may include the arbitrary plural. .
[0039]
The present invention can also be applied to a circuit that distributes one interrupt signal to three or more interrupt request signals.
[0040]
In addition, the permission signal output from the interrupt permission register circuit 1 includes any number of the permission signals. Note that the number of permission signals output from the interrupt permission register circuit 1 includes fewer permission signals than the number of interrupt signals, and a plurality of interrupt signals may be permitted or prohibited for one permission signal. good.
[0041]
In the description of the embodiment, the case where the first gate circuit 3 and the second gate circuit 4 are provided has been described. However, the 2-input AND gate constituting the second gate circuit 4 is configured by a 3-input AND gate. Then, an interrupt signal, a permission signal, and an inhibition signal INHX may be input to the one three-input AND gate.
[0042]
Further, instead of providing the control register 2, detection means for detecting that all the permission signals output from the interrupt permission register circuit 1 are prohibited and that all the permission signals are values indicating inhibition is provided. The setting of the selection register circuit 5 may be permitted according to the output of the detection means.
[0043]
【Effect of the invention】
As described above, according to the present invention, when assigning a plurality of interrupt signals to the first and second interrupt request signals, the CPU can execute the setting of the selection register circuit while preventing erroneous interrupt processing. .
[0044]
In addition, since the selection register circuit is set through the procedure of setting the control register inhibition signal INHX to the L level for inhibiting the interrupt signal input, for example, erroneous setting of the selection register due to a bug in the program can be prevented. There is an effect.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Interrupt permission register circuit 2 Control register 3 1st gate circuit 4 2nd gate circuit 5 Selection register circuit 6 3rd gate circuit 7 4th gate 8 5th gate circuit 9 6th gate 10 1st interrupt signal 11 2nd interrupt signal 12 First interrupt request signal 13 Second interrupt request signal

Claims (2)

In an interrupt control circuit capable of receiving a plurality of interrupt signals and outputting a plurality of interrupt request signals to the CPU,
For each of the plurality of interrupt signals , an interrupt permission register that stores permission data for determining whether to pass or block and outputs a first signal according to the permission data;
A control register that stores control data for determining whether or not all of the plurality of interrupt signals are to be shut off, and that outputs a second signal according to the control data;
When the second signal indicates that all of the plurality of interrupt signals are in a cutoff state, a third signal for setting all of the plurality of interrupt signals in a cutoff state is output, and the second signal is A first gate circuit that outputs the first signal as it is as a third signal when not indicating that all of the plurality of interrupt signals are to be cut off ;
In response to the third signal, for each of the plurality of interrupt signals, a second gate circuit that is in a passing state or a blocking state ;
A selection register that stores selection data for determining which interrupt request signal is assigned to each of the plurality of interrupt signals, and a selection register that outputs a selection signal according to the selection data;
Depending on the selection signal, for each of said plurality of interrupt signals, comprising a third gate circuit for determining whether allocated to which interrupt request signal, and
When the second signal indicates that all of the plurality of interrupt signals are to be cut off, by allowing writing to the selection register , which interrupt request signal is assigned to each of the plurality of interrupt signals. You can change the assignment or
When the second signal does not indicate that all of the plurality of interrupt signals are to be blocked , writing to the selection register is prohibited, so that which interrupt request signal is generated for each of the plurality of interrupt signals. An interrupt control circuit characterized in that it can not be changed whether it is assigned to the . 2. The interrupt control circuit according to claim 1, wherein the interrupt permission register, the selection register, and the control register can be set from the CPU via a bus BUS.

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