JP2003067197A - Interrupt control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interrupt control circuit capable of safely performing setting operation for allocating a plurality of interrupt signals to a first and second interrupt request signals. SOLUTION: This interrupt control circuit for inputting a plurality of interrupt signals is provided with a select register for allocating the interrupt signals to an interrupt request signal with a higher priority and an interrupt request signal with a lower priority. The circuit is provided with a control register for batch inhibiting the enable signal output of an interrupt enable register circuit for enabling the plurality of interrupt signal inputs, respectively, whereby setting of the select register can be altered only in the case where an inhibit signal output from the control register batch inhibits each enable signal output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt control circuit in a microcomputer, and more particularly to an interrupt control circuit having a function of allocating a plurality of interrupt signals to two interrupt request signals.

[0002]

2. Description of the Related Art In recent years, microcomputers are equipped with a plurality of timer circuits, an interface circuit for communicating with the outside, a low voltage detection circuit for detecting a power supply voltage interruption, for example, in order to increase versatility. Became.
In a microcomputer having such a peripheral circuit built therein, each peripheral circuit requests the CPU to perform a process corresponding to the respective peripheral circuit, and has a built-in interrupt control circuit for arbitrating the respective request signals. .

In a conventional general interrupt control circuit, for example, a plurality of interrupt signals are allocated to a high-speed interrupt request signal having a high priority and a normal process interrupt request signal having a low priority. In general, the allocation of the priority order is fixed by hardware, and the setting is changed at the time of manufacturing the microcomputer product in order to change the allocation by the user. On the other hand, in order to easily change the priority of the interrupt request signal for each interrupt signal, a selection register for allocating each interrupt signal to, for example, a high-speed processing interrupt request signal or a normal processing interrupt request signal is provided. , The selection register is set by a program, the processing priority order for the same interrupt signal input can be changed according to the application of the microcomputer, etc., and the versatility of the microcomputer is improved.

FIG. 2 is a diagram showing a conventional interrupt control circuit.

In FIG. 2, reference numeral 1 denotes an interrupt enable register circuit, which is a first and second interrupt signal 10 and 11.
It is composed of two registers for storing the permission data corresponding to each of the above, and the first and second permission signals EN1 and EN2 are set from the CPU (not shown) via the bus BUS.

A second gate circuit 4 passes or blocks the first and second interrupt signals 10 and 11 according to the first and second permission signals EN1 and EN2.

Reference numeral 5 denotes a selection register circuit, which sets first and second selection signals SL1 and SL2 from the CPU via the bus BUS. The first and second selection signals SL1 and SL2 are signals that determine whether to allocate the first and second interrupt signals 10 and 11 to the first and second interrupt request signals 12 and 13.

Reference numeral 6 denotes a third gate circuit, which is a first and second interrupt signal 1 input through the second gate circuit 4.
0 and 11 are passed or blocked according to the first and second selection signals SL1 and SL2.

A fourth gate 7 gates the first and second interrupt signals 10 and 11 which have passed through the second and third gate circuits 4 and 6, and outputs them as a first interrupt request signal 12 to the CPU. .

Reference numeral 8 is a fifth gate circuit, which is a first and second interrupt signal 1 input through the second gate circuit 4.
0 and 11 are passed or blocked according to the first and second selection signals SL1 and SL2. The third gate circuit 6 and the fifth
The gate circuit 8 complementarily passes or blocks the first and second interrupt signals 10 and 11 input via the second gate circuit 4.

A sixth gate 9 gates the first and second interrupt signals 10 and 11 which have passed through the second and fifth gate circuits 4 and 8, and outputs the second interrupt request signal 13 to the CPU.

The third gate circuit 6 and the fourth gate 7 form a first selector circuit, and the fifth gate circuit 8 and the sixth gate form a second selector circuit.

Next, the operation of the conventional interrupt control circuit of FIG. 2 will be described.

First, the first and second permission signals EN1 shown in FIG.
And the setting state of EN2 and the first and second selection signals SL1 and SL2 will be described. It is assumed that the first and second permission signals EN1 and EN2 are set to H level, the first selection signal SL1 is set to H level, and the second selection signal SL2 is set to L level.
In such a state, when the first interrupt signal 10 is input, the first interrupt signal 10 is the AN of the second gate circuit 4.
AND gate 6a of D gate 4a and third gate circuit 6
And is transferred to the CPU as the first interrupt request signal 12 via the fourth gate 7. On the other hand, since the AND gate 8a of the fifth gate circuit 8 is in the cutoff state,
The first interrupt signal 10 is cut off by the AND gate 8a. Therefore, the first interrupt signal 10 is distributed to the first interrupt request signal 12.

When the second interrupt signal 11 is input, the second interrupt signal 11 is supplied to the AND gate 4b of the second gate circuit 4 and the AND gate 8b of the fifth gate 8.
And is transferred to the CPU as the second interrupt request signal 13 via the sixth gate 9. On the other hand, since the AND gate 6b of the third gate circuit 6 is in the cutoff state,
The second interrupt signal 11 is cut off by the AND gate 6b. Therefore, the second interrupt signal 11 is distributed to the second interrupt request signal 13.

Although the case where the first selection signal SL is at the H level and the second selection signal SL2 is at the L level has been described, for example, the first and second permission signals EN1 and EN2 are at the H level, and the first and the second permission signals are. When the 2 selection signals SL1 and SL2 are at the H level, both the first and second interrupt signals 10 and 11 are distributed as the first interrupt request signal 12, and CP
Transferred to U.

[0017]

In the conventional interrupt control circuit described above, the setting of the selection register circuit 5 can be changed without any particular limitation. Therefore, when the setting of the first selection signal SL1 of the selection register circuit 5 is changed, for example, if the first interrupt signal 10 is at the H level that requests an interrupt, the H level of the first interrupt signal 10 becomes the first and second levels. H for any of the interrupt request signals 12 and 13
There is a problem in that whether or not the level is output is not guaranteed, and an erroneous interrupt request signal is generated against the intention of those skilled in the art.

Since the CPU generally has a processing program corresponding to each of the first and second interrupt request signals 12 and 13, it executes a program different from the program to be originally processed. However, there is a problem that the microcomputer malfunctions.

For this reason, the present invention provides an interrupt control circuit capable of stably performing the setting operation to the selection register circuit which stores the selection signal data for allocating a plurality of interrupt signals to the first interrupt request signal or the second interrupt request signal. The purpose is to provide.

[0020]

The present invention has been made in view of the above points, and is characterized in that an interrupt signal is converted into two or more interrupt request signals in accordance with a selection signal. A selector for allocating and a control register for storing a prohibition signal, wherein the selector prohibits input of the interrupt signal by the prohibition signal,
It is characterized in that the setting permission state of the selection signal is set.

Further, the selector includes a selection register which stores the selection signal when the prohibition signal is input,
It is characterized by comprising a plurality of gates which are turned on or off according to a selection signal of the selection register.

Further, the selector has an interrupt permission register for storing a permission signal for permitting the input of the interrupt signal, and a gate circuit for permitting the interrupt signal according to the permission signal. The interrupt signal is forcibly cut off in accordance with the prohibition signal.

According to the present invention, in the interrupt control circuit, the setting of the selection register circuit for storing the selection signal data for allocating a plurality of interrupt signals to the first interrupt request signal or the second interrupt request signal is performed by the operation of the interrupt control circuit. Can be stably performed.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a diagram for explaining the configuration of the embodiment of the present invention.

The feature of this embodiment is that the control register 2 and the first gate circuit 3 are further provided. In the control register 2, the CPU B (not shown) to the bus B
The prohibition signal INHX is set via US, and the first gate circuit 3 passes or blocks the first and second permission signals EN1 and EN2 according to the prohibition signal INHX. Then, in the selection register circuit 5, in response to the inhibition signal INHX, the first register
The setting of the second selection signals SL1 and SL2 is permitted or prohibited.

In FIG. 1, the same circuits as those in FIG. 2 are designated by the same reference numerals and the description thereof will be omitted. Further, the allocation operation by the interrupt permission register circuit 1 and the selection register circuit 5 is the same as the conventional one, and therefore will be omitted.

Next, the allocation setting operation of the interrupt request signal with respect to the interrupt signal of the interrupt control circuit of FIG. 1 will be described. The first interrupt signal 10 is switched from the first interrupt request signal 12 to the second interrupt request signal 13 and output, and the second interrupt signal 11 is switched to the second interrupt signal 1
When switching from 3 to 1 as the first interrupt request signal 12 is to be output, first, in the control register 2, the L level indicating the prohibition of the first and second permission signals EN1 and EN2 is set at the same time. Prohibition signal INH
X is output as L level.

When the inhibit signal INHX is at the L level, the selection register circuit 5 permits the setting of the first and second selection signals SL1 and SL2, and the CPU causes the bus B
The first selection signal SL1 is set to L level and the second selection signal SL2 is set to H level via US.

Since the inhibition signal INHX is at L level, the first and second permission signals EN1 and EN2 are cut off by the first gate circuit 3. As a result, the first gate circuit 3
Therefore, all output signals are output as L level.

Then, according to the L level of all signals output from the first gate circuit 3, the first and second interrupt signals 1
0 and 11 are cut off by the second gate circuit 4. Therefore,
Since the first and second interrupt request signals 12 and 13 are not generated and do not indicate an interrupt processing request, the CPU
Does not handle interrupts.

Next, when the setting of the selection register circuit 5 is completed, the inhibit signal INHX is sent from the CPU via the bus BUS.
Is set to H level, and the interruption of the first and second permission signals EN1 and EN2 is released. As a result, the first and second permission signals EN1 and EN2 pass through the first gate circuit 3.

Therefore, the first and second interrupt signals 10 and 11 are passed or blocked by the second gate circuit 4 according to the first and second permission signals EN1 and EN2.

When the inhibition signal INHX goes high, the selection register circuit 5 is inhibited from setting the selection data.

Since the first selection signal SL1 is at the L level, the first interrupt signal 10 passes through the second gate circuit 4 and the fifth gate circuit 8 and the second gate circuit 7 through the seventh gate.
It is transferred to the CPU as the interrupt request signal 13. Further, since the second selection signal SL2 is at the H level, the second interrupt signal 11 passes through the second gate circuit 4 and the third gate circuit 6 and the CPU as the first interrupt request signal 12 via the fourth gate. Transferred to.

Therefore, since the first selection signal SL1 is at the L level, the first interrupt signal 10 is distributed to the second interrupt request signal 13, and since the second selection signal SL2 is at the H level, the second interrupt signal 11 is generated. Will be distributed to the first interrupt request signal 13.

This completes the setting of the selection register circuit 5.

As described above, when the setting of the selection signals SL1 and SL2 of the selection register circuit 5 is changed, the first and second interrupt signals 10 input in the second gate circuit 4 are input.
Since 11 and 11 are cut off, the first and second interrupt request signals 12 and 13 are not generated, and it is possible to reliably prevent the CPU from performing erroneous interrupt processing.

In this embodiment, the case of inputting two interrupt signals has been described, but the number of interrupt signals to be input is not limited, and any desired number can be input. When inputting a plurality of arbitrary interrupt signals, the number of AND gates forming the first, second, third and fifth gate circuits 3, 4, 6 and 8 may include the arbitrary plural number. .

The present invention can also be applied to a circuit that distributes one interrupt signal to three or more interrupt request signals.

The enable signal output from the interrupt enable register circuit 1 includes an arbitrary plurality of enable signals. still,
The number of enable signals output from the interrupt enable register circuit 1 may be smaller than the number of interrupt signals, and a plurality of interrupt signals may be enabled or disabled for one enable signal.

In the description of the embodiment, the first gate circuit 3
The case where the second gate circuit 4 and the second gate circuit 4 are provided has been described.
The 2-input AND gate forming the gate circuit 4 may be formed by a 3-input AND gate, and the interrupt signal, the enable signal, and the inhibit signal INHX may be input to one of the 3-input AND gates.

Further, instead of providing the control register 2,
A detection unit is provided which prohibits all the permission signals output from the interrupt permission register circuit 1 and detects that all the permission signals have a value indicating prohibition, and the selection register circuit is provided according to the output of the detection unit. The setting of 5 may be permitted.

[0043]

As described above, according to the present invention, when assigning a plurality of interrupt signals to the first and second interrupt request signals, the CPU executes setting of the selection register circuit while preventing erroneous interrupt processing. It has the effect of being able to.

Further, since the selection register circuit is set through the procedure of setting the inhibition signal INHX of the control register to the L level which inhibits the input of the interrupt signal, for example, the selection register is erroneously set due to a program bug or the like. There is an effect that can prevent.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

1 Interrupt enable register circuit 2 control register 3 First gate circuit 4 Second gate circuit 5 Selection register circuit 6 Third gate circuit 7 Fourth Gate 8 Fifth gate circuit 9th gate 10 First interrupt signal 11 Second interrupt signal 12 First interrupt request signal 13 Second interrupt request signal

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yoshimasa Arai             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Kei Ichikawa             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Shigeo Tanaka             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Ryoji Fujiwara             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Hidekazu Kato             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. (72) Inventor Yoshitoshi Oyamada             2-5-3 Keihan Hondori, Moriguchi City, Osaka Prefecture             Within Yo Denki Co., Ltd. F-term (reference) 5B061 BA02 CC08 CC10 RR02                 5B098 BA12 BB06 BB18 CC01 CC08

Claims (3)

[Claims] 1. A selector, which divides an interrupt signal into two or more interrupt request signals according to a selection signal, and a control register which stores an inhibit signal, wherein the selector inputs the interrupt signal by the inhibit signal. An interrupt control circuit which is prohibited and enters a setting permission state of the selection signal. 2. The selector comprises a selection register that stores the selection signal when the prohibition signal is input, and a plurality of gates that are in a passing or blocking state according to the selection signal of the selection register. The interrupt control circuit according to claim 1, wherein: 3. The selector further includes an interrupt permission register for storing a permission signal for permitting the input of the interrupt signal, and a gate circuit for permitting the interrupt signal according to the permission signal. 3. The interrupt control circuit according to claim 2, wherein the circuit forcibly interrupts the interrupt signal according to the prohibition signal.