JP2008269548A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems wherein an existing microcomputer involves a large circuit scale, high costs, a high power consumption and unbalanced loads of interrupt handling between processing circuits. <P>SOLUTION: A microcomputer includes a plurality of processing circuits, a factor register circuit, a processing circuit selection register circuit, a mask circuit, a priority circuit and a processing circuit selection circuit. The priority circuit outputs an interrupt signal, a vector signal and a selection signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a microcomputer including a plurality of processing circuits (for example, CPUs) to perform a plurality of interrupt processes caused by a plurality of factors.

  In the conventional microcomputer M100 shown in FIG. 6, when any of the factors F1 to Fi (for example, the factor F1) occurs, the first interrupt controller 100 (factor register) to which the factors F1 to Fi are assigned. The circuit 110, the mask circuit 120, and the priority circuit 130.) the first processing circuit A, the interrupt signal indicating that the interrupt processing corresponding to the factor F1 should be executed, and the interrupt processing. A vector signal indicating the address (start address) of the area on the first memory circuit 300 where the contents are stored is output. When the first processing circuit A receives the interrupt signal and the vector signal, the first processing circuit A performs the interrupt according to the contents of the interrupt processing for the factor F1 stored in the area on the first storage circuit 300. Execute the included process.

  In the conventional microcomputer M100 described above, in the same manner as described above, the second interrupt controller 200, the second processing circuit B, and the second memory circuit 400 cooperate to cause a factor F (i + 1). Interrupt processing corresponding to ~ Fn is executed.

  However, since the conventional microcomputer M100 described above requires two interrupt controllers, that is, the first and second interrupt controllers 100 and 200, for the two processing circuits A and B, the circuit scale. As a result, there is a problem that the cost and the power consumption increase.

  The factors F1 to Fi are fixedly assigned to the first interrupt controller 100 (for example, by wiring), and the factors F (i + 1) to Fn are fixedly assigned to the second interrupt controller 200. Since it is assigned, the load of the interrupt process by the first processing circuit A and the load of the interrupt process by the second processing circuit B may not necessarily be balanced.

The first microcomputer according to the present invention is to solve the above-described problems.
A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
Each relationship defines a plurality of relationships that are correspondence relationships between one of the first plurality of factors and one of the plurality of processing circuits that should perform an interrupt process corresponding to the one factor. An interrupt signal indicating that an interrupt process should be executed to the plurality of processing circuits when one of the first plurality of factors occurs; A vector signal indicating an area in which the content of one interrupt process corresponding to one factor is defined, and a processing circuit that should execute the one interrupt process corresponding to the one factor. The processing circuit selection register circuit for outputting a first selection signal;
A processing circuit selection circuit for outputting a second selection signal indicating that the processing circuit is selected to the processing circuit indicated by the first selection signal in response to the first selection signal. .

A second microcomputer according to the present invention includes:
A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
Each relationship defines a plurality of relationships that are correspondence relationships between one of the first plurality of factors and one of the plurality of processing circuits that should perform an interrupt process corresponding to the one factor. An interrupt signal indicating that an interrupt process should be executed to the plurality of processing circuits when one of the first plurality of factors occurs; and The processing circuit selection register circuit for outputting a vector signal indicating a region in which the content of one interrupt process corresponding to the one factor is defined;
In response to the vector signal, a multiplexer circuit that outputs a first selection signal indicating which processing circuit should execute one interrupt process corresponding to the one factor;
A processing circuit selection circuit for outputting a second selection signal indicating that the processing circuit is selected to the processing circuit indicated by the first selection signal in response to the first selection signal;

  According to the first and second microcomputers according to the present invention described above, the processing circuit selection circuit is independent, or the multiplexer circuit and the processing circuit selection circuit cooperate to provide the plurality of processing circuits. By outputting the interrupt signal, the vector signal, and the second selection signal, the plurality of processing circuits can execute the interrupt process without using a plurality of conventional interrupt controllers. As a result, the circuit scale of the microcomputer is smaller than that of the conventional one, and it becomes possible to reduce the cost and power consumption.

  In addition, since the processing circuit selection register circuit can assign to which of the plurality of processing circuits the interrupt processing corresponding to the plurality of factors, interrupt processing between the plurality of processing circuits. Can be balanced.

The third microcomputer according to the present invention is to solve the above-described problems.
A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
Each relationship defines a plurality of relationships that are correspondence relationships between one of the first plurality of factors and one of the plurality of processing circuits that should perform an interrupt process corresponding to the one factor. A processing circuit selection register circuit;
A mask circuit for permitting acceptance of a second plurality of factors of the first plurality of factors and prohibiting acceptance of other remaining factors;
(1) Among the first plurality of factors, when at least two or more factors corresponding to the second plurality of factors permitted to be accepted by the mask circuit are generated, the two or more factors A priority circuit preliminarily defining a priority level at which two or more interrupt processing corresponding to a factor is to be performed, and (2) (2a) that the plurality of processing circuits should execute interrupt processing. And a vector signal indicating a region in which the content of the interrupt processing having the highest priority is defined, and (2b) the plurality of the plurality of rules defined in the processing circuit selection register circuit Based on the relationship, the priority circuit that outputs a first selection signal indicating which processing circuit should execute the highest priority interrupt processing;
A processing circuit selection circuit for outputting a second selection signal indicating that the processing circuit is selected to the processing circuit indicated by the first selection signal in response to the first selection signal. .

A fourth microcomputer according to the present invention includes:
A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
Each relationship defines a plurality of relationships that are correspondence relationships between one of the first plurality of factors and one of the plurality of processing circuits that should perform an interrupt process corresponding to the one factor. A processing circuit selection register circuit;
A mask circuit for permitting acceptance of a second plurality of factors of the first plurality of factors and prohibiting acceptance of other remaining factors;
(1) Among the first plurality of factors, when at least two or more factors corresponding to the second plurality of factors permitted to be accepted by the mask circuit are generated, the two or more factors A priority circuit predefining a priority level at which two or more interrupt processing corresponding to a factor is to be performed, and (2) an interrupt indicating that the plurality of processing circuits should be executed The priority circuit for outputting a signal and a vector signal indicating an area in which the content of the interrupt processing having the highest priority is defined;
In response to the vector signal, a multiplexer circuit that outputs a first selection signal indicating which processing circuit is to execute the highest priority interrupt processing;
A processing circuit selection circuit for outputting a second selection signal indicating that the processing circuit is selected to the processing circuit indicated by the first selection signal in response to the first selection signal. .

  According to the third and fourth microcomputers of the present invention described above, the priority circuit and the processing circuit selection circuit cooperate or the priority circuit, the multiplexer circuit and the processing circuit selection circuit cooperate. Then, by outputting the interrupt signal, the vector signal, and the second selection signal to the plurality of processing circuits, the plurality of processing circuits can be used without using a plurality of conventional interrupt controllers. In addition, the interrupt processing can be executed. As a result, the circuit scale of the microcomputer is smaller than that of the conventional one, and it is possible to reduce the cost and power consumption.

  In addition, since the processing circuit selection register circuit can assign to which of the plurality of processing circuits the interrupt processing corresponding to the plurality of factors, interrupt processing between the plurality of processing circuits. Can be balanced.

  Embodiments of a microcomputer according to the present invention will be described with reference to the drawings.

"Example"
FIG. 1 shows a configuration of a microcomputer according to the embodiment. As shown in FIG. 1, the microcomputer M10 according to the embodiment includes an interrupt controller 10, a CPU selection circuit 20, a first processing circuit (CPU) A, a second processing circuit (CPU) B, A first memory circuit 30 and a second memory circuit 40 are included.

  The interrupt controller 10 includes a factor register circuit 11, a CPU selection register circuit 12, a mask circuit 13, and a priority circuit 14.

  As shown in FIG. 2A, the factor register circuit 11 has a plurality of registers 11 (1) to 11 (n), and a plurality of factors (for example, button depression, temperature detection, etc.) from the outside. (None are shown.)) A plurality of factor generation signals S (F1) to S (Fn) indicating that F1 to Fn are generated are received.

  In the following, for ease of explanation and understanding, it is basically assumed that the factors F1 and F2 have occurred.

  In the factor register circuit 11, for example, when a factor generation signal S (F1) indicating that the factor F1 has occurred is input, the factor register 11 (1) is triggered by the input of the factor generation signal S (F1). , “Present” (unresolved) is set (set). Similarly, when the factor generation signal S (F2) indicating that the factor F2 has occurred is input, the factor register 11 (2) is set to “Yes” when the factor generation signal S (F2) is input. Set to

  As will be described later, the factor register 11 (1) set to “present” causes the first processing circuit A to execute the interrupt processing corresponding to the factor F1 when the first processing circuit A completes the interrupt processing corresponding to the factor F1. It is set (cleared) to “None” (solved). Similarly, when the second processing circuit B completes the interrupt process corresponding to the factor F2, the factor register 11 (2) set to “present”, as will be described later, The processing circuit B sets “none”.

  The CPU selection register circuit 12 is a “processing circuit selection register circuit”, and as shown in FIG. 2B, the factors F1 to Fn and the CPU (first processing circuit) that should process the factors F1 to Fn. A or the second processing circuit B), precisely, the correspondence relationship with the CPU that should execute the interrupt processing corresponding to the factors F1 to Fn is defined in advance. For example, when the factor F1 occurs, the CPU selection register circuit 12 defines that the first processing circuit A should perform an interrupt process for the factor F1, and when the factor F2 occurs Stipulates that the second processing circuit B should perform the interrupt processing for the factor F2.

  As shown in FIG. 2C, the mask circuit 13 predefines whether to permit / inhibit the factors F1 to Fn, more specifically, whether to permit or prohibit the interrupt processing corresponding to the factors F1 to Fn. ing. For example, the mask circuit 13 defines that the interrupt processing corresponding to the factors F1, F2, F3, and Fn is “permitted”, “permitted”, “prohibited”, and “prohibited”, respectively.

  For example, when the factor F1, the factor F2, and the factor F3 are generated, the interrupt processing corresponding to the factor F1 and the interrupt processing corresponding to the factor F2 are “permitted”. The interrupt process can be executed by the first processing circuit A, and the latter interrupt process can be executed by the second processing circuit B. In contrast, since the interrupt process corresponding to the factor F3 is “prohibited”, the interrupt process is executed by the second processing circuit B (FIG. 2B) that should execute the interrupt process. Even if it is shown), it is not executed.

  As shown in FIG. 2D, the priority circuit 14 defines the priority (priority order) of interrupt processing corresponding to the factors F1 to Fn, more precisely, the factors F1 to Fn. For example, the priority circuit 14 defines that the priority of interrupt processing corresponding to the factors F1 and F2 is “extremely high” and “high”, respectively.

  Returning to FIG. 1, the priority circuit 14 indicates that an interrupt process corresponding to any of the factors F1 to Fn should be executed, in other words, an interrupt signal indicating that it is necessary to execute some interrupt process. Sint, a vector signal Svct indicating the start address of the area where the contents of the interrupt processing are stored is output to the first processing circuit A and the second processing circuit B. In addition, the priority circuit 14 outputs to the CPU selection circuit 20 a first selection signal Ssel indicating which of the first processing circuit A and the second processing circuit B should execute the interrupt processing.

  More specifically, for example, if the factor F1 and the factor F2 that are “permitted” by the mask circuit 13 occur, the priority 14 circuit determines the “factor F1 allocation” defined in the CPU selection register circuit 12 in advance. "The first processing circuit A should execute the interrupt processing" and "The factor F2 interrupt processing should be executed by the second processing circuit B", and the priority circuit 14 previously defined "factor By referencing F1 priority “extremely high” and “factor F2 priority“ high ””, factor F1 has priority over factor F2, that is, factor F1 interrupt processing has priority over factor F2 interrupt processing. In addition, it is determined that the first processing circuit A should execute the interrupt processing for the factor F1. As a result of the determination, a selection signal Ssel indicating that the first processing circuit A should be selected is output to the CPU selection circuit 20.

  Upon receiving the selection signal Ssel from the priority circuit 14, the CPU selection circuit 20 outputs the selection signal Ssel1 to the first processing circuit A according to the content indicated by the selection signal Ssel, or outputs the selection signal Ssel1 to the second processing circuit B. The selection signal Ssel2 is output. When the CPU selection circuit 20 receives, for example, the first selection signal Ssel indicating that the first processing circuit A should be selected as described above, the selection indicating that the first processing circuit A is selected. The signal Ssel1 is output to the first processing circuit A.

  The first processing circuit A and the second processing circuit B perform the interrupt processing corresponding to the factors F1 to Fn stored in the first storage circuit 30 and the second storage circuit 40, respectively. Execute based on the contents of.

  For example, the first processing circuit A receives the interrupt signal Sint indicating that it is necessary to execute some interrupt processing as described above from the priority circuit 14, and the interrupt processing corresponding to the factor F1. The vector signal Svct indicating the address “1001” on the first storage circuit 30 is received, and the first processing circuit A selects from the CPU selection circuit 20 as described above. Upon receipt of the selection signal Ssel1 indicating that it has been made, the jump is made to the jump destination address “3100” stored in the address “1001” of the first memory circuit 30 and stored after the address “3100”. The contents of the interrupt process corresponding to the factor F1 are started to be executed. When the execution of the interrupt process corresponding to the factor F1 is completed, the first processing circuit A sets (clears) the factor register 11 (1) in the factor register circuit 11 from “present” to “none”.

  As described above, in the microcomputer M10 of the embodiment, the factor F1 and the factor F2 that are “permitted” by the mask circuit 13, and the priority of the factor F1 is higher than the priority of the factor F2 and the factor F1. When the factor F2 occurs, the priority circuit 14 determines the interrupt signal Sint indicating that it is necessary to perform any interrupt processing, and the address of the area in which the interrupt processing of the factor F1 is stored. The vector signal Svct shown is output to the first processing circuit A and the second processing circuit B, and the interrupt processing is performed in accordance with the contents defined by the priority circuit 14. The CPU selection circuit 2 is output by outputting a selection signal Ssel indicating that it should be executed to the CPU selection circuit 20. However, by outputting Ssel1 indicating that the first processing circuit A has been selected to the first processing circuit A, the first processing circuit A executes an interrupt process corresponding to the factor F1. As a result, the circuit scale is reduced as compared with the conventional microcomputer M100 that requires the two interrupt controllers 100 and 200, and as a result, low cost and low power consumption can be realized.

  Further, it is changed by changing only the setting contents of the CPU selection register circuit 12 which of the first processing circuit A and the second processing circuit B should execute the interrupt processing corresponding to the factors F1 to Fn. Therefore, unlike the conventional microcomputer M100, it is possible to easily balance the interrupt processing load between the first processing circuit A and the second processing circuit B.

<< Modification 1 >>
As shown in FIG. 3, in the interrupt controller 10 of the first modification that replaces the interrupt controller 10 (shown in FIG. 1) of the above-described embodiment, the priority circuit 14 receives the vector signal Svct as a first signal. In addition to outputting to the processing circuit A and the second processing circuit B, outputting to the switching circuit 15, the switching circuit 15 is based on the address defined by the vector signal Svct, for example, the address “1001”. It is learned that the interrupt process is caused by the factor F1, and as a result, the selection signal Ssel indicating that the first processing circuit A should be selected is output to the CPU selection circuit 20. Even with such a configuration, it is possible to obtain the same effect as described above.

<< Modification 2 >>
As shown in FIG. 4, the interrupt controller 10 of the second modified example replacing the interrupt controller 10 (shown in FIG. 1) of the above-described embodiment includes only the factor register circuit 11 and the CPU selection register circuit 12. In other words, the mask circuit 13 and the priority circuit 14 are not included.

  The factor register 11 of the second modification has the same configuration and function as the factor register 11 of the above-described embodiment. On the other hand, the CPU selection register circuit 12 of the second modification includes the factor register 11 of the above-described embodiment. Have the same configuration, but different functions.

  Specifically, in the interrupt controller 10, for example, the factor register 11 (1) in the factor register circuit 11 indicates that the factor F1 has occurred, as shown in FIG. When “present” (unresolved) is set (set) by the input of S (F1), the CPU selection register circuit 12 determines whether the generated factor and the CPU that should execute the interrupt processing corresponding to the factor are executed. Reference is made to the correspondence (shown in FIG. 2B).

  As a result, the CPU selection register circuit 12 knows that the interrupt processing corresponding to the factor F1 should be executed by the first processing circuit A. Further, in place of the priority circuit 14 of the above-described embodiment, the CPU selection register circuit 12 The interrupt signal Sint, the vector signal Svct, and the selection signal Ssel indicating that the first processing circuit A should be selected are output. Hereinafter, by performing the same operation as in the above-described embodiment, the same effect as in the above-described embodiment can be obtained.

<< Modification 3 >>
As illustrated in FIG. 5, the interrupt controller 10 of Modification 3 instead of the interrupt controller 10 of Modification 1 described above (illustrated in FIG. 3) includes a factor register circuit 11, Although the CPU selection register circuit 12 and the switching circuit 15 are included, unlike the first modification, the mask circuit 13 and the priority circuit 14 are not included.

  In the interrupt controller 10 of Modification 3, for example, as shown in FIG. 2A, the factor register 11 (1) in the factor register circuit 11 causes a factor generation signal S () indicating that the factor F1 has occurred. When “present” (unsolved) is set (set) by the input of F1), the CPU selection register circuit 12 refers to the correspondence shown in FIG.

  As a result, the CPU selection register circuit 12 knows that the first processing circuit A should execute the interrupt processing corresponding to the factor F1, and further replaces the priority circuit 14 of the first modification described above. The interrupt signal Sint and the vector signal Svct are output.

  Upon receiving the vector signal Svct, the switching circuit 15 outputs a selection signal Ssel indicating that the first processing circuit A should be selected, like the switching circuit 15 of the first modification. Finally, the interrupt controller 10 outputs the interrupt signal Sint, the vector signal Svct, and the selection signal Ssel as described above, and thereafter performs the same operation as the above-described modification example 1 to thereby modify the modification example 1. The same effect can be obtained.

The figure which shows the structure of the microcomputer of an Example. The figure which shows a factor register circuit, CPU selection register circuit, a mask circuit, and a priority circuit. The figure which shows the structure of the microcomputer of the modification 1. The figure which shows the structure of the microcomputer of the modification 2. The figure which shows the structure of the microcomputer of the modification 3. The figure which shows the structure of the conventional microcomputer.

Explanation of symbols

  M10: Microcomputer, 10: Interrupt controller, 20: CPU selection circuit, A ... First processing circuit, B ... Second processing circuit, 30 ... First memory circuit, 40 ... Second memory circuit, 11 ... cause register circuit, 12 ... CPU selection register circuit, 13 ... mask circuit, 14 ... priority circuit.

Claims (4)

A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
Each relationship defines a plurality of relationships that are correspondence relationships between one of the first plurality of factors and one of the plurality of processing circuits that should perform an interrupt process corresponding to the one factor. An interrupt signal indicating that an interrupt process should be executed to the plurality of processing circuits when one of the first plurality of factors occurs; A vector signal indicating an area in which the content of one interrupt process corresponding to one factor is defined, and a processing circuit that should execute the one interrupt process corresponding to the one factor. The processing circuit selection register circuit for outputting a first selection signal;
A processing circuit selection circuit for outputting a second selection signal indicating that the processing circuit is selected to the processing circuit indicated by the first selection signal in response to the first selection signal. A microcomputer characterized by that. A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
Each relationship defines a plurality of relationships that are correspondence relationships between one of the first plurality of factors and one of the plurality of processing circuits that should perform an interrupt process corresponding to the one factor. An interrupt signal indicating that an interrupt process should be executed to the plurality of processing circuits when one of the first plurality of factors occurs; and The processing circuit selection register circuit for outputting a vector signal indicating a region in which the content of one interrupt process corresponding to the one factor is defined;
In response to the vector signal, a multiplexer circuit that outputs a first selection signal indicating which processing circuit should execute one interrupt process corresponding to the one factor;
In response to the first selection signal, a processing circuit selection circuit that outputs a second selection signal indicating that the processing circuit is selected to a processing circuit indicated by the first selection signal. A microcomputer characterized by. A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
Each relationship defines a plurality of relationships that are correspondence relationships between one of the first plurality of factors and one of the plurality of processing circuits that should perform an interrupt process corresponding to the one factor. A processing circuit selection register circuit;
A mask circuit for permitting acceptance of a second plurality of factors of the first plurality of factors and prohibiting acceptance of other remaining factors;
(1) Among the first plurality of factors, when at least two or more factors corresponding to the second plurality of factors permitted to be accepted by the mask circuit are generated, the two or more factors A priority circuit preliminarily specifying a priority at which two or more interrupt processing corresponding to a factor is to be performed, and (2) (2a) that the plurality of processing circuits should execute interrupt processing. And a vector signal indicating a region in which the content of the interrupt processing having the highest priority is defined, and (2b) the plurality of the plurality of rules defined in the processing circuit selection register circuit Based on the relationship, the priority circuit that outputs a first selection signal indicating which processing circuit should execute the highest priority interrupt processing;
A processing circuit selection circuit for outputting a second selection signal indicating that the processing circuit is selected to the processing circuit indicated by the first selection signal in response to the first selection signal. A microcomputer characterized by that. A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
Each relationship defines a plurality of relationships that are correspondence relationships between one of the first plurality of factors and one of the plurality of processing circuits that should perform an interrupt process corresponding to the one factor. A processing circuit selection register circuit;
A mask circuit for permitting acceptance of a second plurality of factors of the first plurality of factors and prohibiting acceptance of other remaining factors;
(1) Among the first plurality of factors, when at least two or more factors corresponding to the second plurality of factors permitted to be accepted by the mask circuit are generated, the two or more factors A priority circuit predefining a priority level at which two or more interrupt processing corresponding to a factor is to be performed, and (2) an interrupt indicating that the plurality of processing circuits should be executed The priority circuit for outputting a signal and a vector signal indicating an area in which the content of the interrupt processing having the highest priority is defined;
In response to the vector signal, a multiplexer circuit that outputs a first selection signal indicating which processing circuit is to execute the highest priority interrupt processing;
In response to the first selection signal, a processing circuit selection circuit that outputs a second selection signal indicating that the processing circuit is selected to a processing circuit indicated by the first selection signal. A microcomputer characterized by.

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