JP2008269549A - Microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problems wherein an existing microcomputer involves a large circuit scale, high costs, a high power consumption and unbalanced loads of interrupt handling between processing circuits. <P>SOLUTION: A microcomputer includes a plurality of processing circuits, a factor register circuit, a processing circuit selection register circuit, a mask circuit, a priority circuit and a processing circuit selection circuit. The priority circuit outputs an interrupt signal, a vector signal and a selection signal to each of the plurality of processing circuits. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a microcomputer including a plurality of processing circuits (for example, CPUs) to perform a plurality of interrupt processes caused by a plurality of factors.

  In the conventional microcomputer M100 shown in FIG. 4, when any one of the factors F1 to Fi, for example, the factor generation signal S (F1) indicating that the factor F1 is generated is received, the factors F1 to Fi are received. Is assigned to the first interrupt controller 100 (including the factor register circuit 110, the mask circuit 120, and the priority circuit 130), the interrupt processing corresponding to the factor F1 should be executed by the first processing circuit A. An interrupt signal indicating the effect and a vector signal indicating the address (start address) of the area on the first memory circuit 300 in which the contents of the interrupt processing are stored are output. When the first processing circuit A receives the interrupt signal and the vector signal, the first processing circuit A performs the interrupt processing according to the contents of the interrupt processing stored after the head address in the first storage circuit 300. Execute.

  In the conventional microcomputer M100 described above, in the same manner as described above, the second interrupt controller 200, the second processing circuit B, and the second memory circuit 400 cooperate to cause a factor F (i + 1). Interrupt processing corresponding to ~ Fn is executed.

  However, since the conventional microcomputer M100 described above requires two interrupt controllers, that is, the first and second interrupt controllers 100 and 200, for the two processing circuits A and B, the circuit scale. As a result, there is a problem that the cost and the power consumption increase.

  The factors F1 to Fi are fixedly assigned to the first interrupt controller 100 (for example, by wiring), and the factors F (i + 1) to Fn are fixedly assigned to the second interrupt controller 200. Because of the assignment, the interrupt processing load of the first processing circuit A and the interrupt processing load of the second processing circuit B may not always be balanced.

A first microcomputer according to the present invention includes:
A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
A processing circuit selection that defines a plurality of relations, each of which is a correspondence relation between one of the plurality of factors and one of the plurality of processing circuits to perform an interrupt process corresponding to the one factor An interrupt indicating that an interrupt process should be executed for each of the plurality of processing circuits when at least two or more of the first plurality of factors occur in the register circuit A signal, a vector signal indicating a position where the contents of the interrupt processing to be executed by the plurality of processing circuits among the two or more interrupt processing corresponding to the two or more factors, and the processing circuit And a processing circuit selection register circuit that outputs a selection signal indicating that is selected.

  According to the first microcomputer of the present invention, the processing circuit selection register circuit outputs the interrupt signal, the vector signal, and the selection signal for each of the plurality of processing circuits. As in the prior art, for each of the plurality of processing circuits, the interrupt processing to be performed by the processing circuit can be executed. On the other hand, unlike the prior art, two conventional interrupt controllers are required. As a result, low cost and low power consumption can be achieved.

  In addition, since the plurality of factors, that is, to which of the plurality of processing circuits a plurality of interrupt processes corresponding to the plurality of factors can be assigned, can be performed by the processing circuit selection register circuit. It becomes possible to easily balance the load of interrupt processing between the processing circuits.

The second microcomputer according to the present invention is to solve the above problems.
A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
A processing circuit selection that defines a plurality of relations, each of which is a correspondence relation between one of the plurality of factors and one of the plurality of processing circuits to perform an interrupt process corresponding to the one factor A register circuit;
A mask circuit for permitting acceptance of a second plurality of factors of the first plurality of factors and prohibiting acceptance of other remaining factors;
When at least two or more factors corresponding to the second plurality of factors accepted by the mask circuit among the plurality of second factors occur, each of the plurality of processing circuits In addition, a priority circuit predefining a priority level at which two or more interrupt processing corresponding to the two or more factors should be performed, and executes the interrupt processing for each of the plurality of processing circuits. An interrupt signal indicating that the processing is to be performed, a vector signal indicating a position where the content of the interrupt processing having the highest priority for the plurality of processing circuits is defined, and a selection signal indicating that the processing circuit is selected And outputting the priority circuit.

  According to the second microcomputer of the present invention described above, the priority circuit refers to the contents defined in each of the mask circuit, the processing circuit selection register circuit, and the priority circuit. By outputting the interrupt signal, the vector signal, and the selection signal for each of the plurality of processing circuits, each of the plurality of processing circuits has the highest priority for the processing circuit, as in the prior art. On the other hand, unlike conventional systems, two conventional interrupt controllers are not necessary, and as a result, low cost and low power consumption can be achieved.

  Further, since the plurality of factors, more precisely, to which of the plurality of processing circuits a plurality of interrupt processes corresponding to the plurality of factors can be assigned by the processing circuit selection register circuit, It is possible to easily balance the load of interrupt processing among a plurality of processing circuits.

  Embodiments of a microcomputer according to the present invention will be described with reference to the drawings.

<Configuration and operation>
FIG. 1 shows a configuration of a microcomputer according to the embodiment. As shown in FIG. 1, the microcomputer M <b> 10 of the embodiment includes an interrupt controller 10, a first processing circuit (CPU) A, a second processing circuit (CPU) B, and a first storage circuit 30. And a second memory circuit 40.

  The interrupt controller 10 includes a factor register circuit 11, a CPU selection register circuit 12, a mask circuit 13, and a priority circuit 14.

  As shown in FIG. 2A, the factor register 11 circuit includes a plurality of factor registers 11 (1) to 11 (n), and a plurality of factors F1 to Fn (for example, button depression, temperature detection). Etc. (none shown) is received as input of factor generation signals S (F1) to S (Fn) indicating that they have occurred.

  In the following, it is assumed that basically four factors F1, F2, F3, and Fn have occurred in order to facilitate explanation and understanding.

  In the factor register circuit 11, for example, when a factor generation signal S (F1) indicating that the factor F1 has occurred is input, the factor register 11 (1) is triggered by the input of the factor generation signal S (F1). , “Present” (unresolved) is set (set), and similarly, the factor generation signals S (F2), S (F3), and S (F4) indicating that the factor F2, the factor F3, and the factor F4 have occurred. Is input, the factor registers 11 (2), 11 (3), and 11 (n) are set to “present”.

  The factor register 11 (1) set to “present” causes the first processing circuit after the interrupt processing corresponding to the factor F1 is executed by the first processing circuit A as will be described later. A is set (cleared) to “none” (resolved). Similarly, the factor registers 11 (2), 11 (3), and 11 (n) set to “present” also perform interrupt processing corresponding to the factors F2, F3, and Fn, as will be described later. After being executed by the second processing circuit B, the second processing circuit B, and the first processing circuit A, respectively, by the second processing circuit B, the second processing circuit B, and the first processing circuit A, Each is set (cleared) to “none” (resolved).

  The CPU selection register circuit 12 is a “processing selection register circuit”, and as shown in FIG. 2B, the factors F1 to Fn and the CPU to process the factors F1 to Fn, more precisely the factors The correspondence relationship with the CPU that should execute the interrupt processing corresponding to F1 to Fn is defined in advance. For example, the CPU selection register circuit 12 performs an interrupt process corresponding to the factors F1, F2, F3, and Fn as a first processing circuit A, a second processing circuit B, a second processing circuit B, and a first processing. It defines that each circuit A should execute.

  As shown in FIG. 2C, the mask circuit 13 predefines whether to permit / inhibit the factors F1 to Fn, more specifically, whether to permit or prohibit the interrupt processing corresponding to the factors F1 to Fn. ing. For example, the mask circuit 13 defines that the interrupt processing corresponding to the four factors F1, F2, F3, and Fn is “permitted”, “permitted”, “permitted”, and “prohibited”, respectively.

  As shown in FIG. 2 (D1), the priority circuit 14 defines the priority (priority) of the factors to be processed by the first processing circuit A among the factors F1 to Fn. In other words, The priority for interrupt processing to be performed by the first processing circuit A is defined. The priority circuit 14 includes, for example, the first processing circuit A that causes the factors F1, F4, F6,. . . , Fn is specified to be executed. The priority circuit 14 further defines that the priority of interrupt processing corresponding to the factors F1, F4, and F6 is “high”, “medium”, and “low”, respectively, while the mask circuit 13 stipulates that the priority of the interrupt processing corresponding to the factor Fn “prohibited” is “−” (indefinite (= actual prohibition)).

  As shown in FIG. 2 (D2), the priority circuit 14 defines the priority for the factor to be processed by the second processing circuit B among the factors F1 to Fn. The priority for interrupt processing to be performed by the processing circuit B is defined. The priority circuit 14 includes, for example, the second processing circuit B that causes factors F2, F3, F5,. . . , F (n-1) is specified to be interrupted. The priority circuit 14 further defines that the priority of interrupt processing corresponding to the factors F2, F3, and Fn is “high”, “extremely high”, and “low”, respectively, The fact that the priority of the interrupt process corresponding to the factor F5 (not shown in FIG. 2C) that is “prohibited” by the circuit 13 is “−” (indefinite (= actual prohibition)). It prescribes.

  Returning to FIG. 1, the priority circuit 14 includes an interrupt signal Sint1 indicating that the first processing circuit A needs to perform some kind of interrupt processing, and the first processing circuit A. A vector signal Svct1 indicating the start address of the area in which the contents of the interrupt processing to be executed by A and a selection signal Ssel1 indicating that the first processing circuit A is selected are output.

  Similarly, the priority circuit 14 causes the second processing circuit B to receive an interrupt signal Sint2 indicating that the second processing circuit B needs to perform some interrupt processing, and the second processing circuit B. Outputs a vector signal Svct2 indicating the start address of the area in which the contents of the interrupt processing to be executed are stored, and a selection signal Ssel2 indicating that the second processing circuit B is selected.

  More specifically, for example, when the factors F1, F2, F3, and Fn occur, the mask circuit 13 receives the interrupt processing for the factors F1, F2, and F3 among the factors F1, F2, F3, and Fn. On the other hand, acceptance of the interrupt processing for the factor Fn is “prohibited”. Next, the priority circuit 14 determines from the specified contents of the CPU selection register circuit 12 (illustrated in FIG. 2B) that “the interrupt processing of the factor F1 corresponds to the first processing circuit A”, and , The fact that the interrupt processing of factor F2 and the interrupt processing of factor F3 correspond to the second processing circuit B is acquired. Furthermore, the priority circuit 14 knows that “the factor F3 has a higher priority than the factor F2” from the specified contents of the priority circuit 14 itself (shown in FIG. 2 (D2)).

  As a result, the priority circuit 14 finally executes “interrupt processing of the factor F1 to the first processing circuit A” and “executes interrupt processing of the factor F3 to the second processing circuit B. After that, it is determined that the interrupt processing of the factor F2 is to be executed by the second processing circuit B ”. As a result of the determination, the priority circuit 14 stores the first processing circuit A in which the interrupt signal Sint1 indicating that the interrupt processing of the factor F1 has occurred and the contents of the interrupt processing of the factor F1 are stored. A vector signal Svct1 indicating the start address “1001” of the area on the storage circuit 30 and a selection signal Ssel1 indicating that the first processing circuit A is selected are output. On the other hand, the priority circuit 14 stores, in the second processing circuit B, the interrupt signal Sint2 indicating that the interrupt processing of the factor F3 has occurred, and the contents of the interrupt processing of the factor F3 are stored in the second memory. The vector signal Svct2 indicating the start address “2003” of the area on the circuit 40 and the selection signal Ssel2 indicating that the second processing circuit B is selected are output.

  The first processing circuit A and the second processing circuit B basically store the interrupt processing corresponding to the factors F1 to Fn in the first storage circuit 30 and the second storage circuit 40. It executes based on the contents of the interrupt process. More specifically, for example, when the first processing circuit A receives the interrupt signal Sint1, the vector signal Svct1, and the selection signal Ssel1 as described above from the priority circuit 14, the address “of the first storage circuit 30” Jump to the jump destination address “3100” stored in “1001” and start executing the interrupt processing for the factor F1 stored after the address “3100”. When completing the interrupt processing of the factor F1, the first processing circuit A sets (clears) the factor register 11 (1) in the factor register circuit 11 from “present” (unresolved) to “none” (resolved). )

  Similarly, when the second processing circuit B receives the interrupt signal Sint2, the vector signal Svct2, and the selection signal Ssel2 from the priority circuit 14, the address “2003” of the second storage circuit 40 is received. Is jumped to the jump destination address “5300”, and the execution of the interrupt processing for the factor F3 stored after the address “5300” is started. When the interrupt processing for the factor F3 is completed, the second processing circuit B sets the factor register 11 (3) in the factor register circuit 11 from “present” to “none”.

  When the factor register 11 (3) is set to “none”, the priority circuit 14 causes the second processing circuit B to cause the second processing circuit B to execute the factor F2 interrupt processing. An interrupt signal Sint2 indicating that the interrupt processing has occurred, a vector signal Svct2 indicating the start address “2002” of the area on the second memory circuit 40 in which the contents of the interrupt processing of the factor F2 are stored, and When the second processing circuit B receives the three signals Sint2, Svct2, and Ssel2 and outputs the selection signal Ssel2 indicating that the second processing circuit B has been selected, the factor F2 The execution of the interrupt process is started.

"effect"
As described above, in the microcomputer M10 of the embodiment, the priority circuit 14 outputs the interrupt signal Sint1, the vector signal Svct1, and the selection signal Ssel1 to the first processing circuit A, so that the first processing circuit A Then, the interrupt processing of the factor F1 is executed, and at the same time, the interrupt signal Sint2, the vector signal Svct2, and the selection signal Ssel2 are output to the second processing circuit B. Since the interrupt processing is executed, the first processing circuit A and the second processing circuit B can execute the interrupt processing separately as in the conventional case. In addition, unlike the conventional case, two interrupts are performed. Since the controllers 100 and 200 are not required, the circuit scale is reduced, and as a result, low cost and low power consumption can be realized. It made.

  Further, it is changed by changing only the setting contents of the CPU selection register circuit 12 which of the first processing circuit A and the second processing circuit B should execute the interrupt processing corresponding to the factors F1 to Fn. Therefore, unlike the conventional microcomputer M100, the processing load can be easily balanced between the first processing circuit A and the second processing circuit B.

<Modification>
As shown in FIG. 3, the interrupt controller 10 of the modified example has a factor register circuit 11 and a CPU selection register circuit 12 in the same manner as the interrupt controller 10 of the above-described embodiment. Unlike the interrupt controller 10, the mask circuit 13 and the priority circuit 14 are not provided. In the microcomputer M10 of the modification, when the factor generation signals S (F1) and S (F2) indicating that the factors F1 and F2 are generated are input, the factor registers 11 (1) and 11 ( 2) is set to “Yes” (unresolved).

  After setting the factor registers 11 (1) and 11 (2), the CPU selection register circuit 12 refers to the correspondence shown in FIG. It is learned that the processing circuit A should execute, and that the second processing circuit B should execute the interrupt processing corresponding to the factor F2.

  After the knowledge, the CPU selection register circuit 12 assigns to the first processing circuit A that should execute the interrupt process corresponding to the factor F1 the interrupt that indicates that the interrupt process should be executed, as in the embodiment. An interrupt signal Sint1, a vector signal Svct1 indicating the area where the contents of the interrupt processing corresponding to the factor F1 are stored, and a selection signal Ssel1 indicating that the first processing circuit A is selected, and In the second processing circuit B that should execute the interrupt process corresponding to the factor F2, the interrupt signal Sint2 indicating that the interrupt process should be executed and the contents of the interrupt process corresponding to the factor F2 are stored. A vector signal Svct2 indicating the area in which the current signal is present and a selection signal Ssel2 indicating that the second processing circuit B has been selected are output. Hereinafter, the same effect as that of the embodiment can be obtained by performing the same operation as that of the embodiment.

The figure which shows the structure of the microcomputer of an Example. The figure which shows the prescription | regulation content of the factor register circuit, CPU selection register circuit, mask circuit, and priority circuit of an Example. The figure which shows the structure of the microcomputer of a modification. The figure which shows the structure of the conventional microcomputer.

Explanation of symbols

  M10: Microcomputer, 10: Interrupt controller, A: First processing circuit, B: Second processing circuit, 30: First storage circuit, 40: Second storage circuit, 11: Factor register circuit, 12 ... CPU selection register circuit, 13 ... mask circuit, 14 ... priority circuit.

Claims (2)

A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
A processing circuit selection that defines a plurality of relations, each of which is a correspondence relation between one of the plurality of factors and one of the plurality of processing circuits to perform an interrupt process corresponding to the one factor An interrupt indicating that an interrupt process should be executed for each of the plurality of processing circuits when at least two or more of the first plurality of factors occur in the register circuit A signal, a vector signal indicating a position where the contents of the interrupt processing to be executed by the plurality of processing circuits among the two or more interrupt processing corresponding to the two or more factors, and the processing circuit And a processing circuit selection register circuit for outputting a selection signal indicating that is selected. A plurality of processing circuits in which each interrupt processing is to perform a plurality of interrupt processing due to one of the first plurality of factors;
A factor register circuit indicating whether each of the first plurality of factors has been solved or not;
A processing circuit selection that defines a plurality of relations, each of which is a correspondence relation between one of the plurality of factors and one of the plurality of processing circuits to perform an interrupt process corresponding to the one factor A register circuit;
A mask circuit for permitting acceptance of a second plurality of factors of the first plurality of factors and prohibiting acceptance of other remaining factors;
When at least two or more factors corresponding to the second plurality of factors accepted by the mask circuit among the plurality of second factors occur, each of the plurality of processing circuits And a priority circuit preliminarily defining a priority level at which two or more interrupt processing corresponding to the two or more factors should be performed, and executing the interrupt processing for each of the plurality of processing circuits. An interrupt signal indicating that the processing is to be performed, a vector signal indicating a position where the content of the interrupt processing having the highest priority for the plurality of processing circuits is defined, and a selection signal indicating that the processing circuit is selected And a priority circuit for outputting the microcomputer.

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