JP4906734B2 - ビデオ処理 - Google Patents

ビデオ処理 Download PDF

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Publication number
JP4906734B2
JP4906734B2 JP2007541436A JP2007541436A JP4906734B2 JP 4906734 B2 JP4906734 B2 JP 4906734B2 JP 2007541436 A JP2007541436 A JP 2007541436A JP 2007541436 A JP2007541436 A JP 2007541436A JP 4906734 B2 JP4906734 B2 JP 4906734B2
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JP
Japan
Prior art keywords
execution unit
vector
scalar
stream
data
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Expired - Lifetime
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JP2007541436A
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English (en)
Japanese (ja)
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JP2008521097A (ja
Inventor
シリッシュ ガドレ，
アシッシュ カランディカー，
スティーヴン リュウ，
クリストファー， ティー． チェン，
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エヌヴィディア コーポレイション
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Priority claimed from US11/267,638 external-priority patent/US8493396B2/en
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Publication of JP2008521097A publication Critical patent/JP2008521097A/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/436—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation using parallelised computational arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • General Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Advance Control (AREA)
  • Image Processing (AREA)
  • Image Analysis (AREA)
JP2007541436A 2004-11-15 2005-11-14 ビデオ処理 Expired - Lifetime JP4906734B2 (ja)

Applications Claiming Priority (11)

Application Number Priority Date Filing Date Title
US62841404P 2004-11-15 2004-11-15
US60/628,414 2004-11-15
US11/267,599 2005-11-04
US11/267,638 2005-11-04
US11/267,638 US8493396B2 (en) 2004-11-15 2005-11-04 Multidimensional datapath processing in a video processor
US11/267,875 2005-11-04
US11/267,599 US8416251B2 (en) 2004-11-15 2005-11-04 Stream processing in a video processor
US11/267,700 2005-11-04
US11/267,700 US8698817B2 (en) 2004-11-15 2005-11-04 Video processor having scalar and vector components
US11/267,875 US8687008B2 (en) 2004-11-15 2005-11-04 Latency tolerant system for executing video processing operations
PCT/US2005/041329 WO2006055546A2 (en) 2004-11-15 2005-11-14 A video processor having a scalar component controlling a vector component to implement video processing

Publications (2)

Publication Number Publication Date
JP2008521097A JP2008521097A (ja) 2008-06-19
JP4906734B2 true JP4906734B2 (ja) 2012-03-28

Family

ID=36407688

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007541436A Expired - Lifetime JP4906734B2 (ja) 2004-11-15 2005-11-14 ビデオ処理

Country Status (5)

Country Link
EP (1) EP1812928A4 (de)
JP (1) JP4906734B2 (de)
KR (5) KR101002485B1 (de)
CA (1) CA2585157A1 (de)
WO (1) WO2006055546A2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0519597D0 (en) * 2005-09-26 2005-11-02 Imagination Tech Ltd Scalable multi-threaded media processing architecture
WO2015035336A1 (en) 2013-09-06 2015-03-12 Futurewei Technologies, Inc. Method and apparatus for asynchronous processor pipeline and bypass passing
US10275370B2 (en) 2015-01-05 2019-04-30 Google Llc Operating system dongle
KR102067714B1 (ko) * 2016-11-17 2020-01-17 주식회사 엘지화학 배터리 모듈 및 이를 포함하는 배터리 팩
US20210141697A1 (en) * 2018-03-06 2021-05-13 DinoplusAI Holdings Limited Mission-Critical AI Processor with Multi-Layer Fault Tolerance Support
KR102067128B1 (ko) * 2018-06-07 2020-01-16 코츠테크놀로지주식회사 헬스 모니터링 장치 및 이를 포함하는 대화면 시현기
WO2022220835A1 (en) * 2021-04-15 2022-10-20 Zeku, Inc. Shared register for vector register file and scalar register file

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3614740A (en) 1970-03-23 1971-10-19 Digital Equipment Corp Data processing system with circuits for transferring between operating routines, interruption routines and subroutines
US4101960A (en) * 1977-03-29 1978-07-18 Burroughs Corporation Scientific processor
US4541046A (en) * 1981-03-25 1985-09-10 Hitachi, Ltd. Data processing system including scalar data processor and vector data processor
US4985848A (en) * 1987-09-14 1991-01-15 Visual Information Technologies, Inc. High speed image processing system using separate data processor and address generator
US4965716A (en) * 1988-03-11 1990-10-23 International Business Machines Corporation Fast access priority queue for managing multiple messages at a communications node or managing multiple programs in a multiprogrammed data processor
US4958303A (en) * 1988-05-12 1990-09-18 Digital Equipment Corporation Apparatus for exchanging pixel data among pixel processors
US5210834A (en) * 1988-06-01 1993-05-11 Digital Equipment Corporation High speed transfer of instructions from a master to a slave processor
US5040109A (en) * 1988-07-20 1991-08-13 Digital Equipment Corporation Efficient protocol for communicating between asychronous devices
JPH0795766B2 (ja) * 1989-06-30 1995-10-11 株式会社日立製作所 デジタル・データ通信装置及びそれに使用するデータ通信アダプタ
US5179530A (en) * 1989-11-03 1993-01-12 Zoran Corporation Architecture for integrated concurrent vector signal processor
US5418973A (en) * 1992-06-22 1995-05-23 Digital Equipment Corporation Digital computer system with cache controller coordinating both vector and scalar operations
EP0607988B1 (de) * 1993-01-22 1999-10-13 Matsushita Electric Industrial Co., Ltd. Programmgesteuertes Prozessor
US5574944A (en) * 1993-12-15 1996-11-12 Convex Computer Corporation System for accessing distributed memory by breaking each accepted access request into series of instructions by using sets of parameters defined as logical channel context
JPH0877347A (ja) * 1994-03-08 1996-03-22 Texas Instr Inc <Ti> 画像／グラフィックス処理用のデータ処理装置およびその操作方法
JPH08153032A (ja) * 1994-11-29 1996-06-11 Matsushita Electric Ind Co Ltd ネットワーク経由データ先読みバッファ方法
JP3619565B2 (ja) * 1995-04-26 2005-02-09 株式会社ルネサステクノロジ データ処理装置、及びそれを用いたシステム
US6331856B1 (en) * 1995-11-22 2001-12-18 Nintendo Co., Ltd. Video game system with coprocessor providing high speed efficient 3D graphics and digital audio signal processing
KR100262453B1 (ko) * 1996-08-19 2000-08-01 윤종용 비디오데이터처리방법및장치
US6058465A (en) * 1996-08-19 2000-05-02 Nguyen; Le Trong Single-instruction-multiple-data processing in a multimedia signal processor
US5812147A (en) * 1996-09-20 1998-09-22 Silicon Graphics, Inc. Instruction methods for performing data formatting while moving data between memory and a vector register file
US5893066A (en) * 1996-10-15 1999-04-06 Samsung Electronics Co. Ltd. Fast requantization apparatus and method for MPEG audio decoding
US5949410A (en) * 1996-10-18 1999-09-07 Samsung Electronics Company, Ltd. Apparatus and method for synchronizing audio and video frames in an MPEG presentation system
JP3983394B2 (ja) * 1998-11-09 2007-09-26 株式会社ルネサステクノロジ 幾何学処理プロセッサ
US6496902B1 (en) * 1998-12-31 2002-12-17 Cray Inc. Vector and scalar data cache for a vector multiprocessor
JP3639464B2 (ja) * 1999-07-05 2005-04-20 株式会社ルネサステクノロジ 情報処理システム
US7093104B2 (en) * 2001-03-22 2006-08-15 Sony Computer Entertainment Inc. Processing modules for computer architecture for broadband networks
JP3840966B2 (ja) * 2001-12-12 2006-11-01 ソニー株式会社 画像処理装置およびその方法
US7305540B1 (en) * 2001-12-31 2007-12-04 Apple Inc. Method and apparatus for data processing
US6785772B2 (en) * 2002-04-26 2004-08-31 Freescale Semiconductor, Inc. Data prefetching apparatus in a data processing system and method therefor
US6957317B2 (en) * 2002-10-10 2005-10-18 Intel Corporation Apparatus and method for facilitating memory data access with generic read/write patterns
US20060064517A1 (en) * 2004-09-23 2006-03-23 Honeywell International Inc. Event-driven DMA controller

Also Published As

Publication number Publication date
KR100880982B1 (ko) 2009-02-03
KR101084806B1 (ko) 2011-11-21
WO2006055546A2 (en) 2006-05-26
KR101030174B1 (ko) 2011-04-18
KR20080080419A (ko) 2008-09-03
WO2006055546A9 (en) 2007-09-27
CA2585157A1 (en) 2006-05-26
KR20070063580A (ko) 2007-06-19
KR20100093141A (ko) 2010-08-24
EP1812928A2 (de) 2007-08-01
KR100917067B1 (ko) 2009-09-15
KR20090020715A (ko) 2009-02-26
WO2006055546A3 (en) 2008-06-19
KR101002485B1 (ko) 2010-12-17
JP2008521097A (ja) 2008-06-19
KR20110011758A (ko) 2011-02-08
EP1812928A4 (de) 2010-03-31

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