JP4899992B2 - Front-end integrated circuit - Google Patents

Description

The present invention relates to a front-end integrated circuit .

In communication equipment such as a radio receiver and a television receiver, an AGC circuit is provided at a high frequency stage or an intermediate frequency stage, and the gain is controlled so that the level of the intermediate frequency signal is constant. And as a method or circuit for controlling the gain,
(1) Connect the input resistor and negative feedback resistor to the operational amplifier, and change the gain by switching these resistors.
(2) In the above item (1), the resistor is the on-resistance of the transistor.
(3) Connect the drain and source of the FET between the emitters of the transistors constituting the differential amplifier, and control the drain-source resistance to control the negative feedback amount and change the gain.
and so on.

For example, there are the following prior art documents.
JP-A-6-291572 JP 2004-304775 A

  However, switching between the input resistor and the negative feedback resistor as in (1) and (2) can reduce distortion, but the gain change becomes stepped and the gain changes. To increase the resolution of the change, a large number of input resistors and negative feedback resistors are required. In addition, even in such a case, since the change of the gain is stepped, when applied to the AGC circuit, the AGC characteristic is not smooth and the reception quality is deteriorated.

  On the other hand, in the case of the item (3), the gain can be changed continuously, so that the reception quality does not deteriorate as in the cases of the items (1) and (2). However, as in (3), when using the drain-source resistance of the FET, the circuit distortion characteristics are determined by the linearity of the FET drain-source resistance, but when the negative feedback amount is large, A signal having an amplitude close to the input signal is applied to the FET, and the drain-source resistance changes. For this reason, when the input signal is large, the distortion becomes large and the practicality is poor. In the case of item (3), the relationship between the gain control voltage and the gain does not have a logarithmic characteristic (dB linear), and some nonlinear circuit is required for the gain control voltage.

  Further, when an FET is used to control the gain of the AGC circuit, when the threshold voltage (pinch-off voltage) VTH of the FET varies, this is equivalent to the variation of the DC component of the AGC voltage. The characteristics vary, for example, as shown in FIG. That is, the solid line VTYP is a characteristic when the threshold voltage VTH of the FET is a representative value (reference value), the broken line VTH + is a characteristic when the threshold voltage VTH is higher than the representative value VTYP, and the broken line VTH− is a threshold. This is a characteristic when the gate voltage VTH is lower than the representative value VTYP.

  If the gain characteristics vary in this way, the AGC circuit's transient response characteristics vary greatly due to variations in the loop gain of the AGC circuit and differences in the gain control range with respect to the AGC voltage, resulting in increased distortion and stable level. The nature will be impaired.

  For this reason, when the high frequency stage and the intermediate frequency stage are constituted by individual parts, it is necessary to select the characteristics of the FET, which increases the man-hour and the cost. In addition, when an IC is used, the relative variation of FETs can be suppressed, but the variation of absolute values is large, and the performance of the high frequency stage and the intermediate frequency stage varies.

  The present invention is intended to solve the above problems.

A front-end integrated circuit according to the present invention is a front-end integrated circuit having a variable gain amplifier that amplifies a high-frequency signal or an intermediate-frequency signal in a front-end circuit that converts a received signal in a wide band into an intermediate-frequency signal. An input terminal to which a variable control voltage for controlling the gain of the gain amplifier is input; a control voltage forming circuit that converts the variable control voltage input to the input terminal into a control voltage and outputs the control voltage to the variable gain amplifier; The variable gain amplifier is connected in multiple stages in series with an operational amplifier for amplifier and an inverting input terminal of the operational amplifier for amplifier, and a plurality of high frequency signals or intermediate frequency signals are input from a front stage of the front end circuit. Connected between (m + 1) series resistors and the output terminal of the operational amplifier for amplifier and the inverting input terminal. A plurality of m drains and sources connected between the connection middle point of each of the negative feedback resistance elements and the two series resistors adjacent to each other in the multistage connection and the inverting input terminal of the amplifier operational amplifier Amplifying the high-frequency signal or the intermediate-frequency signal and outputting the amplified signal from the output terminal of the operational amplifier for amplifier, and the control voltage forming circuit is configured to output each of the plurality of m amplifier FETs. A plurality of m voltage conversion circuits that individually output control voltages to the gate, and a power supply terminal, and each of the voltage conversion circuits is for conversion in which the variable control voltage is input to a non-inverting input terminal An operational amplifier, a first FET whose gate is connected to an output terminal of the conversion operational amplifier to form a voltage follower circuit, a source of the first FET, and the conversion operational amplifier A voltage source connected to the inverting input terminal through a first resistor; and a second resistor connected between the drain of the first FET and the power supply terminal. The drain of the first FET and the second resistor The voltage at the connection point with the two resistors is output as a control voltage obtained by converting the variable control voltage to the gate of the corresponding amplifier FET, and the voltage sources of the plurality of m voltage conversion circuits are In a multi-stage connection, the voltage of the voltage source corresponding to the output series resistor is higher than the voltage of the voltage source corresponding to the input side series resistor. When increasing from the value of 1 to the second value, due to the voltage difference of the voltage sources of the plurality of m voltage conversion circuits, the variable control voltage becomes the voltage of the corresponding voltage source, Off in order from the input side From the off-state, from the off-state to the on-state in order from the input side, and finally all the on-state. Until the state is reached, the drain-source resistance gradually decreases, and the drain-source resistances of the plurality of m amplifier FETs continuously change from on to off independently of each other.

  According to the present invention, the gain can be continuously controlled over a wide input range. Moreover, even if the threshold voltage of the FET varies, the intended gain characteristic can be obtained, and it is more effective particularly when the circuit is integrated.

  Furthermore, when applied to an AGC circuit, variations in AGC transient response characteristics over a wide input range can be suppressed, and an increase in distortion and level instability can be suppressed.

[1-1] Example of Front-End Circuit FIG. 1 shows an example of a front-end circuit that can receive television broadcasts in various countries regardless of the broadcast format. In this example, the frequency used in the television broadcasting of each country is
(A) 46 to 147 MHz (VL band)
(B) 147-401MHz (VH band)
(C) 401-887MHz (U band)
In this case, the frequency can be changed corresponding to the target channel in each reception band. Note that “MOS-FET” is simply referred to as “FET”.

  That is, in FIG. 1, a portion 10 surrounded by a chain line indicates the front end circuit, which is integrated into a one-chip IC. The IC (front end circuit) 10 has terminal pins T11 to T19 for external connection.

  Then, the broadcast wave signal of the television broadcast is received by the antenna ANT, and the received signal is selectively supplied from the terminal pin T11 to the antenna tuning circuits 12A to 12C through the switch circuit 11. In this case, the antenna tuning circuits 12A to 12C respectively correspond to the reception bands of the above items (A) to (C), and a plurality of tuning capacitors are selectively connected according to digital data to set the tuning frequency. As a result, it is configured to tune to the received signal of the target frequency (channel).

  The received signals from the tuning circuits 12A to 12C are supplied to the switch circuit 15 through the high frequency amplifiers 13A to 13C and further through the interstage tuning circuits 14A to 14C. In this case, the tuning circuits 14A to 14C are configured similarly to the tuning circuits 12A to 12C, but the tuning circuit 14A is a retune circuit. Further, the tuning capacitors of the tuning circuits 12A to 14C are built in the IC 10, and the tuning coil is externally attached to the IC 10. Further, the switch circuit 15 is switched in conjunction with the switch circuit 11, and therefore, the received signal SRX of the target reception band is extracted from the switch circuit 15. The extracted reception signal SRX is supplied to the mixer circuits 12I and 12Q.

  In addition, a signal that becomes a local oscillation signal is formed by the PLL 30. That is, the oscillation signal of the VCO 31 is supplied to the variable frequency dividing circuit 32 and divided into signals having a frequency of 1 / N (N is a positive integer), and this frequency divided signal is supplied to the phase comparison circuit 33. Further, a clock of a reference frequency (frequency is about 1 to 2 MHz) is supplied to the signal forming circuit 34 from the outside through the terminal pin T15 and is divided into a signal of a predetermined frequency f34, and this divided signal is supplied to the phase comparison circuit 33. Supplied as a reference signal.

  Then, the comparison output of the phase comparison circuit 33 is supplied to the loop filter 35, and a DC voltage whose level changes in accordance with the phase difference between the output signal of the variable frequency dividing circuit 32 and the output signal of the forming circuit 34 is extracted. This DC voltage is supplied to the VCO 31 as a control voltage of the oscillation frequency f31. A smoothing capacitor C11 is externally attached to the filter 35 through a terminal pin T16.

Therefore, the oscillation frequency f31 of the VCO 31 is
f31 = N · f34 (11)
Therefore, if the frequency division ratio N is controlled by a system control microcomputer (not shown), the oscillation frequency f31 of the VCO 31 can be changed. For example, the frequency f31 is 1.8 to 3.6 GHz corresponding to the reception band and the reception frequency (reception channel).

  Then, the oscillation signal of the VCO 31 is supplied to the variable frequency dividing circuit 36 and is divided to a frequency of 1 / M (for example, M = 2, 4, 8, 16, 32). 37 is divided into frequency-divided signals SLOI and SLOQ having a frequency of 1/2 and orthogonal to each other, and these signals SLOI and SLOQ are supplied to the mixer circuits 21I and 21Q as local oscillation signals.

here,
fLO: If the frequency of the local oscillation signals SLOI, SLOQ,
fLO = f31 / (2M)
= N · f34 / (2M)
= F34 · N / (2M) (12)
It becomes. Therefore, by changing the frequency dividing ratios M and N, the local oscillation frequency fLO can be changed over a wide range at a predetermined frequency step.

Also,
SRX: Received signal desired to be received SUD: Image jamming signal
SRX = ERX ・ sinωRXt
ERX: Amplitude of received signal SRX
ωRX = 2πfRX
fRX: Center frequency of received signal SRX SUD = EUD · sinωUDt
EUD: Amplitude of image disturbance signal SUD
ωUD = 2πfUD
fUD: The center frequency of the image disturbing signal SUD.

Further, regarding local oscillation signals SLOI and SLOQ,
SLOI ＝ ELO ・ sinωLOt
SLOQ ＝ ELO ・ cosωLOt
ELO: Amplitude of signals SLOI and SLOQ
ωLO = 2πfLO
And

However, at this time
ωIF = 2πfIF
fIF: intermediate frequency. For example, 4 to 5.5 MHz (change according to the broadcasting system)
Then, in the case of the upper heterodyne method,
fRX = fLO-fIF
fUD = fLO + fIF
It is.

Therefore, the following signals SIFI and SIQQ are output from the mixer circuits 21I and 21Q. That is,
SIFI = (SRX + SUD) × SLOI
= ERX · sinωRXt × ELO · sinωLOt
+ EUD ・ sinωUDt × ELO ・ sinωLOt
= Α {cos (ωRX−ωLO) t−cos (ωRX + ωLO) t}
+ Β {cos (ωUD−ωLO) t−cos (ωUD + ωLO) t}
SIFQ = (SRX + SUD) × SLOQ
= ERX · sinωRXt × ELO · cosωLOt
+ EUD ・ sinωUDt × ELO ・ cosωLOt
= Α {sin (ωRX + ωLO) t + sin (ωRX−ωLO) t}
+ Β {sin (ωUD + ωLO) t + sin (ωUD−ωLO) t}
α = ERX ・ ELO / 2
β = EUD ・ ELO / 2
The signals SIFI and SIFQ are extracted.

Then, these signals SIFI and SIFQ are supplied to the low-pass filter 22 which is wider than the occupied bandwidth (for example, 6 to 8 MHz) of the video intermediate frequency signal and the audio intermediate frequency signal. Signal components (and local oscillation signals SLOI and SLOQ) of (ωRX + ωLO) and (ωUD + ωLO) are removed, and the low-pass filter 22
SIFI = α · cos (ωRX−ωLO) t + β · cos (ωUD−ωLO) t
= Α · cosωIFt + β · cosωIFt (13)
SIFQ = α · sin (ωRX−ωLO) t + β · sin (ωUD−ωLO) t
= -Α ・ sinωIFt + β ・ sinωIFt (14)
Is taken out.

These signals SIFI and SIFQ are supplied to a complex bandpass filter (polyphase bandpass filter) 24 through an amplitude phase correction circuit 23 described later. This complex bandpass filter 24 is
(a) It has a frequency characteristic of a band pass filter.
(b) A 90 ° phase difference is given between the signal SIFI and the signal SIFX.
(c) On the frequency axis, it has two bandpass characteristics with a center frequency of a frequency f0 and a frequency -f0 that are symmetrical with respect to the zero frequency, and this can be selected according to the relative phase of the input signal. it can.
It has the following characteristics.

Therefore, in the complex band-pass filter 24, the signal SIFQ is delayed by 90 ° with respect to the signal SIFI by the above items (b) and (c).
SIFI = α ・ cosωIFt + β ・ cosωIFt (15)
SIFQ = -α · sin (ωIFt-90 °) + β · sin (ωIFt-90 °)
= Α ・ cosωIFt−β ・ cocωIFt (16)
It is said. That is, between the signal SIFI and the signal SIFQ, the signal component α · cosωIFt is in phase with each other, and the signal component β · cocωIFt is in phase with each other.

  Then, the signals SIFI and SIFQ are supplied to the level correction amplifier 25, the signal SIFI and the signal SIFQ are added, and the following signal SIF is extracted from the level correction amplifier 25.

That is,
SIF = SIFI + SIFQ
= 2α ・ cosωIFt
= ERX / ELO / cosωIFt (17)
Is taken out.

  This extracted signal SIF is nothing but an intermediate frequency signal when the signal SRX is received by the upper heterodyne system. The intermediate frequency signal SIF does not include the image disturbance signal SUD. The amplitude / phase correction circuit 23 is for correcting the amplitude and phase of the signals SIFI and SIFQ so that the equation (17) is sufficiently established, that is, the image disturbance signal SUD is minimized. is there.

  Further, at this time, in the level correction amplifier 25, even if the levels of the signals SIFI and SIFQ differ depending on the broadcasting system, the signal SIF is not changed so that the AGC characteristics (particularly, the AGC start level) described later do not change. Level is corrected.

  The intermediate frequency signal SIF is output to the terminal pin T12 through the AGC variable gain amplifier 26, and further through the band-pass filter 27 for cutting and aliasing the direct current.

  Therefore, if the division ratios M and N are changed, the target frequency (channel) can be selected according to the equation (12), and the intermediate frequency signal SIF output to the terminal pin T12 corresponds to the broadcasting system. If demodulated, the target broadcast can be viewed.

  Thus, according to the front end circuit 10, it is possible to deal with a wide frequency range of 46 to 887 MHz with a single chip IC. In addition, the front end circuit 10 can be realized with a smaller number of parts without deteriorating the interference characteristics over a wide frequency range. Furthermore, the single front-end circuit 10 can cope with the difference between the broadcasting systems of digital broadcasting and analog broadcasting and the broadcasting system depending on the region in the world.

  In addition, reception interference due to clock signal harmonics or the like is reduced, resulting in an increase in reception sensitivity. Furthermore, since all circuit components can be made on-chip, except for the capacitor C11, the PLL 30 can be a PLL that is resistant to disturbance and has less interference. Moreover, since only the tuning circuits 14A to 14C are connected to the high-frequency amplifiers 13A to 13C, respectively, the load is light and the high-frequency amplifiers 13A to 13C can be reduced in distortion.

[1-1-1] Example of AGC A detailed description will be given later of a method for controlling AGC in the high-frequency amplifiers 13A to 13C and the variable gain amplifier 26 and a method for solving the above-described problems.

  Then, the AGC voltage VAGC is formed in a baseband processing circuit described later, and this AGC voltage VAGC is supplied as a gain control signal to the AGC variable gain amplifier 26 through the terminal pin T14. Accordingly, the AGC of the intermediate frequency stage is thereby performed.

  Further, for example, when the level of the target received signal SRX is too large, or when the interference signal of a large level is mixed in the received signal SRX, the AGC at the intermediate frequency stage cannot cope with it. Therefore, the signals SIFI and SIFQ output from the low-pass filter 22 are supplied to the level detection circuit 41, and whether or not the levels of the signals SIFI and SIFQ before AGC is performed in the AGC variable gain amplifier 26 exceeds a predetermined value. Detected.

  Then, this detection signal and the AGC voltage VAGC at the terminal pin T14 are supplied to the adding circuit 42, and the added output is supplied to the forming circuit 43 to form the delayed AGC voltage VDAGC. This delayed AGC voltage VDAGC is used as the high frequency amplifier. 13A to 13C are supplied as gain control signals, and delay AGC is performed.

  Accordingly, since the optimum AGC operation can be performed from the D / U of the strength of the desired received signal and the strength of many signals that are not desired to be received, it is desired even if digital broadcasting and analog broadcasting or a mixture of them is mixed. Broadcast can be received well.

[1-1-2] Example of test / adjustment voltage The signals SIFI and SIFQ output from the low-pass filter 22 are supplied to the linear detection circuit 44, and detected and smoothed to indicate the levels of the signals SIFI and SIFQ. The DC voltage V44 is output, and this voltage V44 is output to the terminal pin T13.

  The DC voltage V44 output to the terminal pin T13 is used when the front end circuit 10 is tested or adjusted. For example, it can be used when checking the level of an input signal (received signal) over a wide frequency range, that is, unlike an output through a narrow-band intermediate frequency filter, from the antenna terminal pin T11 to the mixer circuits 21I, 21Q. It is possible to directly check the attenuation characteristic of the wide band with respect to the previous signal lines.

  When adjusting the antenna tuning circuits 12A to 12C and the interstage tuning circuits 14A to 14C, the input test signal is applied to the antenna terminal pin T11, and the AGC voltage VAGC supplied to the terminal pin T14 is fixed to a predetermined value. For example, tracking adjustment can be performed from a change in the DC voltage V44. Furthermore, adjustment of each function of the front end circuit 10 and measurement of characteristics can be performed by digital data, automatic adjustment and automatic measurement can be performed, and the results can be stored in the nonvolatile memory 51.

[1-1-3] Constant Voltage Circuit The IC 10 is provided with a constant voltage circuit 53 and is supplied with the power supply voltage + VCC from the terminal pin T17. The constant voltage circuit 53 forms a constant voltage of a predetermined value from the power supply voltage + VCC using the band gap of the PN junction, and the formed constant voltage is supplied to each circuit of the IC 10. The output voltage of the constant voltage circuit 53 can be finely adjusted.

  Therefore, even when each circuit is configured by FETs, the voltage supplied to these circuits can be set higher, and the performance of the FETs can be maximized.

[1-1-4] Initial Setting The center frequency and passband width of the complex bandpass filter 24, the correction amount of the amplitude / phase correction circuit 23, and the gain of the level correction amplifier 25 depend on the broadcast system of the received television broadcast. Since it is necessary to respond, it is variable and can be set from the outside. For example, the complex band pass filter 24 has a variable center frequency of 3.8 to 5.5 MHz and a pass band of 5.7 to 8 MHz.

  Then, the set values of these circuits 23 to 25 are written from the terminal pin T18 to the nonvolatile memory 51 at the time of assembly or factory shipment. Similarly, the tracking data (data for finely adjusting the tuning frequency) of the tuning circuits 12A to 12C and 14A to 14C and the data for finely adjusting the output voltage of the constant voltage circuit 53 are also sent from the terminal pin T18 to the nonvolatile memory 51. Is written to. Therefore, the characteristics of each circuit can be set to be compatible with the broadcast system of the received television broadcast.

If the signals SLOI and SLOQ supplied from the frequency divider 37 to the mixer circuits 21I and 21Q are reversed from the above, the equation (17) is expressed as SIF = SIFI + SIFQ
= -2β ・ cosωIFt
= EUD / ELO / cosωIFt
Therefore, the image disturbance signal SUD is taken out to the terminal pin T13. Therefore, the amplitude / phase correction circuit 23 is adjusted so that the image disturbance signal SUD at this time is minimized, and the adjustment data is written in the nonvolatile memory 51.

[1-1-5] Operation in Use When the receiver using the IC 10 is turned on, the set value of the nonvolatile memory 51 is copied to the buffer memory 52, and the copied set value is stored in the circuit. 12A to 12C, 14A to 14C, 23 to 25, and 53 are supplied as default values.

  When the user selects a channel, data for that purpose is supplied from the microcomputer for system control (not shown) to the buffer memory 52 through the terminal pin T19 and temporarily stored, and the stored data is stored in the switch circuit. 11, 15 and tuning circuits 12A to 12C, 14A to 14C, and variable frequency dividing circuits 32 and 36, a reception band including a target channel (frequency) is selected, and in the selected reception band, The target channel is selected.

[1-1-6] Summary According to the front end circuit 10 shown in FIG. 1, as shown in the items (1) to (3), it is possible to receive a television broadcast in a frequency band of 46 to 887 MHz. At that time, the center frequency and passband width of the complex bandpass filter 24 are variable, so that not only domestic terrestrial digital television broadcasts and terrestrial analog television broadcasts but also overseas digital television broadcasts and analog television broadcasts. Can also respond.

[1-2] Example of Baseband Processing Circuit FIG. 2 shows an example of the baseband processing circuit, which processes the intermediate frequency signal SIF output from the front end circuit 10 and outputs a color video signal and an audio signal. To do. That is, in FIG. 11, a portion 60 surrounded by a chain line indicates the baseband processing circuit, which is integrated into a one-chip IC. The IC (baseband processing circuit) 60 has terminal pins T61 to T67 for external connection.

  The intermediate frequency signal SIF output from the terminal pin T12 of the front end circuit 10 is supplied to the A / D converter circuit 61 through the terminal pin T61 and A / D converted into a digital intermediate frequency signal. SIF is supplied to the filter 62 to remove unnecessary frequency components.

  At the time of receiving digital television broadcast, the digital intermediate frequency signal SIF from the filter 62 is supplied to the demodulating circuit 63, and the baseband digital signal is demodulated and taken out. The demodulated output is supplied to the error correcting circuit 64. The error-corrected data stream is output and this data stream is output to the terminal pin T62. Therefore, if the signal at the terminal pin T62 is decoded according to the broadcasting system, the original color video signal and audio signal can be obtained.

  At the time of receiving an analog television broadcast, the digital intermediate frequency signal SIF from the filter 62 is supplied to the video intermediate frequency filter 71 to extract the digital video intermediate frequency signal, and the ghost component is removed from this signal by the ghost removal circuit 72. After that, the digital color video signal is demodulated by being supplied to the demodulation circuit 73. The digital signal is supplied to the D / A converter circuit 74 and D / A converted into an analog color video signal, and this color video signal is output to the terminal pin T63.

  Further, at the time of receiving an analog television broadcast, the digital intermediate frequency signal SIF from the filter 62 is supplied to the audio intermediate frequency filter 81 and the digital audio intermediate frequency signal is taken out, and this signal is supplied to the demodulation circuit 82 and is supplied to the digital audio signal. Is demodulated. This digital audio signal is supplied to the D / A converter circuit 84 and D / A converted into audio signals of the left and right channels, and these audio signals are output to the terminal pins T64 and T65.

  Further, the AGC voltage VAGC is formed in the AGC voltage forming circuit 91, and this AGC voltage VAGC is output to the terminal pin T67 and supplied to the terminal pin T14 of the front end circuit 10, and as described above, the AGC and the high frequency of the intermediate frequency stage. Stage delay AGC is performed.

  Further, a clock having a predetermined frequency is formed in the clock forming circuit 92, and this clock is supplied to each part of the baseband processing circuit 60, and is also transmitted through the terminal pin T66 and further through the terminal pin T15 of the front end circuit 10. It is supplied to the forming circuit 34.

  Therefore, reception interference due to clock harmonics or the like is reduced, resulting in an increase in reception sensitivity.

[2] Variable Gain Amplifier As described above, the variable gain amplifier 26 is required to have low distortion and a gain change characteristic of a logarithmic characteristic (dB linear). Further, in the case of the low intermediate frequency system corresponding to the analog broadcast and the digital broadcast as described in [1], the harmonic gain of the carrier component of the video signal or the audio signal is kept in the pass band as it is in the variable gain amplifier 26. There is a need for lower distortion than a receiving system that uses a normal high intermediate frequency.

  Furthermore, for analog television receiver broadcasting, high S / N is also required at the same time, and it is necessary to reduce distortion even with low noise and high signal output voltage. The same applies to the high-frequency amplifiers 12A to 12C.

  The present invention provides a variable gain amplifier that can satisfy such requirements.

  FIG. 3 shows an example of the variable gain amplifier 26. That is, in this example, one end of the level correction amplifier 25 is connected to the inverting input terminal of the operational amplifier 261 through the series circuit of the resistors R21 to R24, and the other end is connected to the non-inverting input terminal of the operational amplifier 261. A bias voltage EO is supplied to the end and the non-inverting input end.

  Further, between the connection point of the resistor R21 and the resistor R22 and the inverting input terminal of the operational amplifier 261, the drain and the source of the FET (M21) are connected, and the connection point of the resistor R22 and the resistor R23; The drain and source of the FET (M22) are connected between the inverting input terminal of the operational amplifier 261, and the FET is connected between the connection point of the resistor R23 and the resistor R24 and the inverting input terminal of the operational amplifier 261. The drain and source of (M23) are connected.

  Then, in a control voltage forming circuit to be described later, gain control voltages D21 to D23 are formed from the AGC voltage VAGC, and these control voltages D21 to D23 are respectively supplied to the gates of the FETs (M21 to M23) and their backs are also provided. The gate is grounded. The output terminal of the operational amplifier 261 is connected to its inverting input terminal through a negative feedback resistor Rf and to the input terminal of the bandpass filter 27.

According to such a configuration, the FETs (M21 to M23) are on / off controlled in accordance with the levels of the control voltages D21 to D23. When all of the FETs (M21 to M23) are on, the intermediate frequency signal SIF from the level correction amplifier 25 is supplied to the operational amplifier 261 through the resistor R21 (and FET (M21)), so that the variable gain amplifier The gain GV of 26 is
GV = Rf / R21 (21)
It becomes. This is the maximum gain.

However, when the FET (M21) is off and the FETs (M22, M23) are on, the intermediate frequency signal SIF from the level correction amplifier 25 passes through the resistors R21, R22 (and FET (M22)) and the operational amplifier 261. Therefore, the gain GV of the variable gain amplifier 26 is
GV = Rf / (R21 + R22) (22)
Thus, the gain GV decreases.

Further, when the control voltage D21 becomes an intermediate level between the ON level and the OFF level of the FET (M21), the resistance r21 between the drain and source of the FET (M21) is a value corresponding to the control voltage D21. Therefore, the gain GV of the variable gain amplifier 26 at this time is GV = Rf / (R21 + (R22‖r21)) (23)
‖ Indicates a parallel value. Since r21 = 0 when the FET (M21) is on, equation (23) agrees with equation (21). When FET (M21) is off, r21 = ∞, so equation (23) becomes (22 ) Matches the expression. That is, the gain GV continuously changes in the range from the value of the expression (21) to the value of the expression (22) corresponding to the control voltage D21.

At this time, the change ratio (ratio between the maximum gain and the minimum gain) GRTO of the gain GV of the variable gain amplifier 26 with respect to the control voltage D21 is GRTO = (R21 + R22) / R21 from the equations (21) and (22).
It becomes.

Similarly, when FET (M21) is off and FET (M23) is on, when FET (M22) is on,
GV = Rf / (R21 + R22) (22)
When the FET (M22) is off,
GV = Rf / (R21 + R22 + R23) (24)
It becomes.

Therefore, the gain GV continuously changes in the range from the value of the expression (22) to the value of the expression (25) corresponding to the control voltage D22. The change ratio GRTO of the gain GV by the FET (M22) at this time is
GRTO = (R21 + R22 + R23) / (R21 + R22)
It becomes.

When the FETs (M21, M22) are off, when the FET (M23) is on,
GV = Rf / (R21 + R22 + R23) (24)
And when off,
GV = Rf / (R21 + R22 + R23 + R24) (25)
And the change ratio GRTO of the gain GV by the FET (M23) is
GRTO = (R21 + R22 + R23 + R24) / (R21 + R22 + R23)
It becomes.

Therefore, when the change ratio GRTO of the gain GV by one of the FETs (M21 to M23) is 6 dB,
R21 = R22 = R, R23 = 2R, R24 = 4R
R: It may be set to a predetermined resistance value.

  In other words, if it is set as such, 6 dB gain control can be performed by each of the FETs (M21 to M23), and the range of the 6 dB gain control is as shown in equations (21) to (25). Since they do not overlap and are continuous, the gain can be continuously controlled over 18 dB (= 6 dB × 3 stages) as a whole.

  Generally, by setting the resistance ratio of the resistors R21 to R24, the control range of the gain covered by one stage (one set of FET and resistor) can be arbitrarily set, and it corresponds to the number of stages. The gain can be continuously controlled with respect to the range. At this time, the gain control range can be expanded by increasing the number of stages.

In this case, if the voltage of the intermediate frequency signal SIF supplied to the variable gain amplifier 26 is the voltage EIF, the maximum signal voltage applied to the FETs (M21 to M23) is EIF × R2 / (R1 + R2).
Therefore, as the control range of the gain GV per stage is increased, a voltage closer to the input signal is applied to the FET. The distortion generated from the FET increases as the voltage applied between the drain and source of the FET increases. Therefore, the control amount of gain per stage is determined from the required distortion amount.

  FIG. 4 shows a measurement example of the third-order intermodulation distortion with respect to the AGC voltage (control voltage), which is displayed by an input intercept point (IIP3) of the third-order intermodulation distortion. The gain control range per stage is 3 dB. In this case, it can be seen that the distortion characteristics are better than in the case of 6 dB. Therefore, the gain control range per stage is preferably 3 dB. In this case, the AGC variable gain amplifier 26 in the intermediate frequency stage requires a control range of about 40 dB, so that 14 stages (≈3 dB). × 14 stages).

[3] Control Voltage Forming Circuit The control voltage forming circuit is a circuit for forming control voltages D21 to D23 from the AGC voltage VAGC. In the gain control circuit 26 shown in FIG. 3, the drain potential and the source potential of the FET (M21) are equal to the potential of the non-inverting input terminal of the operational amplifier 261 and are the voltage EO. Therefore, when the FET (M21) is turned on, the control voltage D21 is at least VGS + EO
VGS: A gate-source voltage of the FET is required.

If the on-resistance rON of the FET (M21) is sufficiently smaller than the resistor R21, the signal voltage applied to the FET (M21) is
EIF × rON / (R21 + rON) ≒ EIF × rON / R21
Thus, although the occurrence of distortion is small, a sufficient overdrive voltage is required for this purpose.

On the other hand, when the FET (M21) is off, to prevent it from turning on even when the signal voltage is large,
VD21 + EIF x R22 / (R21 + R22)-EO <VTH
VD21: The gate voltage of the FET (M21) is a necessary condition. That is, if this state is established, no distortion occurs.

  From the above, the control voltage forming circuit is configured as shown in FIG. 5, for example. That is, in FIG. 5, reference numeral 45 indicates the control voltage forming circuit. In this example, the operational amplifier Q51 and the FET (M51) form a voltage follower circuit, and the AGC voltage VAGC from the terminal pin T14 is the non-operational amplifier Q51. While being supplied to the inverting input, the source of the FET (M51) is connected to the voltage source of the bias voltage V51 through the resistor R51, and the drain thereof is connected to the terminal T10 through the resistor R54. The constant voltage VDD is supplied from the constant voltage circuit 53 to the terminal T10, and the bias voltage V51 is also formed by the constant voltage circuit 53.

  Further, the drain of the FET (M65) of the bias voltage forming circuit 46 to be described later is connected to the gate of the FET (M54), the drain of the FET (M54) is connected to the terminal T10, and the source thereof is the resistor R57. And further connected to the drain of the FET (M51) through the drain and source of the FET (P51), and the gate of the FET (P51) is grounded. The voltage VO is taken out from the drain of the FET (M65). Thus, the first conversion circuit 451 for converting the AGC voltage VAGC into the control voltage D21 is configured.

  Similarly, a second conversion circuit 452 for converting the AGC voltage VAGC into the control voltage D22 is configured by the elements Q52, M52, M55, P52, R52, R55, R58 and the bias voltage V52. Further, the elements Q53, M53, M56, P53, R53, R56, R59 and the bias voltage V53 constitute a third conversion circuit 453 for converting the AGC voltage VAGC into the control voltage D23. Although details will be described later, the drain voltage of the FET (M51 to M53) becomes the control voltage D21 to D23 of the FET (M21 to M23) of the variable gain amplifier 26 shown in FIG.

  According to such a configuration, it is possible to obtain control voltages D21 to D23 that change as shown in FIG. 6, for example, with respect to the AGC voltage VAGC. Here, the control voltage D22 will be mainly described for convenience.

  That is, when VAGC ≦ V52, the FET (M52) is off, and the drain current I52 of the FET (M52) does not flow as shown in FIG. Therefore, the drain voltage D22 of the FET (M52) is equal to the voltage VDD (3V in FIG. 6). In this state, the FET (P52) is forward-biased and turned on.

  However, when the AGC voltage VAGC rises and VAGC> V52, the FET (M52) is turned on and its source potential changes corresponding to the AGC voltage VAGC, and the drain of the FET (M52) A current I52 obtained by voltage / current conversion from the AGC voltage VAGC flows. As shown in FIG. 6, the current I52 is linearly proportional to the AGC voltage VAGC and flows through the resistor R55. Therefore, the drain voltage D22 of the FET (M52) decreases rapidly as the AGC voltage VAGC increases. To go.

  When the voltage drop across the resistor R55 exceeds the threshold voltage VTH of the FET (M55), the FET (M55) is also turned on. Therefore, when the AGC voltage VAGC further increases, the current I52 flows mainly through the series circuit of the FET (M55), the resistor R58 and the FET (P52), and therefore the change of the control voltage D22 with respect to the change of the AGC voltage VAGC is The voltage becomes gentle according to the voltage-current characteristics of the FET (M55), and the control voltage D22 gradually decreases as the AGC voltage VAGC increases.

  When the control voltage D22 decreases to the predetermined value VLIM due to the increase of the AGC voltage VAGC, the FET (P52) is reverse-biased and turned off. Thereafter, the current I52 flows only through the resistor R55, and therefore the change in the AGC voltage VAGC. On the other hand, the control voltage D22 decreases rapidly.

  The control voltage D22 is supplied to the FET (M22), but the FET (P52) has a current I52 of the FET (M52) when the AGC voltage VAGC greatly exceeds the gain control range of the FET (M22). This is for current limiting so as not to become excessive. Thus, a control voltage D22 that changes as shown in FIG. 6 is formed from the AGC voltage VAGC.

  Further, by changing the voltage V52, the curve of the control voltage D2 moves in the left-right direction (the level direction of the AGC voltage VAGC) in FIG. Therefore, in FIG. 5, by setting the voltages V51 to V53 to a predetermined value in the relationship of V51 <V52 <V53, the control voltages D21 to D23 having the characteristics shown in FIG. 6 are applied to the drains of the FETs (M51 to M53). Can be obtained. In FIG. 6, V51 = 0, V52 = 40 mV, and V53 = 100 mV.

  Since these control voltages D21 to D23 are supplied to the gates of the FETs (M21 to M23) of the variable gain amplifier 26, the gain of the variable gain amplifier 26 can be controlled as described in [2]. AGC can be performed.

  At this time, as shown in FIG. 5, the currents I51 to I53 change linearly with respect to the AGC voltage VAGC, and the currents I51 to I53 flow through the FETs (M54 to M56) to control voltage V21 to Since the change of V23 is obtained, that is, the linearly changing currents I51 to I53 are converted into the control voltages D21 to D23 according to the voltage-current characteristics of the FETs (M54 to M56), so that the AGC voltage VAGC changes. On the other hand, the gain change of the variable gain amplifier 26 has a logarithmic characteristic (dB linear).

  Further, the difference between the voltages V51 to V53 and the number of FETs (M21 to M23) and the number of stages of the conversion circuits 451 to 453 (in this case, three stages) become the input voltage range of the AGC voltage VAGC. A gain change coefficient (-dB / V) is determined.

  FIG. 7 is a diagram illustrating the effect of control characteristics when two stages of conversion circuits 451 and 452 are provided. That is, in this characteristic diagram, V51 = 0 and V52 = 100 mV, and curve A shows that FET (M21) operates in the range of VAGC = 0-60 mV, and FET (M22) has VAGC = 100- The state of operating in the range of 160 mV is shown.

  Therefore, in order to make it continuously variable, it is only necessary to set V52 = 40 mV. That is, as shown by the arrow, the operation range B of the FET (M22) moves in the direction in which the AGC voltage VAGC is small. Thus, the logarithmic characteristic (dB linear) indicated by the curve C can be obtained. Curve D shows the gain characteristics when a voltage that varies linearly in proportion to the AGC voltage VAGC is supplied to the FETs (M21, M22). It turns out that it cannot be obtained.

  Thus, according to the circuits of FIGS. 3 and 5, for example, 6 dB gain control is performed by each of the FETs (M21 to M23) corresponding to the AGC voltage VAGC, and the 6 dB gain control ranges overlap. Therefore, the gain is continuously controlled over 18 dB as a whole.

[4] Bias Voltage Forming Circuit As described with reference to FIG. 11, generally, the threshold voltage VTH of the FET varies, and the threshold voltage VTH of the FET (M54 to M56, M21 to M23) also varies. There is variation. As a result, the variable gain characteristic or the AGC characteristic varies or becomes insufficient.

A circuit for compensating for variations in the threshold VTH is the bias voltage forming circuit 46 in FIG. In this case, as described in [3], in order to turn on the FETs (M21 to M23), the control voltages D21 to D23 must be at least VGS + EO.
EO: A predetermined bias voltage supplied from the constant voltage circuit 53 is required.

Furthermore, in the region where the FETs (M21 to M23) operate as variable resistance elements,
D21 = VO-VGO
VGO: Because it is a gate voltage, VO = VGO + VGS + EO
Thus, the output voltage VO of the bias voltage forming circuit 46 needs to change twice as much as the variation of the threshold voltage VTH. That is, it is necessary to compensate for variations in the threshold voltages VTH of the FETs (M54, M21), (M55, M22), (M56, M23).

  Therefore, in the bias voltage forming circuit 46 shown in FIG. 5, a current mirror circuit 461 is configured by FETs (P61, P62) with the terminal T10 as a reference potential point, and from the drain of the FET (P61) on the input side. A predetermined constant current Is is taken out by the constant current source Q61.

The drain of the FET (P62) is connected to the drain of the FET (M61), and the gate of the FET (M61) is connected to the voltage source of the reference voltage VREF through the resistor R61. Further, the drain of the FET (P62) is connected to the gate of the FET (P63), the source is connected to the terminal T10, and the drain is connected to the drain of the FET (M62). , FET (M63, M64) and ground mirror as a reference potential point, and FET (M62) as an input side constitutes a current mirror circuit 462. The drain of the FET (M63) on the output side is Connected to the gate of FET (M61). Further, the drain of the FET (P62) is connected to the gate of the FET (M65), the drain of the FET (M65) is connected to the terminal T10 through the resistor R62, and the source thereof is connected to the drain of the FET (M64). The

The FETs (M63, M64) can be selected by selecting their sizes, that is, by setting their gate widths.
I64 = n ・ I63 (31)
I64: drain current of FET (M64) I63: drain current of FET (M63) n: positive predetermined value The reference voltage VREF is also taken out from the constant voltage source 53.

According to such a configuration, the drain current I63 of the FET (M63) flows from the voltage source of the voltage VREF to the drain through the resistor R61.
VGS: If the voltage between the gate and source of FET (M61) is
I63 = (VREF−VGS) / R61 (32)
Or VGS = VREF−I63 ・ R61 (33)
It becomes.

  Since the constant current Is of the constant current source Q61 is also the input current of the current mirror circuit 461, the current Is is output from the drain of the FET (P62) on the output side.

  At this time, if the drain current of the FET (M61) is smaller than the drain current Is of the FET (P62) due to variations in the threshold voltage of the FET, the FET (P63) is biased in the off direction, and the FET (P63) The drain current of P63) is reduced, and this drain current is also the input current of the current mirror circuit 462, so the drain current I63 of the FET (M63) is also reduced. Accordingly, the gate-source voltage VGS of the FET (M63) is increased from the equation (33), so that the drain current of the FET (M61) is increased.

  On the contrary, if the drain current of the FET (M61) is larger than the drain current Is of the FET (P62), the drain current I63 of the FET (M63) becomes large, and the gate-source voltage VGS of the FET (M63). Therefore, the drain current of the FET (M61) becomes small.

  That is, negative feedback is applied with reference to the drain current Is of the FET (P62), and the drain current Is is equal to the constant current Is of the constant current source Q61. Therefore, negative feedback is applied with reference to the constant current Is of the constant current source Q61, and the drain current of the FET (M61) is stabilized at the reference value Is.

  That is, the gate bias voltage of the FET (M61) changes so that the drain current of the FET (M61) becomes the reference value Is. This change is realized by a change in the drain current I63 of the FET (M63). Therefore, the drain current I63 detects the variation in the threshold voltage VTH of the FET (M61).

  At this time, since the FET (M63) is the output side FET of the current mirror circuit 462 together with the FET (M64), the drain current I64 of the FET (M64) also detects the variation in the threshold voltage VTH of the FET (M61). It becomes current. In addition, since the currents I64 and I63 have the relationship of the equation (31), the current I64 is n times larger than the current I63.

And
VO: voltage obtained at the drain of the FET (M65) VDD: voltage at the terminal T10 IO: current flowing through the resistor R62
VO = VDD-IO ・ R62 (34)
It becomes. Also,
IO = I64 (35)
It is.

Therefore, substituting equation (35) into equation (34) and further substituting equations (31) and (32),
VO = VDD-n (VREF-VGS) / R61 / R62
= VDD-nVREF.R62 / R61 + nVGS.R62 / R61 (36)
It becomes.

This output voltage VO is supplied to the gate of the FET (M54). In order to include the value 2VGS in the voltage VO,
nR62 / R61 = 2 (37)
Should be set. That is, if it is set in that way, equation (36) becomes
VO = VDD-nVREF.R62 / R61 + 2VGS (38)
It becomes.

  When the gate-source voltage VGS of the FET (M54, M21) varies, the voltage VO in the equation (36) also changes by the same magnitude in the same direction in the IC. As a result, as a result, the FET (M54, The variation in the gate-source voltage VGS of M21) can be absorbed.

  Similarly, variations in the gate-source voltage VGS of the FETs (M55, M22) and (M56, M23) can be absorbed.

  Therefore, as described in FIG. 3, for example, 6 dB gain control is performed by each of the FETs (M21 to M23) corresponding to the AGC voltage VAGC, and the 6 dB gain control range does not overlap. And since it is continuous, the gain is continuously controlled over 18 dB as a whole.

  FIG. 8 is a diagram showing a gain characteristic with respect to the AGC voltage VAGC when the threshold voltage VTH is compensated and when it is not compensated. However, this is a case where two stages of conversion circuits 451 and 452 are provided.

  The curve ETYP is a characteristic when the threshold voltage VTH is a representative value, the curve F- is a characteristic when the threshold voltage VTH is varied by 0.2V, but is not compensated, and the curve E- Is the characteristic when the compensation is made. A curve F + is a characteristic when the threshold voltage VTH varies in a direction higher by 0.2V but is not compensated, and a curve E + is a characteristic when the compensation is made.

  As described above, when the variation in the threshold voltage VTH is not compensated (curves F− and F +), the linearity of the AGC characteristic is greatly deteriorated and the gain is increased with respect to the same AGC voltage VAGC. Nearly 5dB will be different. However, when the threshold voltage VTH is compensated (curves E-, E +), the linearity of the characteristics is improved and the gain variation with respect to the same AGC voltage VAGC is suppressed to 1 dB or less.

  Thus, according to the bias voltage forming circuit 46, even if the gate-source voltages of the FETs (M54 to M56, M21 to M23) vary, the voltage VO also changes by the same magnitude in the same direction. (M54 to M56, M21 to M23) can be absorbed in the variation in the gate-source voltage, and as a result, the variation and variation in the gain of the variable gain amplifier 26 due to the variation in the threshold voltage VTH of the FET, Alternatively, variations in the AGC characteristics at the intermediate frequency stage and fluctuations in the characteristics can be suppressed.

[5] Variable gain amplifier (other examples)
The variable gain amplifier 26 shown in FIG. 9 is a case where two sets of the variable gain amplifiers 26 shown in FIG. Then, capacitors Cf and Cf are connected in parallel to the negative feedback resistors Rf and Rf to improve the high frequency characteristics.

[6] Control voltage forming circuit (other examples)
FIG. 10 shows another example of the control voltage forming circuit 45. In this example, operational amplifiers Q51 to Q53, FETs (M51 to M53), resistors R51 to R53, resistors R54 to R56, and bias voltages V51 to V53 are configured similarly to the example shown in FIG. The gate of the FET (M54 to M56) is connected to the drain of the FET (M65) to supply the voltage VO, and the source of the FET (M54 to M56) is connected to the FET (M51 to M53) through the resistors R57 to R59. The drains of the FETs (M54 to M56) are connected to the terminal T10 through the drains and sources of the FETs (P51 to P53), and the gates of the FETs (P51 to P53) are connected to the FETs (P61 and P62) Connected to the gate.

Therefore, when the AGC voltage VAGC increases, the currents I51 to I53 are
I51 = (VAGC−V51) / R51
I52 = (VAGC−V52) / R52
I53 = (VAGC−V53) / R53
Therefore, as the AGC voltage VAGC increases, the currents I51 to I53 increase, and the FETs (M21 to M23) are sequentially turned off. In this case, a large current is required to lower the control voltages D21 to D23 to near the ground potential, and this current is tripled (generally multiplied by the number of stages), resulting in a large current. Although it is necessary not to flow, this circuit can limit the current more accurately than the circuit shown in FIG.

  That is, in the circuit shown in FIG. 5, the current limiting FETs (P51 to P53) need to be limited by a current several times the necessary current in order to reduce the influence on the gain control characteristics. There is. However, in the circuit shown in FIG. 10, FETs (P51 to P63) are connected in series to the FETs (M54 to M56) and the FETs (P51 to P53) are used as the output side of the current mirror circuit 461. In (P51 to P53), a current larger than the constant current proportional to the constant current Is of the constant current source Q61 does not flow. Since the currents I51 to I53 are determined by the voltage drop of the resistors R54 to R56 having a large value and the constant current value by the FETs (P51 to P53), the wasteful current is reduced.

[7] Summary According to the above-described gain control amplifier, the gain can be continuously controlled over a wide range, and even if there is a variation in the threshold voltage VTH of the FET, the variation is compensated for. Gain characteristics can be obtained. In particular, it is more effective when the circuit is integrated into an IC.

  Therefore, when applied to an AGC circuit, variations in loop gain as an AGC circuit can be suppressed. For example, as shown by a curve C in FIG. 7, the gain control range for the AGC voltage is set to a target range. Therefore, variation in the transient response characteristics of AGC can be suppressed, and an increase in distortion and level instability can be suppressed.

  Further, in the digitized receiver as shown in FIGS. 1 and 2, when the AGC voltage forming circuit 91 D / A converts the digital AGC voltage to the analog AGC voltage VAGC, the D / A converter circuit There is no need to increase the dynamic range or resolution.

[8] Others In the above description, the gain control is performed in three stages. However, the gain change range per stage and the number of stages can be changed in accordance with specifications required for gain control.

  In the above description, the gain control amplifier is applied to a variable gain amplifier for intermediate frequency signals, but can be applied to, for example, high frequency amplifiers 13A to 13C. In this case, for example, each of the high-frequency amplifiers 13A to 13C is constituted by a cascode amplifier using an FET, and a control voltage corresponding to the control voltages D21 to D23 is supplied to the gate of the FET on the output side (gate ground side). That's fine. The control voltage can be formed in the formation circuit 43 as described above.

[List of abbreviations]
A / D: Analog to Digital
AGC: Automatic Gain Control
D / A: Digital to Analog
D / U: Desire to Undesire ratio
FET: Field Effect Transistor
IC: Integrated Circuit
IIP3: Third Order Input Intercept Point
MOS: Metal Oxide Semiconductor
PLL: Phase Locked Loop
S / N: Signal to Noise ratio
VCO: Voltage Controlled Oscillator

It is a systematic diagram showing one form of a front end circuit to which the present invention can be applied. It is a systematic diagram showing one form of a baseband processing circuit. It is a connection diagram showing one embodiment of the present invention. It is a figure which shows the example of a measurement of the characteristic of the circuit of FIG. It is a connection diagram showing one embodiment of the present invention. FIG. 6 is a characteristic diagram for explaining the operation of the circuit of FIG. 5. FIG. 6 is a diagram illustrating a measurement example of characteristics of the circuit in FIG. 5. FIG. 6 is a diagram illustrating a measurement example of characteristics of the circuit in FIG. 5. It is a connection diagram which shows the other form of this invention. It is a connection diagram which shows the other form of this invention. It is a figure which shows an example of the characteristic of FET.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Front end circuit (IC), 12A-12C ... Antenna tuning circuit, 13A-13C ... High frequency amplifier, 14A-14C ... Interstage tuning circuit, 15A-15C ... Input buffer circuit, 16A-16C ... Voltage comparison circuit, 17A ˜17C: Buffer circuit, 21A and 21B: Mixer circuit, 22: Low pass filter, 23: Amplitude phase correction circuit, 24: Complex band pass filter, 25: Level correction amplifier, 26: Variable gain amplifier, 27: Band pass filter, DESCRIPTION OF SYMBOLS 30 ... PLL, 37 ... Frequency dividing circuit, 41 ... Level detection circuit, 43 ... Delay AGC voltage formation circuit, 44 ... Linear detection circuit, 45 ... Control voltage formation circuit, 46 ... Bias voltage formation circuit, 51 ... Non-volatile memory, 52 ... Buffer memory, 53 ... Constant voltage circuit, 60 ... Baseband processing circuit (IC)

Claims (4)

A front-end integrated circuit having a variable gain amplifier that amplifies a high-frequency signal or an intermediate-frequency signal in a front-end circuit that converts a received signal in a wide band into an intermediate-frequency signal,
An input terminal to which a variable control voltage for controlling the gain of the variable gain amplifier is input;
A control voltage forming circuit that converts the variable control voltage input to the input terminal into a control voltage and outputs the control voltage to the variable gain amplifier;
Have
The variable gain amplifier is
An operational amplifier for amplifier,
A plurality of (m + 1) series resistors connected in series to the inverting input terminal of the operational amplifier for amplifier, and receiving the high frequency signal or intermediate frequency signal from the front stage of the front end circuit ;
A negative feedback resistance element connected between the output terminal of the amplifier operational amplifier and the inverting input terminal ;
A plurality of m amplifier FETs each having a drain and a source connected between a connection midpoint between two series resistors adjacent to each other in the multistage connection and an inverting input terminal of the amplifier operational amplifier;
And amplifies the high frequency signal or intermediate frequency signal and outputs from the output terminal of the operational amplifier for amplifier,
The control voltage forming circuit is
A plurality of m voltage conversion circuits for individually outputting control voltages to the respective gates of the plurality of m amplifier FETs;
A power terminal;
Have
Each of the above voltage conversion circuits
A conversion operational amplifier in which the variable control voltage is input to the non-inverting input terminal;
A first FET whose gate is connected to the output terminal of the conversion operational amplifier to form a voltage follower circuit;
A voltage source connected through a first resistor to a source of the first FET and an inverting input terminal of the conversion operational amplifier;
A second resistor connected between the drain of the first FET and the power supply terminal;
The voltage at the connection point between the drain of the first FET and the second resistor is output to the corresponding gate of the amplifier FET as a control voltage obtained by converting the variable control voltage,
The voltage sources of the plurality of m voltage conversion circuits are:
In the multistage connection, the voltage of the voltage source corresponding to the output side series resistor is higher than the voltage of the voltage source corresponding to the input side series resistor,
The multiple m amplifier FETs are:
When the variable control voltage increases from the first value to the second value,
Due to the voltage difference of the voltage sources of the plurality of m voltage conversion circuits, the variable control voltage becomes the voltage of the corresponding voltage source, so that the transition from the OFF state is started in order from the input side. , From the all-off state to the on-state from the off-state in order from the input side, eventually all the on-state,
The drain-source resistance gradually decreases from the start of the transition from the off state to the on state,
It said plurality of m between the drain and source of the amplifier FET resistance continuously changes to off from on independently of each other
Front-end integrated circuit. A plurality of (m + 1) series resistors connected in multiple stages are
A first series resistor, a second series resistor, a third series resistor, and a fourth series resistor connected directly in order from the input side;
When the resistance value of the first series resistor is R, the resistance value of the second series resistor is R, the resistance value of the third series resistor is 2R, and the resistance value of the fourth series resistor is 4R. Is
The front end integrated circuit according to claim 1. Forming a compensation voltage having a value corresponding to a variation in the threshold voltage of the plurality of amplifier FETs;
The compensation voltage is supplied to the plurality of m amplifier FETs together with the control voltage.
The front end integrated circuit according to claim 1 or 2. The received signal in the broadband is
Analog and digital television broadcast signals
The front end integrated circuit according to any one of claims 1 to 3.

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