JP2008160672A - Input circuit of mixer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid deterioration of characteristics in a wide frequency range in an input circuit of a mixer circuit. <P>SOLUTION: The mixer circuit 21I is targeted, in which one of a drain and a source of a MOS-FET is connected to an output end of a signal source 15A of a received signal SRX, the other is connected to an input end of a buffer amplifier, a local oscillation signal SLOI is supplied to a gate and a signal SIFI in which the received signal SRX is switched by the local oscillation signal SLOI is supplied to the buffer amplifier. The input circuit of the mixer circuit is provided with a voltage comparator circuit 16A which compares voltage of DC potential VRX of the output end of the signal source 15A and DC potential VS of an input end of the buffer amplifier. Comparative output of the voltage comparator circuit 16A is fed back to the signal source 15A so that the DC potential VRX of the output end of the signal source 15A is equal to the DC potential Vs of the input end of the buffer amplifier. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an input circuit of a mixer circuit.

  A superheterodyne receiver multiplies a received signal by a local oscillation signal by a mixer circuit and converts the frequency of the received signal to an intermediate frequency signal. As a passive type mixer circuit, for example, as shown in FIG. 6 or FIG. Some use CMOS-FETs.

  That is, in both mixer circuits, the switching circuit 1 is composed of FETs, and the buffer amplifier 2 is connected to the output side thereof. In the switching circuit 1, the received signal is switched by the local oscillation signal, and the mixer output including the intermediate frequency signal of the received signal is taken out from the buffer amplifier 2.

For example, there are the following prior art documents.
Japanese Patent Laid-Open No. 2005-244397 JSSCC Vol.40, No.5, May 2005 “CMOS passive Mixer with low flicker noise for low-power Direct-conversion Receiver”

  However, in the mixer circuit of FIG. 6, if there is a difference between the DC potential at the input end of the switching circuit 1 and the DC potential at the output end (if there is a DC offset), the difference potential is equivalent to the DC input. As a result, noise increases, distortion increases, or a signal component equal to the local oscillation signal supplied to the gate leaks to the buffer amplifier 2.

  For this reason, in the mixer circuit of FIG. 6, it is necessary to prevent a DC offset from occurring between the DC potential at the output end of the signal source of the received signal and the DC potential at the input end of the buffer amplifier 2. Since 1 is composed of a MOS-FET, it is difficult to stably obtain such a state.

  In that respect, since the mixer circuit of FIG. 7 supplies the received signal to the switching circuit 1 through the capacitors C1 and C2, the DC offset as described above can be solved. However, if capacitors C1 and C2 are used, in the case of a wideband receiver, it is necessary to increase the capacitance of capacitors C1 and C2 in order to receive a low-frequency received signal. At this time, a large area is required. The parasitic capacitance will also increase. Then, when the frequency of the received signal is high, the received signal is greatly attenuated by the parasitic capacitance, leading to a decrease in reception sensitivity and a decrease in C / N. In addition, the load on the high-frequency amplifier in the previous stage that supplies the reception signal increases, and distortion increases.

  The present invention is intended to solve the above problems.

In this invention,
One of the drain and source of the MOS-FET is connected to the output terminal of the signal source of the received signal,
The other of the drain and the source is connected to the input terminal of the buffer amplifier,
A local oscillation signal is supplied to the gate of the MOS-FET,
A signal obtained by switching the received signal with the local oscillation signal is supplied to the buffer amplifier.
A voltage comparison circuit that compares the voltage between the DC potential at the output terminal of the signal source and the DC potential at the input terminal of the buffer amplifier;
The input circuit of the mixer circuit that feeds back the comparison output of the voltage comparison circuit to the signal source so that the DC potential of the output end of the signal source is equal to the DC potential of the input end of the buffer amplifier. It is what.

  According to the present invention, a one-chip IC can be realized over a wide frequency range, and there is no deterioration in characteristics as a mixer circuit.

[1] Example of Receiving Circuit (Overall) Carrier frequencies (channels) used for television broadcasting vary from country to country, and color systems include NTSC, PAL, SECAM, and the like. In addition, there are analog broadcasting and digital broadcasting.

  Therefore, a reception signal system for television broadcasting, a front-end circuit that receives television broadcasting and outputs an intermediate frequency signal, and a baseband processing circuit that processes the output of the front-end circuit and outputs color video signals and audio signals It is considered to be divided into That is, by doing so, the difference in the broadcasting system of television broadcasting is dealt with.

  First, an example of a front end circuit and a baseband processing circuit to which the present invention can be applied will be described.

[1-1] Example of Front-End Circuit FIG. 1 shows an example of a front-end circuit that can receive television broadcasts in various countries regardless of the broadcast format. In this example, the frequency used in the television broadcasting of each country is
(A) 46 to 147 MHz (VL band)
(B) 147-401MHz (VH band)
(C) 401-887MHz (U band)
In this case, the frequency can be changed corresponding to the target channel in each reception band.

  That is, in FIG. 1, a portion 10 surrounded by a chain line indicates the front end circuit, which is integrated into a one-chip IC. The IC (front end circuit) 10 has terminal pins T11 to T19 for external connection.

  Then, the broadcast wave signal of the television broadcast is received by the antenna ANT, and the received signal is selectively supplied from the terminal pin T11 to the antenna tuning circuits 12A to 12C through the switch circuit 11. In this case, the antenna tuning circuits 12A to 12C correspond to the reception bands of the items (A) to (C), respectively, and the tuning frequency is changed by changing the capacitance of the tuning capacitor with digital data. As a result, it is configured to tune to a received signal having a target frequency (channel).

  The received signals from the tuning circuits 12A to 12C are supplied to the switch circuit 15 through the high frequency amplifiers 13A to 13C and further through the interstage tuning circuits 14A to 14C. The switch circuit 15 is switched in conjunction with the switch circuit 11, and therefore, the received signal SRX of the target reception band is extracted from the switch circuit 15. The extracted reception signal SRX is supplied to the mixer circuits 12I and 12Q.

  Although the tuning circuits 14A to 14C are configured similarly to the tuning circuits 12A to 12C, the tuning circuit 14A is a retune circuit. Although not shown, the tuning capacitors of the tuning circuits 12A to 14C are built in the IC 10, and the tuning coil is externally attached to the IC 10.

  Further, in the VCO 31, an oscillation signal having a predetermined frequency is formed. The VCO 31 is for forming a local oscillation signal and constitutes a part of the PLL 30. That is, the oscillation signal of the VCO 31 is supplied to the variable frequency dividing circuit 32 and divided into signals having a frequency of 1 / N (N is a positive integer), and this frequency divided signal is supplied to the phase comparison circuit 33. Further, a clock (frequency is about 1 to 2 MHz) is supplied from the outside to the signal forming circuit 34 through the terminal pin T14 and is divided into a signal of a predetermined frequency f34, and this divided signal is supplied to the phase comparison circuit 33 as a reference signal. Supplied.

  Then, the comparison output of the phase comparison circuit 33 is supplied to the loop filter 35, and a DC voltage whose level changes in accordance with the phase difference between the output signal of the variable frequency dividing circuit 32 and the output signal of the forming circuit 34 is extracted. This DC voltage is supplied to the VCO 31 as a control voltage of the oscillation frequency f31. A smoothing capacitor C11 is externally attached to the filter 35 through a terminal pin T15.

Therefore, the oscillation frequency f31 of the VCO 31 is
f31 = N · f34 (1)
Therefore, if the frequency division ratio N is controlled by a system control microcomputer (not shown), the oscillation frequency f31 of the VCO 31 can be changed. For example, the frequency f31 is 1.8 to 3.6 GHz corresponding to the reception band and the reception frequency (reception channel).

  Then, the oscillation signal of the VCO 31 is supplied to the variable frequency dividing circuit 36 and is divided to a frequency of 1 / M (for example, M = 2, 4, 8, 16, 32). 37 is divided into frequency-divided signals SLOI and SLOQ having a frequency of 1/2 and orthogonal to each other, and these signals SLOI and SLOQ are supplied to the mixer circuits 21I and 21Q as local oscillation signals.

here,
fLO: If the frequency of the local oscillation signals SLOI, SLOQ,
fLO = f31 / (2M)
= N · f34 / (2M)
= F34 · N / (2M) (2)
It becomes. Therefore, by changing the frequency dividing ratios M and N, the local oscillation frequency fLO can be changed over a wide range at a predetermined frequency step.

Also,
SRX: Received signal desired to be received SUD: Image jamming signal
SRX = ERX ・ sinωRXt
ERX: Amplitude of received signal SRX
ωRX = 2πfRX
fRX: Center frequency of received signal SRX SUD = EUD · sinωUDt
EUD: Amplitude of image disturbance signal SUD
ωUD = 2πfUD
fUD: The center frequency of the image disturbing signal SUD.

Further, regarding local oscillation signals SLOI and SLOQ,
SLOI ＝ ELO ・ sinωLOt
SLOQ ＝ ELO ・ cosωLOt
ELO: Amplitude of signals SLOI and SLOQ
ωLO = 2πfLO
And

However, at this time
ωIF = 2πfIF
fIF: intermediate frequency. For example, 4 to 5.5 MHz (change according to the broadcasting system)
Then, in the case of the upper heterodyne method,
fRX = fLO-fIF
fUD = fLO + fIF
It is.

Therefore, the following signals SIFI and SIQQ are output from the mixer circuits 21I and 21Q. That is,
SIFI = (SRX + SUD) × SLOI
= ERX · sinωRXt × ELO · sinωLOt
+ EUD ・ sinωUDt × ELO ・ sinωLOt
= Α {cos (ωRX−ωLO) t−cos (ωRX + ωLO) t}
+ Β {cos (ωUD−ωLO) t−cos (ωUD + ωLO) t}
SIFQ = (SRX + SUD) × SLOQ
= ERX · sinωRXt × ELO · cosωLOt
+ EUD ・ sinωUDt × ELO ・ cosωLOt
= Α {sin (ωRX + ωLO) t + sin (ωRX−ωLO) t}
+ Β {sin (ωUD + ωLO) t + sin (ωUD−ωLO) t}
α = ERX ・ ELO / 2
β = EUD ・ ELO / 2
The signals SIFI and SIFQ are extracted.

Then, these signals SIFI and SIFQ are supplied to the low-pass filter 22 which is wider than the occupied bandwidth (for example, 6 to 8 MHz) of the video intermediate frequency signal and the audio intermediate frequency signal. Signal components (and local oscillation signals SLOI and SLOQ) of (ωRX + ωLO) and (ωUD + ωLO) are removed, and the low-pass filter 22
SIFI = α · cos (ωRX−ωLO) t + β · cos (ωUD−ωLO) t
= Α · cosωIFt + β · cosωIFt (3)
SIFQ = α · sin (ωRX−ωLO) t + β · sin (ωUD−ωLO) t
= -Α ・ sinωIFt + β ・ sinωIFt (4)
Is taken out.

These signals SIFI and SIFQ are supplied to a complex bandpass filter (polyphase bandpass filter) 24 through an amplitude phase correction circuit 23 described later. This complex bandpass filter 24 is
(a) It has a frequency characteristic of a band pass filter.
(b) The phase shift characteristic is also provided, and the signal SIFI is phase-shifted by a value φ (φ is an arbitrary value).
(c) Similarly, the signal SIFQ is phase-shifted by a value (φ−90 °).
(d) On the frequency axis, it has two bandpass characteristics with a center frequency of a frequency f0 and a frequency -f0 that are symmetrical with respect to the zero frequency, and this can be selected according to the relative phase of the input signal. it can.
It has the following characteristics.

Therefore, in the complex band-pass filter 24, the signal SIFQ is delayed by 90 ° with respect to the signal SIFI by the above items (b) and (c).
SIFI = α ・ cosωIFt + β ・ cosωIFt (5)
SIFQ = -α · sin (ωIFt-90 °) + β · sin (ωIFt-90 °)
= Α ・ cosωIFt−β ・ cocωIFt (6)
It is said. That is, between the signal SIFI and the signal SIFQ, the signal component α · cosωIFt is in phase with each other, and the signal component β · cocωIFt is in phase with each other.

  Then, the signals SIFI and SIFQ are supplied to the level correction amplifier 25, the signal SIFI and the signal SIFQ are added, and the following signal SIF is extracted from the level correction amplifier 25.

That is,
SIF = SIFI + SIFQ
= 2α ・ cosωIFt
= ERX / ELO / cosωIFt (7)
Is taken out. This extracted signal SIF is nothing but an intermediate frequency signal when the signal SRX is received by the upper heterodyne system. The intermediate frequency signal SIF does not include the image disturbance signal SUD. The amplitude / phase correction circuit 23 corrects the amplitude and phase of the signals SIFI and SIFQ so that the expression (7) is sufficiently established, that is, the image disturbance signal SUD is minimized.

  Further, at this time, in the level correction amplifier 25, even if the levels of the signals SIFI and SIFQ differ depending on the broadcasting system, the signal SIF is not changed so that the AGC characteristics (particularly, the AGC start level) described later do not change. Level is corrected.

  The intermediate frequency signal SIF is output to the terminal pin T12 through the AGC variable gain amplifier 26, and further through the band-pass filter 27 for cutting and aliasing the direct current.

  Therefore, the target frequency (channel) can be selected by changing the frequency dividing ratios M and N in accordance with the equation (2), and the intermediate frequency signal SIF output to the terminal pin T12 corresponds to the broadcasting system. If demodulated, the target broadcast can be viewed.

[1-1-1] Example of AGC An AGC voltage VAGC is formed in a baseband processing circuit to be described later, and this AGC voltage VAGC is supplied as a gain control signal to the AGC variable gain amplifier 26 through a terminal pin T16. . Therefore, normal AGC is performed by this.

  Further, for example, when the level of the target reception signal SRX is too large, or when the interference signal of a large level is mixed in the reception signal SRX, the above-described normal AGC cannot cope with it. Therefore, the signals SIFI and SIFQ output from the low-pass filter 22 are supplied to the level detection circuit 41, and it is detected whether or not the levels of the signals SIFI and SIFQ before the AGC is performed in the AGC amplifier 26 exceed a predetermined value. . The detection signal and the AGC voltage VAGC at the terminal pin T16 are supplied to the adder circuit 42, and the added output is supplied to the forming circuit 43 to form a delayed AGC voltage. 13C is supplied as a gain control signal, and delay AGC is performed.

[1-1-2] Example of test / adjustment voltage The signals SIFI and SIFQ output from the low-pass filter 22 are supplied to the linear detection circuit 44, and detected and smoothed to indicate the levels of the signals SIFI and SIFQ. The DC voltage V44 is output, and this voltage V44 is output to the terminal pin T13.

  The DC voltage V44 output to the terminal pin T13 is used when the front end circuit 10 is tested or adjusted. For example, it can be used when checking the level of an input signal (received signal) over a wide frequency range, that is, unlike an output through a narrow-band intermediate frequency filter, from the antenna terminal pin T11 to the mixer circuits 21I, 21Q. It is possible to directly check the attenuation characteristic of the wide band with respect to the previous signal lines.

  When adjusting the antenna tuning circuits 12A to 12C and the interstage tuning circuits 14A to 14C, the input test signal is applied to the antenna terminal pin T11, and the AGC voltage VAGC supplied to the terminal pin T16 is fixed to a predetermined value. For example, tracking adjustment can be performed from a change in the DC voltage V44.

[1-1-3] Channel Selection The correction amount of the amplitude phase correction circuit 23, the center frequency and pass bandwidth of the complex bandpass filter 24, and the gain of the level correction amplifier 25 are the broadcasting system of the received television broadcast. Therefore, it is possible to set it from the outside as well as being variable. For example, the complex band pass filter 24 has a variable center frequency of 3.8 to 5.5 MHz and a pass band of 5.7 to 8 MHz.

  Then, the set values of these circuits 23 to 25 are written from the terminal pin T18 to the nonvolatile memory 51 and copied to the buffer memory 52 at the time of assembly or factory shipment, and the copied set values are stored in the circuit 23. To each of .about.25.

  Similarly, data for finely adjusting the tuning frequency of the tuning circuits 12A to 12C and 14A to 14C is similarly written from the terminal pin T18 to the nonvolatile memory 51 and copied to the buffer memory 52, and the copied data is tuned. It is supplied to each of the circuits 12A to 14C.

  Therefore, the characteristics of the circuits 23 to 25 can be set to those corresponding to the broadcast system of the received television broadcast. Note that the set value in the nonvolatile memory 51 is copied to the buffer memory 52 even when the receiver using the IC 10 is turned on, and the copied set value is supplied to each of the circuits 23 to 25. The

  When the user selects a channel, data for that purpose is supplied from the microcomputer for system control (not shown) to the buffer memory 52 through the terminal pin T19 and temporarily stored, and the stored data is stored in the switch circuit. 11, 15 and tuning circuits 12A to 12C, 14A to 14C, and variable frequency dividing circuits 32 and 36, a reception band including a target channel (frequency) is selected, and in the selected reception band, The target channel is selected.

[1-1-4] Others The IC 10 is provided with a constant voltage circuit 53, and the power supply voltage + VCC is supplied from the terminal pin T17. The constant voltage circuit 53 forms a constant voltage of a predetermined value from the power supply voltage + VCC using the band gap of the PN junction, and the formed constant voltage is supplied to each circuit of the IC 10.

  The output voltage of the constant voltage circuit 53 can be finely adjusted, and the set value is stored in the nonvolatile memory 51 and supplied to the constant voltage circuit 53 through the buffer memory 52.

[1-1-5] Summary According to the front end circuit 10 shown in FIG. 1, as shown in the items (A) to (C), it is possible to receive a television broadcast in a frequency band of 46 to 887 MHz. At that time, the center frequency and passband width of the complex bandpass filter 24 are variable, so that not only domestic terrestrial digital television broadcasts and terrestrial analog television broadcasts but also overseas digital television broadcasts and analog television broadcasts. Can also respond.

[1-2] Example of Baseband Processing Circuit FIG. 2 shows an example of the baseband processing circuit, which processes the intermediate frequency signal SIF output from the front end circuit 10 and outputs a color video signal and an audio signal. To do. That is, in FIG. 2, a portion 60 surrounded by a chain line indicates the baseband processing circuit, which is integrated into a one-chip IC. The IC (baseband processing circuit) 60 has terminal pins T61 to T67 for external connection.

  The intermediate frequency signal SIF output from the terminal pin T12 of the front end circuit 10 is supplied from the terminal pin T61 to the A / D converter circuit 61 and A / D converted into a digital intermediate frequency signal. SIF removes unnecessary frequency components by the filter 62.

  At the time of receiving digital television broadcast, the digital intermediate frequency signal SIF from the filter 62 is supplied to the demodulating circuit 63, and the baseband digital signal is demodulated and taken out. The demodulated output is supplied to the error correcting circuit 64. The error-corrected data stream is output and this data stream is output to the terminal pin T62. Therefore, if the signal at the terminal pin T62 is decoded according to the broadcasting system, the original color video signal and audio signal can be obtained.

  At the time of receiving an analog television broadcast, the digital intermediate frequency signal SIF from the filter 62 is supplied to the video intermediate frequency filter 71 to extract the digital video intermediate frequency signal, and the ghost component is removed from this signal by the ghost removal circuit 72. After that, the digital color video signal is demodulated by being supplied to the demodulation circuit 73. The digital signal is supplied to the D / A converter circuit 74 and D / A converted into an analog color video signal, and this color video signal is output to the terminal pin T63.

  Further, at the time of receiving an analog television broadcast, the digital intermediate frequency signal SIF from the filter 62 is supplied to the audio intermediate frequency filter 81 and the digital audio intermediate frequency signal is taken out, and this signal is supplied to the demodulation circuit 82 and is supplied to the digital audio signal. Is demodulated. This digital audio signal is supplied to the D / A converter circuit 84 and D / A converted into audio signals of the left and right channels, and these audio signals are output to the terminal pins T64 and T65.

  Further, the AGC voltage VAGC is formed in the AGC voltage forming circuit 91, and this AGC voltage VAGC is output to the terminal pin T67 and supplied to the terminal pin T16 of the front end circuit 10. As described above, the normal AGC and the delayed AGC are Done.

  Further, a clock having a predetermined frequency is formed in the clock forming circuit 92, and this clock is supplied to each part of the baseband processing circuit 60, and is also transmitted through the terminal pin T66 and further through the terminal pin T14 of the front end circuit 10. It is supplied to the forming circuit 34.

[2] Input Circuit of Mixer Circuit According to the Invention [2-1] Outline of Input Circuit of Mixer Circuit According to the Invention FIG. 3 shows an outline of an example of input circuits of the mixer circuits 21I and 21Q according to the invention. A specific connection example of this input circuit will be described in detail in [2-2], but the signal system is configured in a balanced manner.

  That is, the input buffer circuits 15A to 15C are connected to the output terminals of the tuning circuits 14A to 14C, and the output terminals of these input buffer circuits 15A to 15C are connected in common to form a pair of connection points P15 and P15.

  Then, the reception band switching signal SBAND is extracted from the buffer memory 52, and this band switching signal SBAND is supplied as a control signal for the operation of the input buffer circuits 15A to 15C. The operation of the input buffer circuit in the reception band including the channel is permitted, and the operation of the input buffer circuits in other reception bands is prohibited.

  Therefore, the input buffer circuits 15A to 15C operate equivalently as the switch circuit 15, and the reception signal SRX of the target channel is output to the common connection points P15 and P15 in a balanced manner.

  The reception signal SRX output to the common connection points P15 and P15 is supplied to the mixer circuits 21I and 21Q. The mixer circuits 21I and 21Q are composed of a switching circuit 1 and a buffer amplifier 2, for example, as shown in FIG. Then, the local oscillation signals SLOI and SLOQ are supplied from the frequency dividing circuit 37 to the mixer circuits 21I and 21Q. At this time, a predetermined reference voltage VS is supplied from the constant voltage circuit 53 to the mixer circuits 21I and 21Q. Therefore, the signals SIFI and SIFQ are output from the mixer circuits 21I and 21Q.

  Further, a pair of resistors R61 and R62 are connected in series between the common connection points P15 and P15, and the DC potential VRX contained in the reception signal SRX is taken out from the connection middle point. The DC potential VRX is supplied to the voltage comparison circuit 16A, the reference voltage VS is supplied to the voltage comparison circuit 16A, the two voltages are compared, and the comparison output is supplied to the input buffer circuit 15A through the buffer circuit 17A. Is supplied as a signal for feedback control.

  Similarly, the voltage comparison circuit 16B compares the voltage of the DC potential VRX and the reference voltage VS, and the comparison output is supplied as a DC potential feedback control signal to the input buffer circuit 15B through the buffer circuit 17B. The DC potential VRX and the reference voltage VS are compared in voltage by the voltage comparison circuit 16C, and the comparison output is supplied as a DC potential feedback control signal to the input buffer circuit 15C through the buffer circuit 17C.

  However, at this time, the band switching signal SBAND from the buffer memory 52 is supplied to the voltage comparison circuits 16A to 16C as a control signal for their operation, and is made effective by the switch circuits 11 and 15 among the voltage comparison circuits 16A to 16C. The operation of the voltage comparison circuit corresponding to the received band is permitted, and the operation of the other voltage comparison circuits is prohibited.

  According to such a configuration, when the operation of the input buffer circuit 15A is permitted by the band switching signal SBAND, for example, the DC potential VRX of the reception signal SRX output from the tuning circuit 14A and the reference voltage VS are The voltage comparison circuit 16A compares them. At this time, the operation of the voltage comparison circuits 16B and 16C is prohibited. As a result, the comparison output of the voltage comparison circuit 16A is fed back to the input buffer circuit 15A through the buffer circuit 17A. As a result of this feedback, the DC potential VRX of the reception signal SRX output from the tuning circuit 14A is made equal to the reference voltage VS. .

  Therefore, in the mixer circuits 21I and 21Q, the DC potential (= VRX) on the input side of the switching circuit 1 (see FIG. 6) is equal to the DC potential (= VS) on the output side, which increases noise and distortion. Or the local oscillation signals SIFI and SIFQ supplied to the gate can be prevented from leaking to the buffer amplifier 2.

  Further, even if capacitors corresponding to the coupling capacitors C1 and C2 in FIG. 7 are required, the input buffer circuits 15A to 15C can have the minimum necessary capacity. For example, the input buffer circuit 15C having a high frequency of the received signal SRX. In, the area required for the coupling capacitor can be reduced. Accordingly, since the parasitic capacitance is also reduced, the attenuation of the reception signal SRX can be suppressed, and the reception sensitivity and C / N are not reduced. Further, the distortion is not increased by affecting the high-frequency amplifiers 13A to 13C.

[2-2] Specific Example of Input Circuit of Mixer Circuit According to the Present Invention FIGS. 4 and 5 show specific connection examples of the input circuits of the mixer circuits 21I and 21Q according to the present invention. 4 and 5, the input circuit is shown divided for convenience of space, and # 1 to # 8 in FIGS. 4 and 5 are connected to each other. Note that the signal system of this input circuit is also configured in a balanced manner like the reception signal system. In the following, both the N-channel MOS-FET and the P-channel MOS-FET are simply referred to as “FETs” for the sake of simplicity, and the N-channel and the P-channel are referred to as necessary.

  4 mainly shows the input buffer circuit 15A of the switch circuit 15. The input buffer circuit 15A includes a buffer circuit 15P that handles one received signal + SRX of the balanced type received signals ± SRX, and the other received signal. A buffer circuit 15M that handles SRX.

  Then, the balance type received signal ± SRX is taken out from the tuning circuit 14A, and the received signal + SRX is complementary-connected through the capacitors C11 and C12, ie, the source follower FET, that is, the N channel FET (Q11) and the P channel FET. (Q12) is supplied to each gate. A predetermined bias voltage is supplied from the bias circuit 151 to the gate.

  The bias circuit 151 includes resistors R11 and R12, a drain and a source of a P-channel FET (Q13), a source and a drain of an N-channel FET (Q14), and a resistor R13 connected in series. A reception band switching signal SBAND is supplied from the buffer memory 52 to the resistor R11 of the series circuit, and the resistor R13 of the series circuit is commonly used for the sources of the P-channel FET (Q15) and the N-channel FET (Q16). Connected.

  The drain of the FET (Q15) is connected to the power supply line # 1, the drain of the FET (Q16) is connected to the ground line # 4, and the reception band switching signal is connected to the gates of these FETs (Q15, Q16). SBAND is supplied. The source of the FET (Q11, Q12) is connected to one of the connection points P15, P15.

  Therefore, when SBAND = "H" level, the "H" level voltage is supplied to the resistor R11. Since SBAND = "H" level, the FET (Q15) is turned off and the FET (Q16) is turned on, and the ground level of the ground line # 4 is supplied to the resistor R15. As a result, an appropriate bias voltage is supplied from the bias circuit 151 (series circuit of the elements R11 to R13) to the gates of the FETs (Q11, Q12), and the FETs (Q11, Q12) operate in the active region. From these sources, the received signal + SRX is taken out.

  However, when SBAND = "L" level, the "L" level voltage is supplied to the resistor R11. Since SBAND = "L" level, the FET (Q15) is turned on and the FET (Q16) is turned off, and the voltage of the power supply line # 1 is supplied to the resistor R15. As a result, a bias voltage having a reverse polarity is supplied from the bias circuit 151 to the gates of the FETs (Q11, Q12), and the FETs (Q11, Q12) are sufficiently turned off. + SRX is no longer output.

  Therefore, the buffer circuit 15P can turn on and off the reception signal + SRX, and operates in the active region when it is on.

  Further, the buffer circuit 15M is configured in exactly the same way as the buffer circuit 15M. Therefore, the buffer circuit 15M can turn on and off the reception signal -SRX and operates in the active region when it is on. . Further, the input buffer circuits 15B and 15C are configured similarly to the input buffer circuit 15A.

  Accordingly, one of the input buffer circuits 15A to 15C operates effectively in response to the reception band switching signal SBAND, and the reception circuits selected by the tuning circuits 14A to 14C through the input buffer circuit that is operating effectively. Signals ± SRX are taken out at connection points P15 and P15.

  Then, the received signals ± SRX taken out at the connection points P15 and P15 are supplied to the mixer circuits 21I and 21Q as shown in FIG. The mixer circuits 21I and 21Q are configured in a passive type by a pair of switching circuits 211 and a pair of buffer amplifiers 212, as in FIG.

  That is, the received signal + SRX is commonly supplied to the drains of the N-channel FETs (Q21, Q22) through the resistor R21, and the received signal -SRX is supplied to the drains of the N-channel FETs (Q23, Q24) through the resistor R22. While being supplied in common, the sources of the FETs (Q21, Q23) are connected to each other, and the sources of the FETs (Q22, Q24) are connected to each other. Thus, the switching circuit 211 is configured.

  A balanced local oscillation signal SLOI is supplied from the frequency divider 37 between the gates of the FETs (Q21, Q24) and the FETs (Q22, Q23), and a balanced signal is supplied from the switching circuit 211. SIFI is retrieved. A balanced buffer amplifier 212 is directly connected to the switching circuit 211, and a signal SIFI is extracted from the buffer amplifier 212. At this time, the reference voltage VS is supplied from the constant voltage circuit 53 to the buffer amplifier 212.

  Further, the mixer circuit 21Q is configured similarly to the mixer circuit 21I, and a balanced signal SIFQ is taken out.

  In order to make the DC potential on the input side of the switching circuit 211 equal to the DC potential (= VS) on the output side, the voltage comparison circuits 16A to 16C and the buffer circuits 17A to 17C described in [2-1] are provided. Thus, common mode feedback control is performed so that the DC potential on the input side of the switching circuit 211 is equal to the DC potential on the output side.

  That is, as shown in FIG. 5, the source of the N-channel FET (Q61, Q62) is connected to the drain of the N-channel FET (Q63) to form a differential amplifier 161, and the gate of the FET (Q61) A reference voltage VS is supplied. A pair of resistors R61 and R62 are connected in series between the connection points P15 and P15, and the DC potential VRX contained in the received signal SRX is taken out from the connection middle point. ) Is supplied to the gate.

  The drains of the P-channel FETs (Q65, Q66) are connected to the drains of the FETs (Q61, Q62). These FETs (Q65, Q66) constitute a current mirror circuit 162 having the power supply line # 1 as a reference potential point and the FET (Q66) as an input side.

  Further, the voltage obtained at the source of the FET (Q15, Q16) in FIG. 4 is supplied to the gate of the N-channel FET (Q68) as shown in FIG. The FET (Q68) is grounded, a constant current source Q67 is connected to the drain, and the drain is connected to the drain of the N-channel FET (Q64). This FET (Q64), together with the FET (Q63), constitutes a current mirror circuit 163 with the ground line # 4 as a reference potential point and the FET (Q64) as an input side.

  Therefore, when the input buffer circuit 15A is enabled (active state) by the reception band switching signal SBAND, since the sources of the FETs (Q15, Q16) are at "L" level, the FET (Q68) is off. As a result, the output current of the constant current source Q67 is supplied to the FET (Q64), and a constant current having the same magnitude as the output current of the constant current source Q67 flows through the FET (Q63). Therefore, the FETs (Q61, Q62) operate as the differential amplifier 161, and the FETs (Q65, Q66) also operate as the current mirror circuit 162.

  As a result, in the differential amplifier 161, the DC potential VRX (DC potential on the input side of the switching circuit 211) is compared with the reference voltage VS (DC potential on the output side of the switching circuit 211), and the comparison output (error) Voltage) VERR is output from the drain of FET (Q61, Q65). In this case, the error voltage VERR is caused by the input buffer circuit 15A. In addition, the differential amplifier 161 and the current mirror circuit 162 operate as the voltage comparison circuit 16A.

  When the input buffer circuit 15B or 15C is enabled by the reception band switching signal SBAND, the source of the FET (Q15, Q16) is “H” level, so the FET (Q68) is on. As a result, the output current of the constant current source Q67 is bypassed by the FET (Q68), the FET (Q63) is turned off, and the differential amplifier 161 and the current mirror circuit 162 do not operate. As a result, even if the DC potential VRX is output from the connection midpoint of the resistors R61 and R62, the error voltage VERR is not output from the voltage comparison circuit 16A.

  In this case, since the input buffer circuit 15A is enabled by the reception band switching signal SBAND, the error voltage VERR from the voltage comparison circuit 16A constitutes the buffer circuit 17A as shown in FIG. The N channel FETs (Q71, Q72) are supplied to the gates thereof, and their sources are connected to the drains of the constant current source FET (Q73). The drain of the FET (Q71) is connected to the connection point between the resistor R11 and the resistor R12 of the bias circuit 151 in the buffer circuit 15P, and the drain of the FET (Q72) is the resistance of the bias circuit 151 in the buffer circuit 15M. Connected to the connection point of the resistor R11 and the resistor R12.

  In the buffer circuit 17A, the capacitor C71 and the resistor R71 are for removing the component of the reception signal SRX that remains in the error voltage VERR. Further, the voltage comparison circuits 16B and 16C and the buffer circuits 17B and 17C are configured similarly to the voltage comparison circuit 16A and the buffer circuit 17A.

  According to such a configuration, when the input buffer circuit 15A is enabled (active state) by the reception band switching signal SBAND, for example, the error voltage VERR caused by the input buffer circuit 15A is as described above. Since the error voltage VERR is output from the voltage comparison circuit 16A and supplied to the gates of the FETs (Q71, Q72), the resistors R11, R12 of the buffer circuit 15P are being connected corresponding to the magnitude of the error voltage VERR. The voltage at the point and the voltage at the midpoint of connection of the resistors R11 and R12 of the buffer circuit 15M change.

  As a result, the DC potential of each source of the FETs (Q11, Q12) and (Q11, Q12) of the input buffer circuit 15A, that is, the DC potential VRX of the reception signal ± SRX output from the input buffer circuit 15A is feedback-controlled. This coincides with the reference DC potential VS. That is, the DC potential on the input side of the switching circuit 211 is equal to the DC potential on the output side. The above operation is the same when the input buffer circuit 15B or 15C is enabled.

  Thus, according to the circuits of FIGS. 4 and 5, no DC offset is generated between the input side and the output side of the switching circuit 211, so that an increase in noise and distortion can be suppressed or supplied to the gate. It is possible to prevent the local oscillation signal SIFI (and SIFQ) being leaked to the buffer amplifier 2.

  The input buffer circuits 15A to 15C require coupling capacitors C11 and C12. However, the input buffer circuits 15A to 15C can have the minimum capacity for each of the input buffer circuits 15A to 15C. For example, in the input buffer circuit 15C having a high received signal frequency. Reduces the area required for the capacitors C11 and C12. Accordingly, since the parasitic capacitance is also reduced, the attenuation of the reception signal SRX can be suppressed, and the reception sensitivity and C / N are not reduced. Further, the distortion is not increased by affecting the high-frequency amplifiers 13A to 13C.

  Furthermore, the capacitors C11 and C12 and the input impedance of the FETs (Q11 and Q12) constitute a high-pass filter. However, since the FETs (Q11 and Q12) are used as source followers and the input impedance is high, the capacitors C11 and C12 are Even with a small capacity, the cutoff frequency can be lowered, which is particularly advantageous in the input buffer circuit 15A that handles the lowest frequency band.

  Further, since the load impedance of the FETs (Q11, Q12) is only the mixer circuits 21I, 21Q and the parasitic capacitance, the load is less affected by the increase in frequency, and the FETs (Q11, Q12) operate as a source follower. Deterioration of distortion at the time can be suppressed.

  Furthermore, the output impedance of the FETs (Q11, Q12) is determined by the bias current, the magnitude of the switching FETs (Q21 to Q24), and the resistors R21, R22. Bands can be switched efficiently.

  Further, the error voltage VERR from the voltage comparison circuits 16A to 16C is fed back to the buffer circuits 15P and 15M in the common mode, and since the feedback is only this common mode, the reception characteristics are hardly affected. .

[3] Summary The mixer circuit and its input circuit are summarized as follows. That is,
(11) One IC can correspond to the passive mixer circuits 21I and 21Q over a wide frequency range of 46 to 887 MHz.

  (12) Since the reception band is divided and the high-frequency input stage is selectively operated, one set of mixer circuits 21I and 21Q can cope with a wide frequency range.

  (13) Since no DC offset is generated between the input side and output side of the switching circuit 211, an increase in noise and distortion can be suppressed, or the local oscillation signal SIFI (and SIFQ supplied to the gate) ) Can be prevented from leaking to the buffer amplifier 2.

  (14) The input buffer circuits 15A to 15C require the coupling capacitors C11 and C12. However, the input buffer circuits 15A to 15C can have the minimum necessary capacity for each of the input buffer circuits 15A to 15C. In, the area required for the capacitors C11 and C12 is reduced. Accordingly, since the parasitic capacitance is also reduced, the attenuation of the reception signal SRX can be suppressed, and the reception sensitivity and C / N are not reduced. Further, the distortion is not increased by affecting the high-frequency amplifiers 13A to 13C.

  (15) Since the FETs (Q11, Q12) are source followers and have high input impedance, the cut-off frequency can be lowered even when the capacitors C11, C12 are small, and the input buffer circuit handles the lowest frequency band in particular. Advantageous at 15A.

  (16) Since the load impedance of the FETs (Q11, Q12) is only the mixer circuits 21I, 21Q and the parasitic capacitance, the load is less affected by the increase in frequency, and the FETs (Q11, Q12) operate as a source follower. Degradation of distortion when doing so can be reduced even at high frequencies.

  (17) The output impedance of the FETs (Q11, Q12) is determined by the bias current, the size of the switching FETs (Q21-Q24), and the resistors R21, R22. The reception band can be switched efficiently.

  (18) The error voltage VERR from the voltage comparison circuits 16A to 16C is fed back to the buffer circuits 15P to 15M in the common mode, and since the feedback is only in the common mode, the error voltage VERR almost affects the reception characteristics. Absent.

  (19) Although the reception band is divided into three, since the mixer circuits 21I and 21Q are one set, the number of adjustment points is small and the number of switching is also small, so that the stability is improved.

  (20) For example, when the input buffer circuit 15A is off, the FETs (Q11, Q12) are reverse-biased by the bias circuit 151, so that a large level received signal SRX is supplied to the FETs (Q11, Q12). However, the off state of the FETs (Q11, Q12) can be maintained.

  (21) Since only the tuning circuits 14A to 14C are connected to the high frequency amplifiers 13A to 13C, respectively, the load is light and the high frequency amplifiers 13A to 13C can be reduced in distortion.

  (22) Since the high frequency amplifiers 13A to 13C can be set to low distortion, it is possible to make use of the fact that the passive mixer circuits 21I and 21Q have low distortion.

  (23) It is possible to absorb variations in characteristics in the manufacture of MOS-FETs and always perform a good mixer process.

[4] Others In the above, the intermediate frequency signal component of the received signal SRX in the signals SIFI and SIFQ is reversed in phase by the local oscillation signals SLOI and SLOQ and the complex bandpass filter 24, and the intermediate frequency signal component of the image disturbing signal SUD is in phase. In this case, the intermediate frequency signal SIF of the received signal SRX can be obtained by subtracting the signal SIFI and the signal SIF1.

  Further, the connection position of the amplitude phase correction circuit 23 and the complex bandpass filter 24 can be reversed.

Furthermore, in the amplifier 25, if the equation (6) is subtracted from the equation (5),
SIF = SIFI-SIFQ
= 2β · cosωIFt
= EUD / ELO / cosωIFt (8)
Thus, since the image disturbing signal SUD can be taken out, the amplitude and phase of the signals SIFI and SIFQ can be corrected in the amplitude phase correcting circuit 23 so that the image disturbing signal SUD is minimized.

[List of abbreviations]
A / D: Analog to Digital
AGC: Automatic Gain Control
C / N: Carrier to Noise ratio
CMOS: Complementary MOS
D / A: Digital to Analog
D / U: Desire to Undesire ratio
FET: Field Effect Transistor
IC: Integrated Circuit
MOS: Metal Oxide Semiconductor
NTSC: National Television System Committee
PAL: Phase Alternation by Line
PLL: Phase Locked Loop
SECAM: Sequential a Memoire Color Television System
VCO: Voltage Controlled Oscillator

It is a systematic diagram showing one form of a front end circuit to which the present invention can be applied. It is a systematic diagram which shows one form of the baseband process part which can be connected to the circuit of FIG. It is a systematic diagram showing one embodiment of the present invention. It is a connection diagram which shows a part of one form of this invention. FIG. 5 is a connection diagram showing a continuation of FIG. 4. It is a connection diagram which shows an example of a mixer circuit. It is a connection diagram which shows the other example of a mixer circuit.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... Front end circuit (IC), 12A-12C ... Antenna tuning circuit, 13A-13C ... High frequency amplifier, 14A-14C ... Interstage tuning circuit, 15A-15C ... Input buffer circuit, 16A-16C ... Voltage comparison circuit, 17A ˜17C: Buffer circuit, 21A and 21B: Mixer circuit, 22: Low pass filter, 23: Amplitude phase correction circuit, 24: Complex band pass filter, 25: Level correction amplifier, 26: Variable gain amplifier, 27: Band pass filter, DESCRIPTION OF SYMBOLS 30 ... PLL, 37 ... Frequency divider circuit, 41 ... Level detection circuit, 43 ... Delay AGC voltage formation circuit, 44 ... Linear detection circuit, 51 ... Non-volatile memory, 52 ... Buffer memory, 53 ... Constant voltage circuit, 60 ... Base Band processing circuit (IC)

Claims (4)

One of the drain and source of the MOS-FET is connected to the output terminal of the signal source of the received signal,
The other of the drain and the source is connected to the input terminal of the buffer amplifier,
A local oscillation signal is supplied to the gate of the MOS-FET,
A signal obtained by switching the received signal with the local oscillation signal is supplied to the buffer amplifier.
A voltage comparison circuit that compares the voltage between the DC potential at the output terminal of the signal source and the DC potential at the input terminal of the buffer amplifier;
The input circuit of the mixer circuit that feeds back the comparison output of the voltage comparison circuit to the signal source so that the DC potential of the output end of the signal source is equal to the DC potential of the input end of the buffer amplifier. . The input circuit of the mixer circuit according to claim 1,
The output stage of the signal source is a complementary-connected MOS-FET,
An input circuit of a mixer circuit in which a bias circuit for supplying a bias voltage to the gate of the MOS-FET is controlled by a comparison output of the voltage comparison circuit. The input circuit of the mixer circuit according to claim 2,
The signal source is a plurality,
The output ends of the plurality of signal sources are connected to each other,
An input circuit for a mixer circuit, wherein a switching signal for selectively switching the plurality of signal sources to be supplied to the mixer circuit is supplied to the bias circuit. The input circuit of the mixer circuit according to claim 3,
An input circuit for a mixer circuit, wherein the plurality of signal sources are selectively switched by reversing the polarity when the switching signal is supplied to the bias circuit.

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