JP2001053564A - Current switching circuit, variable gain amplifier and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a variable gain amplifier with superior various characteristics. SOLUTION: Attenuator circuits 32 to 34 cascade-connected to input signals, amplifiers 42 to 44 for respectively supplying the respective output signals of the attenuator circuits 32 to 34 and resistors R55 and R56 connected in common to the output ends of the amplifiers 42 to 44 are provided. An operation current source in common with the amplifiers 42 to 44, plural transistors whose collector and emitter are respectively serially provided in a current line between the amplifiers 42 to 44 and the operation current source, the plural resistors respectively connected between the bases of the transistors and plural current sources for making a prescribed current respectively flow to the resistors are provided. By controlling the current made to respectively flow to the resistors by the current source corresponding to control signals, level controlled output signals are obtained from the resistors R55 and R56.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a current switching circuit, a variable gain amplifier, and a receiver using the same.

[0002]

2. Description of the Related Art As digital audio broadcasting, DAB (digital audio broadcasting according to the Eureka 147 standard) is adopted in Europe, and ISDB-T is proposed in Japan.

[0003] ISDB-T has a transmission bandwidth of 432 kHz (in the case of narrow-band ISDB-T). Modulation method: OFDM multiplexing method: By adopting MPEG2, digital audio data and digital data of a plurality of channels can be simultaneously transmitted. Broadcast. In the case of narrow-band ISDB-T, the current VHF television broadcasting band is scheduled to be used for broadcasting.

An AM receiver is provided with an AGC circuit, and is controlled so that the level of the AM detection output is constant irrespective of the received electric field intensity. That is, a variable gain amplifier is provided in the signal line of the high frequency signal or the intermediate frequency signal, and the gain is feedback-controlled by the DC voltage (AGC voltage) included in the AM detection output.

In a digital audio broadcasting receiver, even if the main signal processing circuit performs digital processing,
Since analog processing is performed up to the preceding stage, an AGC circuit is required.

As a variable gain amplifier that can be used in an AGC circuit, for example, there is a circuit as shown in FIG.
That is, the output signal of the signal source A10 is
Attenuator circuits A11 to A13
, Signals whose levels are sequentially reduced are output. The output signal is supplied to the differential amplifiers A21 to A23, respectively, and the output signal of the signal source A10 is supplied to the differential amplifier A20. The differential amplifiers A20 to A23 are connected to common load resistors Ra and Rb.

The following operation is performed according to the magnitude relationship between the control voltage VCTL and the bias voltages Va, Vb, Vc.

(A) When VCTL <Va Since the transistor Qa is turned on and the transistor Qb is turned off, the constant current source Qg is connected to the differential amplifier A20, and only the differential amplifier A20 becomes effective. Operate. Therefore, the output signal of the signal source A10 is taken out to the resistors Ra and Rb through the differential amplifier A20.

(B) When Va <VCTL <Va + Vb The transistor Qa is turned off, the transistor Qb is turned on, the transistor Qc is turned on, and the transistor Qd is turned off. As a result, the differential amplifier A21 only operates effectively. Therefore, the attenuator circuit A
The output signal of 11 is passed through a differential amplifier A21 to a resistor Ra,
Rb.

(C) Va + Vb <VCTL <Va + Vb + V
At the time of c, the transistors Qe, Qd, and Qb are turned on, and only the differential amplifier A22 operates effectively.
Twelve output signals are passed through a differential amplifier A22 to a resistor Ra,
Rb.

(D) When VCTL> Va + Vb + Vc Since the transistors Qf, Qd, and Qb are turned on and only the differential amplifier A23 operates effectively, the attenuator circuit A
The 13 output signals are passed through a differential amplifier A23 to a resistor Ra,
Rb.

Therefore, the circuit shown in FIG.
The CTL operates as a variable gain amplifier whose gain changes in four stages.

Further, the transistors Qa to Qf
Is also operated in the active region, so that the transistor Q
The collector currents of a, Qc, Qe and Qf are controlled by the control voltage VCT.
By changing L as shown in FIG. 14, for example, the gain can be changed continuously.

That is, for example, when VCTL = Va, the output current of the constant current source Qg is determined by the transistors Qa and Qc.
The differential amplifiers A20 and A21 operate effectively. Therefore,
The output signal of the signal source A10 is taken out through the differential amplifier A20, and the output signal of the attenuator circuit A11 is output from the differential amplifier A20.
At this time, the output current of the differential amplifier A20 and the output current of the differential amplifier A21 are added in the resistors Ra and Rb.

However, at this time, the differential amplifiers A20, A21
Is the current obtained by shunting the output current of the constant current source Qg, and is smaller than when the transistors Qa and Qc are completely turned on. Therefore, the gain of the differential amplifiers A20 and A21 is as follows. It is smaller than when it is completely on.

Therefore, when VCTL = Va, the variable gain amplifier has a gain when only the differential amplifier A20 is effectively operating and a gain when only the differential amplifier A21 is effectively operating. Gain between the two. And
If the control voltage VCTL moves away from the reference voltage Va, the ratio when the output current of the constant current source Qg is shunted to the transistors Qa and Qc changes in accordance with the control voltage VCTL. It changes from the gain when VCTL = Va.

Accordingly, the variable gain amplifier has a continuous gain ranging from the maximum gain determined by the differential amplifier A20 to the minimum gain determined by the attenuator circuits A11 to A13 and the differential amplifier A23 in accordance with the control voltage VCTL. Will change.

[0018]

As described above, FIG.
Operates as a variable gain amplifier. In this variable gain amplifier, the stacked transistors Qf
Control voltage VCTL between the base and emitter of Qd, Qd and Qb
When the gain is minimized, that is, when the transistor Qf is turned on, the value of the control voltage VCTL increases, which is disadvantageous for lowering the operating voltage. If the number of stages of the attenuator circuit and the differential amplifier is increased to expand the range, the transistors corresponding to the transistors Qa to Qf are further stacked, so that it becomes more difficult to reduce the voltage. In particular, as shown in FIG.
If the voltages Va to Vc are set so that f operates in the active region, it becomes more difficult to lower the voltage.

Further, when the variable gain amplifier is used in an AGC circuit of a digital audio broadcasting receiver, the variable gain amplifier is required to have low distortion. That is, D
In AB and ISDB-T, one broadcast wave is composed of a plurality of carrier signals. For example, narrowband ISDB-
In the case of T, the broadcast wave is composed of 109 carrier signals distributed every 4 kHz in mode 1, and is composed of 433 carrier signals distributed every 1 kHz in mode 2.

Therefore, in a digital audio broadcasting receiver, if the linearity of the variable gain amplifier is poor, the received signal and the intermediate frequency signal passing through the variable gain amplifier will be distorted, and the distortion component will be reduced to the original carrier. Sometimes indistinguishable from a signal. Therefore, it is required that the variable gain amplifier used in the AGC circuit of the digital audio broadcasting receiver has less distortion.

The present invention seeks to solve the above problems.

[0022]

According to the present invention, for example, a plurality of attenuator circuits cascade-connected to an input signal, a plurality of amplifiers to which respective output signals of the plurality of attenuator circuits are respectively supplied, An extraction circuit commonly connected to the output terminals of the plurality of amplifiers, an operating current source common to the plurality of amplifiers, and a collector line connected to a current line between the plurality of amplifiers and the operating current source. A plurality of transistors each having a series connection between the emitters, a plurality of resistors respectively connected between the bases of the plurality of transistors, and a plurality of current sources for supplying a predetermined current to the plurality of resistors, respectively; Has,
The variable gain amplifier is configured such that the plurality of current sources control the currents flowing through the plurality of resistors in accordance with a control signal, thereby obtaining an output signal whose level is controlled from the extraction circuit. Therefore, the current supplied from the common operating current source to the plurality of amplifiers changes according to the control signal, and the output signals of the plurality of attenuator circuits are continuously switched and output.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [ISDB-T Receiver (No. 1)] An ISDB-T receiver is configured as shown in FIG. 1, for example. FIG. 1 shows a case of a receiver for a narrow band ISDB-T, which is a case where a direct conversion system is configured.

That is, a broadcast wave of the narrow band ISDB-T is received by the antenna 11, and the received signal is supplied to an antenna tuning circuit 12 of an electronic tuning system, and a reception signal S12 of a target frequency is taken out. S12 is AG
It is supplied to mixer circuits 15A and 15B through a variable gain amplifier 13 for C and an inter-stage tuning circuit 14 of an electronic tuning system. The details of the variable gain amplifier 13 will be described later.

An oscillation signal having a frequency twice as high as the carrier frequency (center frequency) of the reception signal S12 is formed in the PLL 21, and this oscillation signal is supplied to the frequency dividing circuit 22 and equal to the carrier frequency of the reception signal S12. Further, the frequency is divided into two signals whose phases are different from each other by 90 °, and the divided signal is supplied to the mixer circuits 15A and 15B as a local oscillation signal.

Thus, in the mixer circuits 15A and 15B, the received signal S12 is frequency-converted into baseband signals S15A and S15B whose phases are different from each other by 90 °, ie, I-axis and Q-axis baseband signals S15A and S15B.

At this time, from the PLL 21, the V
A part of the control voltage supplied to the variable capacitance diode of CO (not shown) is extracted, and this control voltage is supplied to the tuning circuit 1.
2 and 14 are supplied as tuning voltages, and tuning to the received signal S12 is realized.

The signals S15A and S15B from the mixer circuits 15A and 15B are supplied to the low-pass filters 16A and 16A, respectively.
B → AGC variable gain amplifiers 17A, 17B → Supplied to demodulation circuit 19 through signal lines of low-pass filters 18A, 18B. Although not shown, the demodulation circuit 19 performs complex Fourier transform, frequency deinterleaving, time deinterleaving, and digital decoding of a target channel among a plurality of channels in correspondence with a modulation process at the time of ISDB-T transmission. It performs demodulation processing such as audio data selection, error correction and data decompression.

Therefore, from the demodulation circuit 19, audio signals L and R of a target program out of a plurality of programs (channels) are extracted.

At this time, the low-pass filter 18
Signals S15A and S15B from A and 18B are supplied to an AGC detection circuit 25 to form an AGC voltage V25.
The C voltage V25 is supplied to the variable gain amplifiers 17A and 17B as a gain control signal.

Further, the signals S15A and S15B from the mixer circuits 15A and 15B are supplied to an AGC detection circuit 23 to form a delayed AGC voltage V23. The AGC voltage V23 is supplied to an addition circuit 24 and the AGC voltage V25 Is supplied to the adding circuit 24. Then, an addition voltage V24 of the AGC voltages V23 and V25 is taken out from the addition circuit 24,
This voltage V24 is supplied to the variable gain amplifier 13 as a gain control signal.

Therefore, the AGC is performed on the received signal S12 from the tuning circuit 12 by the AGC voltage V24, and the low-pass filter 16 is controlled by the AGC voltage V25.
AGC is performed on the baseband signals S15A and S15B from A and 16B. At this time, since the AGC voltage V24 is an added voltage of the delayed AGC voltage V23 and the AGC voltage V25, the AGC range for the reception signal S12 can be expanded.

The receiver is provided with tuning circuits 12, 1
4. PLL 21 VCO resonance circuit and demodulation circuit 19
Except for the above, a one-chip IC can be realized.

[ISDB-T Receiver (Part 2)] FIG.
The case where the narrow band ISDB-T receiver is configured in a superheterodyne system.

That is, a broadcast wave of the narrow band ISDB-T is received by the antenna 11, and the received signal is supplied to an antenna tuning circuit 12 of an electronic tuning system to extract a reception signal S12 of a target frequency. S12 is AG
It is supplied to mixer circuits 15A and 15B through a variable gain amplifier 13 for C and an inter-stage tuning circuit 14 of an electronic tuning system.

Further, an oscillation signal having a predetermined frequency is formed in the PLL 21, and this oscillation signal is supplied to the frequency dividing circuit 22, and the carrier frequency (center frequency) of the reception signal S12 is generated.
For example, 500 kHz higher and the phases are 90
The signal is divided into two different signals, and the divided signal is supplied to the mixer circuits 15A and 15B as a local oscillation signal.

Thus, in the mixer circuits 15A and 15B, the received signal S12 is frequency-converted into two intermediate frequency signals S15A and S15B (intermediate frequency is 500 kHz) whose phases are different from each other by 90 °.

At this time, from the PLL 21, the V
A part of the control voltage supplied to the variable capacitance diode of CO (not shown) is extracted, and this control voltage is supplied to the tuning circuit 1.
2 and 14 are supplied as tuning voltages, and tuning to the received signal S12 is realized.

Then, the intermediate frequency signals S15A and S15B from the mixer circuits 15A and 15B are
A and 16B are supplied to the phase shift circuits 26A and 26B. In the phase shift circuits 26A and 26B, for example, the original signal components included in the intermediate frequency signals S15A and S15B have the same phase, and the image components have the opposite phase. Phase-shifted. Then, the intermediate frequency signal S15A after this phase shift,
S15B is supplied to the adding circuit 27, from which the image component is canceled and an intermediate frequency signal S15 having the original signal component is extracted.

Subsequently, the intermediate frequency signal S15 is supplied to the demodulation circuit 19 through the signal line of the band pass filter 28 for the intermediate frequency filter, the variable gain amplifier 17 for the AGC, and the low pass filter 18. , Audio signals L and R of a target program out of a plurality of programs are extracted.

At this time, the intermediate frequency signal S15 from the low-pass filter 18 is supplied to the AGC detection circuit 25 to form an AGC voltage V25. The AGC voltage V25 is supplied to the variable gain amplifier 17 as a gain control signal. You.

Further, low-pass filters 16A, 16B
The intermediate frequency signals S15A and S15B from the AGC detection circuit 2
3 to form a delayed AGC voltage V23.
The GC voltage V23 is supplied to the addition circuit 24, and A
The GC voltage V25 is supplied to the adding circuit 24. Then, the addition circuit 24 outputs the addition voltage V24 of the AGC voltages V23 and V25.
The voltage V24 is supplied to the variable gain amplifier 13 as a gain control signal.

Therefore, the AGC is performed on the received signal S12 from the tuning circuit 12 by the AGC voltage V24, and the bandpass filter 28 is controlled by the AGC voltage V25.
The AGC is performed on the intermediate frequency signal S15 from the AGC.

[Variable Gain Amplifier] Variable Gain Amplifier 13
Is configured as shown in FIGS. 3 and 4, for example. 3 and 4 show the variable gain amplifier 13 divided into two parts for the sake of space, and the right side of FIG.
Continue to the left of

The variable gain amplifier 13 shown in FIGS. 3 and 4 includes four cascade-connected attenuator circuits 31-31.
34, differential amplifiers 40 to 44 for extracting the input signal and the output signal of each stage, and cascode amplifiers 51 to 54
And a current switching circuit 60.

That is, in the variable gain amplifier 13 shown in FIGS. 3 and 4, the series circuit of the resistors R01 to R03 is connected to the secondary coil L12 of the tuning coil (not shown) of the tuning circuit 12, and the tuning circuit 12 , The received signal S12 is extracted in a balanced manner. At this time, the output impedance of the tuning circuit 12 is, for example, 50Ω.

Further, the attenuator circuits 31 to 34
For example, the configuration is as shown in FIG. That is, the capacitor C is connected between one input terminal T31 and the output terminal T33.
31 and a parallel circuit of a resistor R31 are connected,
A parallel circuit of a resistor R32 and a capacitor C32 is connected between the output terminal T33 and the midpoint terminal T35. A capacitor C is connected between the other input terminal T32 and the output terminal T34.
33 and a parallel circuit of a resistor R33 are connected,
A parallel circuit of a resistor R34 and a capacitor C34 is connected between the output terminal T34 and the midpoint terminal T35.

Thus, the balance type attenuator circuits 31 to 34 are respectively constituted by the elements R31 to R34 and C31 to C34.

The attenuator circuits 31 to 3
4 also constitutes a balance type ladder attenuator circuit 30. Of the attenuator circuits 31 to 34, the output terminals T33 and T34 of the previous stage attenuator circuit are connected to the input terminals T31 and T32 of the next stage attenuator circuit. Connected. The input terminals T31, T31 of the attenuator circuit 31
32 is connected to the output terminal of the tuning circuit 12, that is, both ends of the resistor R02, and the terminals T35 are connected to each other.

In this case, the attenuator circuit 31
In each of 34, C31 ・ R31 = C32 ・ R32 C33 ・ R33 = C34 ・ R34.

When the attenuation amounts of the attenuator circuits 31 to 34 are made equal, the attenuator circuits 31 to 34
3, the values of the elements R31 to R34 and C31 to C34 are made equal to each other, and the elements R32 and R34 of the attenuator circuit 34
Is half the value of the elements R32 and R34 of the attenuator circuit 31, and the values of the elements C32 and C32 of the attenuator circuit 34 are
The value of 34 is twice the value of the elements C32 and C34 of the attenuator circuit 31.

Further, the attenuation per stage of each of the attenuator circuits 31 to 34 is 1 / n [times] (where n> 1).
Then, R32 / R31 = 2 / (n-1) C31 / C32 = 2 / (n-1) For example, the attenuation per stage is 8 dB.

3 and 4, transistors (Q11, Q12) to (Q41, Q42) are provided, and the bases of the transistors Q01, Q02 are connected to both ends of the resistor R02, respectively. The base is connected to the output terminals T33 and T34 of the attenuator circuit 31, respectively.

Similarly, transistors (Q21, Q22),
The bases of (Q31, Q32) and (Q41, Q42) are the output terminals (T33, T34) of the attenuator circuits 32, 33, 34,
(T33, T34) and (T33, T34). The transistors (Q01, Q02) to (Q41, Q
42) is the current terminal T of the current switching circuit 60
60 to T64.

The details of the current switching circuit 60 will be described later. However, the current switching circuit 60 has an AGC voltage V24 (like the transistors Qa to Qf in FIG. 13).
, The constant current source inside the current switching circuit 60 is connected to one of the current terminals T60 to T64.
The suction-type constant currents I03 to I43 are selectively supplied to 60 to T64. Therefore, the transistors (Q01, Q0
2) Among (Q41, Q42), the transistor in which a constant current flows operates as a differential amplifier.

A DC bias power supply VBB is connected between the terminals T35 of the attenuator circuits 31 to 34 and the ground.

Then, the collectors of the transistors Q01 and Q11 are connected to the emitter of the transistor Q51 having a common base to form a cascode amplifier 51. The collectors of the transistors Q02 and Q12 are connected to the transistor Q51 having a common base.
The cascode amplifier 52 is configured by being connected to the emitter of the cascode amplifier 52.

The collectors of the transistors Q21, Q31 and Q41 are connected to the emitter of a transistor Q53 having a common base to form a cascode amplifier 53. The collectors of the transistors Q22, Q32 and Q42 are connected to the emitter of a transistor Q54 having a common base. Are connected to the cascode amplifier 54.

Further, in this case, the transistors Q51, Q51
Each collector of 53 is connected to a common load resistor R55, and each collector of transistors Q52 and Q54 is also connected to a common load resistor R56. The signals obtained from these load resistors R55 and R56 are tuned to the next-stage tuning circuit. 14. Further, the emitters of the transistors Q51 to Q54 are pulled up to the power supply potential + VCC by the resistors R51 to R54.

According to such a configuration, when the reception signal S12 is output from the tuning circuit 12, this signal S12 is attenuated by the attenuator circuits 31 to 34 in order of, for example, 8 dB. A received signal S12 whose level is sequentially reduced by 8 dB is output.

The bias voltage from the DC bias power supply VBB is applied to the resistors R31 to R31 of the attenuator circuits 31 to 34.
It is supplied to the bases of the transistors Q01 to Q42 through R34.

At this time, the following operation is performed according to the magnitude of the AGC voltage V24. In addition,
Hereinafter, it is assumed that VL <VM <VH <VV.

In the case of V24 <VL In this case, in the current switching circuit 60, a constant current source is connected to the current terminal T60, and the transistors Q01 and Q02
Is supplied with a constant current I03. Therefore, the transistors Q01 and Q02 operate effectively as the differential amplifier 40, and the transistors Q01 and Q02 and the transistors Q51 and Q51
Q52 constitutes the cascode amplifiers 51 and 52. At this time, since no constant current is output to the current terminals T61 to T64, the transistors of the differential amplifiers 41 to 44 and the cascode amplifiers 53 and 54 are off.

Therefore, the received signal S12 output from the tuning circuit 12 is selected by the differential amplifier 40, and is connected to the resistor R5 through the cascode amplifiers 51 and 52.
5. Retrieved by R56 and output to the next stage.

In the case of VL ≦ V24 <VM In this case, in the current switching circuit 60, a constant current source is connected to the current terminal T61, and the transistors Q11 and Q12
Is supplied with a constant current I13. Therefore, the transistors Q11 and Q12 effectively operate as the differential amplifier 41, and the transistors Q11 and Q12 and the transistors Q51 and Q51
Q52 constitutes the cascode amplifiers 51 and 52.

Therefore, the received signal S12 output from the first stage attenuator circuit 31 is selected by the differential amplifier 41, and the cascode amplifiers 51 and 52 are selected.
Output to the next stage.

In the case of VM ≦ V24 <VH In this case, in the current switching circuit 60, a constant current source is connected to the current terminal T62, and the transistors Q21 and Q22
Is supplied with a constant current I23. Therefore, the transistors Q21 and Q22 effectively operate as the differential amplifier 42, and the transistors Q21 and Q22 and the transistors Q53 and Q53
Q54 constitutes the cascode amplifiers 53.

Therefore, the received signal S12 output from the second-stage attenuator circuit 32 is output through the differential amplifier 42 and the cascode amplifiers 53 and 54.

In the case of VH ≦ V24 <VV In this case, the transistor Q3 is connected through the current terminal T63.
1, a constant current I33 is supplied to Q32, and a transistor Q31,
Q32 effectively operates as the differential amplifier 43. Therefore, the received signal S12 output from the third-stage attenuator circuit 33 is output through the differential amplifier 43 and the cascode amplifiers 53 and 54.

In the case of VV ≦ V24 In this case, the transistor Q4 is connected through the current terminal T64.
1, a constant current I43 is supplied to Q42, and a transistor Q41,
Q42 effectively operates as the differential amplifier 44. Therefore, the reception signal S12 output from the fourth stage attenuator circuit 34 is output through the differential amplifier 44 and the cascode amplifiers 53 and 54.

Thus, the circuits of FIGS. 3 and 4
It operates as a variable gain amplifier whose gain changes in five stages when the gain is .about. By the C voltage V24.

Further, in this case, for example, the differential amplifier 4
If the current I03 of 0 and the current I13 of the differential amplifier 41 are continuously changed in the opposite directions, the gain of the differential amplifier 40 and the gain of the differential amplifier 41 are continuously changed in the opposite directions. Therefore, the total gain can be continuously changed from the gain when only the differential amplifier 40 is effectively operating to the gain when only the differential amplifier 41 is effectively operating. The same applies to the differential amplifiers 41 to 44.

Therefore, the gain of the variable gain amplifier is continuously changed from the maximum gain determined by the differential amplifier 40 to the minimum gain determined by the attenuator circuits 31 to 34 and the differential amplifier 44 corresponding to the AGC voltage V24. Will change.

As described above, according to the circuits of FIGS. 3 and 4, the output signals of the tuning circuit 12 and the attenuator circuits 31 to 34 are selected by the differential amplifiers 40 to 44 according to the AGC voltage V24, and the cascode amplifier 51, 5
2 or 53, 54. Therefore, the circuits of FIGS. 3 and 4 operate as the variable gain amplifier 13 whose gain changes continuously. At this time, AGC is performed.

In this case, since the reception signal S12 of an appropriate level is selected and extracted by the differential amplifiers 40 to 44 from the output signals of the tuning circuit 12 and the attenuator circuits 31 to 34, that is, the reception signal S12 Is adjusted to an appropriate level by the attenuator circuits 31 to 34 and then extracted by the differential amplifiers 40 to 44, so that generation of distortion can be suppressed.

Further, in the attenuator circuits 31 to 34, since the signal is divided or attenuated also by the capacitors C31 to C34, the value of the resistors R31 to R34 is sufficiently compared with the output impedance of the tuning circuit 12 of 50Ω. 1.25 kΩ, for example, so that the noise figure is not deteriorated by the resistors R31 to R34, and a variable gain amplifier with little noise can be obtained.

The bias voltage from the DC bias power supply VBB is applied to the transistor Q01 through resistors R31 to R34.
To Q32, it is not necessary to newly provide a circuit for supplying a bias voltage to the transistors Q01 to Q32.

Further, by adding the input capacitance of the transistors Q01 to Q32 to the value of the capacitors C31 to C34, the input capacitance can be ignored. Further, C
By setting 31 · R31 = C32 · R32 and C33 · R33 = C34 · R34, the frequency characteristics can be made flat. Therefore, the frequency characteristics can be broadened.

Further, for example, the reception signal S12 output from the attenuator circuit 34 is supplied to the load resistors R55 and R56 through the differential amplifier 44 and the cascode amplifiers 53 and 54.
(In this case), the transistors Q51 and Q52 are off, so that even if the reception signal S12 from the tuning circuit 12 leaks to the collector through the base-collector capacitance of the transistors Q01 and Q02. The leak signal is blocked by the transistors Q51 and Q52 and is not output to the load resistors R55 and R56. Therefore, the resistors R55 and R56 do not include a leak signal.
That is, the reception signal S12 of the target level is obtained.

Therefore, the attenuator circuits 31 to 34
In a case where the attenuator circuits and the differential amplifiers corresponding to the differential amplifiers 41 to 44 are connected in multiple stages to expand the gain control range or to widen the AGC range, this can be surely realized. For example, if the attenuation per stage of the attenuator circuit is 8 dB, 40
A variable gain range of dB can be obtained.

Further, for example, the transistors Q51 and Q52
Is off, its emitter is pulled up to the power supply potential by the resistors R51 and R52.
Since the transistors 51 and Q52 are sufficiently off, leak signals leaking to the collectors through the base-collector capacitances CBC and CBC of the transistors Q01 and Q02 can be reliably prevented.

For example, when the transistors Q51 and Q52 are off, their emitters are pulled up to the power supply potential by the resistors R51 and R52, and the base and collector are reverse-biased. Can be suppressed. Therefore, an input signal having a large level can be handled, and from this point, the gain control range can be widened.

Further, since the transistors Q51 to Q54 are cascode-connected to the differential amplifiers 40 to 44, even if the differential amplifiers 40 to 43 are connected in multiple stages, an increase in output parasitic capacitance can be suppressed. A decrease in gain at high frequencies can be suppressed.

Further, the frequency of the received signal S12 processed by the variable gain amplifier 13 can be made much higher than the frequency determined by the CR product of the element to be used. In this case, the attenuation of the attenuator circuits 31-33 Since the amount is determined only by the capacitance ratio of the capacitors C11 to C34, the transistor Q
It is only necessary to correct the input capacitance of 01 to Q32. Furthermore, I
C conversion is also possible.

In FIG. 3 and FIG. 4, the cascode amplifiers 51 to 54 prevent the leak signal in the differential amplifier from leaking to another differential amplifier. May be provided for each number of stages in which the leak signal cannot be ignored.

[Current Switching Circuit] First, the concept of the current switching circuit 60 will be described with reference to FIG. FIG.
, The current terminals T60 to T64 are connected to the collectors of the current switching transistors Q03, Q13, Q23, Q33, Q43.
Constant current source Q with ground as reference potential point between emitters
Commonly connected to 60.

A DC bias power supply VB0 is connected between the base of the transistor Q03 and the ground, and variable voltage sources VB1, VB2, VB3 and VB4 are connected between the bases of the transistors Q03, Q13, Q23, Q33 and Q43. Connected respectively.

In this case, the variable voltage sources VB1, VB2, VB3,
The output voltages VB1, VB2, VB3, and VB4 of VB4 are controlled and changed by the AGC voltage V24, and when V24 <VL, only the transistor Q03 is turned on. When VL≤V24 <VM, only the transistor Q13 is turned on. If VM ≤ V24 <VH, only transistor Q23 is turned on. If VH≤V24 <VV, only the transistor Q33 is turned on. If VV≤V24, only the transistor Q43 is turned on. It changes to realize.

Therefore, the voltages VB1 to VB4 change, for example, as follows according to the AGC voltage V24. That is, in the case of VB1 = −ΔV (+ ΔV indicates that the transistor Q03 side has a negative pole,
A voltage having a positive polarity on the transistor Q13 side. VB2 = 0, VB3 = 0, and VB4 = 0. Then
The transistors Q03 to Q43 are differentially connected to the constant current source Q60, the base potential of the transistor Q03 has the value VB0, and the base potential of the transistors Q13 to Q43 has the value (VB0-.DELTA.V). Therefore, the transistor Q03 is turned on, and the remaining transistors are turned off.

Note that, as described above, the transistors Q03 to Q43
Is turned on and off, so that ΔV = about 0.2 V.

In the case of VB1, VB1 = ΔV, VB2 = −ΔV, VB3 = 0, VB4 = 0. Then, the base potentials of the transistors Q03 and Q23 to Q43 have the value VB0, and the base potential of the transistor Q13 has the value (VB0 + ΔV). Therefore, transistor Q13
Is turned on, and the remaining transistors are turned off.

In the case of VB1, VB2 = 0, VB2 = ΔV, VB3 = −ΔV, and VB4 = 0. Then, the base potential of the transistors Q03, Q13, Q33, and Q43 becomes the value VB0, and the base potential of the transistor Q23 becomes the value (VB0 + ΔV). Therefore, the transistor Q23 is turned on, and the remaining transistors are turned off.

In this case, VB1 = 0, VB2 = 0, VB3 = .DELTA.V, and VB4 =-. DELTA.V. Then, the base potential of the transistors Q03 to Q23 and Q43 becomes the value VB0, and the base potential of the transistor Q33 becomes the value (VB0 + ΔV). Therefore, transistor Q33
Is turned on, and the remaining transistors are turned off.

In the case of VB1 = 0, VB2 = 0, VB3 = 0, VB4 = .DELTA.V. Then, the base potential of the transistors Q03 to Q33 becomes the value VB0, and the base potential of the transistor Q43 becomes the value (VB0 + Δ
V). Therefore, the transistor Q43 is turned on, and the remaining transistors are turned off.

Thus, in the circuit of FIG.
One of the transistors Q03 to Q43 is turned on in response to the voltage V24. When one of the transistors Q03 to Q43 is turned on, the output current I60 of the constant current source Q60 becomes
The current terminal T60 through the turned-on transistor
It flows to the corresponding current terminal of T64. Therefore,
The circuit in FIG. 6 operates as a current switching circuit 60 that distributes the constant current I60 to the terminals T60 to T64.

Further, in this case, for example, the control voltage VB
1. If VB2 is gradually changed from the case to the case, the transistor Q03 is gradually turned off from the on state and the transistor Q13 is gradually turned on from the off state. The current I03 gradually decreases from the maximum value I60 to 0, and the current I13 of the terminal T61 gradually increases from 0 to the maximum value I60.

Therefore, at this time, the variable gain amplifier 1
The gain of 3 continuously changes from the gain when only the differential amplifier 40 is operating effectively to the gain when only the differential amplifier 41 is operating effectively. This means that the currents I13 to I43 and the differential amplifier 41
The same applies to the range from to 44.

Therefore, according to the current switching circuit 60, the gain of the variable gain amplifier 13 is adjusted to the AGC voltage V24
Corresponding to the maximum gain determined by the differential amplifier 40, the attenuator circuits 31 to 34 and the differential amplifier 44
Can be continuously changed up to the minimum gain determined by

In that case, the transistors Q03 to Q03
In order to turn on any one of 43, the base potential of the transistor to be turned on should be a value (VB0 + ΔV),
At this time, since ΔV = about 0.2 V, it is easy to lower the voltage.

[Current Switching Circuit (Implementation Method)] The variable voltage sources VB1 to VB4 in the current switching circuit 60 of FIG.
Can be realized by a resistor and a constant current source that supplies a current to the resistor. That is, as shown in FIG. 7, for example, the current terminals T60 to T64 pass between the collectors and the emitters of the current switching transistors Q03, Q13, Q23, Q33 and Q43, and the constant current source Q60 having the ground as the reference potential point.
Connected in common.

A DC bias power supply VB0 is connected between the base of the transistor Q03 and the ground, and resistors R11, R12, R13 and R14 are connected between the bases of the transistors Q03, Q13, Q23, Q33 and Q43, respectively. Connected. In addition,
For example, R11 = R12 = R13 = R14.

Further, the transistors Q13, Q23, Q33,
The variable constant current sources Q61 and Q61 are connected between the base of Q43 and the ground.
62, Q63 and Q64 are connected respectively, and these constant current sources Q
The magnitude of the output currents I61 to I64 of 61 to Q64 is the AGC voltage V
Controlled by 24.

For example, I61 to I64 = 0, I64 = -IR
(However, IR = .DELTA.V / R14. The currents I61 to I64 are as shown in FIG.
As shown by the arrow in FIG.
The direction flowing out from 11 to R14 is defined as + polarity. ), The resistors R11 to R14 have a positive polarity on the left side and a voltage drop of ΔV is generated, so that the transistor Q03 is turned on and the transistors Q13 to Q43 are turned off.

If I61-I64 = 0 and I64 = IR, the resistors R11-R14 have a positive polarity on the right side.
Since a voltage drop of ΔV is generated, the transistors Q03 to Q33 are turned off and the transistor Q43 is turned on.

That is, in general, the magnitude of the currents I61 to I64 is controlled by the AGC voltage V24, for example, as shown in FIG. 8A. As a result, the collector currents I03 to I43 of the transistors Q03 to Q43 are shown in FIG. 8B. Is controlled as follows. The details of the constant current sources Q61 to Q64 will be described later.

That is, in the case of (1), as the voltage V24 rises from 0, the current I61 becomes the value -2I
It rises from 0 to 0. Also, I62 = 0, I63 = 0
And I64 = -I0. Therefore, the current I61,
Since I64 flows rightward in FIG. 7 with respect to the resistors R11 and R14, the base potential of the transistors Q13 to Q43 becomes lower than the base potential of the transistor Q03 due to the voltage drop across the resistors R11 to R14. As a result, the transistors Q13 to Q43 are turned off and the transistor Q03 is turned on, so that I03 = I60 and I13 to I43 = 0.

In the case of (2), the current I61 increases from 0 to the value I0 as the voltage V24 increases. I62 = 0 and I63 = 0, and I62
64 = -I0. Therefore, the current I61 is connected to the resistor R11.
7, the base potential of the transistor Q13 becomes higher than the base potential of the transistor Q03 as the current I61 increases. As a result, as the current I61 increases, the collector current I03 decreases, and the collector current I13 increases.

Since the current I64 flows rightward in FIG. 7 with respect to the resistors R12 to R14, the transistor Q23
To Q43 become lower than the base potential of transistor Q13. As a result, I23 to I43 = 0.

In the case of (3), as the voltage V24 increases, the current I61 decreases from the value I0 to 0, and the current I62 increases from 0 to the value I0. Also, I63 = 0 and I64 = -I0. Therefore, current I62 is applied to resistor R12 as shown in FIG.
, The base potential of the transistor Q23 increases as the current I62 increases.
Becomes higher than the base potential. As a result, the current I62
Increases, the collector current I13 decreases,
The collector current I23 increases.

At this time, since the transistor Q03 is turned off, I03 = 0. Further, since the current I64 flows rightward in FIG. 7 with respect to the resistors R13 and R14, the base potentials of the transistors Q33 and Q43 become lower than the base potential of the transistor Q23. As a result, I33 =
0 and I43 = 0.

In the case of (4), as the voltage V24 increases, the current I62 decreases from the value I0 to 0, and the current I63 increases from 0 to the value I0. Also, I61 = 0 and I64 = -I0. Therefore, for the same reason as in the case (3), as the current I63 increases, the collector current I23 decreases and the collector current I33 increases. Also, I03 =
0, I13 = 0 and I43 = 0.

In the case of (5), as the voltage V24 increases, the current I63 decreases from the value I0 to 0, and the current I64 changes from the value -I0 to the value I
It increases to 0. Also, I61 = 0 and I62 = 0. Therefore, for the same reason as in the case (3), as the current I64 increases, the collector current I33 decreases, and the collector current I43 increases. Also, I03-I
23 = 0.

In the case of (6), I61 to I63 = 0 and I64 = I0 regardless of the voltage V24. Therefore, transistors Q03 to Q33 are off and M
Since the transistor Q43 is turned on, I03 to I33 = 0 and I43 = I0 regardless of the voltage V24.

Thus, according to the current switching circuit 60 of FIG. 7, the currents I03 to I43 are set according to the AGC voltage V24.
Can be continuously changed as shown in FIG. 8B.

Therefore, according to the current switching circuit 60, the gain of the variable gain amplifier 13 is adjusted to the AGC voltage V24
Corresponding to the maximum gain determined by the differential amplifier 40, the attenuator circuits 31 to 34 and the differential amplifier 44
Can be continuously changed up to the minimum gain determined by

The bases of the transistors Q03 to Q43
Since the voltage between the emitters has a temperature characteristic, the currents I03 to I43
The temperature characteristics of the ratio of the currents I03 to I43 can be corrected by using resistors having predetermined positive temperature coefficients as the resistors R11 to R14. .

[Variable Constant Current Source (Part 1)] The variable constant current sources Q61 to Q64 are configured, for example, as shown in FIG. That is, the emitters of the transistors Q611 and Q612 are connected to each other through the resistor R61, and the emitter of the transistor Q612 is connected to the transistor Q613 for a constant current source.
Are connected to the collector of the differential amplifier 61.
Transistors Q711 and Q712 constitute a current mirror circuit 71 having these input and output sides and a power supply potential + VCC as a reference potential point. The collectors of the transistors Q611 and Q612 are connected to the collectors of the transistors Q711 and Q712, respectively, to form a variable constant current source Q61. The collectors of the transistors Q612 and Q712 are connected to the output terminal t61.

Similarly, transistors (Q621 to Q623)
), (Q631 to Q633) and (Q641 to Q643) constitute differential amplifiers 62, 63 and 64, respectively, and transistors (Q721 and Q722), (Q731 and Q73)
732) and (Q741, Q742) constitute current mirror circuits 72, 73, 74, respectively. Note that a resistor corresponding to the resistor R61 of the differential amplifier 61 is not connected to the differential amplifiers 62 to 64.

The differential amplifiers 62, 63, 6
The collector of one of the transistors Q621, Q631, Q641 is connected to the collector of the transistor Q721, Q731, Q741 on the input side of the current mirror circuit 72, 73, 74, and the other transistor of the differential amplifiers 62, 63, 64 The collectors of Q622, Q632 and Q642 are connected to the power supply line. Also, current mirror circuits 72, 73,
The collectors of transistors Q722, Q732, and Q742 on the output side of 74 are connected to output terminals t62, t63, and t64, respectively.

Further, a second output transistor Q723 is connected to the current mirror circuit 72, and its collector is connected to the collector of the transistor Q613 of the differential amplifier 61. The current mirror circuit 73 is connected to the second and third output transistors Q733 and Q734, and their collectors are connected to the collectors of the transistors Q623 and Q613 of the differential amplifiers 62 and 61, respectively.

Further, the current mirror circuit 74 is connected to the second to fourth output transistors Q743 to Q745, and their collectors are connected to the collectors of the transistors Q633 to Q613 of the differential amplifiers 63 to 61, respectively. You. Further, a transistor Q653 for a constant current source is connected to the collector of the transistor Q742, and the collector current thereof is set to a value I0.

The transistors Q611, Q621, Q
An AGC voltage V24 is supplied to the bases of the transistors 631, Q641 and predetermined reference voltages V1, V2, V3, V4 (where 0 <) are supplied to the bases of the transistors Q612, Q622, Q632, Q642.
V1 <V2 <V3 <V4. The collector currents of the transistors Q613, Q623, Q633, and Q643 have a value of 2I0.

According to such a configuration, the currents I61 to I64
Changes with respect to the AGC voltage V24 as shown in FIG. 10B. That is, first, for simplicity, in FIG. 9, the differential amplifiers 61 to 64 include current mirror circuits 71 to 74.
Is not connected. When a current flows from the power supply + VCC to the ground, the polarity is set to +.

Then, as shown in FIG. 10A, the collector current I611 of the transistor Q611 gradually increases from 0 as the voltage V24 increases, and the voltage V24 increases.
When the value exceeds a certain value, it becomes a constant value 2I0. Further, the collector current I612 of the transistor Q612 gradually decreases from the value 2I0 as the voltage V24 increases, and becomes 0 when the voltage V24 exceeds a certain value. In addition,
When V24 = V1, I611 = I612 = I0.

The transistors Q621, Q631, Q64
The collector currents I621, I631, and I641 of 1 also change similarly to the collector current I611. However, in this case, by selecting the value of the emitter resistor R61 of the differential amplifier 61 in advance, the rate of change of the collector currents I611 and I612 with respect to the change of the voltage V24 changes with the change of the collector currents I621 to I641. 1/2 of the percentage. When V24 = V2, I621 = I0, and V24 = V2.
At the time of 3, I631 = I0, and when V24 = V4, I631 = I0.
641 = I0.

Further, the collector current I653 of the transistor Q653 is constant at the value -I0 regardless of the voltage V24.

In the constant current sources Q61 to Q64 shown in FIG.
1 to 74 are connected. In the constant current source Q64, the collector current I641
Since the current I641 flows through the collector of the transistor Q741 on the input side, the current I641 also flows through the collector of the transistor Q742 on the input side. However, at this time, the collector of the transistor Q742 is connected to the collector of the transistor Q742, and the collector current I653 flows.

Therefore, the current I flowing to the output terminal t64
Since 64 becomes I64 = I641−I653, the current I64 changes as shown in FIG. 10B.

In the constant current source Q63, since the collector current I631 of the transistor Q631 flows through the collector of the transistor Q731 on the input side of the current mirror circuit 73, the current I631 also flows through the collector of the transistor Q732 on the output side. .

However, at this time, the current mirror circuit 7
The current I641 flows into the collector of the transistor Q743, and the current I641 flows into the collector of the transistor Q633.

Therefore, the collector current I631 of the transistor Q631 is larger than the current I631 of FIG.
The current I63 flowing through the output terminal t63 becomes I63 = I631−I641 in FIG. 10A, and the current I63 changes as shown in FIG. 10B.

Further, in the constant current source Q62, for the same reason, the current I62 flowing through the output terminal t62 is I62 = I621-I631-I641 in FIG. 10A, and this current I62 is as shown in FIG. 10B. Change.

In the constant current source Q61, the difference between the collector current of the transistor Q712 and the collector current of the transistor Q612 is equal to the output current I61 of the output terminal t61.
Therefore, I61 = I611-I612, and the current I61 should change as shown by the broken line in FIG. 10B.

However, the transistor Q of the differential amplifier 61
The collector of the 613 has transistors Q723, Q734, Q
Since the currents I621, I631, and I641 are flowing by 745, the output current I61 of the output terminal t61 is I61 = I61-I621-I631-I63 shown by the broken line in FIG. 10B.
641 and changes as shown by the solid line in FIG. 10B.

The changes in the currents I61 to I64 shown in FIG. 10B are the same as those in FIG. 8A, and therefore, the constant currents I03 to I43 change as shown in FIG. 8B.

[Variable constant current source (No. 2)] When the variable constant current sources Q61 to Q64 of FIG. 9 are combined with the current switching circuit 60 of FIG. 7, the transistors Q03 to Q03 are referenced with respect to the base potential VB0 of the transistor Q03. Since the on / off of Q43 is controlled, the base potential VB43 of transistor Q43 is
As shown by the broken line in FIG. 12B, the voltage increases as the AGC voltage V24 increases. Therefore, when the number of stages of the attenuator circuit and the differential amplifier is increased, it is disadvantageous for lowering the voltage.

Therefore, the constant current sources Q61 to Q64 shown in FIG.
In this case, the rise of the base potential VB43 of the transistor Q43 is suppressed. That is, the constant current sources Q61 to Q64 are configured similarly to the case of FIG.

Further, the emitters of the transistors Q821 and Q822 are commonly connected to the collector of the transistor Q823 for a constant current source to form a differential amplifier 82. The AGC voltage V24 is supplied to the base of the transistor Q821. Is supplied with a reference voltage V3.
Then, the collector of the transistor Q821 is connected to the output terminal t62.
And the collector of the transistor Q822 is connected to the power supply line. The magnitude of the collector current of transistor Q823 is set to a value of 2I0.

In such a configuration, the circuit of FIG. 11 is the same as the circuit of FIG. 9 except for the differential amplifier 82, so that the output currents I61, I63, and I64 of the terminals t61, t63, and t64.
Is exactly the same change as FIG. 10B, as shown by the solid line in FIG. 12A. Also, the collector current I621 of the transistor Q621 is equal to the collector current I722 of the transistor Q722.
Therefore, the collector current I722 also changes exactly the same as the output current I62 of FIG. 10B as shown by the broken line in FIG. 12A.

Further, at this time, since the transistor Q821 forms the differential amplifier 82, the collector current I821 changes as shown by a chain line in FIG. 12A. Then, in the circuit of FIG. 11, since I62 = I722-I821, the output current I62 of the terminal t62 changes as shown in FIG. 12A.

Therefore, the base potential VB43 of the transistor Q43 changes as shown by the solid line in FIG.
Even if the C voltage V24 rises, it does not rise above the voltage VB0. Therefore, even when the number of stages of the attenuator circuit and the differential amplifier is increased, it is advantageous for lowering the voltage.

[0142]

According to the present invention, it is easy to lower the voltage. Further, generation of distortion can be suppressed. further,
A variable gain amplifier with less noise can be obtained.

[Brief description of the drawings]

FIG. 1 is a system diagram illustrating one embodiment of the present invention.

FIG. 2 is a system diagram illustrating one embodiment of the present invention.

FIG. 3 is a connection diagram illustrating a part of one embodiment of the present invention.

FIG. 4 is a connection diagram showing a continuation of FIG. 3;

FIG. 5 is a connection diagram for explaining the present invention.

FIG. 6 is a connection diagram for explaining the present invention.

FIG. 7 is a connection diagram illustrating one embodiment of the present invention.

FIG. 8 is a characteristic diagram for explaining the present invention.

FIG. 9 is a connection diagram illustrating one embodiment of the present invention.

FIG. 10 is a characteristic diagram for explaining the present invention.

FIG. 11 is a connection diagram illustrating one embodiment of the present invention.

FIG. 12 is a characteristic diagram for explaining the present invention.

FIG. 13 is a connection diagram for explaining the present invention.

FIG. 14 is a characteristic diagram for explaining the circuit of FIG. 13;

[Explanation of symbols]

11 antenna, 12 tuning circuit, 13 variable gain amplifier, 14 tuning circuit, 15A, 15B mixer circuit, 1
6A, 16B: low-pass filter, 17A, 17B: variable gain amplifier, 18A, 18B: low-pass filter, 1
9 demodulation circuit, 21 PLL, 22 frequency divider circuit, 23
AGC detection circuit, 24 addition circuit, 25 AGC detection circuit, 26A, 26B phase shift circuit, 27 addition circuit, 28
... Band pass filter, 30 ... Ladder attenuator circuit, 31-34 ... Attenuator circuit, 40-44 ... Differential amplifier, 51-54 ... Cascade amplifier, 60 ... Current switching circuit, 61-64 ... Differential amplifier, 71-74 ... Current mirror circuit, Q61-Q64 ... Variable constant current source

Claims (7)

[Claims] 1. A plurality of attenuator circuits cascaded to an input signal, a plurality of amplifiers to which respective output signals of the plurality of attenuator circuits are respectively supplied, and a common connection to output terminals of the plurality of amplifiers And an operating current source common to the plurality of amplifiers, a plurality of amplifiers, and a plurality of current lines provided between the collector and the emitter in a current line between the operating current sources. And a plurality of resistors respectively connected between the bases of the plurality of transistors, and a plurality of current sources for flowing predetermined currents through the plurality of resistors, respectively. By controlling the current flowing through each of the plurality of resistors in accordance with the control signal, a level-controlled output signal is obtained from the extraction circuit. Variable gain amplifier. 2. The variable gain amplifier according to claim 1, wherein the input signal is supplied to a first stage of the plurality of amplifiers, and each output signal of the plurality of attenuator circuits is supplied to a first stage of the plurality of amplifiers. A variable gain amplifier that is supplied to each of the second and subsequent stages. 3. The variable gain amplifier according to claim 1, wherein each of the plurality of attenuator circuits includes a parallel circuit of a first resistor and a capacitor and a parallel circuit of a second resistor and a capacitor. And a circuit connected in series with each other, wherein an output is taken out from the second parallel circuit in each of the attenuator circuits. 4. The variable gain amplifier according to claim 1, wherein the resistor connected between said bases is a resistor having a positive temperature coefficient, and A variable gain amplifier configured to perform temperature correction of a current ratio of currents flowing through a plurality of transistors. 5. A common current source for supplying a current to a plurality of controlled circuits, a collector line and an emitter are provided in series on a current line between the controlled circuit and the common current source, respectively. A plurality of transistors, a plurality of resistors respectively connected between the bases of the plurality of transistors, and a plurality of current sources for supplying a predetermined current to the plurality of resistors, respectively. A current switching circuit configured to control a current flowing through each of the plurality of resistors in accordance with a control signal, thereby distributing a current of the common current source to the plurality of controlled circuits. 6. The current switching circuit according to claim 5, wherein the resistor connected between the bases is a resistor having a positive temperature coefficient, and the current flowing through the plurality of transistors is determined by the temperature coefficient. A current switching circuit that performs temperature compensation of the ratio. 7. A variable gain amplifier is provided on a signal line of a received signal of a broadcast wave. The variable gain amplifier includes a plurality of cascade-connected attenuator circuits, and the output signals of the received signal and the plurality of attenuator circuits. A plurality of amplifiers respectively supplied; an extraction circuit commonly connected to the output terminals of the plurality of amplifiers; an operating current source common to the plurality of amplifiers; the plurality of amplifiers; and the operating current A plurality of transistors each having a collector and an emitter connected in series in a current line between the source, a plurality of resistors respectively connected between the bases of the plurality of transistors, and a plurality of resistors connected respectively to the plurality of resistors. A plurality of current sources for flowing a predetermined current, wherein the reception signal is supplied to a first stage of the plurality of attenuator circuits; A receiver configured to take out an AGC-controlled reception signal from the take-out circuit by controlling a current supplied to each of the plurality of resistors by the current source according to an AGC voltage.