JP4876818B2 - Resin-sealed semiconductor device and manufacturing method thereof - Google Patents

Resin-sealed semiconductor device and manufacturing method thereof Download PDF

Info

Publication number
JP4876818B2
JP4876818B2 JP2006257541A JP2006257541A JP4876818B2 JP 4876818 B2 JP4876818 B2 JP 4876818B2 JP 2006257541 A JP2006257541 A JP 2006257541A JP 2006257541 A JP2006257541 A JP 2006257541A JP 4876818 B2 JP4876818 B2 JP 4876818B2
Authority
JP
Japan
Prior art keywords
resin
semiconductor device
terminal
semiconductor element
terminal member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006257541A
Other languages
Japanese (ja)
Other versions
JP2008078483A (en
Inventor
正親 増田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dai Nippon Printing Co Ltd
Original Assignee
Dai Nippon Printing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dai Nippon Printing Co Ltd filed Critical Dai Nippon Printing Co Ltd
Priority to JP2006257541A priority Critical patent/JP4876818B2/en
Publication of JP2008078483A publication Critical patent/JP2008078483A/en
Application granted granted Critical
Publication of JP4876818B2 publication Critical patent/JP4876818B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

Abstract

<P>PROBLEM TO BE SOLVED: To provide a resin sealed semiconductor device which is small-sized, thin and multi-functional, and in which wire bonding is easily performed in particular, improvement in yield for manufacturing can be expected, productivity is improved and a metal substrate is used as a package, and manufacturing method thereof. <P>SOLUTION: A plurality of terminal members 110 are separately disposed along the periphery of a plurality of stacked semiconductor device groups 120, 121 being stacked, and the semiconductor devices, a bonding wire 130 connecting thereto and the terminal members are integrally sealed by a resin 101. For each of the terminal members, a thick portion thereof is made into thickness 110b of a working material by etching, and thin portions 110a, 110c are formed thin by half etching from one side of the working material. The terminal member has the thick portion and the thin portions, one side thereof is flattened and the other side is made into two steps. A terminal portion of each semiconductor device in which the size of a terminal face is reduced and an internal terminal portion of each of the step of the terminal member are sequentially connected by the bonding wire. <P>COPYRIGHT: (C)2008,JPO&amp;INPIT

Description

本発明は、端子部材を用いた、小型、薄型の樹脂封止型半導体装置とその製造方法に関し、特に、複数個の端子部材を、互いに離間して、半導体素子を複数積層した積層半導体素子群の周辺に沿い離して配設し、該積層半導体素子群と、それに接続するボンディングワイヤと、該複数の端子部材とを一体的に樹脂封止した樹脂封止型半導体装置と、その製造方法に関する。   The present invention relates to a small and thin resin-encapsulated semiconductor device using a terminal member and a method for manufacturing the same, and in particular, a stacked semiconductor element group in which a plurality of terminal elements are separated from each other and a plurality of semiconductor elements are stacked. And a manufacturing method of the resin-encapsulated semiconductor device in which the laminated semiconductor element group, bonding wires connected thereto, and the plurality of terminal members are integrally resin-sealed. .

近年、電子機器の小型化に対応するために、電子機器に搭載される半導体部品を高密度に実装することが要求され、それにともなって、半導体部品の小型化、薄型化が進んでおり、更なる薄型化を廉価に達成できるパッケージが求められている。
このような状況のもと、薄型化に対応するものとして、特開平１１−３０７６７５号公報に記載の接続用リードの上面及び下面を露出させた構造の樹脂封止型半導体装置や、特開平１１−２６０９８９号公報に記載の接続用リードの一部を露出して外部端子としている樹脂封止型半導体装置が提案されている。
一方、システムＬＳＩのワンチップ化の開発が盛んであるが、２次元方向への配線展開となるため、配線の短縮による高速化には限界があり、また、その開発費、開発期間の増加を招いているのが実状で、最近では、これに代わり、半導体素子を３次元方向に積層したパッケージでシステムＬＳＩを実現しようとする試みがなされている。
このようなパッケージをシステムパッケージとも言う。 In recent years, in order to cope with the downsizing of electronic devices, it has been required to mount semiconductor components mounted on electronic devices with high density, and along with that, semiconductor components have become smaller and thinner. There is a need for a package that can achieve a low profile at a low cost.
Under such circumstances, a resin-encapsulated semiconductor device having a structure in which the upper surface and the lower surface of the connection lead described in JP-A-11-307675 are exposed, as disclosed in JP-A-11-307675. A resin-encapsulated semiconductor device has been proposed in which a part of the connection lead described in Japanese Patent No. 260989 is exposed and used as an external terminal.
On the other hand, development of system LSIs on a single chip is active, but since the wiring is expanded in two dimensions, there is a limit to speeding up by shortening the wiring, and the development cost and development period are increased. The actual situation is inviting, and recently, an attempt has been made to realize a system LSI with a package in which semiconductor elements are stacked in a three-dimensional direction.
Such a package is also called a system package.

特開平１１−３０７６７５号公報には、これに記載の樹脂封止型半導体装置を積層し、その上面及び下面を露出させた接続用リードで電気的接続をとった、いわゆるスタック構造の積層型樹脂封止型半導体装置も記載されているが、ここに記載の樹脂封止型半導体装置は、ダイパッドを備えたもので、薄型化は十分でない。
尚、特開平１１−２６０９８９号公報に記載の樹脂封止型半導体装置はスタック構造をとれるものではない。
また、特開平２００２−３３４３４号公報には、パッケージ内に半導体素子（チップ）を積層したパッケージが記載されているが、この構造では、自由度が少なく、汎用化しずらい。 Japanese Patent Application Laid-Open No. 11-307675 discloses a laminated resin having a so-called stack structure in which the resin-encapsulated semiconductor devices described above are stacked and electrically connected by connecting leads with the upper and lower surfaces exposed. Although a sealed semiconductor device is also described, the resin-sealed semiconductor device described herein includes a die pad and is not sufficiently thin.
Note that the resin-encapsulated semiconductor device described in JP-A-11-260989 cannot take a stack structure.
Japanese Patent Laid-Open No. 2002-33434 describes a package in which semiconductor elements (chips) are stacked in a package. However, this structure has a low degree of freedom and is difficult to be generalized.

特開平１１−３０７６７５号公報JP-A-11-307675 特開平１１−２６０９８９号公報Japanese Patent Laid-Open No. 11-260989 特開平２００２−３３４３４号公報Japanese Patent Laid-Open No. 2002-33434

一方、最近では、携帯電話用やデジタルカメラ用として、ＴＳＯＰやＱＦＰを２段重ねして、厚さ２．５ｍｍ程度にした、ＳＲＡＭやフラッシュメモリが多く用いられ、また、パソコンやサーバー等の用途には、基板の両側にＴＳＯＰあるいはＴＣＰを配した、厚さ５ｍｍ以下のＳＤＲＡＭが用いられている。
尚、メモリカードに使用するチップ（半導体素子とも言う）としては厚さが薄いとことが好ましく、１チップの最大厚さは通常１．２ｍｍが標準規格となっており、ＴＳＯＰやＱＦＰの形態で用いられる。
小型、多ピンを実現でき、高速電気特性を得ることができるものとして、有機の配線基材を用いて、その一面にチップを多段に積層し、樹脂封止し、半田ボールを他面に配設した形態もあるが、この形態のものは、先に述べた、ＴＳＯＰやＱＦＰを２段重ねして、厚さ２．５ｍｍ程度にした形態のものより、高価となる。
このような中、小型化、薄型、多機能（多ピン）で、特にワイヤボンディングがし易く、作製上の歩留まりの向上が期待でき、生産性が良い、パッケージで、メタルサブストレートを用いた樹脂封止型の半導体装置を実現することが求めらるようになってきた。 On the other hand, recently, for mobile phones and digital cameras, SRAM and flash memory with TSOP and QFP two-tiered to a thickness of about 2.5 mm are often used, and for applications such as personal computers and servers. For example, an SDRAM having a thickness of 5 mm or less in which TSOP or TCP is arranged on both sides of the substrate is used.
The chip used for the memory card (also referred to as a semiconductor element) is preferably thin, and the maximum thickness of one chip is normally 1.2 mm, which is standard in the form of TSOP or QFP. Used.
Small, multi-pin can be realized and high-speed electrical characteristics can be obtained. Using an organic wiring substrate, chips are stacked in multiple layers on one side, sealed with resin, and solder balls are placed on the other side. Although there is a form that is provided, this form is more expensive than the form in which TSOP and QFP are stacked in two steps to have a thickness of about 2.5 mm.
Under such circumstances, the resin is small, thin, multi-functional (multi-pin), especially easy to wire bond, can be expected to improve the production yield, and has good productivity. It has been required to realize a sealed semiconductor device.

上記のように、近年、半導体部品の小型化、薄型化が進んでおり、更なる薄型化を廉価に達成できるパッケージが求められており、最近では、小型化、薄型、多機能（多ピン）で、特にワイヤボンディングがし易く、作製上の歩留まりの向上が期待でき、生産性が良いパッケージで、メタルサブストレートを用いた樹脂封止型の半導体装置を実現することが求めらるようになってきた。
本発明はこれらに対応するもので、小型化、薄型、多機能（多ピン）で、特にワイヤボンディングがし易く、作製上の歩留まりの向上が期待でき、生産性の良い、パッケージとして、メタルサブストレートを用いた樹脂封止型の半導体装置を提供しようとするものである。
同時に、そのような樹脂封止型半導体装置の製造方法の提供しようとするものである。 As described above, semiconductor components are becoming smaller and thinner in recent years, and there is a need for a package that can achieve further reduction in thickness at a low cost. Recently, miniaturization, thinness, and multifunction (multi-pin) are required. In particular, wire bonding is easy, improvement in manufacturing yield can be expected, and it is required to realize a resin-encapsulated semiconductor device using a metal substrate with a package with good productivity. I came.
The present invention corresponds to these, and is small, thin, multi-functional (multi-pin), particularly easy to wire bonding, can be expected to improve the production yield, and has a good productivity as a metal sub package. An object of the present invention is to provide a resin-encapsulated semiconductor device using a straight.
At the same time, an object of the present invention is to provide a method for manufacturing such a resin-encapsulated semiconductor device.

本発明の樹脂封止型半導体装置は、複数個の端子部材を、互いに離間して、半導体素子を複数積層した積層半導体素子群の周辺に沿い離して配設し、該積層半導体素子群と、それに接続するボンディングワイヤと、該複数の端子部材とを一体的に樹脂封止した樹脂封止型半導体装置であって、前記端子部材は、エッチング加工法にて、加工用素材から、厚肉部を加工用素材の厚さにし、薄肉部を該加工用素材の一面側からのハーフエッチングにて薄肉にして形成されたもので、厚肉部と薄肉部とを有し、一方側を平坦にし、他方の側を２段の段状にし、厚肉部の両側にその端に至る薄肉部を配し、該一方の側の平坦な面を外部端子部とし、該他方の側の各段部の面を内部端子部としており、前記積層半導体素子群は、前記端子部材の薄肉部の厚さより薄い第１の半導体素子を有し、該第１の半導体素子の端子面側に、１以上の薄肉の半導体素子を、端子面の向きを揃え、前記第１の半導体素子を含んで、順次、端子面のサイズが小サイズとなるように積層したもので、該積層半導体素子群の各半導体素子の端子部と、端子部材の各段部の内部端子部とを、ボンディングワイヤにて接続しており、各端子部材を、その前記一方の側の平坦な面を一平面上に揃えて、同じ向きにして、各端子部材の一方の端に至る薄肉部側を半導体素子側に向け、他方の端に至る薄肉部を外側に向けて、配し、各端子部材の一方の側の平坦な面とその側面とを露出させ、且つ、前記第１の半導体素子の端子面でない側の裏面を、各端子部材の前記一方の側の平坦な面に揃えて、前記第１の半導体素子裏面を露出させるようにして、樹脂中に、配置して、全体を端子部材の厚肉部の厚さ幅より大きい幅として、樹脂封止していることを特徴とするものである。
そして、上記の樹脂封止型半導体装置であって、前記端子部材の前記一方の側の平坦な面に半田ボールを備えていることを特徴とするものである。
そしてまた、上記いずれかの樹脂封止型半導体装置であって、前記端子部材の半導体素子側の薄肉部の先端断面は、ハーフエッチング形成面と側面とが鋭角をなすことを特徴とするものである。
また、上記いずれかの樹脂封止型半導体装置であって、前記各端子部材は、その半導体素子側の薄肉部の先端幅を先細としていることを特徴とするものである。
また、上記いずれかの樹脂封止型半導体装置であって、前記各端子部材の前記封止用樹
脂表面と接する表面部に粗面化処理を施したことを特徴とするものであり、前記粗面化処理による、最大高さ粗さＲｙ（ＪＩＳＢＯ６０１−１９９４）が、１μｍ〜２μｍの範囲であることを特徴とするものである。
また、上記いずれかの樹脂封止型半導体装置であって、外部端子部の前記他方側、外側の面と外側側面にわたる切り欠け部を設けていることを特徴とするものである。
また、上記いずれかの樹脂封止型半導体装置であって、端子部材は、Ｃｕ、Ｃｕ系合金、４２％Ｎｉ−Ｆｅ系合金からなることを特徴とするものである。
また、上記いずれかの樹脂封止型半導体装置であって、内部端子部および外部端子部に
、表層として、半田めっき層、金めっき層、銀めっき層、パラジウムめっき層、錫めっき層から選ばれた１つの金属めっき層を、接続用のめっき層として設けていることを特徴とするものである。
また、上記いずれかの樹脂封止型半導体装置であって、半導体素子の厚みが１００μｍ以下であることを特徴とするものである。
また、上記いずれかの樹脂封止型半導体装置であって、ＱＦＮ型あるいはＳＯＮ型であることを特徴とするものである。
尚、最大高さ粗さＲｙの測定は２００μｍ長さで行ったものである。
また、「前記複数個の端子部材を前記半導体素子の周辺に沿い離して配設し、」としているが、これは、各端子部材を半導体素子の周辺に沿い離して配設するとともに、前記複数個の端子部材は、それぞれ、互いに離して配設されていることを前提としている。 In the resin-encapsulated semiconductor device of the present invention, a plurality of terminal members are spaced apart from each other and arranged along the periphery of a laminated semiconductor element group in which a plurality of semiconductor elements are laminated, the laminated semiconductor element group, A resin-encapsulated semiconductor device in which a bonding wire connected thereto and the plurality of terminal members are integrally resin-sealed, wherein the terminal member is formed from a processing material, a thick portion by an etching method. The thickness of the processing material is made thin, and the thin portion is thinned by half-etching from one side of the processing material, and has a thick portion and a thin portion, and one side is flattened. The other side is made into two steps, the thin part reaching the end is arranged on both sides of the thick part, the flat surface on the one side is used as an external terminal part, and each step part on the other side Of the thin-film portion of the terminal member. Has a thin first semiconductor element than is, the terminal side of the first semiconductor element, one or more thin semiconductor device, aligning the orientation of the terminal surfaces, including the first semiconductor element, sequentially The terminal surface of each semiconductor element of the stacked semiconductor element group is connected to the internal terminal part of each stepped portion of the terminal member with a bonding wire. Each terminal member is arranged in the same direction with the flat surface on one side thereof aligned on one plane, and the thin-walled portion side leading to one end of each terminal member faces the semiconductor element side, and the other The thin portion reaching the end of the terminal member is directed outward, the flat surface on one side of each terminal member and the side surface thereof are exposed, and the back surface on the non-terminal surface side of the first semiconductor element is exposed. The back surface of the first semiconductor element is aligned with the flat surface on the one side of each terminal member. So as to exposed, in the resin, arranged as a width larger than the thickness width of the thick portion of the terminal member across, and is characterized in that the sealed with resin.
In the above resin-encapsulated semiconductor device, a solder ball is provided on a flat surface on the one side of the terminal member.
Further, in any one of the above resin-encapsulated semiconductor devices, the tip cross section of the thin portion on the semiconductor element side of the terminal member has an acute angle between the half-etch formation surface and the side surface. is there.
Further, in any of the above resin-encapsulated semiconductor devices, each terminal member is characterized in that the tip width of the thin portion on the semiconductor element side is tapered.
Further, in any one of the above resin-encapsulated semiconductor devices, a roughening treatment is performed on a surface portion of each terminal member that is in contact with the encapsulating resin surface. The maximum height roughness Ry (JISBO601-1994) due to the surface treatment is in the range of 1 μm to 2 μm.
Also, in any one of the above resin-encapsulated semiconductor devices, a cutout portion is provided over the other side, the outer surface, and the outer side surface of the external terminal portion.
In any of the above resin-encapsulated semiconductor devices, the terminal member is made of Cu, a Cu-based alloy, or a 42% Ni—Fe-based alloy.
Further, in any of the above resin-encapsulated semiconductor devices, the internal terminal portion and the external terminal portion are selected from a solder plating layer, a gold plating layer, a silver plating layer, a palladium plating layer, and a tin plating layer as a surface layer. One metal plating layer is provided as a plating layer for connection.
Moreover, in any of the above resin-encapsulated semiconductor devices, the thickness of the semiconductor element is 100 μm or less.
Also, any one of the above resin-encapsulated semiconductor devices is characterized by being QFN type or SON type.
The maximum height roughness Ry was measured at a length of 200 μm.
In addition, although “the plurality of terminal members are arranged apart from the periphery of the semiconductor element”, each of the terminal members is arranged apart from the periphery of the semiconductor element. It is assumed that the individual terminal members are arranged apart from each other.

本発明の樹脂封止型半導体装置の製造方法は、請求項１ないし１１のいずれか１項に記載の樹脂封止型半導体装置の製造方法であって、順に、（ａ）１つの樹脂封止型半導体装置の端子部材の配置に対応した、端子部材の配置を１単位として、ハーフエッチング技術を用いたエッチング加工にて、前記端子部材の外側を支持部で連結した状態で、向きを揃えて面付けして形成し、面付け形成された加工シートを得る加工工程と、（ｂ）接続用の表面めっきを施すめっき処理工程と、（ｃ）面付け形成された加工シートのハーフエッチング面側ではない側を、平板状の真空引き板にて真空引きし、加工シートを真空引き板に密着させた状態で、面付け分だけ、積層半導体素子群を所定の位置に位置決めして、その端子面側ではない裏面を真空引きして、真空引き板に搭載する半導体素子搭載工程と、（ｄ）この状態で、各半導体素子について、その端子と端子部材の内部端子部の端子面とをワイヤボンディング接続するワイヤボンディング工程と、（ｅ）真空引き板を外し、これに代え、モールド用のテープを、加工シートの両面に、それぞれ、各面を覆うように、平面状に貼り、半導体素子の裏面を一方のテープにて貼り固定するテープ貼り工程と、（ｆ）表裏をモールド固定用の平板にて挟み、加工シート全体について、真空引きあるいは減圧してモールドを行う、モールド工程と、（ｇ）表裏のモールド固定用の平板とテープを除去し、必要に応じて半田めっきで外部端子部の外装めっきを施した後、切断用のテープを貼り、該切断用のテープとは反対側からダイシングソーにて切断して、樹脂封止型半導体装置を１個づつに個片化して得る個片化工程と、を行うことを特徴とするものである。 そして、上記の樹脂封止型半導体装置の製造方法であって、平板状の真空引き板が、全面に真空吸着用の孔を配設したものであることを特徴とするものである。   A method for manufacturing a resin-encapsulated semiconductor device of the present invention is the method for manufacturing a resin-encapsulated semiconductor device according to any one of claims 1 to 11, wherein (a) one resin encapsulated in order With the terminal member arrangement corresponding to the arrangement of the terminal member of the type semiconductor device as one unit, in the state where the outside of the terminal member is connected by the support portion in the etching process using the half etching technique, the directions are aligned. A processing step for obtaining a processed sheet formed by imposition and obtaining an imposition, (b) a plating step for performing surface plating for connection, and (c) a half-etched surface side of the impositioned processed sheet The non-side is evacuated with a flat vacuum drawing plate, and the laminated semiconductor element group is positioned at a predetermined position by the imposition, with the processed sheet closely attached to the vacuum drawing plate, and its terminals Vacuum the back side that is not the front side Then, a semiconductor element mounting step for mounting on the vacuum drawing plate, and (d) a wire bonding step for wire bonding connection between the terminal and the terminal surface of the internal terminal portion of the terminal member for each semiconductor element in this state, (E) Remove the vacuum drawing plate and replace it with a molding tape on both sides of the processed sheet so that each surface is covered with a flat surface, and the back of the semiconductor element is attached with one tape. A tape attaching step for fixing, (f) a molding step for sandwiching the front and back with a flat plate for mold fixation, and evacuating or depressurizing the entire processed sheet, and (g) a flat plate for fixing the front and back molds. And, after applying external plating of the external terminal part by solder plating, if necessary, a cutting tape is applied, and a dicing saw is applied to the dicing saw from the side opposite to the cutting tape. Cut and is intended to a singulation process may a resin sealed semiconductor device in one by one with individual pieces, and performing. In the method for manufacturing the resin-encapsulated semiconductor device, the flat vacuum drawing plate is provided with holes for vacuum suction on the entire surface.

あるいは、本発明の樹脂封止型半導体装置の製造方法は、請求項１ないし１１のいずれか１項に記載の樹脂封止型半導体装置の製造方法であって、順に、（Ａ）１つの樹脂封止型半導体装置の端子部材の配置に対応した、端子部材の配置を１単位として、ハーフエッチング技術を用いたエッチング加工にて、前記端子部材の外側を支持部で連結した状態で、向きを揃えて面付けして形成し、面付け形成された加工シートを得る加工工程と、（Ｂ）接続用の表面めっきを施すめっき処理工程と、（Ｃ）面付け形成された加工シートのハーフエッチング面側ではない側を覆うようにモールド用のテープを貼り、面付け分だけ、積層半導体素子群を所定の位置に位置決めして、その端子面側ではない裏面を前記テープに貼り付け搭載する半導体素子搭載工程と、（Ｄ）この状態で、各半導体素子について、その端子と端子部材の内部端子部の端子面とをワイヤボンディング接続するワイヤボンディング工程と、（Ｅ）モールド用のテープを、加工シートの両面に、それぞれ、各面を覆うように、平面状に貼り、半導体素子の裏面を一方のテープにて貼り固定するテープ貼り工程と、（Ｆ）表裏を、それぞれ、テープを介して、モールド固定用の平板にて挟み、加工シート全体について、一括してモールドを行う、一括モールド工程と、（Ｇ）表裏のモールド固定用の平板、テープを除去し、切断用のテープを貼り、該切断用のテープとは反対側からダイシングソーにて切断して、樹脂封止型半導体装置を１個づつに個片化して得る個片化工程と、を行うことを特徴とするものである。 Or the manufacturing method of the resin-sealed semiconductor device of this invention is a manufacturing method of the resin-sealed semiconductor device of any one of Claim 1 thru | or 11 , Comprising: In order, (A) one With the arrangement of the terminal member corresponding to the arrangement of the terminal member of the resin-encapsulated semiconductor device as one unit, in the state where the outside of the terminal member is connected by the support portion in the etching process using the half etching technique, A processing step for obtaining a processed sheet that is formed by imposing and imposing, (B) a plating process for applying surface plating for connection, and (C) a half of the processed sheet formed by imposition A tape for molding is applied so as to cover the side that is not the etched surface side, the laminated semiconductor element group is positioned at a predetermined position by the amount of the imposition, and the back surface that is not the terminal surface side is attached to the tape and mounted. Semiconductor element Mounting step; (D) in this state, for each semiconductor element, a wire bonding step for wire bonding connection between the terminal and the terminal surface of the internal terminal portion of the terminal member; and (E) a tape for molding, a processed sheet A tape application process in which each surface is covered with a flat surface so as to cover each surface, and the back surface of the semiconductor element is fixed with one tape, and (F) front and back surfaces are respectively molded via tape. The whole process sheet is sandwiched between the fixing flat plates and molded all at once. (G) The front and back mold fixing flat plates and tape are removed, and the cutting tape is pasted and cut. And a singulation step obtained by cutting the resin-encapsulated semiconductor device into individual pieces by cutting with a dicing saw from the opposite side of the tape for use.

（作用）
本発明の樹脂封止型半導体装置は、このような構成にすることにより、小型化、薄型、多機能（多ピン）で、特にワイヤボンディングがし易く、作製上の歩留まりの向上が期待でき、生産性の良い、パッケージとして、メタルサブストレートを用いた樹脂封止型の半導体装置の提供を可能としている。
端子部材は、エッチング加工法にて、加工用素材から、厚肉部を加工用素材の厚さにし、薄肉部を該加工用素材の一面側からのハーフエッチングにて薄肉にして形成されたもので、端子部材自体を小型に、精度よく、所望の形状を、生産性良く、得ることができるものとしているが、更に、各端子部材を、その前記一方の側の平坦な面を一平面上に揃えて、同じ向きにして、各端子部材の一方の端に至る薄肉部側を半導体素子側に向け、他方の端に至る薄肉部を外側に向けて、配し、各端子部材の一方の側の平坦な面とその側面とを露出させ、且つ、前記第１の半導体素子の端子面でない側の裏面を、各端子部材の前記一方の側の平坦な面に揃えて、前記第１の半導体素子裏面を露出させるようにして、樹脂中に、配置している構造としていることにより、全体の薄化を可能にしている。
また、積層半導体素子群を用いて、各半導体素子について、端子部材とボンディングワイヤ接続をしていることにより、他機能化（多ピン化）を可能としている。
特に、前記積層半導体素子群は、前記端子部材の薄肉部の厚さより薄い第１の半導体素子を有し、該第１の半導体素子の端子面側に、１以上の薄肉の半導体素子を、端子面の向きを揃え、前記第１の半導体素子を含んで、順次、端子面のサイズが小サイズとなるように積層したもので、該積層半導体素子群の各半導体素子の端子部と、端子部材の各段部の内部端子部とを、ボンディングワイヤにて接続していることにより、接続作業性を良いものとし、且つ、接続信頼性を良いものとしている。
また、後述する、本発明の樹脂封止型半導体装置の製造方法により、面付け状態で作製でき、量産性の良い構造といえる。
更に、端子部材の薄肉部の厚さより、第１の半導体素子の厚さを薄くしていることにより、第１の半導体素子の端子と薄肉部である内部端子部とワイヤボンデインング接続を行う場合、第１のビンディングポイントを第１の半導体素子とすることにより、ワイヤの垂れを防止できる構造となる。
第１の半導体素子に積層した各半導体装置については、該薄肉の段部の面を内部端子として、また、厚肉の段部の面を内部端子部として、ワイヤボンデインング接続を行うことができ、ワイヤボンデインング接続の自由度を大きなものとしている。
これらにより、ワイヤボンデインング接続を行い易くしており、結果として、ワイヤボンデインング接続作業における歩留まりを上げることができる。
各半導体素子の厚みとしては、特に、１００μｍ以下である場合に有効である。
具体的には、前記端子部材の前記一方の側の平坦な面に半田ボールを備えている形態が挙げられる。
パッケージの形態としては、ＱＦＮ型あるいはＳＯＮ型が挙げられる。
(Function)
By adopting such a configuration, the resin-encapsulated semiconductor device of the present invention can be downsized, thin, and multifunctional (multi-pin), particularly easy to wire bond, and can be expected to improve the manufacturing yield. It is possible to provide a resin-encapsulated semiconductor device using a metal substrate as a package with good productivity.
The terminal member is formed by etching using a processing material, with the thick portion made the thickness of the processing material, and the thin portion made thin by half etching from one side of the processing material. The terminal member itself can be made small, accurate, and a desired shape can be obtained with good productivity. Further, each terminal member has a flat surface on the one side on a single plane. Are arranged in the same direction, with the thin-walled portion side reaching one end of each terminal member facing the semiconductor element side and the thin-walled portion reaching the other end facing outward, and one terminal member of each terminal member The first flat surface and the side surface thereof are exposed, and the back surface of the first semiconductor element that is not the terminal surface is aligned with the flat surface on the one side of each terminal member, so that the first The structure is arranged in the resin so that the back surface of the semiconductor element is exposed. By, allowing the entire thinning.
Further, by using a laminated semiconductor element group, each semiconductor element is connected to a terminal member and a bonding wire, thereby enabling other functions (multiple pins).
In particular, the stacked semiconductor element group includes a first semiconductor element that is thinner than a thickness of the thin portion of the terminal member , and one or more thin semiconductor elements are connected to the terminal surface side of the first semiconductor element. The surface direction is aligned, the first semiconductor elements are included, and the terminal surfaces are sequentially stacked so that the size of the terminal surface becomes a small size. A terminal portion of each semiconductor element of the stacked semiconductor element group, and a terminal member By connecting the internal terminal portions of the respective step portions with bonding wires, the connection workability is improved and the connection reliability is improved.
Further, it can be said that the structure can be manufactured in an imposition state by a method for manufacturing a resin-encapsulated semiconductor device of the present invention, which will be described later, and has a high mass productivity.
Further, by making the thickness of the first semiconductor element thinner than the thickness of the thin portion of the terminal member, wire bonding bonding is performed with the terminal of the first semiconductor element and the internal terminal portion which is the thin portion. In this case, by using the first binding point as the first semiconductor element, the wire can be prevented from drooping.
About each semiconductor device laminated | stacked on the 1st semiconductor element, wire bonding bonding can be performed by using the surface of the thin step portion as an internal terminal and the surface of the thick step portion as an internal terminal portion. It is possible to increase the flexibility of wire bonding connection.
As a result, the wire bonding connection is facilitated, and as a result, the yield in the wire bonding connection work can be increased.
The thickness of each semiconductor element is particularly effective when it is 100 μm or less.
Specifically, a form in which solder balls are provided on a flat surface on the one side of the terminal member can be mentioned.
As a form of the package, a QFN type or a SON type can be mentioned.

また、前記端子部材の半導体素子側の薄肉部の先端断面は、ハーフエッチング形成面と側面とが鋭角をなす、請求項３の発明の形態とすることにより、内部端子部の半導体素子側のその長手方向の先端において、温度変化に伴う、樹脂の締め付けが起こる構造で、耐湿性の良い構造となる。
先端が鋭角となった分だけ封止用樹脂の量を増やすことも可能で、封止用樹脂の量が増える分、構造的、品質面で安定する。
特に、ＱＦＰ型である場合には、端子数が多くても、品質面で安定でき、有効である。 尚、前記鋭角の角度としては、８５度以下が好ましい。
また、記各端子部材は、その半導体素子側の薄肉部の先端幅を先細としている、請求項４の発明の形態とすることにより、先端が先細となった分だけ封止用樹脂の量を増やすことも可能で、封止用樹脂の量が増える分、構造的、品質面で安定する。
また、前記各端子部材の前記封止用樹脂表面と接する表面部に粗面化処理を施した、請求項５の発明の形態とすることにより、端子部材と封止用樹脂との密着性の向上が図れる。
特に、前記粗面化処理による、最大高さ粗さＲｙ（ＪＩＳＢＯ６０１−１９９４）が、１μｍ〜２μｍの範囲である場合には、有効である。
また、外部端子部の前記他方側、外側の面と外側側面にわたる切り欠け部を設けている、請求項７の発明の形態とすることにより、その面付け作製において、個片化の際、その切断をし易いものとしている。
特に、樹脂封止工程（モールド工程）においては、特別な形状にキャビティーを設ける必要はなく、平板状のものでその両側を抑えた状態で一括モールドが簡単に行え、量産性、設備の面からも好ましい構造と言える。
端子部材としては、Ｃｕ、Ｃｕ系合金、４２％Ｎｉ−Ｆｅ系合金からなるものが挙げられる。
また、内部端子部の端子面および外部端子部の表裏の端子面に、半田めっき層、金めっき層、銀めっき層、パラジウムめっき層、錫めっき層から選ばれた１つの金属めっき層を、接続用のめっき層としていることにより、ワイヤボンディング接続を信頼性良いものとしている。
また、半導体素子の端子面側でない面を露出させるようにして、配置していることにより、ダイパッドレスからパッケージ内の半導体素子上のレジン厚を増し、組み立て加工し易いものとしており、より放熱性に優れるものとしている。 Further, in the tip section of the thin portion on the semiconductor element side of the terminal member, the half-etch formation surface and the side surface form an acute angle, so that the internal terminal portion on the semiconductor element side has an acute angle. At the front end in the longitudinal direction, the resin is tightened according to the temperature change, and the structure has good moisture resistance.
It is also possible to increase the amount of sealing resin by the amount that the tip has an acute angle, and the amount of sealing resin increases, so that the structure and quality are stabilized.
In particular, in the case of the QFP type, even if the number of terminals is large, the quality can be stabilized and effective. The acute angle is preferably 85 degrees or less.
In addition, each terminal member has a tapered width at the tip of the thin portion on the semiconductor element side. By adopting the form of the invention of claim 4, the amount of sealing resin is reduced by the amount of taper at the tip. It can be increased, and the amount of sealing resin increases, so that the structure and quality are stabilized.
Further, the surface portion of each terminal member in contact with the sealing resin surface is subjected to a roughening treatment, whereby the adhesiveness between the terminal member and the sealing resin is improved. Improvement can be achieved.
In particular, it is effective when the maximum height roughness Ry (JISBO601-1994) by the roughening treatment is in the range of 1 μm to 2 μm.
Further, by providing a cutout portion extending over the other side of the external terminal portion, the outer surface and the outer side surface, in the preparation of the imposition, in the preparation of the imposition, It is easy to cut.
In particular, in the resin sealing process (molding process), it is not necessary to provide a cavity in a special shape, and it is easy to perform batch molding with a flat plate with both sides suppressed. Therefore, it can be said to be a preferable structure.
Examples of the terminal member include those made of Cu, a Cu-based alloy, and a 42% Ni—Fe-based alloy.
In addition, one metal plating layer selected from a solder plating layer, a gold plating layer, a silver plating layer, a palladium plating layer, and a tin plating layer is connected to the terminal surface of the internal terminal portion and the front and back terminal surfaces of the external terminal portion. Therefore, the wire bonding connection is made reliable.
In addition, by disposing the semiconductor element so that the surface that is not on the terminal surface side is exposed, the resin thickness on the semiconductor element in the package is increased from the die padless, making it easier to assemble, and more heat dissipation It is supposed to be excellent.

本発明の樹脂封止型半導体装置の製造方法は、このような構成にすることにより、請求項１〜請求項１１の各発明の薄型の樹脂封止型半導体装置を、量産性良く製造できるものとしている。   The manufacturing method of the resin-encapsulated semiconductor device of the present invention can manufacture the thin resin-encapsulated semiconductor device of each invention of claims 1 to 11 with high productivity by adopting such a configuration. It is said.

本発明は、上記のように、小型化、薄型、多機能（多ピン）で、特にワイヤボンディングがし易く、作製上の歩留まりの向上が期待でき、生産性が良い、パッケージとして、メタルサブストレートを用いた樹脂封止型の半導体装置の提供を可能とした。
同時に、このような樹脂封止型半導体装置の製造方法の提供を可能とした。
このような樹脂封止型半導体装置や積層型樹脂封止型半導体装置は、メモリ用のパッケージ、システムパッケージの他、カードモジュール内、ＩＣカード内、ＰＯＰ（Ｐｏｉｎｔ Ｏｆ Ｐｕｒｃｈａｓｅ ａｄｖｅｒｔｉｓｉｎｇ ）カード内、基板（紙スート等）内等に、特に薄さが求められる場合に、有効に利用できる。 As described above, the present invention is small, thin, multifunctional (multi-pin), particularly easy to wire bond, can be expected to improve the production yield, and has good productivity. It is possible to provide a resin-encapsulated semiconductor device using the above.
At the same time, it is possible to provide a method for manufacturing such a resin-encapsulated semiconductor device.
Such a resin-encapsulated semiconductor device and a laminated resin-encapsulated semiconductor device include a memory package, a system package, a card module, an IC card, a POP (Point Of Purchasing advertising) card, a substrate ( It can be effectively used when a thinness is particularly required in a paper soot or the like.

本発明の実施の形態を図に基づいて説明する。
図１（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第１の例を示した概略断面図で、図１（ｂ）は図１（ａ）のＡ１側から透視してみた図で、図２（ａ）は端子部材の断面図で、図２（ｂ）は図１（ａ）のＢ１側から見た図で、図２（ｃ）は図２（ａ）のＢ２側からみた図で、図２（ｄ）は図２（ｄ）のＢ３側からみた図で、図３（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第２の例を示した概略断面図で、図３（ｂ）は本発明の樹脂封止型半導体装置の実施の形態の第３の例を示した概略断面図で、図３（ｃ）は本発明の樹脂封止型半導体装置の実施の形態の第４の例を示した概略断面図で、図４（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第５の例を示した概略断面図で、図４（ｂ）は本発明の樹脂封止型半導体装置の実施の形態の第６の例を示した概略断面図で、図５（ａ）〜図５（ｅ）は本発明の樹脂封止型半導体装置の製造方法の実施の形態の第１の例の一部製造工程を示した工程断面図で、図６（ｆ）〜図６（ｉ）は、図５に続く製造工程を示した工程断面図で、図６（ｊ）は半田ボールをつけた断面図で、図７（ａ）〜図７（ｆ）は本発明の樹脂封止型半導体装置の製造方法の実施の形態の第２の例の一部製造工程を示した工程断面図で、図８（ｇ）〜図８（ｊ）は、図７に続く製造工程を示した工程断面図で、図８（ｋ）は半田ボールをつけた断面図で、図９はダイシングソーによる切断状態を示した図である。
尚、図１（ａ）は図１（ｂ）のＡ１−Ａ２側から見た図で、図５〜図８においては、分かり易くするために、半導体素子の端子部は省略して示している。
また、図６（ｈ）、図８（ｉ）における両方向矢印は、ダイシングソーの昇降方向を示している。
図１〜図９中、１０１、１０１Ａ、１０２、１０２Ａは樹脂封止型半導体装置、１１０は端子部材、１１０ａ、１１０ｃは薄肉部、１１０ｂは厚肉部、１１０ｆは（一方の側の）平坦な面、１１１ａ、１１１ｂは内部端子部、１１２ａ、１１２ｂは外部端子部、１１４は切り欠け部、１１６は先端部、１１６Ｓは（先端の）側面、１１７はグルーブ（溝部）、１２０は第１の半導体素子（単に半導体素子あるいはチップとも言う）、１２１、１２２、１２３は半導体素子（チップとも言う）、１２０Ｓは（第１の半導体素子の）裏面、１２０ａ、１２１ａ、１２２ａ、１２３ａは端子部、１２５、１２５Ａ、１５Ｂは積層半導体素子群、１３０はボンディングワイヤ、１４０は封止用樹脂（単に樹脂とも言う）、２１０は加工用素材、２１０Ａは加工シート、２２０はレジスト、２３０は端子部材、２３０ａは薄肉部、２３０ｂは厚肉部、２３５は支持部（連結部とも言う）、２３７は凹部、２３７Ａは切り欠け部、２４０は平板状の多孔板（真空引き板とも言う）、２５０は積層半導体素子群、２５１、２５２は半導体素子、２６０はボンディングワイヤ、２７０、２７１は（固定用、モールド用の）テープ、２７５は（ダイシング用の）テープ、２８０は封止用樹脂、２９０は半田ボール、３１０は加工用素材、３１０Ａは加工シート、３２０はレジスト、３３０は端子部材、３３５は支持部（連結部とも言う）、３３７は凹部、３３７Ａは切り欠け部、３４０、３４１は（固定用、モールド用の）テープ、３４５は（切断用の）テープ、３５０は積層半導体素子群、３５１、３５２は半導体素子、３６０はボンディングワイヤ、３７１、３７２はモールド固定用の平板、３８０は封止用樹脂、３９０は半田ボール、４０１は単位の樹脂封止型半導体装置、４１０Ａは加工シート、４１５は枠部、４１６は治具孔、４１７は長孔部、４８５は切断ライン、４８６は切断目印（貫通孔あるいは窪み）である。 Embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a schematic cross-sectional view showing a first example of an embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 1B is seen through from the A1 side of FIG. 2A is a cross-sectional view of the terminal member, FIG. 2B is a view seen from the B1 side of FIG. 1A, and FIG. 2C is B2 of FIG. 2A. 2D is a diagram seen from the B3 side of FIG. 2D, and FIG. 3A is a second example of the embodiment of the resin-encapsulated semiconductor device of the present invention. FIG. 3B is a schematic cross-sectional view showing a third example of the embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 3C is a resin seal of the present invention. FIG. 4A is a schematic sectional view showing a fourth example of the embodiment of the stationary semiconductor device, and FIG. 4A is a schematic sectional view showing the fifth example of the embodiment of the resin-encapsulated semiconductor device of the present invention. FIG. 4 (b) shows the resin-sealed mold of the present invention. FIG. 5A to FIG. 5E are schematic sectional views showing a sixth example of the embodiment of the conductor device, and FIG. 5A to FIG. 5E show the first embodiment of the method for manufacturing the resin-encapsulated semiconductor device of the present invention. 6 (f) to 6 (i) are process cross-sectional views illustrating the manufacturing process subsequent to FIG. 5, and FIG. 6 (j) is a solder ball. 7 (a) to 7 (f) are process cross sections showing a partial manufacturing process of the second example of the embodiment of the method for manufacturing the resin-encapsulated semiconductor device of the present invention. 8 (g) to 8 (j) are process cross-sectional views showing the manufacturing process following FIG. 7, FIG. 8 (k) is a cross-sectional view with solder balls, and FIG. 9 is a dicing saw. It is the figure which showed the cutting state by.
1A is a view as seen from the A1-A2 side of FIG. 1B, and in FIG. 5 to FIG. 8, the terminal portions of the semiconductor elements are omitted for easy understanding. .
6 (h) and FIG. 8 (i), the double arrows indicate the ascending / descending direction of the dicing saw.
1 to 9, 101, 101A, 102, 102A are resin-encapsulated semiconductor devices, 110 is a terminal member, 110a, 110c are thin-walled portions, 110b is a thick-walled portion, and 110f is flat (on one side). 111a and 111b are internal terminal portions, 112a and 112b are external terminal portions, 114 is a notch portion, 116 is a tip portion, 116S is a (side) side surface, 117 is a groove (groove portion), and 120 is a first semiconductor. Elements (also simply referred to as semiconductor elements or chips), 121, 122, and 123 are semiconductor elements (also referred to as chips), 120S is a back surface (of the first semiconductor element), 120a, 121a, 122a, and 123a are terminal portions, 125, 125A and 15B are stacked semiconductor element groups, 130 is a bonding wire, 140 is a sealing resin (also simply referred to as resin), 210 is a processing material, 210 Is a processed sheet, 220 is a resist, 230 is a terminal member, 230a is a thin part, 230b is a thick part, 235 is a support part (also called a connecting part), 237 is a recess, 237A is a notch part, and 240 is a flat plate Perforated plate (also called vacuum drawing plate), 250 is a laminated semiconductor element group, 251 and 252 are semiconductor elements, 260 is a bonding wire, 270 and 271 are tapes (for fixing and molding), 275 is (for dicing) Tape 280, sealing resin, 290, solder balls, 310, processing material, 310A, processing sheet, 320, resist, 330, terminal member, 335, support portion (also referred to as connecting portion), 337, recess, 337A , 340 and 341 are tapes (for fixing and molding), 345 is a tape (for cutting), 350 is a laminated semiconductor element group, 351, 52 is a semiconductor element, 360 is a bonding wire, 371 and 372 are mold fixing flat plates, 380 is a sealing resin, 390 is a solder ball, 401 is a unit resin-encapsulated semiconductor device, 410A is a processed sheet, 415 is A frame part, 416 are jig holes, 417 is a long hole part, 485 is a cutting line, and 486 is a cutting mark (through hole or depression).

はじめに、本発明の樹脂封止型半導体装置の実施の形態の第１の例を、図１に基づいて説明する。
第１の例の樹脂封止型半導体装置１０１は、複数個の端子部材１１０を、互いに離間して、半導体素子１２０、１２１を積層した積層半導体素子群１２５の周辺に沿い積層半導体素子群１２５から離して配設し、該積層半導体素子群１２５と、それに接続するボンディングワイヤ１３０と、該複数の端子部材１１０とを一体的に樹脂封止したＱＦＮ型の樹脂封止型半導体装置である。
そして、各端子部材１１０は、エッチング加工法にて、加工用素材から、厚肉部１１０ｂを加工用素材の厚さにし、薄肉部１１０ａ、１１０ｃを該加工用素材の一面側からのハーフエッチングにて薄肉にして形成されたもので、厚肉部１１０ｂと薄肉部１１０ａ、１１０ｃとを有し、一方側を平坦にし、他方の側を２段の段状にし、厚肉部１１０ｂの両側にその端に至る薄肉部１１０ａ、１１０ｃを配し、該一方の側の平坦な面を外部端子部１１２ａとし、該他方の側の各段部の面を内部端子部１１１ａ、１１１ｂとしている。
また、積層半導体素子群１２５は、端子部材１１０の薄肉部１１０ａ、１１０ｃの厚さより薄い第１の半導体素子１２０の端子側面に、端子面の向きを揃え、第１の半導体素子１２０を含み、順次、端子面のサイズが小サイズとなる、薄肉の半導体素子１２１を樹脂ペースト等により固定して積層したもので、積層半導体素子群１２５の各半導体素子の端子部１２０ａ、１２１ａと、端子部材１１０の各段部の内部端子部１１１ａ、１１１ｂとを、ボンディングワイヤ１３０にて接続している。
半導体素子１２０、１２１は、それぞれ、その周辺に沿い、端子１２０ａ、１２１ａを設けたものである。
特に、各端子部材１１０を、その前記一方の側の平坦な面１１０ｆを一平面上に揃えて、同じ向きにして、各端子部材１１０の一方の端に至る薄肉部１１０ａ側を半導体素子１２０、１２０ａ側に向け、他方の端に至る薄肉部１１０ｃを外側に向けて、配し、各端子部材１１０の一方の側の平坦な面１１０ｆとその側面とを露出させ、且つ、第１の半導体素子１２０の端子面でない側の裏面１２０Ｓを、各端子部材１１０の一方の側の平坦な面１１０ｆに揃えて、第１の半導体素子１２０の裏面１２０Ｓを露出させるようにして、樹脂１４０中に、配置して、全体を端子部材１１０の厚肉部１１０ｂの厚さ幅より大きい幅として、樹脂封止している。 First, a first example of an embodiment of the resin-encapsulated semiconductor device of the present invention will be described with reference to FIG.
In the resin-encapsulated semiconductor device 101 of the first example, a plurality of terminal members 110 are separated from each other, and from the laminated semiconductor element group 125 along the periphery of the laminated semiconductor element group 125 in which the semiconductor elements 120 and 121 are laminated. A QFN type resin-encapsulated semiconductor device in which the laminated semiconductor element group 125, the bonding wires 130 connected thereto, and the plurality of terminal members 110 are integrally resin-sealed, which are arranged apart from each other.
Then, each of the terminal members 110 is etched into a thickness of the thick portion 110b from the processing material, and the thin portions 110a and 110c are half-etched from one side of the processing material. It has a thick part 110b and thin parts 110a, 110c, one side is flattened, the other side is two steps, and the thick part 110b is provided on both sides thereof. The thin portions 110a and 110c reaching the end are arranged, the flat surface on one side is used as the external terminal portion 112a, and the surface of each step on the other side is used as the internal terminal portions 111a and 111b.
In addition, the laminated semiconductor element group 125 includes the first semiconductor elements 120 in which the terminal surfaces are aligned on the terminal side surfaces of the first semiconductor elements 120 thinner than the thickness of the thin portions 110a and 110c of the terminal member 110. The thin semiconductor element 121 having a small terminal surface size is fixed and laminated with a resin paste or the like, and the terminal portions 120a and 121a of each semiconductor element of the laminated semiconductor element group 125 and the terminal member 110 The internal terminal portions 111 a and 111 b of each step portion are connected by a bonding wire 130.
The semiconductor elements 120 and 121 are each provided with terminals 120a and 121a along the periphery thereof.
In particular, each of the terminal members 110 has the flat surface 110f on the one side thereof aligned on a single plane and oriented in the same direction, and the thin portion 110a side reaching one end of each terminal member 110 is disposed on the semiconductor element 120, The thin portion 110c reaching the other end toward the 120a side is arranged outward, the flat surface 110f on one side of each terminal member 110 and its side surface are exposed, and the first semiconductor element The back surface 120S on the side that is not the terminal surface of 120 is aligned with the flat surface 110f on one side of each terminal member 110 so that the back surface 120S of the first semiconductor element 120 is exposed, and is disposed in the resin 140. Then, the whole is sealed with a resin having a width larger than the thickness of the thick portion 110b of the terminal member 110.

本例においては、各端子部材１１０は、その半導体素子１２０、１２０ａ側の薄肉部１１０ａの先端断面は、ハーフエッチング形成面（内部端子部１１１ａ）と側面１１６とが鋭角をなし、また、その半導体素子１２０、１２１側の薄肉部１１０ａの先端幅を先細とし、更に、更に、グルーブを前記一方の面側に配している。（図２（ａ）〜図２（ｄ）を参照）
本例では、厚さ０．２ｍｍのＣｕ材を加工用素材として、薄肉部１１０ａ、１１０ｃの厚さを０．１ｍｍとし、厚さ７０μｍの半導体素子１２０、１２０ａを用いたが、加工用素材としては、Ｃｕ系合金や４２合金（４２％Ｎｉ−Ｆｅ合金）等も適用できる。
本例においては、全体の厚さを、０．３ｍｍ以下とすることができる。
半導体素子１２０、１２１自体の厚さの薄化に対応して、薄型化が達成できる。
このように、端子部材１１０の薄肉部１１０ａの先端形状を工夫していることにより、薄肉部１１０ａの先端において、温度変化による封止用樹脂の締め付けを良くし、耐湿性の良いものとしている。
本例の構造は、薄い半導体素子１２０、１２１と薄い端子部材１１０とを用い、全体の厚さを薄くしながら、且つ、封止用樹脂の厚さを出来る限り厚くしている構造で、封止用樹脂の量を増やすことにより、構造的に品質面安定が期待できる。
また、本例では、第１の半導体素子１２０の端子部１２０ａと薄肉部１１０ａの内部端子部１１１ａとを接続し、半導体素子１２１の端子部１２１ａと厚肉部１１０ｂの内部端子部とを接続しているが、第１の半導体素子１２０の厚さは薄肉子部１１０ａの厚さより薄くなっており、また、積層半導体素子群１２５の厚さも厚肉部１１０ｂ厚さより薄くなっており、これにより、半導体素子１２０、１２１のボンディング作業をし易いものとしている。
第１の例の樹脂封止型半導体装置は、このような構成にすることにより、小型化、薄型、多機能（多ピン）で、特にワイヤボンディングがし易く、作製上の歩留まりの向上が期待でき、生産性の良い、パッケージとしている。 In this example, each terminal member 110 has a half-etch forming surface (internal terminal portion 111a) and a side surface 116 forming an acute angle in the tip cross section of the thin portion 110a on the semiconductor element 120, 120a side. The tip width of the thin portion 110a on the element 120, 121 side is tapered, and a groove is further arranged on the one surface side. (See FIG. 2 (a) to FIG. 2 (d))
In this example, a Cu material having a thickness of 0.2 mm is used as a processing material, the thickness of the thin portions 110a and 110c is set to 0.1 mm, and the semiconductor elements 120 and 120a having a thickness of 70 μm are used. Cu based alloy, 42 alloy (42% Ni-Fe alloy), etc. can also be applied.
In this example, the overall thickness can be set to 0.3 mm or less.
A reduction in thickness can be achieved in response to a reduction in the thickness of the semiconductor elements 120 and 121 themselves.
Thus, by devising the tip shape of the thin portion 110a of the terminal member 110, the sealing resin is tightened by the temperature change at the tip of the thin portion 110a, and the moisture resistance is good.
The structure of this example uses thin semiconductor elements 120 and 121 and a thin terminal member 110, has a structure in which the thickness of the sealing resin is increased as much as possible while reducing the overall thickness. By increasing the amount of the stopping resin, structurally stable quality can be expected.
Further, in this example, the terminal part 120a of the first semiconductor element 120 and the internal terminal part 111a of the thin part 110a are connected, and the terminal part 121a of the semiconductor element 121 and the internal terminal part of the thick part 110b are connected. However, the thickness of the first semiconductor element 120 is thinner than the thickness of the thin portion 110a, and the thickness of the stacked semiconductor element group 125 is also thinner than the thickness of the thick portion 110b. The semiconductor elements 120 and 121 are easily bonded.
By adopting such a configuration, the resin-encapsulated semiconductor device of the first example is miniaturized, thin, and multifunctional (multi-pin), and is particularly easy to wire bond and is expected to improve the manufacturing yield. Can be packaged with good productivity.

第１の例においては、薄型のＱＦＮ型であり、端子部材１１０の数も多く、各端子部材１１０の表面を、過酸化水素溶液にて、粗面化処理している。
これにより、一層の耐湿性の向上が図れる。
表面粗さとしては、最大高さ粗さＲｙ（ＪＩＳＢＯ６０１−１９９４）で１μｍ〜２μｍの範囲が好ましい。
先にも述べたが、ここでは、最大高さ粗さＲｙの測定は２００μｍ長さで行ったものである。 The first example is a thin QFN type, has a large number of terminal members 110, and the surface of each terminal member 110 is roughened with a hydrogen peroxide solution.
Thereby, further improvement in moisture resistance can be achieved.
The surface roughness is preferably in the range of 1 μm to 2 μm in terms of the maximum height roughness Ry (JISBO601-1994).
As described above, here, the measurement of the maximum height roughness Ry was performed with a length of 200 μm.

また、第１の例においては、外部端子部１１１の前記他方側の面と外側側面にわたる切り欠け部１１４を設けており、これにより、その面付け作製において、個片化の際、その切断をし易いものとしている。
特に、樹脂封止工程（モールド工程）においては、特別な形状にキャビティーを設ける必要はなく、平板状のものでその両側を抑えた状態で一括モールドが簡単に行え、量産性、設備の面からも好ましい構造と言える。 Further, in the first example, a cutout portion 114 extending between the other side surface and the outer side surface of the external terminal portion 111 is provided. It is easy to do.
In particular, in the resin sealing process (molding process), it is not necessary to provide a cavity in a special shape, and it is easy to perform batch molding with a flat plate with both sides suppressed. Therefore, it can be said to be a preferable structure.

第１の例においては、図では明示していないが、端子部材１１０の内部端子部１１２の端子面および外部端子部１１１の表裏の端子面に、接続用のめっき層をつけている。
接続用のめっき層として、半田めっき層、金めっき層、銀めっき層、パラジウムめっき層、錫めっき層等の金属めっき層が挙げられる。 In the first example, although not explicitly shown in the drawing, a plating layer for connection is provided on the terminal surface of the internal terminal portion 112 of the terminal member 110 and the front and back terminal surfaces of the external terminal portion 111.
Examples of the plating layer for connection include metal plating layers such as a solder plating layer, a gold plating layer, a silver plating layer, a palladium plating layer, and a tin plating layer.

次に、本発明の樹脂封止型半導体装置の別の形態例を挙げる。
第２の例は、図３（ａ）にその断面を示すように、第１の例の樹脂封止型半導体装置１０１に対して、更に、端子部材１１０一方の側の平坦な面１１０ｆに半田ボール１９０を備えているものである。
配線基板等へ半田ボール溶融により実装を行うことができる。
半田ボール１９０の外径を０．２ｍｍとした場合、加工用素材の厚さは０．２ｍｍであり、全体の厚さを、０．５ｍｍ以下とすることができる。 Next, another embodiment of the resin-encapsulated semiconductor device of the present invention will be given.
In the second example, as shown in a cross section in FIG. 3A, solder is further applied to the flat surface 110f on one side of the terminal member 110 with respect to the resin-encapsulated semiconductor device 101 of the first example. A ball 190 is provided.
Mounting can be performed on a wiring board or the like by melting solder balls.
When the outer diameter of the solder ball 190 is 0.2 mm, the thickness of the processing material is 0.2 mm, and the overall thickness can be 0.5 mm or less.

第３の例の樹脂封止型半導体装置１０２は、図３（ｂ）にその断面を示すように、複数個の端子部材１１０を、互いに離間して、半導体素子１２０、１２１、１２２を積層した積層半導体素子群１２５Ａの周辺に沿い積層半導体素子群１２５Ａから離して配設し、該積層半導体素子群１２５Ａと、それに接続するボンディングワイヤ１３０と、該複数の端子部材１１０とを一体的に樹脂封止したＱＦＮ型の樹脂封止型半導体装置である。
第１の例において、積層半導体素子群１２５を積層半導体素子群１２５Ａに置きかえて、各半導体素子１２０、１２１、１２２の端子部１２０ａ、１２１ａ、１２２ａと端子部材１１０の内部端子部１１０ａ、１１０ｃとをボンディングワイヤ１３０により接続し、第１の例と同様にして、樹脂封止したものである。
本例の端子部材は、厚さ０．２５ｍｍのＣｕ材を加工用素材として、薄肉部１１０ａ、１１０ｃの厚さを０．１２５ｍｍとしているが、サイズ以外、形状や材質については、第１の例と同様のものを用いている。
積層半導体素子群１２５Ａは、第１の例の積層半導体素子群１２５に更に厚さ７０μｍの半導体素子１２２を樹脂ペースト等により固定して積層したものである。
第２の例においては、第１の半導体素子１２０の端子部１２０ａと薄肉部１１０ａの内部端子部１１１ａとを接続し、半導体素子１２１、１２２の端子部１２１ａ、１２２ａと厚肉部１１０ｂの内部端子部とを接続しているが、第１の例の場合と同様、第１の半導体素子１２０の厚さは薄肉子部１１０ａの厚さより薄くなっており、また、第１の半導体素子１２０の裏面１２０から半導体素子１２２の端子部１２２ａまでの厚さも厚肉部１１０ｂの厚さより薄くなっており、また、積層半導体素子群１２５Ａの厚さも厚さも厚肉部１１０ｂの厚さより薄くなっており、これにより、半導体素子１２０、１２１、１２２のボンディング作業をし易いものとしている。
第３の例の構造も、薄い半導体素子１２０、１２１、１２２と薄い端子部材１１０とを用い、全体の厚さを薄くしながら、且つ、封止用樹脂の厚さを出来る限り厚くしている構造で、封止用樹脂の量を増やすことにより、構造的に品質面安定が期待できる。
第３の例の樹脂封止型半導体装置１０２は、このような構成にすることにより、小型化、薄型、多機能（多ピン）で、特にワイヤボンディングがし易く、作製上の歩留まりの向上が期待でき、生産性の良い、パッケージとしている。
第３の例の場合、全体の厚さを、０．３５ｍｍ以下とすることができる。 In the resin-encapsulated semiconductor device 102 of the third example, as shown in the cross section of FIG. 3B, a plurality of terminal members 110 are separated from each other, and semiconductor elements 120, 121, and 122 are stacked. Along the periphery of the laminated semiconductor element group 125A, the laminated semiconductor element group 125A is disposed away from the laminated semiconductor element group 125A, and the laminated semiconductor element group 125A, the bonding wires 130 connected thereto, and the plurality of terminal members 110 are integrally sealed with resin. This is a stopped QFN type resin-encapsulated semiconductor device.
In the first example, the laminated semiconductor element group 125 is replaced with a laminated semiconductor element group 125A, and the terminal portions 120a, 121a, 122a of the semiconductor elements 120, 121, 122 and the internal terminal portions 110a, 110c of the terminal member 110 are replaced. They are connected by bonding wires 130 and sealed with resin in the same manner as in the first example.
In the terminal member of this example, a Cu material having a thickness of 0.25 mm is used as a processing material, and the thickness of the thin portions 110a and 110c is 0.125 mm. However, the shape and material other than the size are the first example. The same thing is used.
The laminated semiconductor element group 125A is obtained by further laminating a semiconductor element 122 having a thickness of 70 μm with a resin paste or the like on the laminated semiconductor element group 125 of the first example.
In the second example, the terminal part 120a of the first semiconductor element 120 and the internal terminal part 111a of the thin part 110a are connected, and the terminal parts 121a and 122a of the semiconductor elements 121 and 122 and the internal terminal of the thick part 110b are connected. As in the first example, the thickness of the first semiconductor element 120 is thinner than the thickness of the thin-walled portion 110a, and the back surface of the first semiconductor element 120 The thickness from 120 to the terminal portion 122a of the semiconductor element 122 is also thinner than the thickness of the thick portion 110b, and the thickness and thickness of the laminated semiconductor element group 125A are also thinner than the thickness of the thick portion 110b. This facilitates the bonding operation of the semiconductor elements 120, 121, and 122.
The structure of the third example also uses the thin semiconductor elements 120, 121, 122 and the thin terminal member 110, and the thickness of the sealing resin is increased as much as possible while reducing the overall thickness. By increasing the amount of sealing resin in the structure, structural stability can be expected structurally.
By adopting such a configuration, the resin-encapsulated semiconductor device 102 of the third example is miniaturized, thin, and multi-functional (multi-pin), and is particularly easy to wire bond and improves the manufacturing yield. Expected to be a productive package.
In the case of the third example, the overall thickness can be set to 0.35 mm or less.

第４の例の樹脂封止型半導体装置１０２Ａは、図３（ｃ）にその断面を示すように、第３の例の樹脂封止型半導体装置１０２に対して、更に、端子部材１１０一方の側の平坦な面１１０ｆに半田ボール１９０を備えているものである。
配線基板等へ半田ボール溶融により実装を行うことができる。
半田ボール１９０の外径を０．２ｍｍとした場合、加工用素材の厚さは０．２５ｍｍであり、全体の厚さを、０．５５ｍｍ以下とすることができる。 As shown in the cross section of FIG. 3C, the resin-encapsulated semiconductor device 102A of the fourth example further includes one terminal member 110 than the resin-encapsulated semiconductor device 102 of the third example. The solder ball 190 is provided on the flat surface 110f on the side.
Mounting can be performed on a wiring board or the like by melting solder balls.
When the outer diameter of the solder ball 190 is 0.2 mm, the thickness of the processing material is 0.25 mm, and the total thickness can be 0.55 mm or less.

第５の例の樹脂封止型半導体装置１０３は、図４（ａ）にその断面を示すように、複数個の端子部材１１０を、互いに離間して、半導体素子１２０、１２１、１２２、１２３を積層した積層半導体素子群１２５Ｂの周辺に沿い積層半導体素子群１２５Ｂから離して配設し、該積層半導体素子群１２５Ｂと、それに接続するボンディングワイヤ１３０と、該複数の端子部材１１０とを一体的に樹脂封止したＱＦＮ型の樹脂封止型半導体装置である。
第３の例において、積層半導体素子群１２５Ａを積層半導体素子群１２５Ｂに置きかえて、各半導体素子１２０、１２１、１２２の端子部１２０ａ、１２１ａ、１２２ａと端子部材１１０の内部端子部１１０ａ、１１０ｃとをボンディングワイヤにより接続し、第３の例と同様にして、樹脂封止したものである。
第５の例の端子部材は、厚さ０．２５ｍｍのＣｕ材を加工用素材として、薄肉部１１０ａ、１１０ｃの厚さを０．１２５ｍｍとしているが、サイズ以外、形状や材質については、第１の例と同様のものを用いている。
積層半導体素子群１２５Ｂは、第３の例の積層半導体素子群１２５Ａに更に厚さ７０μｍの半導体素子１２３を樹脂ペースト等により固定して積層したものである。
第５の例においては、半導体素子１２０、１２１の端子部１２０ａ、１２１ａと薄肉部１１０ａの内部端子部１１１ａとを接続し、半導体素子１２２、１２３の端子部１２２ａ、１２３ａと厚肉部１１０ｂの内部端子部とを接続しているが、第１の半導体素子１２０の厚さは薄肉子部１１０ａの厚さより薄くなっており、且つ、第１の半導体素子１２０の裏面１２０から半導体素子１２１の端子部１２１ａまでの厚さも若干薄肉子部１１０ａの厚さより薄くなっており、更にまた、第１の半導体素子１２０の裏面１２０から半導体素子１２２の端子部１２２ａまでの厚さも厚肉部１１０ｂの厚さより薄くなっており、且つ、第１の半導体素子１２０の裏面１２０から半導体素子１２３の端子部１２３ａまでの厚さも厚肉部１１０ｂの厚さより若干薄くなっており、これにより、半導体素子１２０、１２１、１２２、１２３のボンディング作業をし易いものとしている。
第５の例の構造も、薄い半導体素子１２０、１２１、１２２、１２３と薄い端子部材１１０とを用い、全体の厚さを薄くしながら、且つ、封止用樹脂の厚さを出来る限り厚くしている構造で、封止用樹脂の量を増やすことにより、構造的に品質面安定が期待できる。 第５の例の樹脂封止型半導体装置１０３は、このような構成にすることにより、小型化、薄型、多機能（多ピン）で、特にワイヤボンディングがし易く、作製上の歩留まりの向上が期待でき、生産性の良い、パッケージとしている。
第５の例の場合、全体の厚さを、０．４ｍｍ以下とすることができる。 As shown in FIG. 4A, the resin-encapsulated semiconductor device 103 of the fifth example has a plurality of terminal members 110 separated from each other, and semiconductor elements 120, 121, 122, 123 are arranged. The laminated semiconductor element group 125B is disposed along the periphery of the laminated semiconductor element group 125B and separated from the laminated semiconductor element group 125B, and the laminated semiconductor element group 125B, the bonding wires 130 connected thereto, and the plurality of terminal members 110 are integrally formed. This is a resin-encapsulated QFN type resin-encapsulated semiconductor device.
In the third example, the laminated semiconductor element group 125A is replaced with the laminated semiconductor element group 125B, and the terminal portions 120a, 121a, 122a of the semiconductor elements 120, 121, 122 and the internal terminal portions 110a, 110c of the terminal member 110 are replaced. They are connected by bonding wires and sealed with resin in the same manner as in the third example.
In the terminal member of the fifth example, a Cu material having a thickness of 0.25 mm is used as a processing material, and the thickness of the thin portions 110a and 110c is set to 0.125 mm. The same thing as the example of is used.
The laminated semiconductor element group 125B is obtained by further laminating a semiconductor element 123 having a thickness of 70 μm with a resin paste or the like on the laminated semiconductor element group 125A of the third example.
In the fifth example, the terminal portions 120a and 121a of the semiconductor elements 120 and 121 are connected to the internal terminal portion 111a of the thin portion 110a, and the terminal portions 122a and 123a and the thick portion 110b of the semiconductor elements 122 and 123 are connected. Although the terminal portion is connected, the thickness of the first semiconductor element 120 is smaller than the thickness of the thin-walled portion 110 a, and the terminal portion of the semiconductor element 121 from the back surface 120 of the first semiconductor element 120. The thickness up to 121a is slightly thinner than the thickness of the thin portion 110a, and the thickness from the back surface 120 of the first semiconductor element 120 to the terminal portion 122a of the semiconductor element 122 is also thinner than the thickness of the thick portion 110b. And the thickness from the back surface 120 of the first semiconductor element 120 to the terminal portion 123a of the semiconductor element 123 is also larger than the thickness of the thick portion 110b. Is thinner interference, thereby, it is assumed easily the bonding work of the semiconductor device 120, 121, 122, 123.
The structure of the fifth example also uses thin semiconductor elements 120, 121, 122, 123 and a thin terminal member 110, and while making the entire thickness thin, the thickness of the sealing resin is made as thick as possible. By increasing the amount of sealing resin in the structure, the structural stability can be expected structurally. The resin-encapsulated semiconductor device 103 of the fifth example has such a configuration, and is small, thin, and multi-functional (multi-pin), and is particularly easy to wire bond and improves the manufacturing yield. Expected to be a productive package.
In the case of the fifth example, the overall thickness can be set to 0.4 mm or less.

第６の例の樹脂封止型半導体装置１０３Ａは、図４（ｂ）にその断面を示すように、第５の例の樹脂封止型半導体装置１０３に対して、更に、端子部材１１０一方の側の平坦な面１１０ｆに半田ボール１９０を備えているものである。
配線基板等へ半田ボール溶融により実装を行うことができる。
半田ボール１９０の外径を０．２ｍｍとした場合、加工用素材の厚さは０．２５ｍｍであり、全体の厚さを、０．６ｍｍ以下とすることができる。 The resin-encapsulated semiconductor device 103A according to the sixth example has one terminal member 110 further than the resin-encapsulated semiconductor device 103 according to the fifth example, as shown in FIG. The solder ball 190 is provided on the flat surface 110f on the side.
Mounting can be performed on a wiring board or the like by melting solder balls.
When the outer diameter of the solder ball 190 is 0.2 mm, the thickness of the processing material is 0.25 mm, and the overall thickness can be 0.6 mm or less.

次いで、第１の例の樹脂封止型半導体装置の製造方法の１例を、図５、図６に基づいて、説明する。
尚、これを以って、本発明の樹脂封止型半導体装置の製造方法の１例（第１の例）の説明に代える。
先ず、加工用素材２１０の両面に所定形状にレジスト２２０を配設し（図５（ａ））、１つの樹脂封止型半導体装置の端子部材の配置に対応した、端子部材の配置を１単位として、この配置状態に、ハーフエッチング技術を用いたエッチング加工法にて、両面からエッチングを行い、端子部材２３０を、支持部２３５にて連結した状態で、面付けして形成する。（図５（ｂ））
これにより、１つの樹脂封止型半導体装置の端子部材の配置に対応した、端子部材の配置を１単位として、これが支持部２３５にて連結され面付けされた、加工シート２１０Ａを得る。
加工用素材２１０としては、Ｃｕ、Ｃｕ系合金、４２合金（Ｎｉ４２％−Ｆｅ合金）等が用いられ、エッチング液としては、塩化第二鉄溶液が用いられる。
また、レジスト２２０としては、耐エッチング性のもので、所望の解像性を有し、処理性の良いものであれば特に限定はされない。
次いで、レジスト２２０を除去後、洗浄処理等を施し、全面に接続用の表面めっきを施した（図示していない）後、面付け形成され、表面めっきが施された加工シート２１０Ａのハーフエッチング面側ではない側を平板状の多孔板２４０にて真空引きし、加工シート２１０Ａを多孔板２４０に密着させた状態で（図５（ｃ））、面付け分の数だけ、積層半導体素子群２５０を所定の位置に位置決めして、その端子面側ではない裏面を真空引き用の多孔板２４０にて真空引きして、該多孔板２４０に搭載する。（図５（ｄ））
尚、真空ポンプ、真空配管等、真空引き用の多孔板２４０の真空引き源は別にあるが、ここでは図示していない。
次いで、この状態で、各積層半導体素子群２５０の各半導体素子２５１、２５２について、その端子（図１の１２０ａ、１２１ａに相当）と端子部材２３０の薄肉部（図１の１１０ａに相当）のハーフエッチング面である端子面（内部端子部１１１ａ，１１１ｂに相当）とをワイヤボンディング接続する。（図５（ｅ））
次いで、多孔板２４０を外し、これに代え、モールド用のテープ２７０、２７１を、加工シート２１０Ａの両面に、それぞれ、各面を覆うように、平面状に貼り、半導体素子２５０の裏面をテープ２７０にて貼り固定、表裏をモールド固定用の平板（図示していない）にて挟み、加工シート２１０Ａ全体について、一括してモールドを行い、表裏のモールド固定用の平板を取り外す。（図６（ｆ））
尚、加工シート２１０Ａの端子部材２３０を支持する支持部２３５は、通りぬけ孔等を設けたもので、モールドの際、各面付け間モールド用の樹脂が通りぬけできるような形状になっている。
次いで、モールド用のテープ２７０、２７１を剥がし、切断用のテープ２７５を貼り（図６（ｇ））、該切断用のテープ２７５とは反対側からダイシングソー（図示していない）にて切断して（図６（ｈ））、樹脂封止型半導体装置を１個づつに個片化して得る。（図６（ｉ））
ダイシングソー（図示していない）による切断は、（図６（ｈ）に示すように、凹部２３７とは反対側にて行うもので、この部分は加工用素材の厚さより薄肉で、容易に切断できるものとしている。
ダイシングソー（図示していない）による切断状態は、例えば、図９（ａ）や、図９（ｂ）のようになる。
尚、図９において、単位の樹脂封止型半導体装置４０１は、切断ライン４８５にて互いに分けられた各領域であり、ここでは、説明を分かり易くするため図示していないが、図６（ｈ）の支持部２３５を凹部２３７とは反対側で切断する。
加工シート２１０Ａ（図９の４１０Ａに相当）は、フレームとも呼ばれる。
また、この切断面が、作製される樹脂封止型半導体装置の外部端子の外側側面となる。 尚、切り欠け部２３７Ａの切断された面でない面には接続用のめっきが配設されておりこの部分は接続用に利用し易い。
このようにして、図１に示す第１の例の樹脂封止型半導体装置は製造することができる。
次いで、半田ボール２９０を端子部材２３０所定の位置に配設して、図３（ａ）に示す第２の例の樹脂封止型半導体装置１０１Ａを製造することができる。（図６（ｊ）） Next, an example of a method for manufacturing the resin-encapsulated semiconductor device of the first example will be described with reference to FIGS.
In addition, it replaces with description of one example (1st example) of the manufacturing method of the resin sealing type | mold semiconductor device of this invention by this.
First, resists 220 are arranged in a predetermined shape on both surfaces of the processing material 210 (FIG. 5A), and the arrangement of the terminal members corresponding to the arrangement of the terminal members of one resin-encapsulated semiconductor device is one unit. In this arrangement, etching is performed from both sides by an etching method using a half-etching technique, and the terminal member 230 is formed by being imbedded in a state of being connected by the support portion 235. (Fig. 5 (b))
As a result, a processed sheet 210A is obtained in which the arrangement of the terminal member corresponding to the arrangement of the terminal member of one resin-encapsulated semiconductor device is taken as one unit and is connected and faced by the support portion 235.
As the processing material 210, Cu, Cu-based alloy, 42 alloy (Ni42% -Fe alloy) or the like is used, and ferric chloride solution is used as the etching solution.
The resist 220 is not particularly limited as long as it is resistant to etching, has a desired resolution, and has good processability.
Next, after removing the resist 220, a cleaning process or the like is performed, and surface plating for connection is performed on the entire surface (not shown), and then a half-etched surface of the processed sheet 210A that is surface-applied and surface-plated. The side that is not the side is evacuated by the flat perforated plate 240, and the processed sheet 210A is in close contact with the perforated plate 240 (FIG. 5 (c)). Is positioned at a predetermined position, and the back surface that is not the terminal surface side is evacuated by the perforated plate 240 for evacuation and mounted on the perforated plate 240. (Fig. 5 (d))
Although there are other vacuum sources for the vacuum plate, such as a vacuum pump and a vacuum pipe, they are not shown here.
Next, in this state, for each of the semiconductor elements 251 and 252 of each stacked semiconductor element group 250, the terminals (corresponding to 120a and 121a in FIG. 1) and the thin portions (corresponding to 110a in FIG. 1) of the terminal member 230 are half. A terminal surface (corresponding to the internal terminal portions 111a and 111b) which is an etching surface is connected by wire bonding. (Fig. 5 (e))
Next, the porous plate 240 is removed, and instead of this, molding tapes 270 and 271 are attached to both surfaces of the processed sheet 210A so as to cover each surface, and the back surface of the semiconductor element 250 is attached to the tape 270. The front and back surfaces are sandwiched between mold fixing flat plates (not shown), the entire processed sheet 210A is molded in a lump, and the front and back mold fixing flat plates are removed. (Fig. 6 (f))
The support portion 235 that supports the terminal member 230 of the processed sheet 210A is provided with a through hole or the like, and has a shape that allows the resin for molding between impositions to pass through during molding. .
Next, the tapes 270 and 271 for molding are peeled off, a tape 275 for cutting is applied (FIG. 6G), and cut with a dicing saw (not shown) from the side opposite to the tape 275 for cutting. (FIG. 6 (h)), the resin-encapsulated semiconductor devices are obtained as individual pieces. (Fig. 6 (i))
Cutting with a dicing saw (not shown) is performed on the side opposite to the concave portion 237 (as shown in FIG. 6 (h)), and this portion is thinner than the thickness of the processing material and is easily cut. It is supposed to be possible.
The cutting state by a dicing saw (not shown) is, for example, as shown in FIG. 9A or FIG. 9B.
In FIG. 9, the unit resin-encapsulated semiconductor device 401 is a region separated from each other by a cutting line 485, and is not shown here for easy understanding, but FIG. ) Is cut on the side opposite to the recess 237.
The processed sheet 210A (corresponding to 410A in FIG. 9) is also called a frame.
Further, this cut surface becomes the outer side surface of the external terminal of the resin-encapsulated semiconductor device to be manufactured. Note that a plating for connection is provided on the surface of the cutout portion 237A that is not the cut surface, and this portion is easily used for connection.
In this way, the resin-encapsulated semiconductor device of the first example shown in FIG. 1 can be manufactured.
Next, the solder ball 290 is disposed at a predetermined position of the terminal member 230, and the resin-encapsulated semiconductor device 101A of the second example shown in FIG. 3A can be manufactured. (Fig. 6 (j))

次いで、第１の例の樹脂封止型半導体装置の製造方法の別の１例（第２の例）を、図７、図８に基づいて、説明する。
尚、これを以って、本発明の樹脂封止型半導体装置の製造方法の１例（第２の例）の説明に代える。
先ず、加工用素材３１０の両面に所定形状にレジスト３２０を配設し（図７（ａ））、１つの樹脂封止型半導体装置の端子部材の配置に対応した、端子部材の配置を１単位として、この配置状態に、ハーフエッチング技術を用いたエッチング加工法にて、両面からエッチングを行い、端子部材３３０を、支持部３３５にて連結した状態で、面付けして形成する。（図７（ｂ））
これにより、１つの樹脂封止型半導体装置の端子部材の配置に対応した、端子部材の配置を１単位として、これが支持部３３５にて連結され面付けされた、加工シート３１０Ａを得る。
次いで、レジスト３２０を除去後、洗浄処理等を施し、全面に接続用の表面めっきを施した（図示していない）後、面付け形成され、表面めっきが施された加工シート３１０Ａのハーフエッチング面側ではない側を覆うようにモールド用のテープ３４０を貼り（図７（ｃ））、面付け分の数だけ、積層半導体素子群３５０を所定の位置に位置決めして、その端子面側ではない裏面を前記テープ３４０に貼り付け搭載する。（図７（ｄ））
次いで、この状態で、各積層半導体素子群２５０の各半導体素子２５１、２５２について、その端子と端子部材の内部端子部の端子面とをワイヤボンディング接続する。（図７（ｅ））
次いで、モールド用のテープ３４１を、加工シート３１０Ａの前記テープ３４０とは反対側の面に、覆うように、平面状に貼り、半導体素子３５０の裏面をテープ３４０にて貼り固定した状態で、表裏を、それぞれ、テープ３４０、３４１を介して、モールド固定用の平板３７１、３７２にて挟み、加工シート３１０Ａ全体について、一括してモールドを行う。（図７（ｆ））
ここでは、積層半導体素子群３５０を所定の位置に位置決めする際のテープをそのままモールド用のテープとして使用している。
次いで、表裏のモールド固定用の平板３７１、３７２を除去し（図８（ｇ））、更にテープ３４０、３４１を除去し、必要に応じて半田めっきで外部端子部の外装めっきを施した後、切断用のテープ３４５を貼り（図８（ｈ））、該切断用のテープ３４５とは反対側からダイシングソー（図示していない）にて切断して（図８（ｉ））、樹脂封止型半導体装置を１個づつに個片化して得る。（図８（ｊ））
尚、図７、図８に示す製造方法においても、各工程の処理、各部材等は基本的に図５、図６に示す製造方法に準じるもので、ここでは、説明を省いている。
このようにして、図１に示す第１の例の樹脂封止型半導体装置は製造することができる。
次いで、半田ボール３９０を端子部材３３０所定の位置に配設して、図３（ａ）に示す第２の例の樹脂封止型半導体装置１０１Ａを製造することができる。（図８（ｋ）） Next, another example (second example) of the method for manufacturing the resin-encapsulated semiconductor device of the first example will be described with reference to FIGS.
In addition, it replaces with description of 1 example (2nd example) of the manufacturing method of the resin sealing type | mold semiconductor device of this invention by this.
First, resists 320 are arranged in a predetermined shape on both surfaces of the processing material 310 (FIG. 7A), and the arrangement of the terminal members corresponding to the arrangement of the terminal members of one resin-encapsulated semiconductor device is one unit. In this arrangement state, etching is performed from both sides by an etching method using a half etching technique, and the terminal member 330 is formed by being imbedded in a state where the terminal member 330 is connected by the support portion 335. (Fig. 7 (b))
As a result, a processed sheet 310A is obtained in which the arrangement of the terminal member corresponding to the arrangement of the terminal member of one resin-encapsulated semiconductor device is taken as one unit, and this is connected and faced by the support portion 335.
Next, after removing the resist 320, a cleaning process or the like is performed, and a surface plating for connection is performed on the entire surface (not shown), and then a half-etched surface of the processed sheet 310A that is impositioned and surface-plated. A mold tape 340 is applied so as to cover the side that is not the side (FIG. 7C), and the stacked semiconductor element group 350 is positioned at a predetermined position by the number of impositions, and not the terminal surface side. The back surface is attached to the tape 340 and mounted. (Fig. 7 (d))
Next, in this state, for each semiconductor element 251, 252 of each stacked semiconductor element group 250, the terminal and the terminal surface of the internal terminal portion of the terminal member are connected by wire bonding. (Fig. 7 (e))
Next, the molding tape 341 is applied in a flat shape so as to cover the surface of the processed sheet 310A opposite to the tape 340, and the back surface of the semiconductor element 350 is attached and fixed with the tape 340. Are sandwiched between flat plates 371 and 372 for fixing the mold via tapes 340 and 341, respectively, and the entire processed sheet 310A is molded collectively. (Fig. 7 (f))
Here, the tape used when positioning the laminated semiconductor element group 350 at a predetermined position is used as it is as a tape for molding.
Next, the front and back mold fixing flat plates 371 and 372 are removed (FIG. 8 (g)), the tapes 340 and 341 are further removed, and external plating of the external terminal portion is performed by solder plating as necessary. A cutting tape 345 is attached (FIG. 8 (h)), and cut with a dicing saw (not shown) from the side opposite to the cutting tape 345 (FIG. 8 (i)), and resin-sealed Type semiconductor devices are obtained by one piece. (Fig. 8 (j))
In the manufacturing method shown in FIGS. 7 and 8, the processing of each step, each member, and the like are basically the same as those in the manufacturing method shown in FIGS. 5 and 6, and description thereof is omitted here.
In this way, the resin-encapsulated semiconductor device of the first example shown in FIG. 1 can be manufactured.
Next, the solder ball 390 is disposed at a predetermined position of the terminal member 330, so that the resin-encapsulated semiconductor device 101A of the second example shown in FIG. (Fig. 8 (k))

上記、図５、図６や図７、図８に示す第１の例、第２の例の樹脂封止型半導体装置の製造方法は、第３の例〜第６の樹脂封止型半導体装置の製造にも適用できるものである。   The manufacturing methods of the resin-encapsulated semiconductor devices of the first example and the second example shown in FIGS. 5, 6, 7, and 8 are the third to sixth resin-encapsulated semiconductor devices. It can also be applied to the manufacture of

図１、図３、図４に示す樹脂封止型半導体装置の形態は、ＱＦＮ型であるが、本発明の樹脂封止型半導体装置は、これには限定されない。
ＳＯＮ型の形態をとることもできる。
また、上記では、積層半導体素子群は半導体素子を４層まで積層したものを挙げたが、本発明の樹脂封止型半導体装置においては、半導体素子を４層以上としても良い。
用いる半導体素子の薄化が進めば、更に、多数の半導体素子を積層した形態としても良い。
The resin-encapsulated semiconductor device shown in FIGS. 1, 3, and 4 is a QFN type, but the resin-encapsulated semiconductor device of the present invention is not limited to this.
It can also take the form of a SON.
In the above description, the laminated semiconductor element group has been formed by stacking up to four layers of semiconductor elements. However, in the resin-encapsulated semiconductor device of the present invention, the number of semiconductor elements may be four or more.
If the semiconductor element to be used is further thinned, a large number of semiconductor elements may be stacked.

図１（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第１の例を示した概略断面図で、図１（ｂ）は図１（ａ）のＡ１側から透視してみた図である。FIG. 1A is a schematic cross-sectional view showing a first example of an embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 1B is seen through from the A1 side of FIG. FIG. 図２（ａ）は端子部材の断面図で、図２（ｂ）は図１（ａ）のＢ１側から見た図で図２（ｃ）は図２（ａ）のＢ２側からみた図で、図２（ｄ）は図２（ｄ）のＢ３側からみた図である。2A is a sectional view of the terminal member, FIG. 2B is a view seen from the B1 side of FIG. 1A, and FIG. 2C is a view seen from the B2 side of FIG. 2A. FIG. 2D is a view seen from the B3 side of FIG. 図３（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第２の例を示した概略断面図で、図３（ｂ）は本発明の樹脂封止型半導体装置の実施の形態の第３の例を示した概略断面図で、図３（ｃ）は本発明の樹脂封止型半導体装置の実施の形態の第４の例を示した概略断面図である。FIG. 3A is a schematic sectional view showing a second example of the embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 3B is an implementation of the resin-encapsulated semiconductor device of the present invention. FIG. 3C is a schematic cross-sectional view showing a fourth example of the embodiment of the resin-encapsulated semiconductor device of the present invention. 図４（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第５の例を示した概略断面図で、図４（ｂ）は本発明の樹脂封止型半導体装置の実施の形態の第６の例を示した概略断面図である。FIG. 4A is a schematic sectional view showing a fifth example of the embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 4B is an implementation of the resin-encapsulated semiconductor device of the present invention. It is the schematic sectional drawing which showed the 6th example of the form. 図５（ａ）〜図５（ｅ）は本発明の樹脂封止型半導体装置の製造方法の実施の形態の第１の例の一部製造工程を示した工程断面図である。FIG. 5A to FIG. 5E are process cross-sectional views showing a partial manufacturing process of the first example of the embodiment of the method for manufacturing the resin-encapsulated semiconductor device of the present invention. 図６（ｆ）〜図６（ｉ）は、図５に続く製造工程を示した工程断面図で、図６（ｊ）は半田ボールをつけた断面図である。6 (f) to 6 (i) are process cross-sectional views showing the manufacturing process following FIG. 5, and FIG. 6 (j) is a cross-sectional view with solder balls. 図７（ａ）〜図７（ｆ）は本発明の樹脂封止型半導体装置の製造方法の実施の形態の第２の例の一部製造工程を示した工程断面図である。FIG. 7A to FIG. 7F are process cross-sectional views illustrating a partial manufacturing process of the second example of the embodiment of the method for manufacturing the resin-encapsulated semiconductor device of the present invention. 図８（ｇ）〜図８（ｊ）は、図７に続く製造工程を示した工程断面図で、図８（ｋ）は半田ボールをつけた断面図である。FIG. 8G to FIG. 8J are process cross-sectional views showing the manufacturing process following FIG. 7, and FIG. 8K is a cross-sectional view with solder balls. ダイシングソーによる切断状態を示した図である。It is the figure which showed the cutting | disconnection state by a dicing saw.

符号の説明Explanation of symbols

１０１、１０１Ａ、１０２、１０２Ａ 樹脂封止型半導体装置
１１０ 端子部材
１１０ａ、１１０ｃ 薄肉部
１１０ｂ 厚肉部
１１０ｆ （一方の側の）平坦な面
１１１ａ、１１１ｂ 内部端子部
１１２ａ、１１２ｂ 外部端子部
１１４ 切り欠け部
１１６ 先端部
１１６Ｓ （先端の）側面
１１７ グルーブ（溝部）
１２０ 第１の半導体素子（単に半導体素子あるいはチップとも言う）
１２１、１２２、１２３ 半導体素子（チップとも言う）
１２０Ｓ （第１の半導体素子の）裏面
１２０ａ、１２１ａ、１２２ａ、１２３ａ 端子部
１２５、１２５Ａ、１５Ｂ 積層半導体素子群
１３０ ボンディングワイヤ
１４０ 封止用樹脂（単に樹脂とも言う）
２１０ 加工用素材
２１０Ａ 加工シート
２２０ レジスト
２３０ 端子部材
２３０ａ 薄肉部
２３０ｂ 厚肉部
２３５ 支持部（連結部とも言う）
２３７ 凹部
２３７Ａ 切り欠け部
２４０ 平板状の多孔板（真空引き板とも言う）
２５０ 積層半導体素子群
２５１、２５２ 半導体素子
２６０ ボンディングワイヤ
２７０、２７１ （固定用、モールド用の）テープ
２７５ （ダイシング用の）テープ
２８０ 封止用樹脂
２９０ 半田ボール
３１０ 加工用素材
３１０Ａ 加工シート
３２０ レジスト
３３０ 端子部材
３３５ 支持部（連結部とも言う）
３３７ 凹部
３３７Ａ 切り欠け部
３４０、３４１ （固定用、モールド用の）テープ
３４５ （切断用の）テープ
３５０ 積層半導体素子群
３５１、３５２ 半導体素子
３６０ ボンディングワイヤ
３７１、３７２ モールド固定用の平板
３８０ 封止用樹脂
３９０ 半田ボール
４０１ 単位の樹脂封止型半導体装置
４１０Ａ 加工シート
４１５ 枠部
４１６ 治具孔
４１７ 長孔部
４８５ 切断ライン
４８６ 切断目印（貫通孔あるいは窪み） 101, 101A, 102, 102A Resin-encapsulated semiconductor device 110 Terminal members 110a, 110c Thin portion 110b Thick portion 110f Flat surface 111a, 111b Internal terminal portions 112a, 112b External terminal portion 114 Notched Portion 116 tip 116S (tip) side surface 117 groove (groove)
120 First semiconductor element (also simply referred to as semiconductor element or chip)
121, 122, 123 Semiconductor element (also called chip)
120S (back surface of first semiconductor element) 120a, 121a, 122a, 123a Terminal portions 125, 125A, 15B Multilayer semiconductor element group 130 Bonding wire 140 Sealing resin (also simply referred to as resin)
210 processing material 210A processing sheet 220 resist 230 terminal member 230a thin portion 230b thick portion 235 support portion (also referred to as connecting portion)
237 Concavity 237A Notch 240 Flat perforated plate (also referred to as vacuum drawing plate)
250 Laminated Semiconductor Element Group 251, 252 Semiconductor Element 260 Bonding Wires 270, 271 Tape (for Fixing, Molding) 275 Tape (for Dicing) 280 Sealing Resin 290 Solder Ball 310 Processing Material 310A Processing Sheet 320 Resist 330 Terminal member 335 support portion (also referred to as connecting portion)
337 Recessed portion 337A Notched portion 340, 341 Tape (for fixing, mold) 345 Tape (for cutting) Multilayer semiconductor element group 351, 352 Semiconductor element 360 Bonding wire 371, 372 Flat plate 380 for fixing mold Resin 390 Solder ball 401 Resin-encapsulated semiconductor device 410A Processing sheet 415 Frame portion 416 Jig hole 417 Long hole portion 485 Cutting line 486 Cutting mark (through hole or depression)

Claims (14)

複数個の端子部材を、互いに離間して、半導体素子を複数積層した積層半導体素子群の周辺に沿い離して配設し、該積層半導体素子群と、それに接続するボンディングワイヤと、該複数の端子部材とを一体的に樹脂封止した樹脂封止型半導体装置であって、前記端子部材は、エッチング加工法にて、加工用素材から、厚肉部を加工用素材の厚さにし、薄肉部を該加工用素材の一面側からのハーフエッチングにて薄肉にして形成されたもので、厚肉部と薄肉部とを有し、一方側を平坦にし、他方の側を２段の段状にし、厚肉部の両側にその端に至る薄肉部を配し、該一方の側の平坦な面を外部端子部とし、該他方の側の各段部の面を内部端子部としており、前記積層半導体素子群は、前記端子部材の薄肉部の厚さより薄い第１の半導体素子を有し、該第１の半導体素子の端子面側に、１以上の薄肉の半導体素子を、端子面の向きを揃え、前記第１の半導体素子を含んで、順次、端子面のサイズが小サイズとなるように積層したもので、該積層半導体素子群の各半導体素子の端子部と、端子部材の各段部の内部端子部とを、ボンディングワイヤにて接続しており、各端子部材を、その前記一方の側の平坦な面を一平面上に揃えて、同じ向きにして、各端子部材の一方の端に至る薄肉部側を半導体素子側に向け、他方の端に至る薄肉部を外側に向けて、配し、各端子部材の一方の側の平坦な面とその側面とを露出させ、且つ、前記第１の半導体素子の端子面でない側の裏面を、各端子部材の前記一方の側の平坦な面に揃えて、前記第１の半導体素子裏面を露出させるようにして、樹脂中に、配置して、全体を端子部材の厚肉部の厚さ幅より大きい幅として、樹脂封止していることを特徴とする樹脂封止型半導体装置。 A plurality of terminal members are spaced apart from each other and arranged along the periphery of a laminated semiconductor element group in which a plurality of semiconductor elements are laminated, the laminated semiconductor element group, bonding wires connected thereto, and the plurality of terminals A resin-encapsulated semiconductor device in which a member is integrally resin-encapsulated, wherein the terminal member is formed by etching a thick portion from a processing material to a thickness of the processing material by an etching method. Is made thin by half etching from one side of the processing material, has a thick part and a thin part, one side is flattened, and the other side is made into two steps. The thin wall portion is provided on both sides of the thick wall portion, the flat surface on one side is used as an external terminal portion, and the surface of each step portion on the other side is used as an internal terminal portion. semiconductor element group may have a thin first semiconductor device than the thickness of the thin portion of the terminal member One or more thin semiconductor elements are arranged on the terminal surface side of the first semiconductor element, the terminal surfaces are aligned, and the size of the terminal surface is sequentially reduced to include the first semiconductor element. formed by laminating as a terminal portion of each semiconductor element of the laminated semiconductor element group, and the internal terminal portions of the step portions of the terminal members, are connected by bonding wires, each terminal member, the said The flat surface on one side is aligned on a single plane and oriented in the same direction, with the thin part reaching one end of each terminal member facing the semiconductor element side and the thin part reaching the other end facing outward The flat surface on one side of each terminal member and its side surface are exposed, and the back surface of the first semiconductor element on the side other than the terminal surface is exposed on the one side of each terminal member. In a resin so that the back surface of the first semiconductor element is exposed on a flat surface. Arranged to, as a large width than the thickness width of the thick portion of the terminal member across, resin-encapsulated semiconductor device characterized by being sealed with resin. 請求項１に記載の樹脂封止型半導体装置であって、前記端子部材の前記一方の側の平坦な面に半田ボールを備えていることを特徴とする樹脂封止型半導体装置。   2. The resin-encapsulated semiconductor device according to claim 1, wherein a solder ball is provided on a flat surface on the one side of the terminal member. 請求項１ないし２のいずれか１項に記載の樹脂封止型半導体装置であって、前記端子部材の半導体素子側の薄肉部の先端断面は、ハーフエッチング形成面と側面とが鋭角をなすことを特徴とする樹脂封止型半導体装置。   3. The resin-encapsulated semiconductor device according to claim 1, wherein a half-etch formation surface and a side surface form an acute angle in the tip cross section of the thin portion on the semiconductor element side of the terminal member. A resin-encapsulated semiconductor device. 請求項１ないし３のいずれか１項に記載の樹脂封止型半導体装置であって、前記各端子部材は、その半導体素子側の薄肉部の先端幅を先細としていることを特徴とする樹脂封止型半導体装置。   4. The resin-encapsulated semiconductor device according to claim 1, wherein each terminal member has a tapered width at a tip end of a thin portion on a semiconductor element side. 5. Stop-type semiconductor device. 請求項１ないし４のいずれか１項に記載の樹脂封止型半導体装置であって、前記各端子部材の前記封止用樹脂表面と接する表面部に粗面化処理を施したことを特徴とする樹脂封止型半導体装置。   5. The resin-encapsulated semiconductor device according to claim 1, wherein a roughening process is performed on a surface portion of each terminal member that is in contact with the encapsulating resin surface. Resin-encapsulated semiconductor device. 請求項５に記載の樹脂封止型半導体装置であって、前記粗面化処理による、最大高さ粗さＲｙ（ＪＩＳＢＯ６０１−１９９４）が、１μｍ〜２μｍの範囲であることを特徴とする樹脂封止型半導体装置。   6. The resin-encapsulated semiconductor device according to claim 5, wherein a maximum height roughness Ry (JISBO601-1994) by the roughening treatment is in a range of 1 [mu] m to 2 [mu] m. Stop-type semiconductor device. 請求項１ないし６のいずれか１項に記載の樹脂封止型半導体装置であって、外部端子部の前記他方側、外側の面と外側側面にわたる切り欠け部を設けていることを特徴とする樹脂封止型半導体装置。   7. The resin-encapsulated semiconductor device according to claim 1, wherein a notch portion is provided over the other side, the outer surface, and the outer side surface of the external terminal portion. Resin-sealed semiconductor device. 請求項１ないし７のいずれか１項に記載の樹脂封止型半導体装置であって、端子部材は、Ｃｕ、Ｃｕ系合金、４２％Ｎｉ−Ｆｅ系合金からなることを特徴とする樹脂封止型半導体装置。   8. The resin-encapsulated semiconductor device according to claim 1, wherein the terminal member is made of Cu, a Cu-based alloy, or a 42% Ni—Fe-based alloy. Type semiconductor device. 請求項１ないし８のいずれか１項に記載の樹脂封止型半導体装置であって、内部端子部および外部端子部に、表層として、半田めっき層、金めっき層、銀めっき層、パラジウムめっき層、錫めっき層から選ばれた１つの金属めっき層を、接続用のめっき層として設けていることを特徴とする樹脂封止型半導体装置。   9. The resin-encapsulated semiconductor device according to claim 1, wherein a solder plating layer, a gold plating layer, a silver plating layer, a palladium plating layer is provided as a surface layer on the internal terminal portion and the external terminal portion. 1. A resin-encapsulated semiconductor device, wherein one metal plating layer selected from tin plating layers is provided as a plating layer for connection. 請求項１ないし９のいずれか１項に記載の樹脂封止型半導体装置であって、半導体素子の厚みが１００μｍ以下であることを特徴とする樹脂封止型半導体装置。   10. The resin-encapsulated semiconductor device according to claim 1, wherein the semiconductor element has a thickness of 100 μm or less. 11. 請求項１ないし１０のいずれか１項に記載の樹脂封止型半導体装置であって、ＱＦＮ型あるいはＳＯＮ型であることを特徴とする樹脂封止型半導体装置。   11. The resin-encapsulated semiconductor device according to claim 1, wherein the resin-encapsulated semiconductor device is a QFN type or an SON type. 請求項１ないし１１のいずれか１項に記載の樹脂封止型半導体装置の製造方法であって、順に、（ａ）１つの樹脂封止型半導体装置の端子部材の配置に対応した、端子部材の配置を１単位として、ハーフエッチング技術を用いたエッチング加工にて、前記端子部材の外側を支持部で連結した状態で、向きを揃えて面付けして形成し、面付け形成された加工シートを得る加工工程と、（ｂ）接続用の表面めっきを施すめっき処理工程と、（ｃ）面付け形成された加工シートのハーフエッチング面側ではない側を、平板状の真空引き板にて真空引きし、加工シートを真空引き板に密着させた状態で、面付け分だけ、積層半導体素子群を所定の位置に位置決めして、その端子面側ではない裏面を真空引きして、真空引き板に搭載する半導体素子搭載工程と、（ｄ）この状態で、各半導体素子について、その端子と端子部材の内部端子部の端子面とをワイヤボンディング接続するワイヤボンディング工程と、（ｅ）真空引き板を外し、これに代え、モールド用のテープを、加工シートの両面に、それぞれ、各面を覆うように、平面状に貼り、半導体素子の裏面を一方のテープにて貼り固定するテープ貼り工程と、（ｆ）表裏をモールド固定用の平板にて挟み、加工シート全体について、真空引きあるいは減圧してモールドを行う、モールド工程と、（ｇ）表裏のモールド固定用の平板とテープを除去し、必要に応じて半田めっきで外部端子部の外装めっきを施した後、切断用のテープを貼り、該切断用のテープとは反対側からダイシングソーにて切断して、樹脂封止型半導体装置を１個づつに個片化して得る個片化工程と、を行うことを特徴とする樹脂封止型半導体装置の製造方法。   It is a manufacturing method of the resin-sealed semiconductor device of any one of Claim 1 thru | or 11, Comprising: (a) The terminal member corresponding to arrangement | positioning of the terminal member of one resin-sealed semiconductor device in order. The processed sheet is formed by imposing the surface of the terminal member by aligning the directions in the etching process using a half-etching technique, with the orientation of the terminal member being connected to the support portion, by etching using half etching technology. And (b) a plating process for applying surface plating for connection, and (c) a side that is not the half-etched surface side of the formed sheet is vacuumed with a flat vacuum drawing plate With the processed sheet in close contact with the vacuum drawing plate, the laminated semiconductor element group is positioned at a predetermined position for the imposition, and the back surface that is not the terminal surface side is evacuated, and the vacuum drawing plate Built-in semiconductor element (D) In this state, for each semiconductor element, a wire bonding step of wire bonding connecting the terminal and the terminal surface of the internal terminal portion of the terminal member; and (e) removing the vacuum drawing plate and replacing it with this. A tape application process in which a tape for molding is applied to both sides of the processed sheet in a flat shape so as to cover each surface, and the back surface of the semiconductor element is attached and fixed with one tape; The mold process is performed by vacuuming or decompressing the entire processed sheet by sandwiching it with a mold-fixing flat plate, and (g) removing the front and back mold-fixing flat plate and tape, and solder plating as necessary. After external plating of the external terminal is applied, a cutting tape is applied, and cutting is performed with a dicing saw from the side opposite to the cutting tape, so that one resin-encapsulated semiconductor device is provided. Method for manufacturing a resin-sealed semiconductor device which is characterized in that the singulation process may be singulated, the. 請求項１２に記載の樹脂封止型半導体装置の製造方法であって、平板状の真空引き板が、全面に真空吸着用の孔を配設したものであることを特徴とする樹脂封止型半導体装置の製造方法。   13. The method of manufacturing a resin-sealed semiconductor device according to claim 12, wherein the flat vacuum drawing plate is provided with holes for vacuum suction on the entire surface. A method for manufacturing a semiconductor device. 請求項１ないし１１のいずれか１項に記載の樹脂封止型半導体装置の製造方法であって、順に、（Ａ）１つの樹脂封止型半導体装置の端子部材の配置に対応した、端子部材の配置を１単位として、ハーフエッチング技術を用いたエッチング加工にて、前記端子部材の外側を支持部で連結した状態で、向きを揃えて面付けして形成し、面付け形成された加工シートを得る加工工程と、（Ｂ）接続用の表面めっきを施すめっき処理工程と、（Ｃ）面付け形成された加工シートのハーフエッチング面側ではない側を覆うようにモールド用のテープを貼り、面付け分だけ、積層半導体素子群を所定の位置に位置決めして、その端子面側ではない裏面を前記テープに貼り付け搭載する半導体素子搭載工程と、（Ｄ）この状態で、各半導体素子について、その端子と端子部材の内部端子部の端子面とをワイヤボンディング接続するワイヤボンディング工程と、（Ｅ）モールド用のテープを、加工シートの両面に、それぞれ、各面を覆うように、平面状に貼り、半導体素子の裏面を一方のテープにて貼り固定するテープ貼り工程と、（Ｆ）表裏を、それぞれ、テープを介して、モールド固定用の平板にて挟み、加工シート全体について、一括してモールドを行う、一括モールド工程と、（Ｇ）表裏のモールド固定用の平板、テープを除去し、切断用のテープを貼り、該切断用のテープとは反対側からダイシングソーにて切断して、樹脂封止型半導体装置を１個づつに個片化して得る個片化工程と、を行うことを特徴とする樹脂封止型半導体装置の製造方法。 The method for manufacturing a resin-encapsulated semiconductor device according to any one of claims 1 to 11 , wherein (A) terminals corresponding to the arrangement of terminal members of one resin-encapsulated semiconductor device in order The process of forming an imposition with the arrangement of the members as one unit, with the outer surface of the terminal member connected by a support portion, with the orientation aligned, by etching using a half etching technique. A processing step for obtaining a sheet, (B) a plating processing step for performing surface plating for connection, and (C) a tape for molding so as to cover a side that is not the half-etched surface side of the processed sheet that is impositioned (D) a semiconductor element mounting step in which the stacked semiconductor element group is positioned at a predetermined position by the imposition, and the back surface which is not the terminal surface side is attached to the tape and mounted; about, Wire bonding process for wire bonding connection of the terminal and the terminal surface of the internal terminal portion of the terminal member, and (E) a tape for molding on each side of the processed sheet in a flat shape so as to cover each surface Affixing and fixing the back surface of the semiconductor element with one tape, and (F) sandwiching the front and back sides with a flat plate for mold fixing via the tape, respectively, and processing the entire processing sheet collectively Perform the mold, collective molding process, (G) remove the front and back mold fixing flat plate and tape, apply the cutting tape, cut with a dicing saw from the opposite side of the cutting tape, A method for manufacturing a resin-encapsulated semiconductor device, comprising: a step of dividing the resin-encapsulated semiconductor device into individual pieces.
JP2006257541A 2006-09-22 2006-09-22 Resin-sealed semiconductor device and manufacturing method thereof Expired - Fee Related JP4876818B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006257541A JP4876818B2 (en) 2006-09-22 2006-09-22 Resin-sealed semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006257541A JP4876818B2 (en) 2006-09-22 2006-09-22 Resin-sealed semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2008078483A JP2008078483A (en) 2008-04-03
JP4876818B2 true JP4876818B2 (en) 2012-02-15

Family

ID=39350220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006257541A Expired - Fee Related JP4876818B2 (en) 2006-09-22 2006-09-22 Resin-sealed semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP4876818B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6750416B2 (en) * 2016-09-14 2020-09-02 富士電機株式会社 Semiconductor module and method of manufacturing semiconductor module

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004319577A (en) * 2003-04-11 2004-11-11 Dainippon Printing Co Ltd Resin sealed semiconductor device, its manufacturing process, and stacked resin sealed semiconductor device
JP4373122B2 (en) * 2003-04-28 2009-11-25 大日本印刷株式会社 Resin-sealed semiconductor device and manufacturing method thereof
JP4467903B2 (en) * 2003-04-17 2010-05-26 大日本印刷株式会社 Resin-sealed semiconductor device

Also Published As

Publication number Publication date
JP2008078483A (en) 2008-04-03

Similar Documents

Publication Publication Date Title
US7405468B2 (en) Plastic package and method of fabricating the same
US6429508B1 (en) Semiconductor package having implantable conductive lands and method for manufacturing the same
US7309909B2 (en) Leadframes for improved moisture reliability of semiconductor devices
US8138026B2 (en) Low cost lead-free preplated leadframe having improved adhesion and solderability
JP5544714B2 (en) Resin-encapsulated semiconductor device and manufacturing method thereof, substrate for semiconductor device, and laminated resin-encapsulated semiconductor device
US20100193922A1 (en) Semiconductor chip package
KR101440933B1 (en) Integrated circuit package system employing bump technology
US20190088503A1 (en) Thermosonically bonded connection for flip chip packages
JP4373122B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
JP2005294443A (en) Semiconductor device and its manufacturing method
JP2004319577A (en) Resin sealed semiconductor device, its manufacturing process, and stacked resin sealed semiconductor device
KR100831481B1 (en) Semiconductor device and semiconductor package using the same, and circuit device
JP4876818B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
JP4467903B2 (en) Resin-sealed semiconductor device
JP5217291B2 (en) Resin-sealed semiconductor device and manufacturing method thereof, substrate for semiconductor device, and laminated resin-sealed semiconductor device
JP5167963B2 (en) Resin-sealed semiconductor device, etching member used therefor, and laminated resin-sealed semiconductor device
JP2009231322A (en) Manufacturing method of semiconductor device
JP3802500B2 (en) Lead frame
JP2010080971A (en) Resin sealed semiconductor device and production method thereof
JP2001274310A (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090729

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20110728

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110816

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111012

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20111101

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20111114

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4876818

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20141209

Year of fee payment: 3

LAPS Cancellation because of no payment of annual fees