JP5167963B2 - Resin-sealed semiconductor device, etching member used therefor, and laminated resin-sealed semiconductor device - Google Patents

Resin-sealed semiconductor device, etching member used therefor, and laminated resin-sealed semiconductor device Download PDF

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JP5167963B2
JP5167963B2 JP2008151593A JP2008151593A JP5167963B2 JP 5167963 B2 JP5167963 B2 JP 5167963B2 JP 2008151593 A JP2008151593 A JP 2008151593A JP 2008151593 A JP2008151593 A JP 2008151593A JP 5167963 B2 JP5167963 B2 JP 5167963B2
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resin
semiconductor device
terminal
encapsulated semiconductor
terminal member
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JP2009135406A (en
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正親 増田
幸治 富田
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Dai Nippon Printing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

本発明は、エッチング加工された端子部材を用いた樹脂封止型半導体装置に関し、特に、薄型のＳＯＮ（Ｓｍａｌｌ、Ｏｕｔｌｉｎｅ Ｎｏｎｌｅａｄｅｄ）、ＱＦＮ（Ｑｕａｄ Ｆｌａｔ Ｎｏｎｌｅａｄｅｄ）における反り（ソリとも言う）を解決できる樹脂封止型半導体装置に関する。   The present invention relates to a resin-encapsulated semiconductor device using an etched terminal member, and in particular, a resin capable of solving warpage (also referred to as warping) in a thin SON (Small, Outline Nonloaded) and QFN (Quad Flat Nonloaded). The present invention relates to a sealed semiconductor device.

近年、電子機器の小型化に対応するために、電子機器に搭載される半導体部品を高密度に実装することが要求され、それにともなって、半導体部品の小型化、薄型化が進んでおり、更なる薄型化を廉価に達成できるパッケージが求められている。
このような状況のもと、薄型化に対応するものとして、特開平１１−３０７６７５号公報（特許文献１）に記載の接続用リードの上面及び下面を露出させた構造の樹脂封止型半導体装置や、特開平１１−２６０９８９号公報（特許文献２）に記載の接続用リードの一部を露出して外部端子としている樹脂封止型半導体装置が提案されている。
一方、システムＬＳＩのワンチップ化の開発が盛んであるが、２次元方向への配線展開となるため、配線の短縮による高速化には限界があり、また、その開発費、開発期間の増加を招いているのが実状で、最近では、これに代わり、半導体チップ（半導体素子とも言う）を３次元方向に積層したパッケージでシステムＬＳＩを実現しようとする試みがなされている。
このようなパッケージをシステムパッケージとも言う。 In recent years, in order to cope with the downsizing of electronic devices, it has been required to mount semiconductor components mounted on electronic devices with high density, and along with that, semiconductor components have become smaller and thinner. There is a need for a package that can achieve a low profile at a low cost.
Under such circumstances, a resin-encapsulated semiconductor device having a structure in which the upper and lower surfaces of connection leads described in JP-A No. 11-307675 (Patent Document 1) are exposed as a countermeasure for thinning. In addition, there has been proposed a resin-encapsulated semiconductor device in which a part of a connection lead described in JP-A-11-260989 (Patent Document 2) is exposed and used as an external terminal.
On the other hand, development of system LSIs on a single chip is active, but since the wiring is expanded in two dimensions, there is a limit to speeding up by shortening the wiring, and the development cost and development period are increased. Recently, an attempt has been made to realize a system LSI using a package in which semiconductor chips (also referred to as semiconductor elements) are stacked in a three-dimensional direction.
Such a package is also called a system package.

特開平１１−３０７６７５号公報（特許文献１）には、これに記載の樹脂封止型半導体装置を積層し、その上面及び下面を露出させた接続用リードで電気的接続をとった、いわゆるスタック構造の積層型樹脂封止型半導体装置も記載されている。
尚、特開平１１−２６０９８９号公報（特許文献２）に記載の樹脂封止型半導体装置はスタック構造をとれるものではない。
また、特開平２００２−３３４３４号公報（特許文献３）には、パッケージ内に半導体チップを積層したパッケージが記載されているが、この構造では、自由度が少なく、汎用化しづらい。
特開平１１−３０７６７５号公報 特開平１１−２６０９８９号公報 特開平２００２−３３４３４号公報 Japanese Patent Application Laid-Open No. 11-307675 (Patent Document 1) discloses a so-called stack in which the resin-encapsulated semiconductor devices described above are stacked and electrically connected by connecting leads with the upper and lower surfaces exposed. A laminated resin-encapsulated semiconductor device having a structure is also described.
Note that the resin-encapsulated semiconductor device described in JP-A-11-260989 (Patent Document 2) cannot take a stack structure.
Japanese Patent Application Laid-Open No. 2002-33434 (Patent Document 3) describes a package in which semiconductor chips are stacked in a package, but this structure has a low degree of freedom and is difficult to be generalized.
JP-A-11-307675 Japanese Patent Laid-Open No. 11-260989 Japanese Patent Laid-Open No. 2002-33434

このような中、特に、半導体チップにおけるメモリ容量の大型化は激しく、配線の微細化による高密度化にもかかわらず、メモリー用半導体チップにおいては、そのサイズも大きくなってきているが、最近では、特に、メモリー用半導体チップについては、薄型で、且つ、対向する２辺側にパッドを配列した、あるいは、１辺側にパッドを配列した、ＳＯＮタイプ、４辺側にパッドを配列したＱＦＮタイプの樹脂封止型半導体装置も求められるようになってきた。
しかし、特に、ＳＯＮタイプの樹脂封止型半導体装置において、８ｍｍ×１０ｍｍサイズのレベルより大きくなると、実用上、強度的に弱く、これが問題になっていた。 Under such circumstances, the increase in the memory capacity of the semiconductor chip is particularly severe, and the size of the semiconductor chip for the memory is increasing despite the high density due to the miniaturization of the wiring. In particular, the semiconductor chip for memory is thin and has a SON type in which pads are arranged on two opposite sides, or a pad is arranged on one side, and a QFN type in which pads are arranged on four sides. Also, a resin-sealed semiconductor device has been demanded.
However, in particular, in the SON type resin-encapsulated semiconductor device, when it becomes larger than the level of 8 mm × 10 mm size, it is practically weak in strength, which is a problem.

これに対応する構造として、本願出願人は、先に、ＳＯＮタイプの樹脂封止型半導体装置において、構造強化のためにサポートバーを封止用樹脂内に設けた形態を提案している。（特願２００６−２１３０６０〜特許文献４）
特願２００６−２１３０６０ しかし、このように、サポートバーを設け構造強化を図っても、樹脂封止型半導体装置が反るという別の問題が生じていた。 反りが発生する原因の一つとして、樹脂封止型半導体装置に用いられる部材の熱膨張の差が挙げられ、樹脂封止型半導体装置を構成する部材の配置や部材の占める体積によって反りの程度が変化する。 従来の樹脂封止型半導体装置は樹脂が占める体積の割合が大きいため、樹脂封止型半導体装置全体の熱膨張は樹脂の熱膨張に大きく依存していた。 その結果、モールド後の反りを抑制できていた。 しかし、樹脂封止型半導体装置の薄型化が進むにつれて、樹脂封止型半導体装置に占める封止樹脂の体積の割合が小さくなり、膨張係数の異なる各部材の熱膨張係数の違いや、樹脂封止型半導体装置に占める各部材の割合から、収縮による樹脂封止型半導体装置の反りを抑えきれなくなってきた。 As a structure corresponding to this, the applicant of the present application has previously proposed a form in which a support bar is provided in the sealing resin for strengthening the structure in the SON type resin-encapsulated semiconductor device. (Japanese Patent Application No. 2006-213060 Patent Document 4)
However, even if the support bar is provided and the structure is strengthened as described above, another problem that the resin-encapsulated semiconductor device warps has occurred. One cause of warpage is the difference in thermal expansion of members used in resin-encapsulated semiconductor devices. The degree of warpage depends on the arrangement of members constituting the resin-encapsulated semiconductor device and the volume occupied by the members. Changes. In the conventional resin-encapsulated semiconductor device, since the volume ratio occupied by the resin is large, the thermal expansion of the entire resin-encapsulated semiconductor device largely depends on the thermal expansion of the resin. As a result, it was possible to suppress warping after molding. However, as the resin-encapsulated semiconductor device becomes thinner, the proportion of the volume of the encapsulating resin in the resin-encapsulated semiconductor device becomes smaller. From the proportion of each member in the stationary semiconductor device, it has become impossible to suppress warping of the resin-encapsulated semiconductor device due to shrinkage.

上記のように、近年、半導体部品の小型化、薄型化が進んでおり、更なる薄型化を廉価に達成できるパッケージが求められ、そのようなパッケージを積層して用いることも行われるようになってきている中、最近では、特に、メモリー用半導体チップについては、薄型で、且つ、対向する２辺側にパッドを配列した、あるいは、１辺側にパッドを配列した、ＳＯＮタイプ、４辺側にパッドを配列したＱＦＮタイプの樹脂封止型半導体装置も求められるようになってきた。
特に、ＳＯＮタイプ８ｍｍ×１０ｍｍサイズのレベルより大きいパッケージでは、構成する部材の配置や部材の占める体積のかね合いにより反りが大きくなる傾向があった。
このような現状がある中で、はんだ実装性を確保するために反りを８０μｍ以下にすることが求められていた。
また、樹脂封止型半導体装置のサイズが大きくなると、曲げモーメント長も大きくなることから、パッケージ曲げ強度が劣化することがあった。
このような現状がある中で、はんだ実装性を確保するために反りを８０μｍ以下にすることが求められていた。
本発明はこれらに対応するもので、薄型で、且つ、対向する２辺側にパッドを配列した、あるいは、１辺側にパッドを配列した、ＳＯＮタイプ、４辺側にパッドを配列したＱＦＮタイプの樹脂封止型半導体装置で、８ｍｍ×１０ｍｍサイズのレベルより大きい場合でも、反りが発生しづらい構造の薄型の樹脂封止型半導体装置で、量産性の良いものを提供しようとするものである。
更に、このような薄型の樹脂封止型半導体装置を複数積層した、スタック構造の積層型樹脂封止型半導体装置を提供しようとするものである。
更に、このような薄型の樹脂封止型半導体装置に用いられる、端子部材を多数配列したエッチング加工部材であって、１つの樹脂封止型半導体装置の各端子部材の配置に対応した、端子部材の配置を１単位として、エッチング技術を用いたエッチング加工にて、面付けして形成し、面付け形成しているエッチング加工部材を提供しようとするものである。 As described above, in recent years, semiconductor components have been reduced in size and thickness, and a package capable of achieving further reduction in thickness at low cost has been demanded, and such packages have been stacked and used. In recent years, especially for semiconductor chips for memory, it is thin and has pads arranged on opposite two sides, or pads arranged on one side, SON type, four sides There has also been a demand for a QFN type resin-encapsulated semiconductor device in which pads are arranged.
In particular, in a package larger than the level of the SON type 8 mm × 10 mm size, warpage tends to increase due to the arrangement of the constituent members and the balance of the volume occupied by the members.
Under such circumstances, it has been demanded that the warpage be 80 μm or less in order to ensure solder mountability.
Further, when the size of the resin-encapsulated semiconductor device is increased, the bending moment length is also increased, so that the package bending strength may be deteriorated.
Under such circumstances, it has been demanded that the warpage be 80 μm or less in order to ensure solder mountability.
The present invention corresponds to these, and is thin and has a SON type in which pads are arranged on two opposing sides, or a pad is arranged on one side, and a QFN type in which pads are arranged on four sides. This is a resin-encapsulated semiconductor device having a structure in which warpage does not easily occur even when it is larger than the level of 8 mm × 10 mm size, and is intended to provide a mass-productable semiconductor device. .
It is another object of the present invention to provide a stacked resin-sealed semiconductor device having a stack structure in which a plurality of such thin resin-sealed semiconductor devices are stacked .
Furthermore, it is an etching processed member in which a large number of terminal members are arranged, which is used in such a thin resin-encapsulated semiconductor device, and corresponds to the arrangement of each terminal member of one resin-encapsulated semiconductor device. An arrangement is provided in which an arrangement is used as an unit, and an etching process member that is impositioned and formed by imposition using an etching technique is provided.

本発明の樹脂封止型半導体装置は、外部回路と接続するための外部端子部と、半導体チップと接続するための内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材で、且つ、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部を加工用素材の一面側からのエッチングにより薄肉としている端子部材、複数個と、半導体チップ１つとを、用いて、該複数の端子部材を一平面状にその向きを揃えて、半導体チップの周辺に沿って、外部端子部を外側に向けて、リード部を内側に向けて、配し、半導体チップを前記複数の端子部材のリード部のエッチング形成された面であるエッチング面上まで延設して配し、且つ、半導体チップと所定の端子部材とを電気的に接続し、樹脂封止している２辺パッドＳＯＮ型の樹脂封止型半導体装置であって、各端子部材の、エッチング面側でない非エッチング面側と外部端子部の外側側面とを、露出させ、前記端子部材の厚さにして樹脂封止しており、前記半導体チップは、その対向する２辺に接続用端子を配し、該２辺側にて、それぞれ、前記端子部材の内部端子部と電気的に接続され、且つ、その両面の封止用樹脂の厚さを等しく揃えて、配設されており、前記加工用素材をエッチングして前記端子部材を形成する際に形成された、電気的に独立して、全体を強固にするためのサポートバーを、前記２辺側でない側の、半導体チップの両側に配設しており、封止用樹脂の熱膨張率と端子部材の熱膨張率を等しくしていることを特徴とするものである。
尚、上記で、「両面の封止用樹脂の厚さを等しく」とは、ここでは、両面の封止用樹脂の厚さの差が±０．０２ｍｍの範囲であることを意味する。
そして、上記の樹脂封止型半導体装置であって、端子部材は、Ｃｕ、Ｃｕ系合金、４２％Ｎｉ−Ｆｅ合金のいずれか１からなることを特徴とするものである。
そしてまた、上記いずれか１項に記載の樹脂封止型半導体装置であって、リード部の先端の先端側面部、該先端側面部挟む先端の両側面部を、封止用樹脂と密着性のよい構造としていることを特徴とするものであり、前記封止用樹脂と密着性のよい構造は、リード部の先端の先端側面部、該先端側面部挟む先端の両側面部を、外側に向かい、パッケージ内側となるテーパ形状としているものであることを特徴とするものである。
あるいは、前記封止用樹脂と密着性のよい構造は、リード部の先端の先端側面部、該先端側面部挟む先端の両側面部に、前記リード部のエッチング面に沿い、めっきによる庇を設けていることを特徴とするものである。
また、上記いずれかの樹脂封止型半導体装置であって、前記端子部材には、その加工用素材面側に、溝（グルーブ）およびまたは孔状凹部を設けていることを特徴とするものである。
また、上記いずれかの樹脂封止型半導体装置であって、前記各端子部材の前記封止用樹脂表面と接する表面部に粗面化処理を施したことを特徴とするものであり、前記粗面化処理により、最大高さ粗さＲｙ（ＪＩＳ Ｂ０６０１−１９９４）が、１μｍ〜２μｍの範囲であることを特徴とするものである。
また、上記いずれかの樹脂封止型半導体装置であって、外部端子部の外側側面部に、切り欠け部を設けていることを特徴とするものである。
尚、ここでは明記していないが、本発明の樹脂封止型半導体装置においては、端子部材の他に半導体チップを搭載するダイパッドをリード部と同じように薄肉にして、リード部と同じ平面上に揃えて配した形態もある。
そして、半導体チップと端子部材との電気的な接続は、ワイヤボンディング接続、バンプ接続が適用でき、バンプ接続の場合には、接続により半導体チップを端子部材に固定する形態となる。 The resin-encapsulated semiconductor device of the present invention integrally connects an external terminal portion for connecting to an external circuit and a lead portion including an internal terminal portion for connecting to a semiconductor chip as a part thereof. A terminal member, and from the processing material, at least a part of the external terminal portion is made thick with the thickness of the processing material, and the lead portion is made thin by etching from one side of the processing material, Using a plurality of semiconductor chips and one semiconductor chip, aligning the orientation of the plurality of terminal members in a single plane, with the external terminal portions facing outward along the periphery of the semiconductor chip, and the lead portions facing inward The semiconductor chip is extended and arranged on the etching surface, which is the etching-formed surface of the lead portions of the plurality of terminal members, and the semiconductor chip and the predetermined terminal member are electrically connected to each other. Connect with resin seal A two sides pads SON-type resin-sealed semiconductor device that, for each of the terminal members, an outer side surface of the non-etched side and the external terminal portions not etched surface, is exposed, and the thickness of the terminal member Contact Ri resin encapsulation Te, the semiconductor chip, the arranged connecting terminals facing the two sides at the two sides side, respectively, is an internal terminal portion electrically connected to the terminal member, And, the thickness of the sealing resin on both sides thereof is equalized and arranged, and formed electrically when forming the terminal member by etching the processing material , electrically independently, Support bars for strengthening the whole are disposed on both sides of the semiconductor chip, not on the two sides, so that the thermal expansion coefficient of the sealing resin and the thermal expansion coefficient of the terminal member are equal. It is characterized by this.
In the above description, “equal thickness of the sealing resin on both sides” means that the difference in thickness between the sealing resins on both sides is within a range of ± 0.02 mm .
Then, a top Symbol resin-encapsulated semiconductor device, the terminal member and is characterized Cu, Cu-based alloy, in that it consists of any one of 42% Ni-Fe alloy.
Further, in the resin-encapsulated semiconductor device according to any one of the above, the tip side surface portion at the tip of the lead portion and both side surface portions at the tip sandwiching the tip side surface portion have good adhesion to the sealing resin. The structure having good adhesion to the sealing resin is characterized in that the tip side surface portion at the tip of the lead portion and both side surface portions of the tip sandwiching the tip side surface portion are directed outward, and the package It is characterized by having a tapered shape on the inside.
Alternatively, the structure having good adhesion with the sealing resin is provided with a plating ridge along the etching surface of the lead portion on the tip side surface portion of the tip of the lead portion and on both side surfaces of the tip sandwiching the tip side surface portion. It is characterized by being.
Also, in any of the above resin-encapsulated semiconductor devices, the terminal member is provided with a groove and / or a hole-like recess on the processing material surface side. is there.
Further, in any one of the above resin-encapsulated semiconductor devices, a roughening treatment is performed on a surface portion of each terminal member that is in contact with the encapsulating resin surface. By the surface treatment, the maximum height roughness Ry (JIS B0601-1994) is in the range of 1 μm to 2 μm.
Further, in any one of the aforementioned resin-sealed-type semiconductor device, the outer side surface portion of the external terminal portion, Ru der those characterized in that provided cutout.
Although not specified here, in the resin-encapsulated semiconductor device of the present invention, the die pad on which the semiconductor chip is mounted in addition to the terminal member is made thin like the lead portion, and on the same plane as the lead portion. There is also a form arranged in line.
For the electrical connection between the semiconductor chip and the terminal member, wire bonding connection or bump connection can be applied. In the case of bump connection, the semiconductor chip is fixed to the terminal member by connection.

本発明の積層型樹脂封止型半導体装置は、上記本発明の樹脂封止型半導体装置のいずれか１つ以上を、複数、積層したもので、それぞれ、上側の樹脂封止型半導体装置の下側の外部端子部の端子面と、下側の樹脂封止型半導体装置の上側の外部端子部の端子面とを、重ね合せて電気的に接続していることを特徴とするものである。
そして、上記の積層型樹脂封止型半導体装置であって、樹脂封止型半導体装置の２つ以上が互いにその側面同士を合せて電気的に接続していることを特徴とするものである。 The laminated resin-encapsulated semiconductor device of the present invention is a laminate of any one or more of the above-described resin-encapsulated semiconductor devices of the present invention, each of which is below the upper resin-encapsulated semiconductor device. The terminal surface of the external terminal portion on the side and the terminal surface of the external terminal portion on the upper side of the lower resin-encapsulated semiconductor device are overlapped and electrically connected.
In the laminated resin-encapsulated semiconductor device described above, two or more of the resin-encapsulated semiconductor devices are electrically connected with their side surfaces aligned with each other.

本発明に関わる樹脂封止型半導体装置の製造方法は、上記いずれかの樹脂封止型半導体装置を製造する、樹脂封止型半導体装置の製造方法であって、順に、（ａ）１つの樹脂封止型半導体装置の各端子部材の配置に対応した、端子部材の配置を１単位として、エッチング技術を用いたエッチング加工にて、面付けして形成し、面付け形成された加工シートを得るエッチング加工工程と、（ｂ）接続用の表面めっきを施すめっき処理工程と、（ｃ）面付け形成された加工シートの薄肉のエッチング形成面側ではない側を、平板状の真空引き板にて真空引きし、加工シートを真空引き板に密着させた状態で、面付け分だけ、半導体チップを所定の位置に位置決めして、その端子面側ではない裏面を真空引きして、真空引き板に搭載する半導体チップ搭載工程と、（ｄ）この状態で、各半導体チップについて、その端子と端子部材の内部端子部の端子面とを接続する接続工程と、（ｅ）真空引き板を外し、これに代え、モールド用のテープを、加工シートの両面に、それぞれ、各面を覆うように、平面状に貼り、半導体チップの裏面を一方のテープにて貼り固定するテープ貼り工程と、（ｆ）表裏をモールド固定用の平板にて挟み、加工シート全体について、真空引きあるいは減圧してモールドを行う、モールド工程と、（ｇ）表裏のモールド固定用の平板とテープを除去し、切断用のテープを貼り、該切断用のテープとは反対側からダイシングソーにて切断して、樹脂封止型半導体装置を１個ずつに個片化して得る個片化工程と、を行うもので、且つ、前記エッチング加工工程は、端子部材の薄肉のリード部の厚さをｔ１、半導体チップの厚さをＴ０、前記端子部材の厚さをｔ０とした場合、ｔ０＞Ｔ０で、且つ、ｔ１を（１／２）×（ｔ０−Ｔ０）以下の所望の厚さになるように、エッチング量を調整して行うものであることを特徴とするものであり、平板状の真空引き板が、全面に真空吸着用の孔を配設したものであることを特徴とするものである。
あるいは、本発明に関わる樹脂封止型半導体装置の製造方法は、上記いずれかの樹脂封止型半導体装置を製造する、樹脂封止型半導体装置の製造方法であって、順に、（Ａ）１つの樹脂封止型半導体装置の各端子部材の配置に対応した、端子部材の配置を１単位として、エッチング技術を用いたエッチング加工にて、面付けして形成し、面付け形成された加工シートを得るエッチング加工工程と、（Ｂ）接続用の表面めっきを施すめっき処理工程と、（Ｃ）面付け形成された加工シートのエッチング面側ではない側を覆うようにモールド用のテープを貼り、面付け分だけ、半導体チップを所定の位置に位置決めして、その端子面側ではない裏面を前記テープに貼り付け搭載する半導体チップ搭載工程と、（Ｄ）この状態で、各半導体チップについて、その端子と端子部材の内部端子部の端子面とを接続する接続工程と、（Ｅ）モールド用のテープを、加工シートの両面に、それぞれ、各面を覆うように、平面状に貼り、半導体チップの裏面を一方のテープにて貼り固定するテープ貼り工程と、（Ｆ）表裏を、それぞれ、テープを介して、モールド固定用の平板にて挟み、加工シート全体について、一括してモールドを行う、一括モールド工程と、（Ｇ）表裏のモールド固定用の平板、テープを除去し、切断用のテープを貼り、該切断用のテープとは反対側からダイシングソーにて切断して、樹脂封止型半導体装置を１個ずつに個片化して得る個片化工程と、を行うもので、且つ、前記エッチング加工工程は、端子部材の薄肉のリード部の厚さをｔ１、半導体チップの厚さをＴ０、前記端子部材の厚さをｔ０とした場合、ｔ０＞Ｔ０で、且つ、ｔ１を（１／２）×（ｔ０−Ｔ０）以下の所望の厚さになるように、エッチング量を調整して行うものであることを特徴とするものである。
尚、（１／２）×（ｔ０−Ｔ０）以下の所望の厚さとは、上記本発明の樹脂封止型半導体装置を作製する際に、半導体チップとリード部との固定方法を考慮し、半導体チップの両面の封止用樹脂の厚さが同じくなるようにという意味である。 Method for manufacturing a resin-sealed semiconductor device according to the present onset Ming, to produce any of the above-mentioned resin-sealed semiconductor device, method for manufacturing the resin-sealed semiconductor device, in turn, (a) 1 single With the arrangement of terminal members corresponding to the arrangement of each terminal member of the resin-encapsulated semiconductor device as one unit, imposition is performed by etching using etching technology, and the imposition processed sheet is formed An etching process step to obtain, (b) a plating process step for performing surface plating for connection, and (c) a side that is not the thin etching formation surface side of the processed sheet formed on the surface is formed into a flat vacuum drawing plate With the processed sheet in close contact with the vacuum drawing plate, the semiconductor chip is positioned at a predetermined position for the imposition, and the back surface other than the terminal surface side is evacuated, and the vacuum drawing plate Semiconductor chip mounted on A mounting step; (d) in this state, for each semiconductor chip, a connection step for connecting the terminal and the terminal surface of the internal terminal portion of the terminal member; and (e) removing the vacuum drawing plate and replacing it with a mold. A tape application process in which the tape for use is applied to both sides of the processed sheet so as to cover each surface, and the back surface of the semiconductor chip is attached and fixed with one tape, and (f) the front and back surfaces are molded and fixed. The whole processing sheet is sandwiched between flat plates for molding, and molding is performed by evacuation or decompression, and (g) the front and back mold fixing flat plates and tape are removed, and a cutting tape is applied, A step of singulation obtained by cutting a resin-encapsulated semiconductor device into pieces one by one by cutting with a dicing saw from the side opposite to the cutting tape, and the etching step Is the terminal When the thickness of the thin lead portion of the material is t1, the thickness of the semiconductor chip is T0, and the thickness of the terminal member is t0, t0> T0 and t1 is (1/2) × (t0− T0) It is characterized in that the etching amount is adjusted so as to have a desired thickness of less than or equal to, and a flat vacuum drawing plate is provided with vacuum suction holes on the entire surface. It is characterized by being.
Alternatively, the production method of the wood Aburafutome type semiconductor device according to the present invention produces any of the above resin-sealed semiconductor device, method for manufacturing the resin-sealed semiconductor device, in turn, (A) A process in which the arrangement of the terminal member corresponding to the arrangement of each terminal member of one resin-encapsulated semiconductor device is formed by imposition using an etching technique using an etching technique as a unit. Etching process for obtaining a sheet, (B) a plating process for performing surface plating for connection, and (C) a tape for molding so as to cover the side of the processed sheet that is impositioned and not the etched surface side A semiconductor chip mounting step in which the semiconductor chip is positioned at a predetermined position by the imposition, and the back surface which is not the terminal surface side is attached and mounted on the tape; and (D) in this state, A connecting step for connecting the terminal and the terminal surface of the internal terminal portion of the terminal member, and (E) a tape for molding is applied to both sides of the processed sheet in a flat shape so as to cover each surface. , The tape application process of attaching and fixing the back surface of the semiconductor chip with one tape, and (F) the front and back surfaces are respectively sandwiched between the mold fixing flat plates via the tape, and the entire processed sheet is molded in a lump. (G) The front and back mold fixing flat plates and tape are removed, a cutting tape is applied, and the resin is cut with a dicing saw from the side opposite to the cutting tape. And a step of dividing the sealing type semiconductor device into individual pieces, and the etching step includes setting the thickness of the thin lead portion of the terminal member to t1, Thickness before T0 When the thickness of the terminal member is t0, the etching amount is adjusted so that t0> T0 and t1 is a desired thickness of (1/2) × (t0−T0) or less. It is characterized by being.
Note that the desired thickness of (1/2) × (t0−T0) or less refers to a method of fixing the semiconductor chip and the lead portion when manufacturing the resin-encapsulated semiconductor device of the present invention. This means that the sealing resin on both sides of the semiconductor chip has the same thickness.

本発明のエッチング加工部材は、上記いずれかの樹脂封止型半導体装置に用いられる、端子部材を多数配列したエッチング加工部材であって、１つの樹脂封止型半導体装置の各端子部材の配置に対応した、端子部材の配置を１単位として、エッチング技術を用いたエッチング加工にて、面付けして形成し、面付け形成しており、且つ、端子部材の薄肉のリード部の厚さをｔ１、半導体チップの厚さをＴ０、前記端子部材の厚さをｔ０とした場合、ｔ０＞Ｔ０で、且つ、ｔ１が（１／２）×（ｔ０−Ｔ０）以下の所望の厚さであることを特徴とするものである。   An etching member of the present invention is an etching member in which a large number of terminal members are arrayed, which is used in any of the above resin-encapsulated semiconductor devices, and is arranged for each terminal member of one resin-encapsulated semiconductor device. Correspondingly, the arrangement of the terminal member is set as one unit, and is formed by imposition by etching using an etching technique, and the thickness of the thin lead portion of the terminal member is t1. When the thickness of the semiconductor chip is T0 and the thickness of the terminal member is t0, t0> T0 and t1 is a desired thickness of (1/2) × (t0−T0) or less. It is characterized by.

（作用）
本発明の樹脂封止型半導体装置は、このような構成にすることにより、薄型で、且つ、対向する２辺側にパッドを配列したＳＯＮタイプの樹脂封止型半導体装置で、８ｍｍ×１０ｍｍサイズのレベルより大きい場合でも、半導体チップ両面の端子部材や樹脂の平均的な熱膨張係数がほぼ同じにバランス取れて、半導体チップの両面での平均的な熱膨張のバランスがとれ反りは抑制できるため、量産性の良いものの提供を可能としている。
そして、半導体チップを前記複数の端子部材のリード部のエッチング形成された面であるエッチング面上まで延設して配しており、大きな半導体チップについても、小サイズのパッケージを可能としている。
具体的には、
各端子部材の、エッチング面側でない非エッチング面側と外部端子部の外側側面とを、露出させ、前記端子部材の厚さにして樹脂封止しており、前記半導体チップは、その対向する２辺に接続用端子を配し、該２辺側にて、それぞれ、前記端子部材の内部端子部と電気的に接続され、且つ、その両面の封止用樹脂の厚さを等しく揃えて、配設されており、前記加工用素材をエッチングして前記端子部材を形成する際に形成された、電気的に独立して、全体を強固にするためのサポートバーを、前記２辺側でない側の、半導体チップの両側に配設しており、封止用樹脂の熱膨張率と端子部材の熱膨張率を等しくしていることにより、これを達成している。
例えば、半導体チップの一面側を接着剤（ダイアタッチ剤という）接続固定する場合、接着剤の厚さが無視できる程度であれば、半導体チップの厚さをＴ０、前記端子部材の厚さをｔ０、薄肉のリード部の厚さをｔ１、とした場合、ｔ０＞Ｔ０で、且つ、
ｔ１＝（１／２）×（ｔ０−Ｔ０）
となる。
即ち、半導体チップを、パッケージの厚さ方向で中央に位置させることにより、半導体チップ両面の端子部材や樹脂の平均的な熱膨張係数がほぼ同じにバランス取れて、使用される部材の体積量を含めた半導体チップの両面での平均的な熱膨張のバランスがとれ、反りが抑制できる。
更に、封止用樹脂の熱膨張率と端子部材の熱膨張率を等しくしていることにより、より半導体チップの両面での使用される部材の体積量を含めた部材の平均熱膨張のバランスがとれ、一層反りが発生しづらいものとしている。
特に、通常の封止用樹脂（エポキシ系の材質）は、熱膨張係数が１７×１０-6程度で、１７×１０-6の熱膨張係数のＣｕ、Ｃｕ系合金（例えば、ＯＬＩＮ−１９４、ＯＬＩＮ−７０２５、ＴＡＭＡＣ１５、ＥＦＴＥＣ６４Ｔ、ＫＬＦ１２５）の端子部材が好ましく用いられるが、４×１０-6の熱膨張係数の４２合金（４２％ＮｉーＦｅ合金）や１０×１０-6の熱膨張係数の５０合金（５０％ＮｉーＦｅ合金）を用いても、これに、封止用樹脂の熱膨張係数を合わすことにより、一層反りが発生しづらいものとできる。
また使用する樹脂の具体例として、例えば半導体用エポキシ樹脂封止材、「ＣＥＬ」（日立化成工業製）、半導体封止用エポキシ樹脂成形材料 ［スミコン ＥＭＥ］（住友ベークライト製）、半導体封止用エポキシ樹脂 ＭＰシリーズ（日東電工製）等が挙げられる。
尚、先にも述べたように、ここでは明記していないが、本発明の樹脂封止型半導体装置においては、端子部材の他に半導体チップを搭載するダイパッドをリード部と同じように薄肉にして、リード部と同じ平面上に揃えて配した形態の他、ダイパッドがない形態もあるが、ダイパッドを備えない形態の方が、ダイパッドを備えた形態より、反りに対しての半導体チップ両面のバランスの面では好ましい。
一方、配線基板の温度変化テスト（−５５℃〜１５０℃の温度で繰り返すテスト）に対しては、ダイパッドを備えた形態の方が、ダイパッドを備えない形態よりも好ましい。
ダイパッドを有する場合、ダイパッドと外部端子までの距離が変形のモーメントとなり、ダイパッドなしの樹脂封止型半導体装置よりも外部端子間距離が短い為、変形は小さくなる。
また、先にも述べたように、半導体チップと端子部材との電気的な接続は、ワイヤボンディング接続、バンプ接続が適用できるが、バンプ接続の場合には、接続により半導体チップを端子部材に固定することができ、固定方法を別にとる必要はない。
また、特に２辺パッドの場合のパッケージの反り対策として、構造強化用のサポートバーを配した構造を採っている。 (Function)
The resin-encapsulated semiconductor device of the present invention is a SON-type resin- encapsulated semiconductor device that is thin and has an array of pads on the two opposite sides. The average thermal expansion coefficient of the terminal members and resin on both sides of the semiconductor chip can be balanced to be almost the same even if the level is larger than the level of the above, and the average thermal expansion on both sides of the semiconductor chip can be balanced and warpage can be suppressed. , it is enabling the provision of a good mass productivity.
And, a semiconductor chip is disposed and extended to the plurality of etched surface is etched formed surface of the lead portion of the terminal member, for large semiconductor chips, thereby enabling the small size of the package.
In particular,
Of each of the terminal members, an outer side surface of the non-etched side and the external terminal portions not etched surface, is exposed, Ri Contact sealed with resin in the thickness of the terminal member, said semiconductor chip, its opposite Arranging connection terminals on the two sides, and on the two sides, respectively, are electrically connected to the internal terminal portions of the terminal member, and the thicknesses of the sealing resins on both sides thereof are evenly aligned. A support bar that is formed when the terminal member is formed by etching the processing material and electrically strengthening the whole is not the two sides. This is achieved by making the thermal expansion coefficient of the sealing resin and the thermal expansion coefficient of the terminal member equal to each other.
For example, when one surface side of a semiconductor chip is connected and fixed with an adhesive (referred to as a die attach agent), if the thickness of the adhesive is negligible, the thickness of the semiconductor chip is T0 and the thickness of the terminal member is t0. When the thickness of the thin lead portion is t1, t0> T0, and
t1 = (1/2) × (t0−T0)
It becomes.
That is, by positioning the semiconductor chip in the center in the thickness direction of the package, the average thermal expansion coefficients of the terminal members and the resin on both sides of the semiconductor chip are balanced to be approximately the same, and the volume of the member used is reduced. The average thermal expansion on both sides of the included semiconductor chip is balanced, and warpage can be suppressed.
Furthermore, by making the thermal expansion coefficient of the sealing resin equal to the thermal expansion coefficient of the terminal member, the balance of the average thermal expansion of the member including the volume of the member used on both sides of the semiconductor chip can be more balanced. It is assumed that warpage is less likely to occur.
In particular, a normal sealing resin (epoxy-based material) has a thermal expansion coefficient of about 17 × 10 −6 and a Cu / Cu-based alloy (for example, OLIN-194, 17 × 10 −6 ). Terminal members of OLIN-7025, TAMAC15, EFTEC64T, and KLF125) are preferably used. However, they have a 42 × 42 (Ni-Fe alloy) alloy with a thermal expansion coefficient of 4 × 10 −6 or a thermal expansion coefficient of 10 × 10 −6. Even when 50 alloy (50% Ni-Fe alloy) is used, it can be made more difficult to warp by combining it with the thermal expansion coefficient of the sealing resin.
Specific examples of resins used include, for example, epoxy resin encapsulants for semiconductors, “CEL” (manufactured by Hitachi Chemical), epoxy resin molding materials for semiconductor encapsulants [Sumicon EME] (manufactured by Sumitomo Bakelite), and semiconductor encapsulants Epoxy resin MP series (manufactured by Nitto Denko) and the like can be mentioned.
As described above, although not specified here, in the resin-encapsulated semiconductor device of the present invention, in addition to the terminal member, the die pad for mounting the semiconductor chip is made thin like the lead portion. In addition to the form arranged on the same plane as the lead part, there is also a form without a die pad, but the form without the die pad is more on both sides of the semiconductor chip against warping than the form with the die pad. It is preferable in terms of balance.
On the other hand, for a temperature change test of a wiring board (a test repeated at a temperature of −55 ° C. to 150 ° C.), the form with a die pad is preferable to the form without a die pad.
In the case of having a die pad, the distance between the die pad and the external terminal becomes a moment of deformation, and the distance between the external terminals is shorter than that of the resin-encapsulated semiconductor device without the die pad, so that the deformation becomes small.
As described above, wire bonding connection and bump connection can be applied to the electrical connection between the semiconductor chip and the terminal member. In the case of bump connection, the semiconductor chip is fixed to the terminal member by the connection. You do not need to use a separate fixing method.
In particular as package warpage measures in the case of two sides pads, has a structure which arranged support bars for structural reinforcement.

そして、リードの先端の先端側面部、該先端側面部挟む先端の両側面部を、封止用樹脂と密着性のよい構造としている、請求項３の発明の形態とすることにより、温度変化に耐える、耐湿性の良い構造としている。
前記封止用樹脂と密着性のよい構造としては、リード部の先端の先端側面部、該先端側面部挟む先端の両側面部を、外側に向かい、パッケージ内側となるテーパ形状としている形態や、リード部の先端の先端側面部、該先端側面部挟む先端の両側面部に、前記リード部のエッチング面に沿い、めっきによる庇を設けている形態が挙げられる。
尚、リードの内側の先端断面は、ハーフエッチング形成面と側面とが鋭角をなす形態とすることにより、リード部の長手方向の先端において、温度変化に伴う、樹脂の締め付けが起こる構造で、耐湿性の良い構造となる。
また、先端が鋭角となった分だけ封止用樹脂の量を増やすことも可能で、封止用樹脂の量が増える分、構造的、品質面で安定する。
尚、前記鋭角の角度としては、８５度以下が好ましい。
樹脂との端子部材の引き抜き抑制出来るからである。
更に、前記各端子部材は、そのリード部の内側の先端幅を先細としている形態とすることにより、先端が先細となった分だけ封止用樹脂の量を増やすことも可能で、封止用樹脂の量が増える分、構造的、品質面で安定する。 Further, by adopting the structure of the invention according to claim 3, the tip side surface portion at the tip of the lead and the both side surface portions of the tip sandwiching the tip side surface portion have a structure having good adhesion to the sealing resin, thereby withstanding temperature change. It has a structure with good moisture resistance.
As the structure having good adhesion to the sealing resin, the tip side surface portion at the tip of the lead portion and both side surface portions at the tip sandwiching the tip side surface portion are outwardly tapered, and the taper shape is the inside of the package. There is a form in which ridges by plating are provided along the etching surface of the lead portion on the tip side surface portion of the tip portion and on both side surface portions of the tip sandwiching the tip side surface portion.
In addition, the cross-section of the inner tip of the lead has a structure in which the resin is tightened in accordance with the temperature change at the tip in the longitudinal direction of the lead portion by forming an acute angle between the half-etch formation surface and the side surface. It becomes a good structure.
In addition, the amount of the sealing resin can be increased by the amount of the acute angle of the tip, and the amount of the sealing resin is increased, so that the structure and quality are stabilized.
The acute angle is preferably 85 degrees or less.
This is because the pull-out of the terminal member with the resin can be suppressed.
Furthermore, each terminal member has a shape in which the tip width inside the lead portion is tapered, so that the amount of the sealing resin can be increased by the amount that the tip is tapered. As the amount of resin increases, it stabilizes in terms of structure and quality.

また、前記端子部材には、その加工用素材面側に、溝（グルーブ）およびまたは孔状凹部を設けている、請求項６の発明の形態とすることにより、はんだ付け実装時のはんだ流れを防止できるものとしている。 Further, the terminal member is provided with a groove and / or a hole-like concave portion on the processing material surface side, whereby the solder flow at the time of soldering mounting is achieved by adopting the form of the invention of claim 6. It can be prevented.

また、前記各端子部材の前記封止用樹脂表面と接する表面部に粗面化処理を施した、請求項７の発明の形態としていることにより、端子部材と封止用樹脂との密着性の向上が図れる。
特に、前記粗面化処理による、最大高さ粗さＲｙ（ＪＩＳ Ｂ０６０１−１９９４）が、１μｍ〜２μｍの範囲である場合には、端子部材表面の表面積を広くし、樹脂を食い込ませることから、端子部材と樹脂との密着性を向上できる。
また、外部端子部の外側側面部に、切り欠け部を設けている、請求項１０の発明の形態
としていることにより、その面付け作製において、個片化の際、その切断をし易いものとしている。 Further, the subjected to the roughening treatment on the surface part in contact with the sealing resin surface of each of the terminal members, by which the form of the invention of claim 7, the adhesion between the terminal member and the sealing resin Improvement can be achieved.
In particular, when the maximum height roughness Ry (JIS B0601-1994) by the roughening treatment is in the range of 1 μm to 2 μm, the surface area of the terminal member surface is widened, and the resin is bitten. The adhesion between the terminal member and the resin can be improved.
Further, by providing a cutout portion on the outer side surface portion of the external terminal portion, the invention according to claim 10 makes it easy to cut the piece when it is singulated in the imposition preparation. Yes.

本発明の積層型樹脂封止型半導体装置は、このような構成にすることにより、樹脂封止型半導体装置を積層したスタック構造の積層型樹脂封止型半導体装置の提供を可能としている。   By adopting such a configuration, the laminated resin-encapsulated semiconductor device of the present invention can provide a laminated resin-encapsulated semiconductor device having a stack structure in which resin-encapsulated semiconductor devices are laminated.

本発明に関わる樹脂封止型半導体装置の製造方法は、このような構成にすることにより、請求項１〜請求項９の各発明の薄型の樹脂封止型半導体装置を、量産性良く製造できるものとしている。 Method for producing a dendritic Aburafutome type semiconductor device according to the present onset Ming, by adopting such a configuration, the thin resin-sealed semiconductor device of the invention of claim 1 to claim 9, high mass productivity It can be manufactured.

本発明のエッチング加工部材は、このような構成にすることにより、請求項１〜請求項１１の各発明の薄型の樹脂封止型半導体装置を、量産性良く製造できるものとしている。   The etching processed member of the present invention can manufacture the thin resin-encapsulated semiconductor device of each of the first to eleventh aspects of the present invention with high productivity by adopting such a configuration.

本発明は、上記のように、薄型で、且つ、対向する２辺側にパッドを配列した、あるいは、１辺側にパッドを配列した、ＳＯＮタイプ、４辺側にパッドを配列したＱＦＮタイプの樹脂封止型半導体装置で、８ｍｍ×１０ｍｍサイズのレベルより大きい場合でも、反りが発生しづらい構造の薄型の樹脂封止型半導体装置で、量産性の良いものの提供を可能とした。
更に、このような薄型の樹脂封止型半導体装置を複数積層した、スタック構造の積層型樹脂封止型半導体装置の提供を可能にした。
同時に、このような薄型の樹脂封止型半導体装置の製造方法の提供を可能とした。
更にまた、このような薄型の樹脂封止型半導体装置に用いられる端子部材を、該樹脂封止型半導体装置を量産性に合うエッチング加工部材の形態で供給できるものとしている。 As described above, the present invention is a thin and QFN type in which pads are arranged on opposite two sides, or pads are arranged on one side, and pads are arranged on four sides. Even if the resin-encapsulated semiconductor device is larger than the 8 mm × 10 mm size level, it is possible to provide a thin resin-encapsulated semiconductor device having a structure in which warpage does not easily occur and high-productivity.
Furthermore, it is possible to provide a stacked resin-sealed semiconductor device having a stack structure in which a plurality of such thin resin-sealed semiconductor devices are stacked.
At the same time, it is possible to provide a method for manufacturing such a thin resin-encapsulated semiconductor device.
Furthermore, the terminal member used for such a thin resin-encapsulated semiconductor device can be supplied in the form of an etching member suitable for mass production of the resin-encapsulated semiconductor device.

本発明の実施の形態を図に基づいて説明する。
図１（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第１の例を示した概略断面図で、図１（ｂ）は図１（ａ）のＡ１側から透視してみた図で、図１（ｃ）は、図１（ｂ）の一点鎖線Ａ５−Ａ６ーＡ７−Ａ８におけるサポートバーの断面を示した図で、図２（ａ）は端子部材の断面図で、図２（ｂ）は図１（ａ）のＢ１側から見た図で、図２（ｃ）は図２（ａ）のＢ２側からみた図で、図２（ｄ）は図２（ａ）のＢ３側からみた図で、図３（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第２の例を示した概略断面図で、図３（ｂ）は本発明に関わる樹脂封止型半導体装置の参考実施形態例１を示した概略断面図で、図３（ｃ）は本発明に関わる樹脂封止型半導体装置の参考実施形態例２を示した概略断面図で、図４（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第３の例を示した概略断面図で、図４（ｂ）は図４（ａ）のＥ１側から透視してみた図で、図５は本発明の積層型樹脂封止型半導体装置の実施の形態の第１の例の断面図で、図６は本発明に関わる積層型樹脂封止型半導体装置の参考実施形態例１の断面図で、図７は本発明に関わる積層型樹脂封止型半導体装置の参考実施形態例２の断面図で、図８（ａ）は本発明の積層型樹脂封止型半導体装置の実施の形態の第２の例の断面図で、図８（ｂ）は図８（ａ）のＥ１側からみた図で、図９（ａ）〜図９（ｈ）は本発明に関わる樹脂封止型半導体装置の製造方法の参考実施形態例１の製造工程断面図で、図１０（ａ）〜図１０（ｉ）は本発明に関わる樹脂封止型半導体装置の製造方法の参考実施形態例２の製造工程断面図で、図１１（ａ）、１１（ｂ）はダイシングソーによる切断状態を示した図である。
また、図１２（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第２の例の変形例を示した概略断面図で、図１２（ｂ）は図１２（ａ）のＧ１側から透視してみた図である。
尚、図１（ａ）は図１（ｂ）のＡ２−Ａ３側から見た図である。
また、図５〜図１０においては、分かり易くするために、半導体チップの端子部は省略して示している。
また、図９（ｇ）、図１０（ｈ）における両方向矢印は、ダイシングソーの昇降方向を示している。
また、図１２（ａ）は図１２（ｂ）のＧ２−Ｇ３側から見た図である。
図１〜図１２中、１０１〜１０４、１０１ａ〜１０４ａ、１０１ｂ〜１０４ｂは樹脂封止型半導体装置、１１０は端子部材、１１１は外部端子部、１１１ａ、１１１ｂ、１１１ｃは端子面、１１２はリード部（単にリードとも言う）、１１２ａは端子面（エッチング面でもある）、１１４は切り欠け部、１１６は先端部、１１６Ｓは（先端の）側面、１１７はグルーブ（溝部）、１１８は孔状凹部、１１９はダイパッド、１２０、１２０Ａ、１２０Ｍは半導体チップ（半導体素子とも言う）、１２１は端子、１２１Ａはバンプ接続部（はんだ部）、１３０はボンディングワイヤ、１４０は封止用樹脂、１６０、１６０Ａはサポートバー、１６１ａ，１６２ａは薄肉部、１６２は厚肉部、１６５は延設部分、１８０はテープ、１９０は半田ペースト（導電性ペーストとも言う）、１９５は基材、２１０は加工用素材、２１０Ａは加工シート、２２０はレジスト、２３０は端子部材、２３１は外部端子部、２３２はリード部（単にリードとも言う）、２３５は支持部（連結部とも言う）、２３７は凹部、２３７Ａは切り欠け部、２４０は平板状の多孔板（真空引き板とも言う）、２５０は半導体チップ（半導体素子とも言う）、２６０はボンディングワイヤ、２７０、２７１は（固定用、モールド用の）テープ、２７５は（ダイシング用の）テープ、２８０は封止用樹脂、３０１は単位の樹脂封止型半導体装置、３１０は加工用素材、３１０Ａは加工シート、３１５は枠部、３１６は治具孔、３１７は長孔部、３２０はレジスト、３３０は端子部材、３３５は支持部（連結部とも言う）、３３７は凹部、３３７Ａは切り欠け部、３４０、３４１は（固定用、モールド用の）テープ、３４５は（切断用の）テープ、３５０は半導体チップ（半導体素子とも言う）、３６０はボンディングワイヤ、３７１、３７２はモールド固定用の平板、３８０は封止用樹脂、３８５は切断ライン、３８６は切断目印（貫通孔あるいは窪み）、４０１〜４０８は樹脂封止型半導体装置である。 Embodiments of the present invention will be described with reference to the drawings.
FIG. 1A is a schematic cross-sectional view showing a first example of an embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 1B is seen through from the A1 side of FIG. FIG. 1C is a view showing a cross section of the support bar taken along one-dot chain line A5-A6-A7-A8 in FIG. 1B, and FIG. 2A is a cross-sectional view of the terminal member. 2B is a view from the B1 side in FIG. 1A, FIG. 2C is a view from the B2 side in FIG. 2A, and FIG. 2D is a view from FIG. in view seen from the B3 side, a schematic sectional view showing a second example of the embodiment of the resin encapsulated semiconductor device of FIG. 3 (a) the present invention, FIG. 3 (b) to the onset bright involved in a schematic sectional view showing a reference embodiment 1 of a resin sealed semiconductor device, FIG. 3 (c) schematic cross section showing a reference embodiment 2 of trees Aburafutome type semiconductor device according to the present onset bright Figure 4 (a) shows the book A schematic cross section showing a third example of the embodiment of light of a resin sealed semiconductor device, a view viewed as projected from E1 side of 4 (b) is FIG. 4 (a), the 5 in the first example cross-sectional view of the embodiment of the stacked resin-sealed semiconductor device of the present invention, FIG. 6 is a cross-sectional of reference embodiment 1 of the product layer resin sealed semiconductor device according to the present onset bright in figure 7 embodiment of the laminated resin-sealed semiconductor device in a cross section view of reference embodiment 2 of the product layer resin sealed semiconductor device according to the present onset bright, FIG. 8 (a) the invention in the cross-sectional view of a second example of the embodiment, a diagram viewed from the E1 side of FIG. 8 (b) FIG. 8 (a), the FIG. 9 (a) ~ FIG 9 (h) is tree fat according to this onset bright in manufacturing process sectional views of reference embodiment 1 of a method of manufacturing a sealed type semiconductor device, FIG. 10 (a) ~ FIG 10 (i) is a reference of the method of manufacturing the trees Aburafutome type semiconductor device according to the present onset bright Example embodiment In the manufacturing process cross-sectional view, FIG. 11 (a), 11 (b ) is a diagram showing a cut state by the dicing saw.
FIG. 12A is a schematic cross-sectional view showing a modification of the second example of the embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 12B is G1 in FIG. It is the figure seen through from the side.
1A is a view as seen from the A2-A3 side in FIG. 1B.
Also, in FIG. 5 to FIG. 10, the terminal portions of the semiconductor chip are omitted for easy understanding.
Moreover, the double-directional arrow in FIG.9 (g) and FIG.10 (h) has shown the raising / lowering direction of the dicing saw.
FIG. 12A is a view as seen from the G2-G3 side of FIG.
1 to 12, 101 to 104, 101a to 104a, and 101b to 104b are resin-encapsulated semiconductor devices, 110 is a terminal member, 111 is an external terminal portion, 111a, 111b, and 111c are terminal surfaces, and 112 is a lead portion. 112a is a terminal surface (also an etching surface), 114 is a notch portion, 116 is a tip portion, 116S is a side surface of the tip, 117 is a groove (groove portion), 118 is a hole-like recess, 119 is a die pad, 120, 120A and 120M are semiconductor chips (also referred to as semiconductor elements), 121 is a terminal, 121A is a bump connection part (solder part), 130 is a bonding wire, 140 is a sealing resin, and 160 and 160A are supports Bars 161a and 162a are thin-walled portions, 162 are thick-walled portions, 165 are extended portions, 180 are tapes, and 190 are solder pages. G (also referred to as conductive paste), 195 is a base material, 210 is a processing material, 210A is a processed sheet, 220 is a resist, 230 is a terminal member, 231 is an external terminal portion, and 232 is a lead portion (also simply referred to as a lead). 235 is a support portion (also referred to as a connecting portion), 237 is a recess, 237A is a notch portion, 240 is a flat plate-like porous plate (also referred to as a vacuum drawing plate), 250 is a semiconductor chip (also referred to as a semiconductor element), 260 is Bonding wires, 270 and 271 are tapes (for fixing and molding), 275 is a tape (for dicing), 280 is a sealing resin, 301 is a resin-encapsulated semiconductor device of a unit, 310 is a processing material, 310A is a processed sheet, 315 is a frame portion, 316 is a jig hole, 317 is a long hole portion, 320 is a resist, 330 is a terminal member, and 335 is a support portion (also called a connecting portion). 337 is a recess, 337A is a notch, 340 and 341 are tapes (for fixing and molding), 345 is a tape (for cutting), 350 is a semiconductor chip (also called a semiconductor element), 360 is a bonding wire, 371 , 372 is a mold fixing flat plate, 380 is a sealing resin, 385 is a cutting line, 386 is a cutting mark (through hole or recess), and 401 to 408 are resin-sealed semiconductor devices.

はじめに、本発明の樹脂封止型半導体装置の実施の形態の第１の例を、図１に基づいて説明する。
第１の例の樹脂封止型半導体装置は、外部回路と接続するための外部端子部１１１と、半導体チップ１２０と接続するための内部端子部をその一部として含むリード部１１２とを、一体的に連結してなる端子部材で、且つ、加工用素材から、外部端子部１１１の少なくとも一部を加工用素材の厚さの厚肉にし、リード部１１２を加工用素材の一面側からのエッチングにより薄肉としている端子部材１１０、複数個と、半導体チップ（１２０）１つとを、用いて、該複数の端子部材１１０を一平面状にその向きを揃えて、半導体チップ１２０の周辺に沿って、外部端子部１１１を外側に向けて、内部端子部（リード部１２０のボンディングワイヤ１３０を接続する部分）を内側に向けて、配し、半導体チップ１２０を前記複数の端子部材１１０のリード部１１２のエッチング形成された面であるエッチング面（１１２ａに相当）上まで延設して配し、且つ、半導体チップ１２０と所定の端子部材１１０とを電気的に接続し、樹脂封止している、ＳＯＮタイプの樹脂封止型半導体装置である。
そして、特に、各端子部材１１０の、エッチング面側でない非エッチング面（端子面１１１ｂに相当）側と外部端子部１１１の外側側面（端子面１１１ａ、１１１ｃに相当）とを、露出させ、前記端子部材１１０の厚さにして樹脂封止しており、且つ、前記半導体チップ１２０は、その両面の封止用樹脂の厚さを等しく揃えて、配設されている。
本例では、端子部材１１０の薄肉のリード部１１２の厚さをｔ１、半導体チップ１２０の厚さをＴ０、前記端子部材の厚さをｔ０とした場合、ｔ０＞Ｔ０で、且つ、ｔ１を（１／２）×（ｔ０−Ｔ０）以下の所望の厚さになるようにしている。
半導体チップの一面側を接着剤（ダイアタッチ剤という）接続固定する形態で、接着剤の厚さが無視できる程度であれば、（１／２）×（ｔ０−Ｔ０）が所望の厚さになる。
また、各端子部材１１０の露出した面部を、接続用の端子面１１１ａ、１１１ｂ、１１１ｃとしている。
また、電気的に独立して、全体を強固にするためのサポートバー１６０，１６０Ａとを備えている。
第１の例においては、特に、半導体チップ１２０を、パッケージの厚さ方向で中央に位置させることにより、半導体チップ１２０の両面での使用される部材の体積量を含めた部材の平均熱膨張のバランスがとれ、反りが発生しづらいものとしている。
構造的に反り発生を防止でき、品質面で安定が期待できる。
本例では、１７×１０-6の熱膨張係数のＣｕ材からなる端子部材１１０を用いて、且つ、封止用樹脂の熱膨張率と端子部材の熱膨張率を等しくしており、より半導体チップの両面での使用される部材の体積量を含めた部材の平均熱膨張のバランスがとれ、一層反りが発生しづらいものとしている。
尚、図１（ａ）には明示していないが、本例では、ダイアタッチ剤（ここでは、０．０１ｍｍの厚さ）により、半導体チップの端子面側ではない裏面をリード部１１２に固定している。
また、半導体チップ１２０の厚さをリード部１１２の厚さより薄していることにより、ワイヤボンディング高さをより高く取れるので、ボンディング作業性の向上や歩留まり少なくすることができる。
また、本例は、後述する、本発明の樹脂封止型半導体装置の製造方法により、面付け状態で作製でき、量産性の良い構造といえる。 First, a first example of an embodiment of the resin-encapsulated semiconductor device of the present invention will be described with reference to FIG.
The resin-encapsulated semiconductor device of the first example includes an external terminal portion 111 for connecting to an external circuit and a lead portion 112 including an internal terminal portion for connecting to the semiconductor chip 120 as a part thereof. The connecting terminal member is made of a processing material, and at least a part of the external terminal portion 111 is made thicker than the processing material, and the lead portion 112 is etched from one side of the processing material. The plurality of terminal members 110 and a single semiconductor chip (120) are used to align the orientation of the plurality of terminal members 110 in a single plane, along the periphery of the semiconductor chip 120, The plurality of terminal members 110 are arranged with the external terminal portion 111 facing outward and the internal terminal portion (portion where the bonding wire 130 of the lead portion 120 is connected) facing inward. The lead portion 112 is provided so as to extend to an etching surface (corresponding to 112a), which is an etched surface of the lead portion 112, and the semiconductor chip 120 and a predetermined terminal member 110 are electrically connected and resin-sealed. It is a SON type resin-encapsulated semiconductor device.
In particular, the non-etched surface (corresponding to the terminal surface 111b) side and the outer side surface (corresponding to the terminal surfaces 111a and 111c) of the terminal member 110 that are not on the etching surface side are exposed, and the terminals The thickness of the member 110 is resin-encapsulated, and the semiconductor chip 120 is arranged with the same thickness of the encapsulating resin on both sides.
In this example, when the thickness of the thin lead portion 112 of the terminal member 110 is t1, the thickness of the semiconductor chip 120 is T0, and the thickness of the terminal member is t0, t0> T0 and t1 is ( 1/2) × (t0−T0) or less.
If one side of the semiconductor chip is connected and fixed with an adhesive (referred to as a die attach agent) and the thickness of the adhesive is negligible, (1/2) × (t0−T0) is a desired thickness. Become.
Further, the exposed surface portions of the terminal members 110 are used as connection terminal surfaces 111a, 111b, and 111c.
In addition, it is provided with support bars 160 and 160A that are electrically independent and strengthen the whole.
In the first example, in particular, by positioning the semiconductor chip 120 in the center in the thickness direction of the package, the average thermal expansion of the members including the volume of the members used on both sides of the semiconductor chip 120 is obtained. The balance is balanced and warpage is unlikely to occur.
Structurally, warpage can be prevented and stability in quality can be expected.
In this example, the terminal member 110 made of a Cu material having a thermal expansion coefficient of 17 × 10 −6 is used, and the thermal expansion coefficient of the sealing resin and the thermal expansion coefficient of the terminal member are made equal to each other. The average thermal expansion of the member including the volume of the member to be used on both sides of the chip is balanced, and warpage is less likely to occur.
Although not explicitly shown in FIG. 1A, in this example, the back surface that is not the terminal surface side of the semiconductor chip is fixed to the lead portion 112 by a die attach agent (here, thickness of 0.01 mm). doing.
Further, since the thickness of the semiconductor chip 120 is made thinner than the thickness of the lead portion 112, the wire bonding height can be made higher, so that the bonding workability can be improved and the yield can be reduced.
In addition, this example can be manufactured in an imposition state by a method for manufacturing a resin-encapsulated semiconductor device of the present invention, which will be described later, and can be said to be a structure with good mass productivity.

各端子部材１１０は、エッチング加工法を用いて、平板状の加工用素材から、外部端子部１１１を加工用素材の厚さｔ０の厚肉にし、リード部１１２を加工用素材の一面側からのエッチングにより厚さｔ１の薄肉として、形成されたものである。
ここでは、半導体チップの厚さをＴ０とした場合、ｔ０＞Ｔ０で、且つ、ｔ１が（１／２）×（ｔ０−Ｔ０）以下の所望の厚さである。
尚、薄肉部は、加工用素材の厚さｔ０の半分の厚さより薄いため、エッチング面１１２ａは、ハーフエッチングより深くエッチングして形成されるため、ディープエッチング面とも呼ばれる。
図２に示すように、リード部１１２の半導体チップ１２０側の先端断面は、リード部１１２の端子面１１２ａと先端部１１６の側面１１６Ｓとが鋭角をなし、また、そのリード部１１２の半導体チップ１２０側の先端幅を先細とし、更に、グルーブ（溝部）１１７、孔状凹部１１８を端子面１１１ｂ側に配している。（図２（ａ）〜図２（ｄ）を参照）
また、サポートバー１６０、１６０Ａは、各端子部材を形成する際に、一緒に形成されたもので、薄肉のエッチング部（図１（ｃ）の薄肉部１６１ａ、１６１ｂがこれに相当）を有する。
尚、薄肉部１６１ａは、Ａ１側（図１（ａ）参照）からみえる面がエッチング形成面で、薄肉部１６１ｂは、Ａ１側（図１（ａ）参照）からみえる面が加工用素材面で、ここで図１（ｃ）におけるサポートバー１６０Ａは、サポートバー１６０とは、その延設部分１６５を含めて対称に形成されている。
本例では、厚さ０．２ｍｍのＣｕ材を加工用素材として、リード部１１２の厚さを０．０７ｍｍとし、厚さ７０μｍの半導体チップを用いたが、加工用素材としては、Ｃｕ系合金（例えば、ＯＬＩＮ−１９４、ＯＬＩＮ−７０２５、ＴＡＭＡＣ１５、ＥＦＴＥＣ６４Ｔ、ＫＬＦ１２５）や４２合金（４２％Ｎｉ−Ｆｅ合金）、５０合金（５０％Ｎｉ−Ｆｅ合金）等も適用できる。
通常、半導体チップとして、３０μｍ〜７０μｍの厚さのものが用いられ、リード部１１２の厚さとしては、例えば、０．０５ｍｍ〜０．０７ｍｍの範囲のものが、好ましく用いられる。
半導体チップ１２０自体の厚さの薄化に対応して、薄型化が達成できる。
半導体チップ１２０は、その短辺側の２辺に沿い端子１２１を設けたもので、該２辺に沿い離して端子部材１１０を配置し、対応する半導体チップ１２０の端子１２１と端子部材１１０とをボンディングワイヤ１３０にて接続している。
このように、サポートバー１６０、１６０Ａを設けた構造としていることにより、ＳＯＮタイプの樹脂封止型半導体装置で、半導体チップ自体の厚さの薄化に対応して、薄型化した場合、８ｍｍ×１０ｍｍサイズのレベルより大きくなっても、強度的に対応できるものとしている。
また、半導体チップ１２０の端子面側でない面（裏面）を露出させるようにして、配置していることにより、ダイパッドレスからパッケージ内の半導体チップ上のレジン厚を増し、組み立て加工し易いものとしており、より放熱性に優れるものとしている。
また、端子部材１１０のリード部１１２の先端形状を工夫していることにより、リード部１１２の先端において、温度変化による封止用樹脂の締め付けを良くし、耐湿性の良いものとしている。 Each terminal member 110 is formed from a flat processing material by using an etching method, the external terminal portion 111 is made thick with a thickness t0 of the processing material, and the lead portion 112 is formed from one side of the processing material. It is formed as a thin wall having a thickness t1 by etching.
Here, when the thickness of the semiconductor chip is T0, t0> T0 and t1 is a desired thickness of (1/2) × (t0−T0) or less.
Since the thin portion is thinner than half the thickness t0 of the processing material, the etching surface 112a is formed by etching deeper than half etching, and is also called a deep etching surface.
As shown in FIG. 2, in the tip section of the lead portion 112 on the semiconductor chip 120 side, the terminal surface 112 a of the lead portion 112 and the side surface 116 </ b> S of the tip portion 116 form an acute angle, and the semiconductor chip 120 of the lead portion 112. The front end width is tapered, and a groove (groove) 117 and a hole-shaped recess 118 are arranged on the terminal surface 111b side. (See FIG. 2 (a) to FIG. 2 (d))
The support bars 160 and 160A are formed together when forming each terminal member, and have thin etching portions (the thin portions 161a and 161b in FIG. 1C correspond to this).
The thin-walled portion 161a has a surface that can be seen from the A1 side (see FIG. 1A) as an etching surface, and the thin-walled portion 161b has a surface that can be seen from the A1 side (see FIG. 1A) as a processing material surface. Here, the support bar 160A in FIG. 1C is formed symmetrically with the support bar 160 including the extended portion 165 thereof.
In this example, a Cu material having a thickness of 0.2 mm was used as a processing material, a thickness of the lead portion 112 was 0.07 mm, and a semiconductor chip having a thickness of 70 μm was used. (For example, OLIN-194, OLIN-7025, TAMAC15, EFTEC64T, KLF125), 42 alloy (42% Ni-Fe alloy), 50 alloy (50% Ni-Fe alloy), and the like can also be applied.
Usually, a semiconductor chip having a thickness of 30 μm to 70 μm is used, and a thickness of the lead portion 112 is preferably, for example, in the range of 0.05 mm to 0.07 mm.
The thinning can be achieved in response to the thinning of the thickness of the semiconductor chip 120 itself.
The semiconductor chip 120 is provided with terminals 121 along two sides on the short side, and terminal members 110 are arranged along the two sides, and the corresponding terminals 121 and terminal members 110 of the semiconductor chip 120 are arranged. They are connected by bonding wires 130.
As described above, by providing the support bars 160 and 160A, in the SON type resin-encapsulated semiconductor device, when the thickness of the semiconductor chip itself is reduced, 8 mm × Even if it becomes larger than the level of 10 mm size, it can cope with strength.
In addition, by disposing the semiconductor chip 120 so that the surface (back surface) that is not the terminal surface side is exposed, the resin thickness on the semiconductor chip in the package is increased from the die padless, making it easy to assemble. , More heat dissipation.
Further, by devising the tip shape of the lead portion 112 of the terminal member 110, the tip portion of the lead portion 112 is improved in tightening of the sealing resin due to temperature change, and has high moisture resistance.

第１の例においては、各端子部材１１０の表面を、過酸化水素溶液にて、粗面化処理している。
これにより、一層の耐湿性の向上が図れる。
表面粗さとしては、最大高さ粗さＲｙ（ＪＩＳ Ｂ０６０１−１９９４）で１μｍ〜２μｍの範囲が好ましい。
端子部材表面の表面積を広くし、樹脂を食い込ませることから、端子部材と樹脂との密着性を向上できるからである。
ここでは、最大高さ粗さＲｙの測定はデジタル型の触針式表面粗さ測定器を用い、測定基準長さを２００μｍにして、端子部材表面凹凸の最大高さ粗さＲｙを測定した。
測定方法はＪＩＳ Ｂ０６０１−１９９４の規格に従う。
先にも述べたが、ここでは、最大高さ粗さＲｙの測定は２００μｍ長さで行ったものである。 In the first example, the surface of each terminal member 110 is roughened with a hydrogen peroxide solution.
Thereby, further improvement in moisture resistance can be achieved.
The surface roughness is preferably in the range of 1 μm to 2 μm in terms of the maximum height roughness Ry (JIS B0601-1994).
This is because the surface area of the surface of the terminal member is increased and the resin is bitten, so that the adhesion between the terminal member and the resin can be improved.
Here, the maximum height roughness Ry was measured by using a digital stylus type surface roughness measuring instrument, measuring the maximum reference roughness length of 200 μm, and measuring the maximum height roughness Ry of the terminal member surface irregularities.
The measurement method follows the standard of JIS B0601-1994.
As described above, here, the measurement of the maximum height roughness Ry was performed with a length of 200 μm.

また、第１の例においては、外部端子部１１１の前記他方側の面と外側側面にわたる切り欠け部１１４を設けており、これにより、その面付け作製において、個片化の際、その切断をし易いものとしている。
特に、樹脂封止工程（モールド工程）においては、特別な形状にキャビティーを設ける必要はなく、平板状のものでその両側を抑えた状態で一括モールドが簡単に行え、量産性、設備の面からも好ましい構造と言える。 Further, in the first example, a cutout portion 114 extending between the other side surface and the outer side surface of the external terminal portion 111 is provided. It is easy to do.
In particular, in the resin sealing process (molding process), it is not necessary to provide a cavity in a special shape, and it is easy to perform batch molding with a flat plate with both sides suppressed. Therefore, it can be said to be a preferable structure.

第１の例においては、図では明示していないが、端子部材１１０のリード部１１２の端子面１１２ａおよび外部端子部１１１の端子面１１１ａ、１１１ｂ、１１１ｃに、接続用のめっき層をつけている。
接続用のめっき層として、半田めっき層、金めっき層、銀めっき層、パラジウムめっき層、錫めっき層等の金属めっき層が挙げられる。 In the first example, although not shown in the drawing, a plating layer for connection is provided on the terminal surface 112a of the lead portion 112 of the terminal member 110 and the terminal surfaces 111a, 111b, and 111c of the external terminal portion 111. .
Examples of the plating layer for connection include metal plating layers such as a solder plating layer, a gold plating layer, a silver plating layer, a palladium plating layer, and a tin plating layer.

次に、本発明の樹脂封止型半導体装置の実施の形態の第２の例、参考実施形態例１、参考実施形態例２を、それぞれ、図３（ａ）、図３（ｂ）、図３（ｃ）に基づいて説明する。
第２の例の樹脂封止型半導体装置は、図３（ａ）に示すように、第１の例において、リード部と同じように薄肉にして、リード部と同じ平面上に揃えて、ダイパッド１１９を配したものである。
ダイパッド１１９のサイズとしては、半導体チップ１２０よりもできるだけ小サイズの方が反りの面からは好ましい。
先にも述べたが、ダイパッドを備えない形態の方が、ダイパッドを備えた形態より、反りに対しての半導体チップ両面のバランスの面では好ましい。
一方、配線基板の温度変化テスト（−５５℃〜１５０℃の温度で繰り返すテスト）に対しては、ダイパッドを備えた形態の方が、ダイパッドを備えない形態よりも好ましい。
ダイパッドを有する場合、ダイパッドと外部端子までの距離が変形のモーメントとなり
、ダイパッドなしの樹脂封止型半導体装置よりも外部端子間距離が短い為、変形は小さくなる。
図３（ａ）には明示していないが、第２の例においては、半導体チップ１２０をダイパッド１１９およびリード部１１２にダイアタッチ剤にて固定している。
ダイパッド１１９以外は、第１の例と同じで、図３（ａ）のＢ１側から見た平面図は、
第１の例の図１（ｂ）に示す平面図と同じくなる。
各部についての説明は省く。
図３（ａ）に示す第２の例においては、ダイパッド１１９は半導体チップ１２０の端子面でない裏面のセンター領域のみを保持するものであるが、変形例として、図１２に示すような、半導体チップ１２０の裏面全体を保持する形態も挙げられる。
尚、先にも述べたが、図１２（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第３の例の変形例を示した概略断面図で、図１２（ｂ）は図１２（ａ）のＧ１側から透視してみた図である。
参考実施形態例１の樹脂封止型半導体装置は、図３（ｂ）に示すように、第１の例において、２辺に沿い、それぞれ、端子１２１を配列して設けた２辺タイプの半導体チップ１２０に代えて、半導体チップの中央に１列に端子を配列したセンター配列の１辺タイプの半導体チップ１２０Ａを用いたものである。
図３（ｂ）のＣ１側から見た平面図は図示していないが、センター配列の各端子と、センター配列を挟む両側の各リード部１１２とがワイヤボンディング接続されている。
この形態の場合、第１の例に比べて、ワイヤボンディング長が長くなるため、ボンディ
ングワイヤ１３０の垂れに対応するため、テープ１８０を半導体チップの端子面側に配設している。
他は、第１の例と同じで、各部についての説明は省く。
参考実施形態例２の樹脂封止型半導体装置は、図３（ｃ）に示すように、第３の例において、リード部と同じように薄肉にして、リード部と同じ平面上に揃えて、ダイパッド１１９を配したものである。
図３（c ）のＤ１側から見た平面図は図示していないが、センター配列の各端子と、センター配列を挟む両側の各リード部１１２とがワイヤボンディング接続されている。
ダイパッド１１９のサイズとしては、半導体チップ１２０よりもできるだけ小サイズの
方が反りの面からは好ましい。
他は、第３の例と同じである。
また、図３（ｃ）に示す第４の例においては、ダイパッド１１９は半導体チップ１２０の端子面でない裏面のセンター領域のみを保持するものであるが、変形例として、第２の例の変形例のように、図１２に示すような、半導体チップ１２０の裏面全体を保持する形態も挙げられる。 Next, a second example, a reference embodiment example 1, and a reference embodiment example 2 of the embodiment of the resin-encapsulated semiconductor device of the present invention are respectively shown in FIG. 3 (a), FIG. 3 (b), and FIG. This will be described based on 3 (c).
As shown in FIG. 3A, the resin-encapsulated semiconductor device of the second example has a die pad that is thin in the same manner as the lead portion and aligned on the same plane as the lead portion in the first example. 119 is arranged.
The size of the die pad 119 is preferably smaller than the semiconductor chip 120 in terms of warpage.
As described above, the form without the die pad is preferable in terms of the balance of both sides of the semiconductor chip against the warp than the form with the die pad.
On the other hand, for a temperature change test of a wiring board (a test repeated at a temperature of −55 ° C. to 150 ° C.), the form with a die pad is preferable to the form without a die pad.
In the case of having a die pad, the distance between the die pad and the external terminal becomes a moment of deformation, and the distance between the external terminals is shorter than that of the resin-encapsulated semiconductor device without the die pad, so that the deformation becomes small.
Although not explicitly shown in FIG. 3A, in the second example, the semiconductor chip 120 is fixed to the die pad 119 and the lead portion 112 with a die attach agent.
Except for the die pad 119, it is the same as the first example, and the plan view seen from the B1 side in FIG.
This is the same as the plan view of the first example shown in FIG.
A description of each part is omitted.
In the second example shown in FIG. 3A, the die pad 119 holds only the center region of the back surface that is not the terminal surface of the semiconductor chip 120. However, as a modification, a semiconductor chip as shown in FIG. The form which hold | maintains the whole back surface of 120 is also mentioned.
As described above, FIG. 12A is a schematic cross-sectional view showing a modification of the third example of the embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. It is the figure seen through from the G1 side of Fig.12 (a).
As shown in FIG. 3B, the resin-encapsulated semiconductor device of Reference Embodiment 1 is a two-sided type semiconductor in which terminals 121 are arranged along two sides in the first example. Instead of the chip 120, a one-sided semiconductor chip 120A having a center arrangement in which terminals are arranged in a line at the center of the semiconductor chip is used.
Although not shown in the plan view from the C1 side in FIG. 3B, the terminals of the center array and the lead portions 112 on both sides sandwiching the center array are connected by wire bonding.
In the case of this embodiment, since the wire bonding length is longer than in the first example, the tape 180 is disposed on the terminal surface side of the semiconductor chip in order to cope with the dripping of the bonding wire 130.
Others are the same as those in the first example, and a description of each part is omitted.
As shown in FIG. 3C, the resin-encapsulated semiconductor device of Reference Embodiment 2 is made thin in the same manner as the lead portion in the third example, and is aligned on the same plane as the lead portion. A die pad 119 is provided.
Although the plan view seen from the D1 side in FIG. 3C is not shown, the terminals of the center array and the lead portions 112 on both sides sandwiching the center array are connected by wire bonding.
The size of the die pad 119 is preferably smaller than the semiconductor chip 120 in terms of warpage.
Others are the same as the third example.
In addition, in the fourth example shown in FIG. 3C, the die pad 119 holds only the center region of the back surface that is not the terminal surface of the semiconductor chip 120. However, as a modified example, the modified example of the second example is used. As shown in FIG. 12, there is a form in which the entire back surface of the semiconductor chip 120 is held as shown in FIG.

次に、本発明の樹脂封止型半導体装置の実施の形態の第３の例を、図４に基づいて説明する。
第３の例の樹脂封止型半導体装置は、第１の例と同様の端子部材を用い、第１の例と同様にして、半導体チップ１２０を複数の端子部材１１０のリード部１１２のエッチング形成された面であるエッチング面（１１２ａに相当）上まで延設して配し、且つ、半導体チップ１２０と所定の端子部材１１０とを電気的に接続し、樹脂封止している、ＳＯＮタイプの樹脂封止型半導体装置で、半導体チップ１２０は、その両面の封止用樹脂１４０の厚さを等しく揃えて、配設されている。
ここでも、各端子部材１１０の、非エッチング面（端子面１１１ｂに相当）側と外部端子部の外側側面（端子面１１１ａ、１１１ｃに相当）とを、露出させ、端子部材１１０の厚さにして樹脂封止している。
特に、第３の例は、半導体チップ１２０の端子部に接続用のはんだバンプを設けて、バンプ接続により半導体チップ１２０をリード部１１２に搭載し、半導体チップ１２０と端子部１１０とを電気的に接続したものであり、ここでも、半導体チップ１２０が厚さ方向の真ん中に位置している。
ここでは、バンプ接続により、半導体チップ１２０は端子部材１１０に固定される。
バンプ接続部するために要する厚さをｔ２とすれば、半導体チップ１２０の厚さをＴ０、前記端子部材の厚さをｔ０、端子部材１１０の薄肉のリード部１１２の厚さをｔ１とした場合、ｔ０＞Ｔ０で、且つ、
ｔ１＝［（１／２）×（ｔ０−Ｔ０）］- ｔ２
となる。
第３の例においても、半導体チップ１２０を、パッケージの厚さ方向で中央に位置させることにより、半導体チップ１２０の両面での使用される部材の体積量を含めた部材の平均熱膨張のバランスがとれ、反りが発生しづらいものとしている。
本例でも、１７×１０-6の熱膨張係数のＣｕ材からなる端子部材１１０を用いて、且つ、封止用樹脂の熱膨張率と端子部材の熱膨張率を等しくしており、より半導体チップの両面での使用される部材の体積量を含めた部材の平均熱膨張のバランスがとれ、一層反りが発生しづらいものとしている。
本例も、第１の例と同様に、サポートバー１６０、１６０Ａを備えており、全体をより強固にしている。
尚、図示していないが、ここでは、図４（ｂ）の一点鎖線Ｅ５−Ｅ６ーＥ７−Ｅ８におけるサポートバーの断面は、図１（ｃ）に示す第１の例の場合と同じである。
他は、第１の例と同じで、各部についての説明は省く。 Next, a third example of the embodiment of the resin-encapsulated semiconductor device of the present invention will be described with reference to FIG.
The resin-encapsulated semiconductor device of the third example uses the same terminal member as in the first example, and the semiconductor chip 120 is formed by etching the lead portions 112 of the plurality of terminal members 110 in the same manner as in the first example. A SON type that extends over the etched surface (corresponding to 112a), and is electrically connected to the semiconductor chip 120 and a predetermined terminal member 110 and sealed with resin. In the resin-encapsulated semiconductor device, the semiconductor chip 120 is arranged with the same thickness of the sealing resin 140 on both sides.
Also here, the non-etched surface (corresponding to the terminal surface 111b) side and the outer side surface (corresponding to the terminal surfaces 111a and 111c) of each terminal member 110 are exposed, and the thickness of the terminal member 110 is set. Resin sealed.
In particular, in the third example , a solder bump for connection is provided on the terminal portion of the semiconductor chip 120, the semiconductor chip 120 is mounted on the lead portion 112 by bump connection, and the semiconductor chip 120 and the terminal portion 110 are electrically connected. Here, the semiconductor chip 120 is located in the middle of the thickness direction.
Here, the semiconductor chip 120 is fixed to the terminal member 110 by bump connection.
When the thickness required for the bump connection portion is t2, the thickness of the semiconductor chip 120 is T0, the thickness of the terminal member is t0, and the thickness of the thin lead portion 112 of the terminal member 110 is t1. T0> T0 and
t1 = [(1/2) × (t0−T0)] − t2
It becomes.
Also in the third example , by positioning the semiconductor chip 120 at the center in the thickness direction of the package, the balance of the average thermal expansion of the members including the volume of the members used on both surfaces of the semiconductor chip 120 can be balanced. It is assumed that warping is difficult to occur.
Also in this example, the terminal member 110 made of a Cu material having a thermal expansion coefficient of 17 × 10 −6 is used, and the thermal expansion coefficient of the sealing resin and the thermal expansion coefficient of the terminal member are made equal to each other. The average thermal expansion of the member including the volume of the member to be used on both sides of the chip is balanced, and warpage is less likely to occur.
Similar to the first example, this example also includes support bars 160 and 160A, which further strengthens the whole.
Although not shown in the figure, here, the cross section of the support bar taken along one-dot chain line E5-E6-E7-E8 in FIG. 4B is the same as that in the first example shown in FIG. .
Others are the same as those in the first example, and a description of each part is omitted.

第１の例、第２の例、参考実施形態例１、参考実施形態例２、第３の例の樹脂封止型半導体装置は、それぞれ、同サイズのものを複数個を、例えば４個を、積層して、積層型樹脂封止型半導体装置として用いられる。
この場合、第１の例の樹脂封止型半導体装置は、図５のように積層され、参考実施形態例１の樹脂封止型半導体装置は、例えば、図６のように積層される。
これらの積層型樹脂封止型半導体装置の場合、それぞれ、上側の樹脂封止型半導体装置の下側の外部端子部の端子面と、下側の樹脂封止型半導体装置の上側の外部端子部の端子面とを、重ね合せて、半田ペースト１９０を介して電気的に接続している。
また、例えば、図７に示すように、同サイズの、参考実施形態例１の樹脂封止型半導体装置、第１の例の樹脂封止型半導体装置とを用いて、これらを重ね、積層型樹脂封止型半導体装置として用いられる。
尚、図示していないが、上記のような積層型樹脂封止型半導体装置において、個々に樹脂封止型半導体装置を逆にして積層する形態も挙げられる。
あるいはまた、例えば、図示してはいないが、第１の例、参考実施形態例１の樹脂封止型半導体装置の、異サイズのものを重ね、積層型樹脂封止型半導体装置として用いられる。
尚、上記において、半田ペースト１９０による接続に代え、半田ボールによる接続としても良い。 The resin-encapsulated semiconductor devices of the first example , the second example, the reference embodiment example 1, the reference embodiment example 2, and the third example each have a plurality of, for example, four pieces of the same size. These are laminated and used as a laminated resin-encapsulated semiconductor device.
In this case, the resin-encapsulated semiconductor device of the first example is stacked as shown in FIG. 5, and the resin-encapsulated semiconductor device of Reference Embodiment Example 1 is stacked as shown in FIG. 6, for example.
In the case of these laminated resin-encapsulated semiconductor devices, the terminal surface of the lower external terminal portion of the upper resin-encapsulated semiconductor device and the upper external terminal portion of the lower resin-encapsulated semiconductor device, respectively. These terminal surfaces are overlapped with each other and electrically connected via a solder paste 190.
Further, for example, as shown in FIG. 7, the resin-encapsulated semiconductor device of Reference Embodiment Example 1 and the resin-encapsulated semiconductor device of the first example having the same size are stacked and stacked. Used as a resin-encapsulated semiconductor device.
In addition, although not shown in the drawings, in the above-described laminated resin-encapsulated semiconductor device, a form in which the resin-encapsulated semiconductor devices are laminated in an inverted manner is also included.
Alternatively, for example, although not shown, the resin-encapsulated semiconductor devices of the first example and reference embodiment example 1 are stacked with different sizes and used as a laminated resin-encapsulated semiconductor device.
In the above, instead of the connection by the solder paste 190, the connection by a solder ball may be used.

更に、例えば、図８（ａ）に示すように、同サイズの、８個の第１の例の樹脂封止型半導体装置４０１〜４０８を用いて、横方向に２個を互いに同じにして、その側面同士を合せて電気的に接続したものを更に４層重ねした構造の積層型樹脂封止型半導体装置も挙げられる。
接続される側面同士は導電性ペーストにより接続される。
図８（ｂ）に示すように、半導体装置４０１の半導体チップ１２０と半導体装置４０５の半導体素子１２０Ｍは互いに各機能ピン（端子）を逆に、ミラーイメージで配置しているもので、半導体チップ１２０Ｍは半導体チップ１２０のミラーチップとも言う。
尚、図示していないが、横方向に２個を互いに向きを逆にして、その側面同士を合せて電気的に接続したものを更に４層重ねした構造の積層型樹脂封止型半導体装置も挙げられる。
この場合、各外部端子部については、側面同士の接続、ワイヤボンディング接続は回路的に問題のないようにする。
丸印１〜丸印８は機能ピン（端子）を示すものであり、同じ数のものは同じ機能を示す。
例えば、図１２（ｂ）において、丸印１を電源端子、丸印２をセレクトスイッチ端子、丸印３〜丸印７をＩ／Ｏ端子、丸印８をグランド端子とする。
尚、重ねる樹脂封止型半導体装置の層数としては、４層に限定はされない。
また、第１の例、第２の例、参考実施形態例１、参考実施形態例２、第３の例の樹脂封止型半導体装置の３つ以上を互いにその側面同士を合せて電気的に接続したものも挙げられ、更に、これを２層以上にしたものも挙げられる。
更に、上記のものに、上下の樹脂封止型半導体装置の側面を接続用に用いる形態を併用したものも挙げられる。 Further, for example, as shown in FIG. 8 (a), using the eight resin-encapsulated semiconductor devices 401 to 408 of the first example of the same size, the two are made the same in the lateral direction, A laminated resin-encapsulated semiconductor device having a structure in which four layers of those whose side surfaces are electrically connected to each other are stacked is also included.
The side surfaces to be connected are connected by a conductive paste.
As shown in FIG. 8 (b), the semiconductor chip 120 of the semiconductor device 401 and the semiconductor element 120M of the semiconductor device 405 are obtained by disposing the respective functional pins (terminals) in a mirror image in reverse, and the semiconductor chip 120M. Is also called a mirror chip of the semiconductor chip 120.
Although not shown, there is also a laminated resin-encapsulated semiconductor device having a structure in which two laterally oriented ones are reversed in direction and their side surfaces are aligned and electrically connected to each other to further stack four layers. Can be mentioned.
In this case, for each external terminal portion, the connection between the side surfaces and the wire bonding connection should not cause a problem in terms of circuit.
Circle marks 1 to 8 indicate function pins (terminals), and the same number indicates the same function.
For example, in FIG. 12B, circle 1 is a power supply terminal, circle 2 is a select switch terminal, circles 3 to 7 are I / O terminals, and circle 8 is a ground terminal.
Note that the number of layers of the resin-encapsulated semiconductor device to be stacked is not limited to four.
Further, three or more of the resin-encapsulated semiconductor devices of the first example , the second example, the reference embodiment example 1, the reference embodiment example 2, and the third example are electrically connected to each other with their side surfaces aligned with each other. Examples include a connected one, and further, two or more layers.
Furthermore, what combined the form which uses the side surface of an upper and lower resin-encapsulated semiconductor device for a connection to the above thing is also mentioned.

次いで、第１の例の樹脂封止型半導体装置の製造方法の１例を、図９に基づいて、説明する。
先ず、加工用素材２１０の両面に所定形状にレジスト２２０を配設し（図９（ａ））、１つの樹脂封止型半導体装置の各端子部材とサポートバーの配置に対応した、端子部材とサポートバーの配置を１単位として、この配置状態に、エッチング技術を用いたエッチング加工法にて、両面からエッチングを行い、端子部材２３０と図示していないサポートバーの延設部分１６５（図１の１６５）とを、支持部２３５にて連結した状態で、面付けして形成する。（図９（ｂ））
ここでのエッチング加工工程は、端子部材の薄肉のリード部の厚さをｔ１、半導体チップの厚さをＴ０、前記端子部材の厚さをｔ０とした場合、ｔ０＞Ｔ０で、且つ、ｔ１を（１／２）×（ｔ０−Ｔ０）以下の所望の厚さになるように、エッチング量を調整して行うものである。
例えば、端子部材のリード部（図１の１１２）の薄肉部を形成する側のエッチング量を、反対側より大きくなるように調整してエッチング加工を行う。
具体的には、加工用素材２１０の両面のエッチング時間に差をつけたり、エッチングスプレー圧を調整する。
尚、通常、支持部２３５として、枠状のもの（フレームとも言う）が用いられる。
エッチング加工時には、支持部２３５に、端子部材２３０と図示していないサポートバー（図１の１６０、１６０Ａ）は支持される。
これにより、１つの樹脂封止型半導体装置の端子部材とサポートバーの配置に対応した、端子部材とサポートバーの配置を１単位として、これが支持部２３５にて連結され面付けされた、加工シート２１０Ａを得る。
加工用素材２１０としては、ここではＣｕ材を用いるが、これに限定はされない。
Ｃｕ系合金、４２合金（Ｎｉ４２％−Ｆｅ合金）等も適用できる。
エッチング液としては、塩化第二鉄溶液が用いられる。
また、レジスト２２０としては、耐エッチング性のもので、所望の解像性を有し、処理性の良いものであれば特に限定はされない。 Then, one example of a method of manufacturing a resin-sealed semiconductor device of the first embodiment, based on FIG. 9, described.
First, resists 220 are arranged in a predetermined shape on both surfaces of the processing material 210 (FIG. 9A), terminal members corresponding to the arrangement of each terminal member and support bar of one resin-encapsulated semiconductor device, With the arrangement of the support bar as one unit, in this arrangement state, etching is performed from both sides by an etching method using an etching technique, and the terminal member 230 and the extended portion 165 of the support bar (not shown) (see FIG. 1) 165) in the state of being connected by the support portion 235. (Fig. 9 (b))
In this etching process, when the thickness of the thin lead portion of the terminal member is t1, the thickness of the semiconductor chip is T0, and the thickness of the terminal member is t0, t0> T0 and t1 This is performed by adjusting the etching amount so as to obtain a desired thickness of (1/2) × (t0−T0) or less.
For example, the etching process is performed by adjusting the etching amount on the side where the thin portion of the lead portion (112 in FIG. 1) of the terminal member is formed to be larger than the opposite side.
Specifically, the etching time on both surfaces of the processing material 210 is differentiated or the etching spray pressure is adjusted.
Normally, a frame-like member (also called a frame) is used as the support portion 235.
During the etching process, the support member 235 supports the terminal member 230 and the support bars (not shown) (160 and 160A in FIG. 1).
As a result, a processed sheet in which the arrangement of the terminal member and the support bar corresponding to the arrangement of the terminal member and the support bar of one resin-encapsulated semiconductor device is taken as one unit and is connected and faced by the support portion 235. 210A is obtained.
Although the Cu material is used here as the processing material 210, it is not limited thereto.
A Cu-based alloy, 42 alloy (Ni42% -Fe alloy), etc. can also be applied.
As the etching solution, a ferric chloride solution is used.
The resist 220 is not particularly limited as long as it is resistant to etching, has a desired resolution, and has good processability.

次いで、レジスト２２０を除去後、洗浄処理等を施し、全面に接続用の表面めっきを施した（図示していない）後、面付け形成され、表面めっきが施された加工シート２１０Ａのエッチング面側ではない側を平板状の多孔板２４０にて真空引きし、加工シート２１０Ａを多孔板２４０に密着させた状態で（図９（ｃ））、面付け分の数だけ、半導体チップ２５０を所定の位置に位置決めして、その端子面側ではない裏面を真空引き用の多孔板２４０にて真空引きして、該多孔板２４０に搭載し、この状態で、各半導体チップ２５０について、その端子（図１の１２１に相当）と端子部材２３０の内部端子部（図１の１１２に相当）のエッチング面である端子面とをワイヤボンディング接続する。（図９（ｄ）） 尚、真空ポンプ、真空配管等、真空引き用の多孔板２４０の真空引き源は別にあるが、ここでは図示していない。
次いで、多孔板２４０を外し、これに代え、モールド用のテープ２７０、２７１を、加工シート２１０Ａの両面に、それぞれ、各面を覆うように、平面状に貼り、半導体チップ２５０の裏面をテープ２７０にて貼り固定、表裏をモールド固定用の平板（図示していない）にて挟み、加工シート２１０Ａ全体について、一括してモールドを行い、表裏のモールド固定用の平板を取り外す。（図９（ｅ））
尚、加工シート２１０Ａの端子部材２３０を支持する支持部２３５は、通りぬけ孔等を設けたもので、モールドの際、各面付け間モールド用の樹脂が通りぬけできるような形状になっている。
次いで、モールド用のテープ２７０、２７１を剥がし、切断用のテープ２７５を貼り（図９（ｆ））、該切断用のテープ２７５とは反対側からダイシングソー（図示していない）にて切断して（図９（ｇ））、樹脂封止型半導体装置を１個ずつに個片化して得る。（図９（ｈ））
ダイシングソー（図示していない）による切断は、（図９（ｇ））に示すように、凹部２３７とは反対側にて行うもので、この部分は加工用素材の厚さより薄肉で、容易に切断できるものとしている。
ダイシングソー（図示していない）による切断状態は、例えば、図１１（ａ）や、図１１（ｂ）のようになる。
尚、サポートバー（図１の１６０、１６０Ａ）の延設部分（図１の１６５）を切断するラインが加工シートの長手方向の切断ラインである。
尚、図１１において、単位の樹脂封止型半導体装置３０１は、切断ライン３８５にて互いに分けられる各領域であり、ここでは、説明を分かり易くするため図示していないが、図９の支持部２３５を凹部２３７とは反対側で切断する。
また、この切断面が、作製される樹脂封止型半導体装置の外部端子の外側側面となる。 尚、切り欠け部２３７Ａの切断された面でない面には接続用のめっきが配設されておりこの部分は接続用に利用し易い。
このようにして、図１に示す第１の例の樹脂封止型半導体装置は製造することができる。 Next, after removing the resist 220, a cleaning process or the like is performed, and a surface plating for connection is performed on the entire surface (not shown). Then, the processed sheet 210A is surface-plated and surface-plated. The side that is not is evacuated with a flat plate-like porous plate 240, and the processed sheet 210A is in close contact with the porous plate 240 (FIG. 9C), and the semiconductor chip 250 is a predetermined number of impositions. Positioned at the position, the back surface that is not the terminal surface side is evacuated by the perforated plate 240 for evacuation and mounted on the perforated plate 240. In this state, each semiconductor chip 250 has its terminal (see FIG. 1) and a terminal surface which is an etching surface of an internal terminal portion (corresponding to 112 in FIG. 1) of the terminal member 230 is connected by wire bonding. (FIG. 9D) Although there are other vacuum sources for the vacuum plate, such as a vacuum pump and a vacuum pipe, they are not shown here.
Next, the porous plate 240 is removed, and instead of this, molding tapes 270 and 271 are attached to both surfaces of the processed sheet 210A in a flat shape so as to cover each surface, and the back surface of the semiconductor chip 250 is attached to the tape 270. The front and back surfaces are sandwiched between mold fixing flat plates (not shown), the entire processed sheet 210A is molded in a lump, and the front and back mold fixing flat plates are removed. (Fig. 9 (e))
The support portion 235 that supports the terminal member 230 of the processed sheet 210A is provided with a through hole or the like, and has a shape that allows the resin for molding between impositions to pass through during molding. .
Next, the mold tapes 270 and 271 are peeled off, and a cutting tape 275 is attached (FIG. 9F), and cut with a dicing saw (not shown) from the side opposite to the cutting tape 275. (FIG. 9 (g)), the resin-encapsulated semiconductor devices are obtained as individual pieces. (Fig. 9 (h))
Cutting with a dicing saw (not shown) is performed on the side opposite to the recess 237, as shown in FIG. 9 (g), and this part is thinner than the thickness of the processing material and can be easily It can be cut.
The cutting state by a dicing saw (not shown) is, for example, as shown in FIG. 11 (a) or FIG. 11 (b).
A line for cutting the extended portion (165 in FIG. 1) of the support bar (160, 160A in FIG. 1) is a cutting line in the longitudinal direction of the processed sheet.
In FIG. 11, the unit resin-sealed semiconductor device 301 is a region separated from each other by a cutting line 385, and is not shown here for ease of explanation, but the support portion of FIG. 9. 235 is cut on the side opposite to the recess 237.
Further, this cut surface becomes the outer side surface of the external terminal of the resin-encapsulated semiconductor device to be manufactured. Note that a plating for connection is provided on the surface of the cutout portion 237A that is not the cut surface, and this portion is easily used for connection.
In this way, the resin-encapsulated semiconductor device of the first example shown in FIG. 1 can be manufactured.

次いで、第１の例の樹脂封止型半導体装置の製造方法の別の１例（第２の例）を、図１０に基づいて、説明する。
先ず、加工用素材３１０の両面に所定形状にレジスト３２０を配設し（図１０（ａ））、１つの樹脂封止型半導体装置の各端子部材とサポートバーの配置に対応した、端子部材とサポートバーの配置を１単位として、この配置状態に、エッチング技術を用いたエッチング加工法にて、両面からエッチングを行い、端子部材３３０と図示していないサポートバーの延設部分１６５（図１の１６５）とを、支持部３３５にて連結した状態で、面付けして形成する。（図１０（ｂ））
図９に示す第１の例の場合と同様にして、加工用素材の両面のエッチング量に差を付けてエッチング加工を行う。
これにより、１つの樹脂封止型半導体装置の端子部材、サポートバーの配置に対応した、端子部材とサポートバーの配置を１単位として、これが支持部３３５にて連結され面付けされた、加工シート３１０Ａを得る。
次いで、レジスト３２０を除去後、洗浄処理等を施し、全面に接続用の表面めっきを施した（図示していない）後、面付け形成され、表面めっきが施された加工シート３１０Ａのエッチング面側ではない側を覆うようにモールド用のテープ３４０を貼り（図１０（ｃ））、面付け分の数だけ、半導体チップ３５０を所定の位置に位置決めして、その端子面側ではない裏面を前記テープ３４０に貼り付け搭載し、
この状態で、各半導体チップについて、その端子と端子部材の内部端子部の端子面とをワイヤボンディング接続する。（図１０（ｄ））
次いで、モールド用のテープ３４１を、加工シート３１０Ａの前記テープ３４０とは反対側の面に、覆うように、平面状に貼り、半導体チップ３５０の裏面をテープ３４０にて貼り固定した状態で、表裏を、それぞれ、テープ３４０、３４１を介して、モールド固定用の平板３７１、３７２にて挟み、加工シート３１０Ａ全体について、一括してモールドを行う。（図１０（ｅ））
ここでは、半導体チップ３５０を所定の位置に位置決めする際のテープをそのままモールド用のテープとして使用している。
次いで、表裏のモールド固定用の平板３７１、３７２を除去し（図１０（ｆ））、更にテープ３４０、３４１を除去し、切断用のテープ３４５を貼り（図１０（ｇ））、該切断用のテープ３４５とは反対側からダイシングソー（図示していない）にて切断して（図１０（ｈ））、樹脂封止型半導体装置を１個ずつに個片化して得る。（図１０（ｉ））
尚、図１０に示す製造方法においても、各工程の処理、各部材等は、基本的に、図９に示す製造方法に準じるもので、ここでは、説明を省いている。
このようにして、図１に示す第１の例の樹脂封止型半導体装置は製造することができる。 Next, another example (second example) of the method for manufacturing the resin-encapsulated semiconductor device of the first example will be described with reference to FIG.
First, resists 320 are arranged in a predetermined shape on both surfaces of the processing material 310 (FIG. 10A), terminal members corresponding to the arrangement of each terminal member and support bar of one resin-encapsulated semiconductor device, With the arrangement of the support bar as one unit, in this arrangement state, etching is performed from both sides by an etching method using an etching technique, and the terminal member 330 and the extended portion 165 of the support bar (not shown) (see FIG. 1) 165) are attached to each other in a state where they are connected by the support portion 335. (Fig. 10 (b))
In the same manner as in the case of the first example shown in FIG. 9, the etching process is performed with a difference in the etching amount on both surfaces of the processing material.
As a result, the processed sheet in which the arrangement of the terminal member and the support bar corresponding to the arrangement of the terminal member and the support bar of one resin-encapsulated semiconductor device is taken as one unit and is connected and faced by the support portion 335. 310A is obtained.
Next, after removing the resist 320, a cleaning process or the like is performed, and a surface plating for connection is performed on the entire surface (not shown), and then an imposition surface is formed and the etched surface side of the processed sheet 310A subjected to the surface plating is applied. A tape 340 for molding is applied so as to cover the non-side (FIG. 10C), the semiconductor chip 350 is positioned at a predetermined position by the number of impositions, and the back surface that is not the terminal surface side is placed on the back surface. Affixed to tape 340 and mounted
In this state, for each semiconductor chip, the terminal and the terminal surface of the internal terminal portion of the terminal member are connected by wire bonding. (Fig. 10 (d))
Next, the molding tape 341 is applied in a planar shape so as to cover the surface of the processed sheet 310A opposite to the tape 340, and the back surface of the semiconductor chip 350 is attached and fixed with the tape 340. Are sandwiched between flat plates 371 and 372 for fixing the mold via tapes 340 and 341, respectively, and the entire processed sheet 310A is molded collectively. (Fig. 10 (e))
Here, the tape for positioning the semiconductor chip 350 at a predetermined position is used as it is as a tape for molding.
Next, the front and back mold fixing flat plates 371 and 372 are removed (FIG. 10 (f)), the tapes 340 and 341 are further removed, and a cutting tape 345 is attached (FIG. 10 (g)). From the side opposite to the tape 345, a dicing saw (not shown) is used to cut (FIG. 10H), and the resin-encapsulated semiconductor devices are obtained individually. (Fig. 10 (i))
In the manufacturing method shown in FIG. 10 as well, the processing of each step, each member, and the like are basically the same as those in the manufacturing method shown in FIG. 9, and a description thereof is omitted here.
In this way, the resin-encapsulated semiconductor device of the first example shown in FIG. 1 can be manufactured.

上記、図９、図１０に示す第１の例の樹脂封止型半導体装置の製造方法における各処理工程は、いずれも、第２の例の樹脂封止型半導体装置、参考実施形態例１、参考実施形態例２の樹脂封止型半導体装置の製造にもそのまま適用できるもので、第２の例、参考実施形態例１、参考実施形態例２の各樹脂封止型半導体装置は、上記図９、図１０に示す製造方法において、前記加工用シート（２１０Ａ，３１０Ａに相当）を、各半導体装置に対応した、所定の加工シートに代え、且つ、樹脂封止する前に、半導体チップの表面（端子面）側に、テープを介して、サポートバーあるいは連結部を固定する、テープ貼り付け工程を付け加えれば良く、ここでは、これらの製造方法の詳細な説明は省く。
また、第３の例の樹脂封止型半導体装置を作製する場合には、図９、図１０に示す樹脂封止型半導体装置の製造方法において、その半導体チップの搭載、ワイヤボンディングに代え、バンプ接続により半導体チップをリード部に、接続固定すればよい。 Each of the processing steps in the method for manufacturing the resin-encapsulated semiconductor device of the first example shown in FIGS. 9 and 10 is the same as the resin-encapsulated semiconductor device of the second example, Reference Embodiment Example 1, as it can be applied as it is to manufacture a resin-sealed semiconductor device of reference embodiment 2, the second example, reference embodiment 1, each resin-sealed semiconductor device of reference embodiment 2, FIG 9. In the manufacturing method shown in FIG. 10, the processing sheet (equivalent to 210A, 310A) is replaced with a predetermined processing sheet corresponding to each semiconductor device, and the surface of the semiconductor chip is sealed before resin sealing. What is necessary is just to add the tape sticking process which fixes a support bar or a connection part via a tape on the (terminal surface) side, and omits detailed description of these manufacturing methods here.
In the case of manufacturing a resin-sealed semiconductor device of the third example, FIG. 9, in the manufacturing method of the tree Aburafutome type semiconductor device shown in FIG. 10, mounting the semiconductor chip, instead of the wire bonding, The semiconductor chip may be connected and fixed to the lead portion by bump connection.

尚、本発明の樹脂封止型半導体装置は、上記の第１の例〜第３の例に限定されない。
例えば、第１の例〜第３の例において、半導体チップの端子面側の樹脂部表面に、窪みを設けて、半導体チップの表裏の封止用樹脂の厚さを調整して、反りが発生しづらいようにする形態も挙げられる。
窪みとしては、円柱状、あるいは、矩形柱状の窪みが挙げられるがこれに限定はされない。
大きさは、ワイヤ、インナーリード、サポートバー等に当たらぬサイズで、その深さは、通常、半導体チップの端子面側の樹脂部表面から半導体チップの端子面までの厚さの半分以下とする。 The resin-encapsulated semiconductor device of the present invention is not limited to the first to third examples .
For example, in the first to third examples , warpage occurs by providing a recess in the resin part surface on the terminal surface side of the semiconductor chip and adjusting the thickness of the sealing resin on the front and back of the semiconductor chip. There is also a form that makes it difficult to do.
Examples of the depression include a cylindrical or rectangular columnar depression, but are not limited thereto.
The size is a size that does not hit the wire, inner lead, support bar, etc., and the depth is usually less than half of the thickness from the resin part surface on the terminal surface side of the semiconductor chip to the terminal surface of the semiconductor chip. .

図１（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第１の例を示した概略断面図で、図１（ｂ）は図１（ａ）のＡ１側から透視してみた図で、図１（ｃ）は、図１（ｂ）の一点鎖線Ａ５−Ａ６ーＡ７−Ａ８におけるサポートバーの断面を示した図である。FIG. 1A is a schematic cross-sectional view showing a first example of an embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 1B is seen through from the A1 side of FIG. FIG. 1C is a diagram showing a cross section of the support bar taken along one-dot chain line A5-A6-A7-A8 in FIG. 1B. 図２（ａ）は端子部材の断面図で、図２（ｂ）は図１（ａ）のＢ１側から見た図で、図２（ｃ）は図２（ａ）のＢ２側からみた図で、図２（ｄ）は図２（ｄ）のＢ３側からみた図である。2A is a cross-sectional view of the terminal member, FIG. 2B is a view seen from the B1 side in FIG. 1A, and FIG. 2C is a view seen from the B2 side in FIG. FIG. 2D is a view from the B3 side of FIG. 図３（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第２の例を示した概略断面図で、図３（ｂ）は本発明の樹脂封止型半導体装置の参考実施形態例１を示した概略断面図で、図３（ｃ）は本発明の樹脂封止型半導体装置の参考実施形態例２を示した概略断面図である。FIG. 3A is a schematic sectional view showing a second example of the embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 3B is a reference implementation of the resin-encapsulated semiconductor device of the present invention. a schematic sectional view showing an embodiment 1, FIG. 3 (c) is a schematic sectional view showing a reference embodiment 2 of resin-encapsulated semiconductor device of the present invention. 図４（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第３の例を示した概略断面図で、図４（ｂ）は図４（ａ）のＥ１側から透視してみた図である。FIG. 4A is a schematic cross-sectional view showing a third example of the embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 4B is seen through from the E1 side of FIG. FIG. 本発明の積層型樹脂封止型半導体装置の実施の形態の第１の例の断面図である。It is sectional drawing of the 1st example of embodiment of the lamination type resin sealing type | mold semiconductor device of this invention. 本発明の積層型樹脂封止型半導体装置の参考実施形態例１の断面図である。It is sectional drawing of the reference embodiment example 1 of the lamination type resin sealing type | mold semiconductor device of this invention. 本発明の積層型樹脂封止型半導体装置の参考実施形態例２の断面図である。It is sectional drawing of the reference embodiment example 2 of the lamination type resin sealing type semiconductor device of this invention. 図８（ａ）は本発明の積層型樹脂封止型半導体装置の実施の形態の第２の例の断面図で、図８（ｂ）は図８（ａ）のＥ１側からみた図である。FIG. 8A is a cross-sectional view of a second example of the embodiment of the laminated resin-encapsulated semiconductor device of the present invention, and FIG. 8B is a view seen from the E1 side of FIG. 8A. . 図９（ａ）〜図９（ｈ）は本発明に関わる樹脂封止型半導体装置の製造方法の参考実施形態例１の製造工程断面図である。Figure 9 (a) ~ FIG 9 (h) are cross sectional view of a manufacturing process of Reference Embodiment 1 of a method for manufacturing a resin-sealed semiconductor device according to the present onset bright. 図１０（ａ）〜図１０（ｉ）は本発明に関わる樹脂封止型半導体装置の製造方法の参考実施形態例１の製造工程断面図である。Figure 10 (a) ~ FIG 10 (i) are cross sectional view of a manufacturing process of Reference Embodiment 1 of the manufacturing method of the tree Aburafutome type semiconductor device according to the present onset bright. 図１１（ａ）、１１（ｂ）はダイシングソーによる切断状態を示した図である。FIGS. 11A and 11B are views showing a cutting state by a dicing saw. 図１２（ａ）は本発明の樹脂封止型半導体装置の実施の形態の第２の例の変形例を示した概略断面図で、図１２（ｂ）は図１２（ａ）のＧ１側から透視してみた図である。FIG. 12A is a schematic cross-sectional view showing a modification of the second example of the embodiment of the resin-encapsulated semiconductor device of the present invention, and FIG. 12B is from the G1 side of FIG. It is the figure seen through.

符号の説明Explanation of symbols

１０１〜１０４ 樹脂封止型半導体装置
１０１ａ〜１０４ａ 樹脂封止型半導体装置
１０１ｂ〜１０４ｂ 樹脂封止型半導体装置
１１０ 端子部材
１１１ 外部端子部
１１１ａ、１１１ｂ、１１１ｃ 端子面
１１２ リード部（単にリードとも言う）
１１２ａ 端子面（エッチング面でもある）
１１４ 切り欠け部
１１６ 先端部
１１６Ｓ （先端の）側面
１１７ グルーブ（溝部）
１１８ 孔状凹部
１１９ ダイパッド
１２０、１２０Ａ、１２０Ｍ 半導体チップ（半導体素子とも言う）
１２１ 端子
１２１Ａ バンプ接続部（はんだ部）
１３０ ボンディングワイヤ
１４０ 封止用樹脂
１６０、１６０Ａ サポートバー
１６１ａ，１６２ａ 薄肉部
１６２ 厚肉部
１６５ 延設部分
１８０ テープ
１９０ 半田ペースト（導電性ペーストとも言う）
１９５ 基材
２１０ 加工用素材
２１０Ａ 加工シート
２２０ レジスト
２３０ 端子部材
２３１ 外部端子部
２３２ リード部（単にリードとも言う）
２３５ 支持部（連結部とも言う）
２３７ 凹部
２３７Ａ 切り欠け部
２４０ 平板状の多孔板（真空引き板とも言う）
２５０ 半導体チップ（半導体素子とも言う）
２６０ ボンディングワイヤ
２７０、２７１ （固定用、モールド用の）テープ
２７５ （ダイシング用の）テープ
２８０ 封止用樹脂
３０１ 単位の樹脂封止型半導体装置
３１０ 加工用素材
３１０Ａ 加工シート
３１５ 枠部
３１６ 治具孔
３１７ 長孔部
３２０ レジスト
３３０ 端子部材
３３５ 支持部（連結部とも言う）
３３７ 凹部
３３７Ａ 切り欠け部
３４０、３４１ （固定用、モールド用の）テープ
３４５ （切断用の）テープ
３５０ 半導体チップ（半導体素子とも言う）
３６０ ボンディングワイヤ
３７１、３７２ モールド固定用の平板
３８０ 封止用樹脂
３８５ 切断ライン
３８６ 切断目印（貫通孔あるいは窪み）
４０１〜４０８ 樹脂封止型半導体装置 101-104 Resin-sealed semiconductor devices 101a-104a Resin-sealed semiconductor devices 101b-104b Resin-sealed semiconductor device 110 Terminal member 111 External terminal portions 111a, 111b, 111c Terminal surface 112 Lead portion (also simply referred to as lead)
112a Terminal surface (also etched surface)
114 notch 116 tip 116S (tip) side surface 117 groove (groove)
118 Hole-shaped recess 119 Die pad 120, 120A, 120M Semiconductor chip (also referred to as semiconductor element)
121 Terminal 121A Bump connection part (solder part)
130 Bonding wire 140 Sealing resin 160, 160A Support bars 161a, 162a Thin portion 162 Thick portion 165 Extension portion 180 Tape 190 Solder paste (also referred to as conductive paste)
195 base material 210 processing material 210A processing sheet 220 resist 230 terminal member 231 external terminal portion 232 lead portion (also simply referred to as lead)
235 Supporting part (also called connecting part)
237 Concavity 237A Notch 240 Flat perforated plate (also referred to as vacuum drawing plate)
250 Semiconductor chip (also called semiconductor element)
260 Bonding wires 270, 271 Tape (for fixing and molding) 275 Tape 280 (for dicing) Sealing resin 301 Resin-encapsulated semiconductor device 310 unit processing material 310A Processing sheet 315 Frame portion 316 Jig hole 317 Long hole portion 320 Resist 330 Terminal member 335 Support portion (also referred to as connecting portion)
337 Recess 337A Notch 340, 341 Tape 345 (for fixing and molding) Tape 345 (for cutting) Semiconductor chip (also referred to as semiconductor element)
360 Bonding wires 371 and 372 Mold fixing flat plate 380 Sealing resin 385 Cutting line 386 Cutting mark (through hole or depression)
401 to 408 Resin-sealed semiconductor device

Claims (12)

外部回路と接続するための外部端子部と、半導体チップと接続するための内部端子部をその一部として含むリード部とを、一体的に連結してなる端子部材で、且つ、加工用素材から、外部端子部の少なくとも一部を加工用素材の厚さの厚肉にし、リード部を加工用素材の一面側からのエッチングにより薄肉としている端子部材、複数個と、半導体チップ１つとを、用いて、該複数の端子部材を一平面状にその向きを揃えて、半導体チップの周辺に沿って、外部端子部を外側に向けて、リード部を内側に向けて、配し、半導体チップを前記複数の端子部材のリード部のエッチング形成された面であるエッチング面上まで延設して配し、且つ、半導体チップと所定の端子部材とを電気的に接続し、樹脂封止している２辺パッドＳＯＮ型の樹脂封止型半導体装置であって、各端子部材の、エッチング面側でない非エッチング面側と外部端子部の外側側面とを、露出させ、前記端子部材の厚さにして樹脂封止しており、前記半導体チップは、その対向する２辺に接続用端子を配し、該２辺側にて、それぞれ、前記端子部材の内部端子部と電気的に接続され、且つ、その両面の封止用樹脂の厚さを等しく揃えて、配設されており、前記加工用素材をエッチングして前記端子部材を形成する際に形成された、電気的に独立して、全体を強固にするためのサポートバーを、前記２辺側でない側の、半導体チップの両側に配設しており、封止用樹脂の熱膨張率と端子部材の熱膨張率を等しくしていることを特徴とする樹脂封止型半導体装置。 An external terminal portion for connecting to an external circuit and a lead portion integrally including an internal terminal portion for connecting to a semiconductor chip as a part of the terminal member, and from a processing material , Using at least a part of the external terminal portion as thick as the material for processing, and a terminal member in which the lead portion is thinned by etching from one side of the material for processing, and one semiconductor chip, The plurality of terminal members are aligned in a single plane, and are arranged along the periphery of the semiconductor chip with the external terminal portion facing outward and the lead portion facing inward, The lead portions of the plurality of terminal members are extended and arranged on the etched surface, which is the etched surface, and the semiconductor chip and the predetermined terminal member are electrically connected and resin-sealed 2 side pads SON-type resin sealing A semiconductor device, for each of the terminal members, an outer side surface of the non-etched side and the external terminal portions not etched surface, is exposed, Ri Contact sealed with resin in the thickness of the terminal member, said semiconductor The chip is provided with connection terminals on two opposite sides thereof, electrically connected to the internal terminal portions of the terminal members on the two sides, respectively, and the thickness of the sealing resin on both sides thereof A support bar that is disposed when the processing material is etched to form the terminal member, and is electrically independent and to strengthen the whole. A resin-encapsulated semiconductor device, wherein the resin-encapsulated semiconductor device is disposed on both sides of the semiconductor chip on the side other than the two sides, and the thermal expansion coefficient of the sealing resin is equal to the thermal expansion coefficient of the terminal member. . 請求項１に記載の樹脂封止型半導体装置であって、端子部材は、Ｃｕ、Ｃｕ系合金、４２％Ｎｉ−Ｆｅ合金のいずれか１からなることを特徴とする樹脂封止型半導体装置。 2. The resin-encapsulated semiconductor device according to claim 1 , wherein the terminal member is made of any one of Cu, a Cu-based alloy, and a 42% Ni—Fe alloy. 請求項１ないし２のいずれか１項に記載の樹脂封止型半導体装置であって、リード部の先端の先端側面部、該先端側面部挟む先端の両側面部を、封止用樹脂と密着性のよい構造としていることを特徴とする樹脂封止型半導体装置。 3. The resin-encapsulated semiconductor device according to claim 1, wherein the tip side surface portion at the tip of the lead portion and the both side surfaces at the tip sandwiching the tip side surface portion are in close contact with the sealing resin. A resin-encapsulated semiconductor device characterized by having a good structure. 請求項３に記載の樹脂封止型半導体装置であって、前記封止用樹脂と密着性のよい構造は、リード部の先端の先端側面部、該先端側面部挟む先端の両側面部を、外側に向かい、パッケージ内側となるテーパ形状としているものであることを特徴とする樹脂封止型半導体装置。 4. The resin-encapsulated semiconductor device according to claim 3 , wherein the structure having good adhesion with the encapsulating resin has a tip side surface portion at the tip of the lead portion and both side surface portions at the tip sandwiching the tip side surface portion outside. A resin-encapsulated semiconductor device having a taper shape facing the inside of the package. 請求項３に記載の樹脂封止型半導体装置であって、前記封止用樹脂と密着性のよい構造は、リード部の先端の先端側面部、該先端側面部挟む先端の両側面部に、前記リード部のエッチング面に沿い、めっきによる庇を設けていることを特徴とする樹脂封止型半導体装置。 4. The resin-encapsulated semiconductor device according to claim 3 , wherein the sealing resin and the structure having good adhesiveness are provided on a tip side surface portion at a tip of a lead portion and on both side surface portions of a tip sandwiching the tip side surface portion. A resin-encapsulated semiconductor device, characterized by being provided with plating ridges along the etched surface of the lead portion. 請求項１ないし５のいずれか１項に記載の樹脂封止型半導体装置であって、前記端子部材には、その加工用素材面側に、溝（グルーブ）およびまたは孔状凹部を設けていることを特徴とする樹脂封止型半導体装置。 6. The resin-encapsulated semiconductor device according to claim 1 , wherein the terminal member is provided with a groove and / or a hole-like recess on the processing material surface side. A resin-encapsulated semiconductor device. 請求項１ないし６のいずれか１項に記載の樹脂封止型半導体装置であって、前記各端子部材の前記封止用樹脂表面と接する表面部に粗面化処理を施したことを特徴とする樹脂封止型半導体装置。 7. The resin-encapsulated semiconductor device according to claim 1 , wherein a roughening process is performed on a surface portion of each terminal member that is in contact with the encapsulating resin surface. Resin-encapsulated semiconductor device. 請求項７に記載の樹脂封止型半導体装置であって、前記粗面化処理により、最大高さ粗さＲｙ（ＪＩＳ Ｂ０６０１−１９９４）が、１μｍ〜２μｍの範囲であることを特徴とする樹脂封止型半導体装置。 A resin-sealed semiconductor device of the mounting serial to claim 7, by the roughening process, the maximum height roughness Ry (JIS B0601-1994), characterized in that in the range of 1μm~2μm Resin-sealed semiconductor device. 請求項１ないし８のいずれか１項に記載の樹脂封止型半導体装置であって、外部端子部の外側側面部に、切り欠け部を設けていることを特徴とする樹脂封止型半導体装置。 9. The resin-encapsulated semiconductor device according to claim 1 , wherein a notch portion is provided on an outer side surface portion of the external terminal portion. . 請求項１ないし９のいずれかに記載の樹脂封止型半導体装置の１つ以上を、複数、積層したもので、それぞれ、上側の樹脂封止型半導体装置の下側の外部端子部の端子面と、下側の樹脂封止型半導体装置の上側の外部端子部の端子面とを、重ね合せて電気的に接続していることを特徴とする積層型樹脂封止型半導体装置。 One or more of the resin-encapsulated semiconductor devices according to any one of claims 1 to 9 , wherein a plurality of the resin-encapsulated semiconductor devices are stacked. And a terminal surface of the upper external terminal portion of the lower resin-encapsulated semiconductor device that are overlapped and electrically connected to each other. 請求項１０に記載の積層型樹脂封止型半導体装置であって、樹脂封止型半導体装置の２つ以上が互いにその側面同士を合せて電気的に接続していることを特徴とする積層型樹脂封止型半導体装置。 11. The laminated resin-encapsulated semiconductor device according to claim 10 , wherein two or more of the resin-encapsulated semiconductor devices are electrically connected with their side surfaces aligned with each other. Resin-sealed semiconductor device. 請求項１ないし９のいずれか１項に記載の樹脂封止型半導体装置に用いられる、端子部材を多数配列したエッチング加工部材であって、１つの樹脂封止型半導体装置の各端子部材の配置に対応した、端子部材の配置を１単位として、エッチング技術を用いたエッチング加工にて、面付けして形成し、面付け形成しており、且つ、端子部材の薄肉のリード部の厚さをｔ１、半導体チップの厚さをＴ０、前記端子部材の厚さをｔ０とした場合、ｔ０＞Ｔ０で、且つ、ｔ１が（１／２）×（ｔ０−Ｔ０）以下の所望の厚さであることを特徴とするエッチング加工部材。 10. An etching member in which a large number of terminal members are arranged, which is used in the resin-encapsulated semiconductor device according to claim 1 , wherein each terminal member of one resin-encapsulated semiconductor device is disposed. The thickness of the thin lead portion of the terminal member is determined by imposing the surface of the terminal member with an etching process using an etching technique. When t1, the thickness of the semiconductor chip is T0, and the thickness of the terminal member is t0, t0> T0 and t1 is a desired thickness of (1/2) × (t0−T0) or less. An etched member characterized by that.
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