JP4861907B2 - Semiconductor module manufacturing method and semiconductor module - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor module capable of mounting a semiconductor chip on a wiring board without damaging the fluidity of an underfill agent due to a wiring pattern. <P>SOLUTION: A mounting region A on which a semiconductor chip is to be mounted is predetermined on a mounting surface of a wiring board 12, wiring patterns 18, 20 are formed such that they radially extend from the approximately central position of the mounting region A. The underfill agent 16 is adhered to the approximately central position of the mounting region A in a flowable state, the underfill agent 16 is pushed and spread while pressing the semiconductor chip 14 from the upper side. In this case, the fluidity of the underfill agent 16 is not damaged because wiring patterns 18, 20 are radially formed. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a conductor module configured by mounting a semiconductor chip (bare chip) on a substrate, and a semiconductor module.

  Conventionally, when an IC chip (bare chip) is mounted on a circuit board on which a wiring pattern is formed, an underpressure is caused in a thermocompression bonding process when a bump provided on the IC chip is connected to a wiring pattern on the circuit board by a metal eutectic connection. A method of filling and curing a filling agent is known (for example, see Patent Document 1). In this method, before the IC chip is mounted on the circuit board, an underfill agent is applied on the board in advance, and the IC chip and the circuit board are subjected to thermocompression bonding between the IC chip and the circuit board. The underfill agent is filled in between and expanded, and further heat-cured.

In the above mounting method, a dummy pattern is formed on the circuit board separately from the original wiring pattern, and the underfill agent is applied onto the dummy pattern so that the underfill agent is bumped when the IC chip is pressed. So that it does not spread. For this reason, it is considered that the bumps are directly bonded to the wiring pattern without being buried in the underfill agent, and the metal eutectic connection is favorably performed by heating from the bonding head.
JP 2000-100822 (5th page, FIG. 4, FIG. 6)

  However, in the conventional method, a dummy pattern is formed in the central portion of the position where the IC chip is mounted separately from the pattern on the circuit board. This dummy pattern impedes the fluidity of the underfill agent, and the underfill is uniformly applied. There is a problem that the agent cannot be filled. In particular, in the conventional method, since a plurality of dummy patterns are arranged orthogonally to the longitudinal direction of the IC chip (see FIG. 6 of Patent Document 1), the underfill agent applied to the center of the dummy pattern is the longitudinal direction of the IC chip. It becomes an obstacle when flowing to. In this case, the underfill agent cannot be sufficiently distributed between the IC chip and the circuit board, and as a result, there is a risk of causing poor adhesion of the underfill agent and insufficient adhesive strength.

  In view of this, an object of the present invention is to provide a technique capable of sufficiently ensuring adhesiveness with an underfill agent.

  First, the present invention provides a method for manufacturing a semiconductor module in which an underfill agent flows along a wiring pattern in a process of mounting a semiconductor chip on a mounting surface of a wiring board. A wiring pattern is formed on the mounting surface of the wiring board constituting the semiconductor module. The semiconductor chip has a rectangular shape, and terminals are provided on the back surface thereof. The semiconductor chip has a configuration in which the terminals on the back surface are connected to the wiring pattern while being mounted on the mounting surface of the wiring board. The term “back surface” as used herein refers to a surface facing the mounting surface of the wiring board in a state where the semiconductor chip is mounted, and does not necessarily match the back surface when the semiconductor chip is viewed as a single component. It is not necessary. The underfill agent is interposed between the mounting surface of the wiring board and the back surface of the semiconductor chip, and bonds them together. The manufacturing method of such a semiconductor module includes the following steps.

  Step 1: A semiconductor chip before being mounted on a wiring board is prepared. The semiconductor chip prepared here may be procured (purchased) as a finished product or a semi-finished product, or may be manufactured separately.

Step 2: Here, a mounting area on which the semiconductor chip is to be mounted is defined in advance on the mounting surface before the semiconductor chip is mounted, and a central pattern laid at least at a substantially central position of the mounting area as a wiring pattern , A wiring board is prepared in a state in which a peripheral pattern laid in a manner extending radially from the central pattern to the peripheral portion of the mounting region in a direction along the diagonal line of the semiconductor chip is formed. The wiring board prepared here may also be procured as a finished product or a semi-finished product, or may be manufactured separately.

  In any case, a radial wiring pattern may be formed on the mounting surface of the wiring board on which the semiconductor chip is to be mounted. Note that the mounting area on which the semiconductor chip is to be mounted is virtually rectangular according to the rectangular semiconductor chip. The wiring pattern formed in such a manner that extends radially from the substantially central position in the mounting region extends, for example, in a direction along the side of the mounting region (rectangular semiconductor chip) or in a direction along the diagonal line. It extends. Therefore, the wiring pattern does not simply extend in four vertical and horizontal directions, but extends in more than one direction (for example, eight directions).

  Step 3: Here, an underfill agent is attached in a flowable state to a substantially central position of the mounting area defined on the mounting surface of the wiring board prepared through Step 2 above. In this step, it is not necessary to apply the underfill agent over the entire mounting area, but only to attach (place) an appropriate amount of the underfill agent at a substantially central position.

  Step 4: Here, the semiconductor chip is relatively pressed through the underfill agent against the wiring substrate to which the underfill agent has been attached through the above step 3. With this pressing, the underfill agent is spread in a direction along the radial wiring pattern from a substantially central position of the mounting region between the back surface of the semiconductor chip and the mounting surface of the wiring board.

When a fluid such as an underfill agent is compressed in a narrow space when the semiconductor chip is pressed against the circuit board, the underfill agent tends to spread in all directions (radial) due to its fluidity. In the present invention, the underfill agent is filled while being spread between the semiconductor chip and the wiring board by utilizing the fluidity of the underfill agent. At this time, since the peripheral pattern extends radially from the central pattern laid at a substantially central position of the mounting area, when the underfill agent attached to the substantially central position is spread, its fluidity is inhibited by the peripheral pattern. It will never be done. In addition, since the radial peripheral pattern also acts in the direction of guiding the flow of the underfill agent, the underfill agent can be spread evenly in the mounting area, and the adhesiveness can be sufficiently secured. .

  Step 5: The underfill agent spread between the semiconductor chip and the wiring board is fixed (solidified and cured). The fixing of the underfill agent may proceed little by little in steps 3 and 4 due to, for example, an anaerobic curing phenomenon. However, when a thermosetting resin is used for the underfill agent, finally Is firmly fixed (solidified and cured) by heat-treating the material itself. Thereby, the adhesive strength of an underfill agent can fully be exhibited.

Especially the wiring patterns formed on the wiring board in the above step 2 in the present invention, Ru Tei include at least the following two factors. One is a central pattern laid at a substantially central position of the mounting area, and the other is laid in a manner extending to the peripheral edge of the mounting area in a direction along the diagonal line of the semiconductor chip. It is a peripheral pattern.

  Usually, the wiring pattern is for electrically conducting a plurality of locations at distant positions on the wiring board, and if there is no particular restriction on the handling, the shortest distance (or close to it) between the plurality of locations. The mode of laying at a distance) is natural. Therefore, for example, when connecting a plurality of locations in the peripheral portion of the mounting region, if these are arranged along the same side of the semiconductor chip, the wiring pattern is connected to the side of the semiconductor chip only by the peripheral portion of the mounting region. When laid in parallel, it becomes the shortest distance (or a distance close to the shortest).

  However, since the wiring pattern of such an aspect intersects with the flow direction when the underfill agent is spread, as described in the problem of the prior art, it is a factor that hinders the fluidity of the underfill agent. Become.

  Therefore, in the present invention, the wiring pattern is not set to the shortest distance, but a central pattern is laid at a substantially central position in the mounting area, and a peripheral pattern extending from the central pattern to the peripheral edge in the direction along the diagonal line of the semiconductor chip. Thereby, the wiring pattern does not hinder the fluidity of the underfill agent, and the underfill agent can be spread evenly between the semiconductor chip and the wiring substrate in the above-described step 4.

From the same idea as described above, the following elements may be added to the present invention.
That is, a case is assumed in which the first terminal and the second terminal are formed on the back surface of the semiconductor chip prepared in step 1 so as to be located at both ends of the same side. In this case, the wiring pattern formed on the wiring board prepared in step 2 passes through the substantially central position of the mounting area from the first connection position to be connected to the first terminal at least in the mounting area. It is preferable that a wiring path laid between the second terminal and the second connection position scheduled to be connected to the second terminal is included.

  In this case as well, the wiring pattern that connects the first terminal and the second terminal is originally the shortest distance, so that the wiring pattern is laid in parallel with the side of the semiconductor chip only at the peripheral portion of the mounting region. Is natural. However, in the present invention, the wiring pattern is intentionally rotated to prevent the underfill agent from flowing.

  The above concept is the same when the power supply terminal is formed on the back surface of the semiconductor chip. The power supply terminal is supplied with electric power through a wiring pattern, and here, a case is assumed where a plurality of power supply terminals are formed at the peripheral portion on the back surface of the semiconductor chip. The plurality of power supply terminals are provided to individually supply power to the plurality of semiconductor elements integrated on the semiconductor chip.

  In this case, the wiring pattern formed in the above step 2 includes a power supply path that connects a plurality of power supply terminals, and this power supply path is formed at a substantially central position of the mounting region. The first pattern and the second pattern formed in such a manner as to extend along the direction in which the underfill agent is pushed and spread are connected to the first pattern.

  Normally, when wiring patterns are connected to a plurality of power supply terminals, for example, it is natural that a branch point is set at one place in the mounting area and the wiring pattern is laid on each power supply terminal at the shortest distance from the branch point. It is.

  However, in the present invention, in order to realize a mode in which the fluidity of the underfill agent is not hindered by the wiring pattern constituting the power supply path, the power supply path is intentionally configured from the first pattern and the second pattern. The second pattern is distributed and connected to each power supply terminal from the first pattern at a substantially central position.

  Secondly, the present invention provides a semiconductor module having a structure in which a semiconductor chip is mounted on a mounting surface of a wiring board and an underfill agent is fixed. In particular, the semiconductor module of the present invention has a wiring pattern that does not hinder the fluidity of the underfill agent filled between the semiconductor chip and the wiring board.

  In the semiconductor module of the present invention, a rectangular semiconductor chip is mounted on the wiring board, and a plurality of terminals are formed on the peripheral edge of the back surface of the semiconductor chip. A wiring board mounts a semiconductor chip on the mounting surface facing the back surface of the semiconductor chip. On the mounting surface of the wiring board, in the mounting area where the semiconductor chip is mounted, a wiring pattern is formed in a manner extending radially from its substantially central position. Such a wiring pattern connects a plurality of terminals at the peripheral edge of the mounting area.

  The semiconductor module of the present invention is in its completed state (product or semi-finished product state), and is interposed between the mounting surface of the wiring substrate and the back surface of the semiconductor chip, so that the underfill agent is fixed, whereby the wiring substrate and the semiconductor The chip is bonded to each other. Such an underfill agent is filled and filled in a direction along the wiring pattern from a substantially central position of the mounting area in a flowable state before the fixing.

  That is, in the present invention, since a radial wiring pattern is formed on the mounting surface of the wiring board, when filling the underfill agent between the mounting surface of the wiring board and the back surface of the semiconductor chip in the manufacturing process, The pattern has a structure that does not hinder the fluidity of the underfill agent. Thereby, the semiconductor module of this invention can fully ensure the adhesive strength of an underfill agent in the completion state, and can improve the reliability as a product (or semi-finished product) greatly.

  Note that all of the various configurations mentioned in the method for manufacturing a semiconductor module can be employed as technical features added to the semiconductor module of the present invention. That is, the following technical features may be added to the semiconductor module of the present invention.

(1) In the semiconductor module of the present invention, the wiring pattern includes at least a central pattern laid at a substantially central position of the mounting region, and a peripheral edge of the mounting region from the central pattern in a direction along a diagonal line of the semiconductor chip. And a peripheral pattern laid in a manner extending to the portion.

(2) In the semiconductor module of the present invention, a first terminal and a second terminal are formed on the back surface of the semiconductor chip at both ends of the same side, and the wiring board is prepared. In the wiring pattern formed in the process, at least in the mounting region, the semiconductor chip is connected to the first terminal of the semiconductor chip from the first connection position via the substantially central position of the mounting region. And a wiring path laid between the second terminal and the second connection position scheduled to be connected to the second terminal.

(3) In the semiconductor module of the present invention, on the back surface of the semiconductor chip, a plurality of power supply terminals for receiving power supply through the wiring pattern are formed on the peripheral portion thereof. As a power supply path for connecting between the power terminals, a first pattern formed at a substantially central position of the mounting region and a direction extending in a direction in which the underfill agent is pushed and extended are connected to the first pattern. And a second pattern formed in a manner.

  By adding the features (1) to (3) above, the wiring pattern of the wiring board does not hinder the fluidity when filling the underfill agent, so that the underfill agent is spread evenly and the semiconductor chip and the wiring substrate Can be firmly bonded. Thereby, the reliability as a semiconductor module is improved in a completed state (product or semi-finished product).

  The present invention can greatly improve the quality, reliability, and performance of a semiconductor module manufactured as a product or a semi-finished product by preventing the flow failure of the underfill agent that occurs during the manufacturing process.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a longitudinal sectional view schematically showing a basic structure of a semiconductor module 10. The semiconductor module 10 completed as a product or a semi-finished product has a structure in which a semiconductor chip 14 is mounted on a mounting surface of a wiring substrate (insulating substrate) 12, and these are bonded to each other through an underfill agent 16. Has been.

  On the wiring board 12, a wiring pattern 18 made of, for example, a metal thin film (copper foil) is formed on the front mounting surface. On the other hand, bumps 14b are formed on the back surface of the semiconductor chip 14 via, for example, pads 14a on the periphery thereof. In the state shown in FIG. 1, the bumps 14b are reliably bonded to the wiring pattern 18 (for example, soldered). , Ultrasonic bonding, etc.). Although not shown in FIG. 1, another wiring pattern may be formed on the back surface of the wiring board 12, or the wiring board 12 may be a multilayer board.

  The semiconductor chip 14 is a bare chip in which a semiconductor integrated circuit is formed on a silicon substrate, for example. Here, even when the semiconductor chip 14 is mounted face-down on the wiring substrate 12, for convenience, the surface facing the mounting surface of the wiring substrate 12 (the surface facing down in FIG. 1) is the semiconductor chip. No. 14 “Back”. The semiconductor chip 14 may be packaged.

  The underfill agent 16 is fixed (solidified and cured) in a state of being evenly filled between the back surface of the semiconductor chip 14 and the mounting surface of the wiring substrate 12. For such an underfill agent 16, for example, an epoxy resin or the like can be used. The underfill agent 16 preferably protrudes slightly from the periphery of the semiconductor chip 14 to form a fillet.

  FIG. 2 is a perspective view showing the semiconductor module 10 disassembled into a wiring board 12 and a semiconductor chip 14. As shown in FIG. 2, the semiconductor chip 14 is formed in a rectangular shape (rectangular plate shape) by dicing a silicon wafer. Although an example of a rectangle is shown here, the shape of the semiconductor chip 14 may be a square.

  On the other hand, a mounting area A of the semiconductor chip 14 is defined on the mounting surface of the wiring board 12 as indicated by a two-dot chain line in FIG. The semiconductor chip 14 is mounted on the wiring board 12 in a state of being placed in the mounting area A. Note that the shape and size of the wiring substrate 12 are not limited to the form shown in FIG.

  On the mounting surface of the wiring board 12, in addition to the wiring pattern 18, a plurality of wiring patterns 20, 22, 24, and 26 are formed. Of these, for example, the two wiring patterns 18 and 20 are connected to the bumps 14 b of the semiconductor chip 14. In the mounting area A, lands 18a and 20a for connecting to the bumps 14b are formed at a plurality of positions, and these lands 18a and 20a are electrically connected by the wiring patterns 18 and 20, respectively.

  FIG. 3 is an enlarged plan view showing in detail the mode of the wiring patterns 18 and 20 in the mounting area A. FIG. The mounting area A has a rectangular shape in accordance with the shape of the semiconductor chip 14. In the mounting area A, two diagonal lines L (one-dot chain line in FIG. 2) of the semiconductor chip 14 can be virtually defined. On the mounting surface of the wiring board 12, the position of the intersection of these diagonal lines L can be defined as the center of the mounting area A.

  The wiring patterns 18 and 20 are laid in such a manner that they extend radially from a substantially central position (not necessarily coincident with the exact center) of the mounting area A to the peripheral edge thereof. Among these, one wiring pattern 18 includes one central pattern 18b (first pattern) and five peripheral patterns 18c, 18d, and 18e (second pattern). The other one-line wiring pattern 20 includes one central pattern 20b (first pattern) and three peripheral patterns 20c and 20d (second pattern).

  Each of the central patterns 18b and 20b is laid in a manner extending in a direction along the long side of the semiconductor chip 14 at a substantially central position of the mounting region A. The lengths of the central patterns 18b and 20b are appropriate and are not limited to the illustrated example.

  Further, some of the peripheral patterns 18c and 20c are laid in a manner extending in a direction (parallel) along the diagonal line L, respectively. The peripheral patterns 18c and 20c may be positioned on the diagonal line L or may be positioned away from the diagonal line L.

  The other peripheral patterns 18d and 20d are laid in a manner extending in the direction along the short side of the semiconductor chip 14, respectively. In addition, the peripheral pattern 18 e included in one system wiring pattern 18 is laid in a manner extending in a direction along the long side of the semiconductor chip 14.

  The semiconductor module 10 of the present embodiment uses these wiring patterns 18 and 20 as, for example, power supply paths, and the lands 18a and 20a of the wiring patterns 18 and 20 are semiconductor elements at a plurality of locations on the semiconductor chip 14. In order to individually supply power to (active elements, functional elements, etc.), they are provided separately at a plurality of locations. In this case, the bumps 14b of the semiconductor chip 14 are used as power supply terminals.

  Each wiring pattern 18, 20 connects lands 18 a, 20 a arranged at a plurality of locations in the mounting area A. Originally, the wiring patterns 18 and 20 may be laid in a manner in which the lands 18a and 20a are connected to each other at the shortest distance (or a distance close thereto). It can be seen that the central patterns 18b and 20b are laid on each other, and the lands 18a and 20a are connected to each other by going through the peripheral patterns 18c to 18e, 20c and 20d.

  The above-described aspects of the wiring patterns 18 and 20 have the following advantages in the manufacturing process of the semiconductor module 10. Hereinafter, the manufacturing method of the semiconductor module 10 will be described in the order of steps, and the advantages of this embodiment will be described.

  FIG. 4 is a diagram illustrating a method for manufacturing the semiconductor module 10 in the order of steps. Hereinafter, the steps will be described in order.

[Step 1]
As a pre-process of the mounting operation, a semiconductor chip 14 (bare chip) before being mounted on the wiring board 12 is prepared. The semiconductor chip 14 prepared here may be manufactured separately in the previous process, or may be procured (purchased).

[Step 2]
Similarly, as a pre-process, the wiring board 12 on which the wiring patterns 18 and 20 are formed in the above-described manner is prepared. The wiring board 12 prepared here may also be manufactured separately in the previous process or may be procured (purchased).

  When the semiconductor chip 14 and the wiring board 12 are prepared in steps 1 and 2 before the mounting operation, the process proceeds to the following mounting operation.

[Step 3]
4A and 4B: The underfill agent 16 is attached to the mounting surface of the wiring board 12 in a flowable state. At this time, the position where the underfill agent 16 is attached is set to the substantially central position of the mounting area A. The underfill agent 16 is attached, for example, while a necessary amount flows out from the nozzle N.

[Step 4]
In FIG. 4C: The semiconductor chip 14 is pressed against the wiring board 12 through the attached underfill agent 16. Here, the wiring substrate 12 is kept stationary in a horizontal posture, and the semiconductor chip 14 is lowered from above using, for example, a jig G. The jig G lowers the semiconductor chip 14 in the vertical direction while holding the semiconductor chip 14 in parallel at a position directly above the mounting area A.

  In FIG. 4, (D): As the semiconductor chip 14 is pressed, the underfill agent 16 is spread from the substantially central position of the mounting area A toward the peripheral edge. At this time, the underfill agent 16 flows so as to be evenly spread in the mounting area A.

  In combination with the step 4 (or after the step 4), the bumps 14b are bonded to the lands 18a and 20a of the wiring patterns 18 and 20, respectively. For example, when the bump 14b is solder, a reflow process is executed, and when the bump 14b is gold, an ultrasonic bonding process is executed.

[Step 5]
In FIG. 4, (E): the underfill agent 16 spread between the semiconductor chip 14 and the wiring substrate 12 is fixed. When the underfill agent 16 is a thermosetting resin, heat treatment is performed.

  FIG. 5 is a plan view schematically showing how the underfill agent 16 is pushed and expanded in the above-described step 4. FIG. 6 is a plan view (a state in which the semiconductor chip 14 is removed) showing a state in which the underfill agent 16 is pushed and expanded in the mounting area A. In the present embodiment, in addition to the wiring patterns 18 and 20 not hindering the fluidity of the underfill agent 16, the wiring patterns 18 and 20 further function as a flow guide for guiding the flow of the underfill agent 16.

  That is, since the central patterns 18b and 20b are formed in parallel to the long side of the semiconductor chip 14 at a substantially central position of the mounting area A, the central patterns 18b and 20b are arranged in the direction of the long side of the semiconductor chip 14 between them. An extending groove-like flow path is formed. In addition, flow paths extending in the direction of the diagonal line L of the semiconductor chip 14 are formed on both sides of each of the peripheral patterns 18c and 20c. Similarly, flow paths extending in the direction of the short side of the semiconductor chip 14 are formed on both sides of each of the peripheral patterns 18d and 20d, and the long sides of the semiconductor chip 14 are respectively set on both sides of the peripheral pattern 18e. A flow path extending in the direction is formed.

  For this reason, the underfill agent 16 first flows in the flow path between the central patterns 18b and 20b from a substantially central position, and is spread so as to be guided in the direction along the long side of the semiconductor chip 14. Note that the underfill agent 16 is also spread in the direction along the short side of the semiconductor chip 14 outside the central patterns 18b and 20b when viewed from the substantially central position. Further, at a position away from the substantially central position, the underfill agent 16 flows through each flow path, and as a result, is uniformly spread in eight directions (directions along the two diagonals L, the long side and the short side of the semiconductor chip 14). It will be.

  Thereby, as shown in FIG. 6, the underfill agent 16 can be evenly distributed in the rectangular mounting region A, and the adhesive strength can be sufficiently exhibited.

  The present invention can be implemented with various modifications without being limited to the above-described embodiments. In one embodiment, the two systems of the wiring patterns 18 and 20 are taken as an example, but more wiring patterns may be formed radially. Moreover, the wiring patterns 18 and 20 do not need to branch from the central patterns 18b and 20b in multiple directions, and may be laid radially on a single line.

  In the embodiment, an example is given in which each wiring pattern 18, 20 connects three or more lands 18 a, 20 a, but each wiring pattern 18, 20 is, for example, the same side (long) of the semiconductor chip 14. Two bumps 14b formed at both ends of the side or the short side may be connected.

  For example, if the bumps 14b of the semiconductor chip 14 are formed at the four corner positions on the back surface, the lands 18a and 20a are also formed in the mounting region A at positions corresponding to the four corner positions, respectively. In this case, each wiring pattern 18, 20 has a land 18 a, 20 a (second connection) at the other end via a substantially central position from the land 18 a, 20 a (first connection position) at one end of the same side. Until the position) is laid in a V-shaped (or inverted V-shaped) manner. At this time, it may be connected to the central patterns 18b and 20b similar to those of the embodiment at a substantially central position.

  In the embodiment, the wiring patterns 18 and 20 are used as power supply paths. However, the wiring patterns 18 and 20 may be used as signal paths.

It is a longitudinal section showing roughly the basic structure of a semiconductor module. It is the perspective view which decomposed | disassembled and showed the semiconductor module into the wiring board and the semiconductor chip. It is an enlarged plan view which shows the form of the wiring pattern in a mounting area | region in detail. It is the figure explaining the manufacturing method of the semiconductor module in order of a process. It is the top view which showed typically a mode that an underfill agent was expanded in the process 4. FIG. It is a top view which shows a mode that the underfill agent was expanded in the mounting area | region.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Semiconductor module 12 Wiring board 14 Semiconductor chip 14b Bump 16 Underfill agent 18 Wiring pattern 18a Land 18b Central pattern 18c, 18d, 18e Peripheral pattern 20 Wiring pattern 20a Land 20b Central pattern 20c, 20d, 20e Peripheral pattern

Claims (4)

A wiring board having a wiring pattern formed on a mounting surface; a rectangular semiconductor chip provided on a back surface where a terminal for connecting to the wiring pattern faces the mounting surface; a mounting surface of the wiring board; In a method for manufacturing a semiconductor module comprising an underfill agent that is interposed between a back surface of a semiconductor chip and adheres the wiring substrate and the semiconductor chip to each other,
Preparing the semiconductor chip before being mounted on the wiring board;
A mounting area on which the semiconductor chip is to be mounted on the mounting surface before the semiconductor chip is mounted is defined in advance, and a central pattern laid at least at a substantially central position of the mounting area as the wiring pattern, Preparing the wiring board in a state in which a peripheral pattern laid in a form extending radially from a pattern to a peripheral portion of the mounting region in a direction along a diagonal line of the semiconductor chip is formed;
Attaching the underfill agent in a flowable state to a substantially central position of the mounting region defined on the mounting surface of the wiring board;
The semiconductor chip is relatively pressed against the wiring substrate via the underfill agent, and the underfill agent is pressed between the back surface of the semiconductor chip and the mounting surface of the wiring substrate along with the pressing. A step of spreading in the direction along the peripheral pattern from the central pattern laid at a substantially central position of the mounting area;
And a step of fixing the spread underfill agent. In the manufacturing method of the semiconductor module of Claim 1,
On the back surface of the semiconductor chip, a first terminal and a second terminal are respectively formed at both ends of the same side,
The wiring pattern formed in the step of preparing the wiring board has a substantially central position of the mounting region from a first connection position to be connected to the first terminal of the semiconductor chip at least in the mounting region. A method of manufacturing a semiconductor module, comprising: a wiring path laid between the second terminal and a second connection position that is to be connected to the second terminal of the semiconductor chip . In the manufacturing method of the semiconductor module of Claim 1 or 2,
On the back surface of the semiconductor chip, a plurality of power supply terminals for receiving power supply through the wiring pattern are formed on the peripheral edge thereof,
The wiring pattern formed in the step of preparing the wiring board includes a power supply path that connects the plurality of power supply terminals,
The power supply path includes a first pattern formed at a substantially central position of the mounting area, and a second pattern formed in a manner extending along the direction in which the underfill agent is pushed and spread continuously to the first pattern. the method of manufacturing a semiconductor module, which comprises and. A rectangular semiconductor chip having a plurality of terminals formed on the periphery of the back surface;
A wiring board for mounting the semiconductor chip on a mounting surface facing the back surface of the semiconductor chip;
A central pattern formed at a substantially central position in the mounting area on which the semiconductor chip is mounted on the mounting surface of the wiring board, and a peripheral portion of the mounting area in a direction along a diagonal line of the semiconductor chip from the central pattern Including a peripheral pattern laid in a radially extending manner, and a wiring pattern that connects the plurality of terminals at the peripheral edge of the mounting region by the peripheral pattern,
The wiring substrate and the semiconductor chip are bonded to each other by being interposed and fixed between the mounting surface of the wiring substrate and the back surface of the semiconductor chip, and the mounting region is in a flowable state before fixing. An underfill agent filled and spread in a direction along the peripheral pattern from a substantially central position;
Semiconductor module with.