JP4859710B2 - Offset correction circuit - Google Patents

Description

  The present invention generally relates to an amplifier, and more particularly to an offset correction circuit that corrects an offset of the amplifier.

  In an amplifier using an operational amplifier, an offset voltage is superimposed on an input signal. Therefore, when the amplifier has gain, the offset voltage superimposed on the input signal is also amplified by the gain.

  When the output of the amplifier is connected to an encoder having a companding law, the influence of offset appears remarkably when a small signal is input. Therefore, in such a case, it is necessary to detect the offset and provide the amplifier with an input for canceling the offset according to the detection result to reduce the influence of the offset. With such a feedback control configuration, it is possible to prevent an offset from appearing in the output even if the offset of the amplifier fluctuates due to temperature change, voltage fluctuation, or the like.

  Immediately after the operation of the amplifier is started, such as when the power is turned on, a large offset often occurs because the offset correction function has not yet been activated. When such a large offset exists, it takes a long time to cancel the offset by feedback control of the offset correction function. Therefore, correct operation cannot be expected for a while at the start of operation of the amplifier.

  In order to solve this problem, there is a technique for shortening the time until the offset is canceled by taking measures such as increasing the offset correction amount by one correction operation at the start of the operation (Patent Document 1). reference).

  FIG. 1 is a block diagram showing a configuration of a conventional offset correction circuit. The offset correction circuit shown in FIG. 1 includes an offset correction circuit 11 that is a correction target circuit, an offset detection circuit 12 that detects an offset of an output of the offset correction circuit 11 and outputs an offset detection signal, and an output from the offset detection circuit 12. A correction instruction signal generation circuit 13 that generates a correction instruction signal in accordance with the offset detection signal to be changed, and an offset correction signal generation circuit 14 that changes an offset correction input voltage to the offset correction circuit 11 in accordance with the correction instruction signal.

  FIG. 2 shows an example of the circuit configuration of the offset correction circuit of FIG. The offset correction circuit 11 includes an amplifier 21 and resistance elements 22 to 24. The offset detection circuit 12 includes a comparator 25. The correction instruction signal generation circuit 13 includes a counter 26 and an AND circuit 27. The offset correction signal generation circuit 14 includes an amplifier 28, a capacitive element 29 having a capacitance value C1, a capacitive element 30 having a capacitance value C21, a capacitive element 31 having a capacitance value C22, a flip-flop (FF) 32, and switches SW1 to SW3.

  In the offset correction circuit 11, the amplifier 21, the resistance element 22 connected between the inverting input of the amplifier 21 and the input terminal IN, and the resistance element connected between the inverting input of the amplifier 21 and the output terminal OUT. 23 constitutes an inverting amplifier. Further, the output OF of the amplifier 28 of the offset correction signal generation circuit 14 is coupled to the inverting input of the amplifier 21 through the resistance element 24. By this combination, the output OF of the offset correction signal generation circuit 14 is supplied to the offset correction circuit 11 as an offset correction input voltage. The inverting amplifier inverts and amplifies the sum of the input voltage and OF and outputs the result.

  The comparator 25 of the offset detection circuit 12 compares the output voltage of the offset correction circuit 11 and the signal ground SG, and outputs an offset detection signal P that is a comparison result. The offset detection signal P becomes HIGH when the output voltage is higher than the signal ground SG, and becomes LOW when the output voltage is lower than the signal ground SG.

  The counter 26 of the correction instruction signal generation circuit 13 performs a count-up operation synchronized with the clock signal CK8K when the offset detection signal P is HIGH, and performs a count-down operation synchronized with the clock signal CK8K when the offset detection signal P is LOW. When the count value reaches the maximum value by counting up or when the count value reaches the minimum value by counting down, the ripple carry output RC changes from LOW to HIGH. The ripple carry output RC is input to the reset input RST of the counter 26, and the counter 26 is reset by the HIGH state of the ripple carry output RC and set to an intermediate value in the countable range.

  When the ripple carry output RC is in the HIGH state, the AND circuit 27 sets the correction instruction signal COR to HIGH during the LOW pulse period of the clock signal CK8K. The correction instruction signal COR output from the correction instruction signal generation circuit 13 is supplied to the switch SW1 of the offset correction signal generation circuit 14 and controls the connection state of the switch SW1. The correction instruction signal generation circuit 13 takes in the ripple carry output RC of the counter 26 to the flip-flop 32 of the offset correction signal generation circuit 14 and supplies it as a trigger signal.

  The flip-flop 32 of the offset correction signal generation circuit 14 takes in the offset detection signal P supplied from the offset detection circuit 12 in response to the change of the ripple carry output RC supplied from the correction instruction signal generation circuit 13 to HIGH. . The output of the flip-flop 32 is supplied as a switch control signal S to the switch SW2, and controls the connection state of the switch SW2. The switch SW2 is connected to the power supply voltage VD side when the switch control signal S is HIGH (in the positive offset state), and is connected to the ground voltage VS side when the switch control signal S is LOW (in the negative offset state). Connected to.

  When the mode instruction signal MODE indicates the normal mode, the switch SW3 of the offset correction signal generation circuit 14 is connected to the capacitive element 30 side. When the mode instruction signal MODE indicates the high speed mode, the switch SW3 of the offset correction signal generation circuit 14 is connected to the capacitive element 31 side.

For example, in the normal mode, the switch SW1 is connected to the switch SW2 when the correction instruction signal COR is LOW, and the capacitance element 30 has a polarity according to the offset state (positive offset state or negative offset state) at that time. Charge is charged. That is, in the positive offset state, charges are accumulated so that the terminal on the switch SW3 side of the capacitive element 30 has a voltage higher than the signal ground SG. In the negative offset state, charges are accumulated so that the terminal on the switch SW3 side of the capacitive element 30 has a voltage lower than the signal ground SG. If the signal ground SG is just between the power supply voltage VD and the ground voltage VS, the charge amount Q1 accumulated in the capacitive element 30 is
Q1 = ± C21 × SG
It becomes.

When the correction instruction signal COR is HIGH during the period of the LOW pulse of the clock signal CK8K, the switch SW1 is connected to the input side of the amplifier 28 only during that period. As a result, the charge accumulated in the capacitive element 30 is discharged and moved to the capacitive element 29. As a result, the change in the output voltage OF of the amplifier 28, that is, the amount of change ΔOF in the offset correction voltage due to one offset correction operation (one charge / discharge of the capacitive element 30) is:
ΔOF = ± C21 × SG / C1
It becomes.

In the high-speed mode, the switch SW3 is connected to the capacitive element 31 side, and the capacitive element 31 is used for the offset correction operation. Therefore, in the high-speed mode, the offset correction voltage change amount ΔOF by one offset correction operation (single charge / discharge of the capacitive element 31) is:
ΔOF = ± C22 × SG / C1
It becomes. By making the capacitance C22 of the capacitive element 31 sufficiently larger than the capacitance C21 of the capacitive element 30, a sufficiently high-speed offset correction operation can be realized.

  FIG. 3 is a diagram showing an example of changes in each signal in the operation of the offset correction circuit of FIG. 2 described above.

  In this example, as the counter 26, a 5-bit up / down counter whose count value CNT becomes 10,000 (10h) at reset is used. For example, the count value CNT is increased / decreased every 125 μs by an 8 kHz clock signal CK8K. When the offset detection signal P is HIGH, the count value CNT is increased, and when the offset detection signal P is LOW, the count value CNT is decreased. When the offset detection signal P is HIGH and the count value CNT is 11110 (1Eh), or when the offset detection signal P is LOW and the count value CNT is 00001 (01h), the counter is detected at the next rising edge of the clock signal CK8K. 26 ripple carry RC becomes HIGH. In the subsequent LOW period of the clock, the correction instruction signal COR becomes HIGH. In accordance with the HIGH state of the correction instruction signal COR, the switch SW1 is connected to the input side of the amplifier 28, and the offset correction operation is executed. Further, at the next clock, the count value CNT is reset to return to the initial value of 10000 (10h), the correction instruction signal COR becomes LOW, and the switch SW1 is connected to the switch SW2 side.

  By taking the offset detection signal P into the flip-flop 32 at the rising edge of the ripple carry RC, the switch control signal S is set to HIGH or LOW. Depending on the HIGH or LOW of the switch control signal S, whether the switch SW2 is connected to the VD side or the VS side is controlled. FIG. 3 shows the operation when the mode instruction signal MODE indicates the normal mode, and the switch SW3 selects the capacitor 30 of the capacitor C21. The capacitor 30 of the capacitor C21 stores charges having a polarity according to the state of the switch SW2, as shown.

In the conventional offset correction circuit described with reference to FIGS. 1 to 3, it is necessary to provide a charge charging capacitor 31 having a large capacitance value in order to shorten the offset correction time. Since the capacitive element requires a relatively large circuit area, the cost is greatly affected in the recent miniaturization technology era. Therefore, it is desirable not to use the capacitive element as much as possible.
JP-A-5-183437 JP-A-62-290216 JP 59-191930 A

  In view of the above, an object of the present invention is to provide an offset correction circuit that can shorten the offset correction time without providing an additional capacitive element.

The offset correction circuit detects an offset of the output of the correction target circuit and outputs an offset detection signal, and a first that changes in synchronization with the clock signal of the first frequency according to the offset detection signal. A first correction instruction signal generating circuit for generating a correction instruction signal, and a second that changes in synchronization with a clock signal having a second frequency higher than the first frequency in accordance with the offset detection signal in the high-speed operation mode. A second correction instruction signal generation circuit for generating a correction instruction signal of the second and a charge / discharge of the capacitor element in response to a change in the first correction instruction signal when not in the high-speed operation mode. The offset correction input voltage to the circuit to be corrected is changed by a change in the amount of charge of the capacitive element accompanying the discharge operation, and at least the second in the high-speed operation mode. An offset that changes the offset correction input voltage to the correction target circuit due to a change in the amount of charge of the capacitive element accompanying the charge / discharge operation by charging / discharging the capacitive element in response to a change in the positive instruction signal look including a correction signal generating circuit, said second correction instruction signal generating circuit, when the first of the offset detection signal taken in synchronization with the clock signal of the frequency is the same value continuously for a predetermined time period, The offset correction input voltage is repeatedly changed at a frequency equal to the second frequency by repeating HIGH and LOW of the second correction instruction signal at a frequency equal to the second frequency .

  According to at least one embodiment of the present invention, in the high-speed operation mode, by using the second correction instruction signal that changes in synchronization with the clock signal having the second frequency higher than the first frequency, Charge / discharge operation is performed more frequently at a higher frequency than during normal operation. Therefore, the offset correction input voltage can be changed at high speed in the high-speed operation mode while using the same capacitive element in the high-speed operation mode and in the normal operation mode. This eliminates the need for an additional capacitor element and reduces the cost of the integrated circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 4 is a block diagram showing the configuration of an embodiment of the offset correction circuit according to the present invention. The offset correction circuit shown in FIG. 4 includes an offset correction circuit 51 that is a correction target circuit, an offset detection circuit 52 that detects an offset of the output of the offset correction circuit 51 and outputs an offset detection signal, and a first correction instruction signal. A generation circuit 53, a second correction instruction signal generation circuit 54, and an offset correction signal generation circuit 55 are included.

  The first correction instruction signal generation circuit 53 generates a first correction instruction signal that changes in synchronization with the clock signal having the first frequency in accordance with the offset detection signal. The second correction instruction signal generation circuit 54 operates in the high-speed operation mode, and changes in synchronization with a clock signal having a second frequency higher than the first frequency according to the offset detection signal. Is generated.

  The offset correction signal generation circuit 55 charges / discharges the capacitive element in response to the change of the first correction instruction signal when not in the high-speed operation mode, thereby changing the charge amount of the capacitive element accompanying the charge / discharge operation. The offset correction input voltage to the offset correction circuit 51 is changed. The offset correction signal generation circuit 55 further charges and discharges the capacitor element in response to at least a change in the second correction instruction signal in the high-speed operation mode, so that the charge of the capacitor element associated with the charge / discharge operation is obtained. The offset correction input voltage to the offset correction circuit 51 is changed by changing the amount.

  In the above configuration, in the high-speed operation mode, the charge / discharge operation of the capacitive element is performed more than in the normal operation by using the second correction instruction signal that changes in synchronization with the clock signal having the second frequency higher than the first frequency. Even run more frequently at higher frequencies. Therefore, the offset correction input voltage can be changed at high speed in the high-speed operation mode while using the same capacitive element in the high-speed operation mode and in the normal operation mode.

  Note that the first correction instruction signal generation circuit 53 may be operated not only in the normal operation mode but also in the high-speed operation mode. In this case, in the high-speed operation mode, the first correction instruction signal from the first correction instruction signal generation circuit 53 and the second correction instruction signal from the second correction instruction signal generation circuit 54 are both offset correction operations. Will be used.

  FIG. 5 is a diagram showing an example of the circuit configuration of the offset correction circuit of FIG. The offset correction circuit 51 includes an amplifier 61 and resistance elements 62 to 64. The offset detection circuit 52 includes comparators 65 and 66, an XNOR circuit 67, and resistance elements 68 to 71. The first correction instruction signal generation circuit 53 includes a counter 72 and AND circuits 73 and 74. The second correction instruction signal generation circuit 54 includes a shift register (SR) 75, an AND circuit 76, a NOR circuit 77, an OR circuit 78, an AND circuit 79, and a flip-flop (FF) 80. The offset correction signal generation circuit 55 includes an amplifier 81, a capacitance element 82 having a capacitance value C1, a capacitance element 83 having a capacitance value C2, an OR circuit 84, an OR circuit 85, a flip-flop (FF) 86, a resistance element 87 having a resistance value R1, It includes a resistance element 88 having a resistance value R2, a resistance element 89 having a resistance value R3, a resistance element 90 having a resistance value R4, and switches SW1 and SW2.

  In the offset correction circuit 51, an amplifier 61, a resistance element 62 connected between the inverting input of the amplifier 61 and the input terminal IN, and a resistance element connected between the inverting input of the amplifier 61 and the output terminal OUT. 63 constitutes an inverting amplifier. Further, the output OF of the amplifier 81 of the offset correction signal generation circuit 55 is coupled to the inverting input of the amplifier 61 through the resistance element 64. By this combination, the output OF of the offset correction signal generation circuit 55 is supplied to the offset correction circuit 51 as an offset correction input voltage. The inverting amplifier inverts and amplifies the sum of the input voltage and OF and outputs the result.

  The comparator 65 of the offset detection circuit 52 compares the output voltage of the offset correction circuit 51 with the first reference voltage, and supplies an output indicating the comparison result to the XNOR circuit 67. The comparison result becomes HIGH when the output voltage is higher than the first reference voltage, and becomes LOW when the output voltage is lower than the first reference voltage. Here, the first reference voltage is a voltage obtained by dividing the power supply voltage VD and the signal ground SG by the resistance elements 68 and 69 at a predetermined ratio.

  Similarly, the comparator 66 of the offset detection circuit 52 compares the output voltage of the offset correction circuit 51 with the second reference voltage and supplies an output indicating the comparison result to the XNOR circuit 67. The comparison result becomes HIGH when the output voltage is higher than the second reference voltage, and becomes LOW when the output voltage is lower than the second reference voltage. Here, the second reference voltage is a voltage obtained by dividing the signal ground SG and the ground voltage VS by the resistance elements 70 and 71 at a predetermined ratio.

  The output EN of the XNOR circuit 67 becomes HIGH when both the output from the comparator 65 and the output from the comparator 66 are HIGH or both are LOW. If the output from the comparator 65 and the output from the comparator 66 do not match, the output EN of the XNOR circuit 67 is LOW. This output EN is supplied as an enable signal to the first correction instruction signal generation circuit 53 and the second correction instruction signal generation circuit 54.

  The first reference voltage is a voltage SG + ΔV that is slightly higher than the signal ground voltage SG, and the second reference voltage is a voltage SG−ΔV that is slightly lower than the signal ground voltage SG. When the output signal of the offset correction circuit 51 is between the first reference voltage and the second reference voltage, the offset detection circuit 52 sets the enable signal EN to LOW and does not execute the offset correction control. When the output signal of the offset correction circuit 51 is outside the voltage range from the first reference voltage to the second reference voltage, the offset detection circuit 52 sets the enable signal EN to HIGH to execute offset correction control. The offset detection circuit 52 outputs the output of the comparator 66 as an offset detection signal P.

  As described above, the offset detection circuit 52 is configured to output the enable signal EN indicating whether the offset is greater than or equal to a predetermined threshold (outside the range of SG ± ΔV) or below (in the range of SG ± ΔV). For example, the first correction instruction signal generation circuit 53 is configured not to operate when the enable signal EN indicates that the offset is equal to or less than a predetermined threshold. As a result, it is possible to suppress the generation of noise accompanying an unnecessary offset correction control operation when there is no signal.

  The counter 72 of the first correction instruction signal generation circuit 53 executes a count operation when the enable signal EN from the offset detection circuit 52 is HIGH and the mode instruction signal MODE is LOW indicating the normal operation mode. The counter 72 performs a count-up operation synchronized with the clock signal CK8K when the offset detection signal P is HIGH, and performs a count-down operation synchronized with the clock signal CK8K when the offset detection signal P is LOW. When the count value reaches the maximum value by counting up or when the count value reaches the minimum value by counting down, the ripple carry output RC changes from LOW to HIGH. The ripple carry output RC is input to the reset input RST of the counter 72, and the counter 72 is reset by the HIGH state of the ripple carry output RC and set to an intermediate value within the countable range.

  When the ripple carry output RC is in the HIGH state, the AND circuit 74 sets the first correction instruction signal COR1 to HIGH during the LOW pulse period of the clock signal CK8K. The first correction instruction signal COR1 output from the first correction instruction signal generation circuit 53 is supplied to the switch SW1 via the OR circuit 84 of the offset correction signal generation circuit 55, and controls the connection state of the switch SW1. . The first correction instruction signal generation circuit 53 takes in the ripple carry output RC of the counter 72 to the flip-flop 86 via the OR circuit 85 of the offset correction signal generation circuit 55 and supplies it as a trigger signal.

  The shift register 75 of the second correction instruction signal generation circuit 54 operates by being released from the reset when the enable signal EN from the offset detection circuit 52 is HIGH. The shift register 75 operates in synchronization with the clock signal CK8K, takes in the offset detection signal P from the offset detection circuit 52 as a data input, and sequentially propagates it through a plurality of dependently connected internal registers. The AND circuit 76 sets its output AL1 to HIGH when the stored values of all the internal registers of the shift register 75 become “1”. When the stored values of all the internal registers of the shift register 75 become “0”, the NOR circuit 77 sets its output AL0 to HIGH. Thereby, when the offset detection signal P is HIGH continuously for a predetermined period or when the offset detection signal P is LOW continuously for a predetermined period, the output of the OR circuit 78 becomes HIGH.

  The AND circuit 79 ANDs the output of the OR circuit 78, the clock signal CK64K, and the mode instruction signal MODE. As a result, the output of the AND circuit 79 is synchronized with the clock signal CK64K when the offset detection signal P is fixed to either HIGH or LOW continuously for a predetermined period and the mode instruction signal MODE is HIGH indicating the high-speed operation mode. Thus, the signal repeats HIGH / LOW alternately. The output of the AND circuit 79 is output from the second correction instruction signal generation circuit 54 as the control signal S2, and is supplied to the flip-flop 86 through the OR circuit 85 of the offset correction signal generation circuit 55 as a trigger signal.

  The output of the AND circuit 79 is converted into a signal that becomes HIGH during the LOW period of the clock signal CK64K by the flip-flop 80 that operates to capture in response to the falling edge of the clock signal CK64K, and is output as the second correction instruction signal COR2. 2 is output from the correction instruction signal generation circuit 54. The second correction instruction signal COR2 output from the second correction instruction signal generation circuit 54 is supplied to the switch SW1 via the OR circuit 84 of the offset correction signal generation circuit 55, and controls the connection state of the switch SW1. .

  Here, the clock signal CK8K is a clock signal having a frequency of, for example, 8 kHz, and the clock signal CK64K is a clock signal having a frequency of, for example, 64 kHz. Therefore, the second correction instruction signal COR2 is a signal that alternately repeats HIGH / LOW at a higher frequency than the first correction instruction signal COR1. In the configuration example shown in FIG. 5, the first correction instruction signal COR1 is output in synchronization with the clock signal CK8K only when the counter 72 reaches the maximum value or the minimum value. Is a signal of a lower frequency. On the other hand, since the second correction instruction signal COR2 repeats HIGH / LOW in complete synchronization with the clock signal CK64K, the second correction instruction signal COR2 has a frequency equal to the frequency of the clock signal CK64K.

  The flip-flop 86 of the offset correction signal generation circuit 55 changes the ripple carry output RC supplied from the first correction instruction signal generation circuit 53 to HIGH or a control signal supplied from the second correction instruction signal generation circuit 54. In response to the change of S2 to HIGH, the offset detection signal P supplied from the offset detection circuit 52 is captured. The output of the flip-flop 86 is supplied as a switch control signal S to the switch SW2, and controls the connection state of the switch SW2. The switch SW2 is connected to the terminal CP when the switch control signal S is HIGH (in the positive offset state), and is connected to the terminal CN side when the switch control signal S is LOW (in the negative offset state). Is done.

  Here, a voltage obtained by dividing the power supply voltage VD and the signal ground voltage SG by the resistance elements 87 and 88 at a ratio of R1: R2 is supplied to the terminal CP. The terminal CN is supplied with a voltage obtained by dividing the signal ground voltage SG and the ground voltage (power supply ground) VS by a ratio of R3: R4 by the resistance elements 89 and 90. The meaning of voltage division by this resistor string will be described later.

  When the mode instruction signal MODE indicates the normal operation mode, the offset correction signal generation circuit 55 performs the offset correction operation based on the ripple carry output RC and the first correction instruction signal COR1 from the first correction instruction signal generation circuit 53. Execute. When the mode instruction signal MODE indicates the high-speed operation mode, the offset correction signal generation circuit 55 performs the offset correction operation based on the control signal S2 from the second correction instruction signal generation circuit 54 and the second correction instruction signal COR2. Execute.

In the normal operation mode, when the first correction instruction signal COR1 is LOW, the switch SW1 is connected to the switch SW2 side, and has the polarity according to the offset state (positive offset state or negative offset state) at that time. The element 83 is charged with electric charge. That is, in the positive offset state, charges are accumulated so that the terminal on the switch SW1 side of the capacitive element 83 has a voltage higher than the signal ground SG. In the negative offset state, charges are accumulated so that the terminal on the switch SW1 side of the capacitive element 83 has a voltage lower than the signal ground SG. If the voltage at the terminal CP is higher than the signal ground voltage SG by ΔVcharge and the voltage at the terminal CN is lower than the signal ground voltage SG by ΔVcharge, the charge amount Q1 stored in the capacitor 83 is
Q1 = ± C2 × ΔVcharge
It becomes.

When the first correction instruction signal COR1 becomes HIGH only during the LOW pulse period of the clock signal CK8K, the switch SW1 is connected to the input side of the amplifier 81 only during that period. As a result, the charge accumulated in the capacitor 83 is discharged and moved to the capacitor 82. As a result, the change in the output voltage OF of the amplifier 81, that is, the amount of change ΔOF in the offset correction voltage due to one offset correction operation (one charge / discharge of the capacitive element 83) is:
ΔOF = ± C2 × ΔVcharge / C1
It becomes.

In the high-speed operation mode, when the second correction instruction signal COR2 becomes LOW during the HIGH pulse period of the clock signal CK24K, the switch SW1 is connected to the switch SW2 side, and the offset state at that time (positive offset state or negative offset state) The capacitor 83 is charged with the polarity according to When the second correction instruction signal COR2 becomes HIGH during the LOW pulse period of the clock signal CK64K, the switch SW1 is connected to the input side of the amplifier 81 only during that period. As a result, the charge accumulated in the capacitor 83 is discharged and moved to the capacitor 82. As a result, the change in the output voltage OF of the amplifier 81, that is, the amount of change ΔOF in the offset correction voltage due to one offset correction operation (one charge / discharge of the capacitive element 83) is:
ΔOF = ± C2 × ΔVcharge / C1
It becomes. The second correction instruction signal COR2 is a signal that repeats HIGH / LOW at high speed in synchronization with the clock signal CK64K, and the capacitive element 83 repeats charging / discharging at high speed in accordance with the repetition of HIGH / LOW. Therefore, the offset can be corrected at high speed in the high-speed operation mode.

  FIG. 6 is a diagram illustrating an example of changes in each signal in the normal operation mode of the offset correction circuit of FIG. FIG. 7 is a diagram illustrating an example of changes in each signal when the offset correction circuit of FIG. 5 is in the high-speed operation mode.

  In the example shown in FIG. 6, as the counter 72, a 5-bit up / down counter whose count value CNT becomes 10000 (10h) at the time of resetting is used. For example, the count value CNT is increased / decreased every 125 μs by an 8 kHz clock signal CK8K. When the offset detection signal P is HIGH, the count value CNT is increased, and when the offset detection signal P is LOW, the count value CNT is decreased. When the offset detection signal P is HIGH and the count value CNT is 11110 (1Eh), or when the offset detection signal P is LOW and the count value CNT is 00001 (01h), the counter is detected at the next rising edge of the clock signal CK8K. 72 Ripple carry RC becomes HIGH. In the subsequent LOW period of the clock, the first correction instruction signal COR1 becomes HIGH. According to the HIGH state of the first correction instruction signal COR1, the switch SW1 is connected to the input side of the amplifier 81, and an offset correction operation is executed. Further, at the next clock, the count value CNT is reset to return to the initial value of 10000 (10h), the first correction instruction signal COR1 becomes LOW, and the switch SW1 is connected to the switch SW2 side.

  By taking the offset detection signal P into the flip-flop 86 at the rising edge of the ripple carry RC, the switch control signal S is set to HIGH or LOW. Depending on the HIGH or LOW of the switch control signal S, it is controlled whether the switch SW2 is connected to the CP side or the CN side. As shown in the figure, a charge having a polarity corresponding to the state of the switch SW2 is stored in the capacitor 83 of the capacitor C2.

  As shown in FIG. 6, the count value CNT of the counter 72 changes only when the enable signal EN is HIGH, and the count value CNT of the counter 72 does not change when the enable signal EN is LOW. Thereby, an unnecessary offset correction control operation can be suppressed.

  In the operation in the high-speed operation mode shown in FIG. 7, it is assumed that the clock signal CK64K has a frequency that is eight times the frequency of the clock signal CK8K. The operation synchronized with CK64K is shown. If a positive offset state continues at the output OUT of the offset correction circuit 51, the output AL1 of the AND circuit 76 becomes HIGH. In response to the HIGH state of the output AL1, the control signal S2 becomes HIGH during the HIGH pulse period of the clock signal CK64K, and the second correction instruction signal COR2 becomes HIGH during the LOW pulse period of the clock signal CK64K.

  Whether the switch SW2 is connected to the CP side or the CN side is controlled in accordance with the HIGH / LOW of the offset detection signal P at the rising timing of the control signal S2. As shown in the figure, a charge having a polarity corresponding to the state of the switch SW2 is stored in the capacitor 83 of the capacitor C2. Further, when the second correction instruction signal COR2 is LOW, the switch SW1 is connected to the switch SW2 side (indicated as “S” in SW1 in FIG. 7), and when the second correction instruction signal COR2 is HIGH, the switch SW1 is connected. SW1 is connected to the amplifier 81 side (indicated as “A” in SW1 in FIG. 7).

  In the configuration shown in FIG. 5, as described above, the voltage obtained by dividing the power supply voltage VD and the signal ground voltage SG at a ratio of R1: R2, and the signal ground voltage SG and the ground voltage (power ground) VS. A voltage divided by a ratio of R3: R4 is generated and supplied to the capacitor 83. With this configuration, the offset voltage correction amount by one offset correction operation (one charge / discharge of the capacitor 83) can be reduced. Below, the effect of this structure is demonstrated.

  In the operation of the conventional offset correction circuit shown in FIG. 2, even when there is no signal output of the offset correction circuit 51, the operation for correcting the offset to the plus side and the operation for correcting the offset to the minus side are executed alternately. It will be. In other words, the output OUT of the offset correction circuit 51 fluctuates up and down by the amount of offset correction by one offset correction operation.

  For example, when the output of the offset corrected circuit 51 is connected to an encoder, the output of the encoder is, for example, a code according to the μ rule defined in the PCM encoding method of the ITU-T recommendation G.711 audio frequency band signal. When the output of the offset correction circuit 51 is connected to the device, the offset correction amount by one offset correction operation is less than 2 of the step width with respect to the identification value 8159 corresponding to the maximum load level (maximum value of the signal voltage). Then, the influence on the encoder by the offset correction operation is eliminated. Therefore, the offset correction amount by one offset correction operation may be less than 1/4080 of the maximum value of the signal voltage. If the movable range of the output voltage with respect to the power supply voltage range is 80%, the offset correction amount needs to be less than about 1/10000 with respect to the power supply voltage of VD-VS. In the configuration example shown in FIG. 2, the voltage applied to the capacitive element 30 is ½ of the power supply voltage, and thus the capacitance value of the capacitive element 29 needs to be 5000 times or more the capacitance value of the capacitive element 30.

  Since the capacitance element mounted on the integrated circuit cannot be set to a very small capacitance value in consideration of the influence of stray capacitance of other wirings, the lower limit of the capacitance value of the capacitance element 30 is determined. As a result, the capacitive element 29 needs to have a very large capacitance value, which causes an increase in layout area, that is, a cost increase.

  In the configuration of the present invention shown in FIG. 5, as described above, the offset correction amount by one offset correction operation is ΔOF = ± C2 × ΔVcharge / C1. Therefore, by reducing ΔVcharge, a sufficiently small offset correction amount can be realized without increasing the capacitance value C1 of the capacitive element 29 so much.

  Further, by setting the offset correction amount ΔOF to be equal to or smaller than the threshold value of the offset detection circuit 52, that is, ΔOF <2 × ΔV, the offset is always set to be equal to or smaller than the threshold value when the offset correction for changing the output polarity is performed. it can. In the conventional example, the low-level rectangular wave having the amplitude of the offset correction voltage is generated as noise because the offset correction operation is repeatedly and continuously executed during normal operation and no signal. On the other hand, in the present invention, when offset correction with changing polarity is performed, the offset is always equal to or less than the threshold value, so that the offset correction operation is not continuously executed. Therefore, noise due to a rectangular wave as in the prior art does not occur.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a block diagram which shows the structure of the conventional offset correction circuit. It is a figure which shows an example of a circuit structure of the offset correction circuit of FIG. FIG. 3 is a diagram illustrating an example of changes in signals in the operation of the offset correction circuit in FIG. 2. It is a block diagram which shows the structure of the Example of the offset correction circuit by this invention. FIG. 5 is a diagram illustrating an example of a circuit configuration of an offset correction circuit in FIG. 4. It is a figure which shows an example of the change of each signal in the normal operation mode of the offset correction circuit of FIG. It is a figure which shows an example of the change of each signal at the time of the high-speed operation mode of the offset correction circuit of FIG.

Explanation of symbols

51 Offset correction circuit 52 Offset detection circuit 53 First correction instruction signal generation circuit 54 Second correction instruction signal generation circuit 55 Offset correction signal generation circuit

Claims (5)

An offset detection circuit that detects an offset of the output of the correction target circuit and outputs an offset detection signal;
A first correction instruction signal generating circuit that generates a first correction instruction signal that changes in synchronization with a clock signal of a first frequency in accordance with the offset detection signal;
A second correction instruction signal generation circuit for generating a second correction instruction signal that changes in synchronization with a clock signal having a second frequency higher than the first frequency in accordance with the offset detection signal in the high-speed operation mode; ,
By performing charge / discharge on the capacitive element in response to a change in the first correction instruction signal when not in the high-speed operation mode, the correction target circuit is changed due to a change in the charge amount of the capacitive element accompanying the charge / discharge operation. And changing the offset correction input voltage to the capacitor, and charging / discharging the capacitive element in response to at least the change of the second correction instruction signal in the high-speed operation mode, the change in the charge amount of the capacitive element seen contains the offset correction signal generating circuit for changing the offset correction input voltage to the correction target circuit, the second correction instruction signal generating circuit, the first frequency of the clock signal When the offset detection signal captured in synchronism with the signal has the same value continuously for a predetermined period, HIGH and L of the second correction instruction signal at a frequency equal to the second frequency. By repeating W, offset correction circuit, characterized in that changing repeatedly the offset correction input voltage at a frequency equal to the second frequency.   The offset detection circuit is configured to output an enable signal indicating whether the offset is greater than or less than a predetermined threshold, and the first correction instruction signal generation circuit is less than the predetermined threshold 2. The offset correction circuit according to claim 1, wherein said offset correction circuit does not operate when said enable signal indicates.   The offset detection circuit is configured to output an enable signal indicating whether the offset is greater than or less than a predetermined threshold, and the second correction instruction signal generation circuit is less than the predetermined threshold 2. The offset correction circuit according to claim 1, wherein said offset correction circuit does not operate when said enable signal indicates.   A first end of the capacitor of the offset correction signal generation circuit is connected to a reference voltage, and a second end of the capacitor is connected to a first voltage between the power supply voltage and the reference voltage or the reference voltage via a switch. The offset correction circuit according to claim 1, wherein the offset correction circuit is configured to be connected to any one of a second voltage and a ground voltage.   The first correction instruction signal generation circuit operates in a mode other than the high-speed operation mode and does not operate in the high-speed operation mode, and the second correction instruction signal generation circuit operates in the high-speed operation mode and operates in the high-speed operation mode. 2. The offset correction circuit according to claim 1, wherein the offset correction circuit does not operate except at times.

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