JP2002305447A - Dc offset compensating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realizes a DC offset compensating circuit in which DC offset can be estimated with high accuracy through a small circuit scale, even if narrow- band low-pass characteristics are employed at estimating of the DC offset. SOLUTION: An up/down counter 21 counts up, when the output value from an AD converter 5 is large than 0 and counts down, when it is smaller than 0. Every time the AD converter 5 outputs an output value N times, the up/down counter 21 outputs a count, while rounding into a three-value, before being reset to 0. A moving average circuit 22 stores output values from the up/down counter 21 corresponding to recent M number of times and outputs a value proportional to these moving average values. Consequently, a value proportional to the integrated output value from the up/down counter 21 is outputted at the same output rate as that of the up/down counter 21. Furthermore, an integrating circuit 23 outputs a value proportional to the integrated output value from the moving average circuit 22 as the estimated value of DC offset.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DC offset compensating circuit for estimating a DC offset based on the output of a circuit to be compensated for the DC offset. And a DC offset compensation circuit for compensating for a DC offset by subtracting.

[0002]

2. Description of the Related Art When an analog signal is passed through a differential amplifier circuit, the characteristics of a differential pair transistor and the like vary.
A direct current (DC) offset component is added to the output signal.
Therefore, the differential amplifier circuit itself, an operational amplifier having the differential amplifier circuit as an input, an analog filter including the operational amplifier, an ADC (Analog to Digital Converter),
2. Description of the Related Art In a circuit such as a DAC (Digital to Analog Converter), a DC offset compensating circuit has conventionally been widely used to compensate for a DC offset of the circuit.

For example, a DC offset compensating circuit 101 disclosed in Japanese Patent Application Laid-Open No. 59-181719 is a circuit for compensating for a DC offset of a circuit including a filter 103 and an ADC 105 as shown in FIG. Reference numeral 103 denotes a subtraction circuit 11 for subtracting the DC offset amount specified by the integration processing unit 112 from the input signal.
1 is provided.

In the integration processing unit 112, an up / down counter 121 is operated by a sign detector 113 to detect A
While it is confirmed that the output of the DC 105 is not 0, the count value is increased / decreased according to the MSB of the digital value output by the ADC 105. Further, when the up / down counter 121 overflows, the switched-capacitor type integration circuit 122 increases or decreases the integrated value by a predetermined unit voltage based on the carry signal and the borrow signal of the up / down counter 121, and
The integration result is output to the subtraction circuit 111 as an analog signal indicating a DC offset value. At the time of overflow, the count value of the up / down counter 121 is reset.

In the above configuration, the positive or negative tendency of the output of the ADC 105 is detected by the integration operation of the up / down counter 121, and the DC offset amount is obtained by integrating the integration result by the switched capacitor type integration circuit 122. ing.

Here, since the DC offset amount usually hardly changes with time, it has a frequency component lower than the signal component of the circuit. Therefore, the up / down counter 121 and the switched capacitor type integrator 12
The DC offset amount can be estimated by sufficiently narrowing the low-pass characteristic at the time of the integration operation of 2.

[0007]

However, in the DC offset compensating circuit 101 having the above configuration, when compensating for a DC offset of a wideband amplifier, a filter, or a high-speed ADC, for example, the up / down counter 121 is used.
If the number of stages of the up-down counter 121 is increased in order to narrow the low-pass characteristic when the switched-capacitor-type integration circuit 122 performs the integration operation, the downsampling rate increases. As a result, in order to improve the accuracy of estimating the DC offset, a low-pass filter is required before the up-down counter 121, which causes a problem that the circuit scale is likely to increase.

Specifically, the up / down counter 121
Is increased, the downsampling rate, that is, the output rate R of the ADC 105 with respect to the sampling rate Rc of the switched capacitor type integrator 122 is increased.
The ratio of ad (Rad / Rc) increases, and the sampling rate Rc of the switched-capacitor integrator 122 decreases.

Here, the output of the up / down counter 121 has a frequency component equal to or more than の of the sampling rate Rc due to the aliasing. Therefore, when the sampling rate Rc becomes low, the aliasing component caused by the aliasing estimates the DC offset. It is easy to appear in the frequency band (approximately DC frequency band) referenced when
The accuracy of estimating the DC offset amount is reduced.

On the other hand, in order to improve the accuracy of estimating the DC offset amount, a low-pass filter is provided in a stage preceding the up-down counter 121, so that the input signal to the up-down counter 121 has a half of the sampling rate Rc. When the above frequency components are attenuated, the DC offset amount estimation accuracy is improved, but a circuit having a relatively large circuit size such as a low-pass filter is required, and the circuit size of the DC offset compensation circuit 101 is increased.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to estimate a DC offset with a small circuit scale even when a low-pass characteristic at the time of integration is sufficiently narrowed. An object of the present invention is to realize a DC offset compensating circuit capable of estimating a DC offset amount with high accuracy.

[0012]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a DC offset compensating circuit according to the present invention estimates an amount of DC offset based on a discrete time output of a circuit to be compensated for DC offset. In a DC offset compensating circuit having means and a subtracting means arranged on a signal path of the circuit and subtracting the DC offset amount estimated by the estimating means, the following means is employed.

That is, the estimating means sets N × M of a constant sampling period of the discrete time output, where N is an integer of 1 or more and M is an integer of 2 or more.
Integrating means for integrating the discrete time output over N times, and outputting the output every N times the sample period; and output means for integrating the output of the integrating means and outputting a signal indicating the DC offset amount. It has. In addition, the calculation accuracy of the integration is determined according to the accuracy required when estimating the DC offset amount, and if sufficient accuracy can be ensured, a numerical value is calculated in the middle to simplify the circuit configuration of the DC offset compensation circuit. The calculation may be rounded.

In the above configuration, the integrating means includes, for example,
By integration using a moving average, N
The result of integrating the discrete-time output over × M times is output every N times the sample period. The output of the integrating means is further integrated by the output means and output as a DC offset amount. On the other hand, in the circuit to be compensated for the DC offset, the subtraction means arranged on the signal path subtracts the DC offset amount from the input signal. This allows
The DC offset of the circuit is compensated.

According to the above arrangement, the integrating means outputs the integration result of N times the sample period, although the result of integration of the discrete time output is output over N × M times the sample period. Output in a cycle.

Therefore, the output rate of the integrating means is M times higher than that of an integrating circuit which outputs the result of integrating the discrete time output over N × M times the sample period every N × M times the sample period. Become. As a result, although the integrating means having the above configuration has the same low-pass frequency characteristics as the integrating circuit of the comparative example, the amount of attenuation at the Nyquist frequency can be increased as compared with the comparative example. As a result, aliasing components can be reduced, and the estimation accuracy of the DC offset amount can be improved.

Here, in the configuration of the comparative example, in order to improve the accuracy of estimating the DC offset amount, a filter circuit is provided before the integrating circuit to reduce aliasing components. It is necessary to add a circuit with a large circuit scale.

On the other hand, in the above configuration, since the output rate of the integration means is improved to reduce aliasing components, the circuit is relatively small-scale without providing the filter circuit. Therefore, the DC offset amount can be estimated with sufficient accuracy.

Further, a DC offset compensation circuit according to the present invention is provided with estimating means for estimating a DC offset amount based on a discrete time output of a circuit to be compensated for a DC offset, and is provided on a signal path of the circuit. In order to solve the above-mentioned problem, a DC offset compensating circuit having a DC offset amount estimated by the estimating means and a subtracting means for subtracting the DC offset amount is characterized by taking the following means.

That is, if the estimating means sets a predetermined integer equal to or greater than 1 to N, every N times a fixed sampling period of the discrete time output, the estimating means sets the approximate N of the discrete time output.
A first integral means for outputting an output value proportional to a value obtained by integrating the first and second integral values.
A storage means for storing one value and an output value proportional to a value obtained by integrating M output values of the first integration means with reference to the storage of the storage means. A second integration means for outputting a signal having a period shorter than M times as large as an output of the second integration means, and an output means for outputting a signal indicating the DC offset amount.

In order to improve the accuracy of estimating the DC offset amount, the ratio of the output period of the first integration means to the sample period (for example, N times) and the discrete time referred to when integrating the output value are determined. Number of outputs (eg, Nc)
Is preferably the same, but it is required to reduce the circuit size rather than the accuracy of estimating the DC offset amount, and moreover,
If the circuit scale can be reduced by setting Nc to be smaller than N, N and Nc are substantially the same, and Nc is set to a value smaller than N if the estimation accuracy can be reduced. May be. In addition, the calculation accuracy of the integration is determined according to the accuracy required when estimating the DC offset amount, and if sufficient accuracy can be ensured, a numerical value is calculated in the middle to simplify the circuit configuration of the DC offset compensation circuit. The calculation may be rounded.

In the above configuration, the first integration means outputs an output value at a cycle N times the sample cycle, and the storage means stores the latest M or M-1 output values.
Furthermore, the second integration means refers to the storage means,
An output value proportional to a value obtained by integrating M output values of the first integration means is output in a cycle shorter than M times the output cycle of the first integration means. Even when the storage means stores M-1, the output value proportional to the value obtained by integrating the M values can be obtained by referring to the storage of the storage means and the output of the first integration means. Can be calculated.

According to this structure, each output of the second integrating means depends on the M outputs of the first integrating means, but has a cycle shorter than M times the output cycle of the first integrating means. Is output. Therefore, when compared with a configuration in which the second integration means outputs an output value at a cycle M times the output cycle of the first integration means, the Nyquist The attenuation at the frequency can be increased. Therefore, without providing a filter circuit for reducing aliasing components, with a relatively small circuit scale,
The DC offset amount can be estimated with sufficient accuracy.

In the DC offset compensating circuit according to the present invention, when a predetermined integer equal to or greater than 1 is set to N instead of the above-mentioned first integrating circuit, the discrete time output is N times the fixed sampling period. Each time, a first integration means for outputting an output value obtained by binarizing or ternarizing a value obtained by integrating substantially N discrete time outputs is provided.

In this configuration, although rough quantization such as binarization or ternary quantization is performed, the output of the second integration means depends on the M output values of the first integration means. Instead, it is output at a cycle shorter than M times the output cycle of the first integration means. Therefore, as described above, even if the second integrator has the same low-pass frequency characteristic as compared with a configuration in which the second integrator outputs an output value at a period M times the output period of the first integrator, Regardless, the amount of attenuation at the Nyquist frequency can be increased. As a result, the DC offset amount can be estimated with sufficient accuracy with a relatively small circuit scale without providing a filter circuit for reducing aliasing components.

Further, in addition to each of the above configurations, it is preferable that the second integration means outputs an output value in an output cycle of the first integration means. In this configuration, the output rate of the second integration means can be increased by a factor of M, as compared with a configuration in which the second integration means outputs an output value at a cycle M times the output cycle of the first integration means. As a result, the amount of attenuation at the Nyquist frequency can be set larger, and the aliasing component can be further reduced.

In each of the above structures, the second integrating means holds the output value of the immediately preceding second integrating means and the second integrating means calculates the next output value of the second integrating means. (1) arithmetic means for adding a value proportional to the current output value of the integration means to the value held by the holding means, reading the oldest output value from the storage means, and subtracting from the value held by the holding means; May be provided.

According to this configuration, the calculating means adds a value proportional to the current output value of the first integrating means to the output value of the second integrating means immediately before being held by the holding means, and A value proportional to the oldest output value of the means is subtracted to calculate the next output value of the second integrating means. Therefore, it is possible to reduce the amount of calculation as compared with a configuration in which M output values of the first integration means are added for each output cycle of the second integration means and a value proportional to the addition result is output. The circuit scale of the means can be reduced.

As another preferred embodiment of the second integration means, when a reduction in circuit size is particularly required, the second integration means outputs the binarized or ternary output value to the output value. It is desirable to give to the means.

According to this configuration, since the second integration means only needs to be able to output a binary or ternary output value, it can be realized with a smaller circuit scale. Further, since the output of the second integration means is binarized or ternary, the integration result is reduced, and the circuit scale of the output means can be reduced. In particular,
When the output means is a digital circuit, the output means can be realized not by an accumulator but by an even smaller circuit such as an up / down counter. Further, even when the output means is an analog circuit, the number of types of voltage values to be output by the second integration means is reduced, so that the circuit scale of the second integration means can be reduced. As a result, a DC offset compensating circuit having a significantly smaller circuit scale can be realized.

Further, irrespective of the presence / absence and configuration of the second integration means, it is desirable to provide an N value setting means for changing the value of N in addition to the above configuration. According to this configuration, N
The following speed can be changed when the DC offset compensating circuit estimates the DC offset amount depending on the magnitude of the value set as.

For example, by reducing the value of N, the rate at which the output means outputs the DC offset amount can be improved, so that the following speed of the DC offset compensation circuit can be increased. Therefore, for example, even when the DC offset of the circuit greatly changes, for example, when the power is turned on or when the gain is changed, it is possible to compensate by following the fluctuation of the DC offset.

On the other hand, when the N value setting means sets the value of N to a large value, the follow-up speed when the DC offset compensating circuit estimates the DC offset can be slowed down. Even if it fluctuates, the fluctuation of the DC offset amount can be suppressed.

The N value setting means sets the value of N to a value smaller than the normal value for a certain time when the power of the circuit is turned on or when the circuit returns from the halt state. , It is desirable to return to the normal value.

Here, in the circuit to be compensated for the DC offset, the DC offset greatly changes when the power is turned on or when returning from the sleep state, so that the following speed of the DC offset compensation circuit needs to be increased. On the other hand, since the DC offset does not change much during normal times, if the tracking speed is set to be high, the DC offset amount changes due to a change in the output value due to the signal component of the circuit, and the output signal of the circuit may be distorted. There is.

On the other hand, according to the above configuration, the N value setting means sets the value of N to a value smaller than the normal value for a fixed time when the power is turned on or when returning from the sleep state. Without distorting the output signal of the above circuit,
When turning on the power or returning from the sleep state, the DC offset of the circuit can be reliably compensated.

Further, in the case where the circuit outputs an analog signal irrespective of the presence or absence of the N value setting means, the estimating means calculates the result of discrete time sampling of the analog signal,
It is desirable to have a comparator that outputs the discrete time output.

According to the above configuration, the comparator converts the analog signal into a discrete time and discrete value output. Therefore, even when the circuit for which the DC offset is to be compensated outputs the analog signal, the comparator converts the analog signal into a discrete value. The DC offset can be compensated without any trouble.

[0039]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
The following is a description based on FIG. That is, the DC offset compensation circuit according to the present embodiment includes:
For example, amplifiers, filters, ADCs (Analog to Digita
l Converter) or DAC (Digital to Analog)
Converter), such as a circuit including a circuit having a direct current (DC) offset, estimating the DC offset based on the output, and negatively feedback the estimated value to compensate for the DC offset of the system, for example, , Broadband amplifiers and filters, or high-speed ADCs (Ana
log to Digital Converter) and high-speed DAC (Digital t
o It is particularly suitable for high-speed systems such as analog converters.

As shown in FIG. 1, a DC offset compensating circuit 1 according to the present embodiment includes, for example, a filter 3 and an A
A circuit for compensating for a DC offset of a system (circuit) including the DC5, which is provided in the filter 3 and subtracts a designated value from a signal passing through the filter 3; An integration processing unit (estimating means) for instructing the subtraction circuit 11 by estimating the DC offset by integrating the output value of the above while rounding the output value, and using the estimated value as a subtraction amount.
12 are provided.

The filter 3 is a filter for removing aliasing noise in the ADC 5, and is realized, for example, as an active filter including a plurality of amplifiers. Further, the subtraction circuit 11 is realized as one of the amplifiers, and when a voltage indicating the estimated value of the DC offset is applied, the subtraction circuit 11 can subtract the estimated value from the input signal.

The integration processing unit 12 counts up when the output value of the ADC 5 is larger than 0, and counts down when the output value is smaller than 0, and outputs the output value a predetermined number of times (N times). Each time, after the count value is rounded to the three values {-1, 0, +1} and output, 0
Up / down counter to be reset (first integrating means)
21 and the latest M times of the output values of the up-down counter 21 are stored, and a value proportional to the moving average value of these M values is output.
A moving average circuit (second integrating means) 22 that outputs a value proportional to the integrated value of the output value of the up / down counter 21 at the same output rate Rc as the output rate Rc of the above, and the output value of the moving average circuit 22 is integrated. And an integration circuit (output means) 23 for inputting a value proportional to the integration result to the subtraction circuit 11 as an estimated value of the DC offset.

The moving average circuit 22 and the integrating circuit 2
The proportionality constant of 3 is set to a value that allows the subtraction circuit 11 to cancel the DC offset when the DC offset compensation circuit 1 estimates the DC offset without error. Further, the up / down counter 21 and the moving average circuit 22 correspond to the integration means described in the claims.

Here, the output value of the moving average circuit 22 is A
Although determined based on the N × M output values of the DC5, the output rate Rc of the moving average circuit 22 is Rc = Rad / N where the output rate of the ADC5 is Rad. Therefore, the up-down counter 21 and the moving average circuit 22 (both are hereinafter referred to as a pre-stage unit)
When the transfer function Hma (f) for the frequency f [Hz] is calculated ignoring the quantization error, as shown in the following equation (1), | Hma (f) | ² = [1-cos ｛(2π F · M) / (Rc)｝] / [1−cos ｛(2π · f) / (N · Rc)｝] (1) and expressed in terms of the output rate Rad of the ADC 5, As shown in equation (2), | Hma (f) | ² = [1-cos {(2π · f · M · N) / (Rad)}] / [1-cos ｛(2π · f) / ( Rad)｝] (2)

Here, as a comparative example, the moving average circuit 22
Is provided, an accumulation circuit is provided which is reset to 0 each time the up / down counter 21 outputs M output values, and a value proportional to the integral value of the output value of the up / down counter 21 is
At an output rate Rcp (= Rad / (N × M)) of 1 / M of the output rate of the up / down counter 21, the integration circuit 2
3, the transfer function Ha (f) for the frequency f [Hz] of the up / down counter 21 and the accumulator circuit (both are hereinafter referred to as a precedent part) according to the comparative example is as described above. Similarly to the equation (1), when the calculation is performed ignoring the quantization error, as shown in the following equation (3), | Ha (f) | ² = [1−cos ｛(2π · f) / (Rcp) )｝] / [1−cos ｛(2π · f) / (M · N · Rcp)｝] (3), and expressed in terms of the output rate Rad of the ADC 5 in the same manner as in the above equation (2). | Ha (f) | ² = [1-cos {(2π · f · M · N) / (Rad)}] / [1-cos ｛(2π · f), as shown in the following equation (4): ) / (Rad)｝] (4)

As is clear from comparison of the above equations (2) and (4), the sampling frequency Rad of the ADC 5 is
The transfer functions of the former part are the same as each other, but the output rate of the former part, that is, the sampling frequency is actually different from each other, and the former part according to the present embodiment has a higher sampling rate. Frequency is high.
Here, in the case of sampling, only half the sampling frequency is effective. Therefore, as shown in Expression (1), it is possible to secure a wider stopband by performing the moving average using the pre-stage according to the present embodiment. .

Further, in the case of sampling, a frequency component equal to or more than の of the sampling frequency is filtered by sampling, and is returned to a frequency band equal to or less than １ ／. Therefore, when the moving average is performed and the sampling frequency Rc is set higher as in the present embodiment, the aliasing component is reduced more than when the sampling frequency Rcp is set lower as in the comparative example. Dramatic reduction can be achieved, and the accuracy of DC offset estimation can be improved.

For example, the sampling frequency R of the ADC 5
ad is 15.36 [MHz], N = 512, M = 8, N
In the case of × M = 4096, the integral operation of the 4096 data is
It has the frequency characteristics shown in FIG. In the frequency characteristic of FIG. 2, the gain is normalized to the maximum value = 1.

Here, when the moving average is obtained as in the present embodiment, the output rate of the preceding stage is 30000 [Hz], and the effective frequency band is 0 [Hz] to 15000 [H].
z], and the frequency component of 15000 [Hz] or more is
As an aliasing component, it enters the effective frequency band. On the other hand, if the moving average is not performed as in the comparative example, the output rate of the preceding stage is 3750 [Hz], and the effective frequency band is 0 [Hz] to 1875 [Hz], and 1875 [Hz].
[Hz] or more frequency components enter the effective frequency band as aliasing components.

On the other hand, as shown in FIG. 2, the frequency characteristic of the integration operation is the return frequency 187 when the moving average is not performed.
At 5 [Hz], for example, 0.6 or more, it is not sufficiently attenuated. As a result, components outside the effective range are replaced with the original DC.
(0 [Hz]), and the signal component near DC greatly changes. Therefore, in order to improve the accuracy of estimating the DC offset, it is necessary to suppress a frequency component equal to or higher than the aliasing frequency in a signal input to the front stage, for example, by providing a narrow band filter before the front stage. There is.

On the other hand, as in the present embodiment, when the moving average is performed, the return frequency becomes as large as 15000 [Hz]. As a result, even when the frequency characteristics of the integration operation are the same, the gain in the band equal to or higher than the return frequency is sufficiently attenuated. For example, in the case of the characteristic of FIG. I have. Therefore, even if components other than the effective frequency band enter the effective frequency band, they do not significantly affect the signal components near DC.
As described above, the moving average circuit 22 performs the integration operation together with the up / down counter 21 and the moving average circuit 2
2 suppresses an increase in the downsampling rate, so that the DC offset can be estimated with sufficiently high accuracy without providing a new narrow band filter unlike the comparative example.

Here, if M is small, the moving average circuit 2
2 can be realized with a smaller circuit scale than the narrow band filter. Therefore, as in the comparative example, the number of bits of the up / down counter 21 is increased, and the circuit scale can be reduced as compared with the case where a narrow band filter is provided.

The moving average circuit 22 outputs a value corresponding to the latest M outputs of the up / down counter 21 by moving average, so that the output value is changed every time the up / down counter 21 outputs a value. Despite the output,
The calculation accuracy of each output value is kept the same as when no moving average is performed.

Incidentally, the DC offset compensating circuit 1 having the above configuration is a simple circuit in which a filter is not provided in a stage preceding the up / down counter 21. Can be compensated. Further, since the output of the ADC 5 is sufficiently blunted by the integration characteristic of the DC offset compensating circuit 1, the DC offset compensating circuit 1 is not affected by the low frequency components of the signal input to the filter 3 and the ADC 5. , The DC offset can be estimated and compensated.

However, when the characteristics of these circuits change, for example, by switching the gain of an amplifier provided in a circuit disposed before the filter 3 or in a circuit such as the filter 3 or the ADC 5, or ADC5
When the DC offset changes more than usual, such as when the power supply of the system including the power supply is turned on, the change in the DC offset is slowed down by the integration characteristic of the DC offset compensation circuit 1 set according to the normal time. Therefore, the DC offset compensation circuit 1 cannot sharply change the DC offset estimation signal. As a result,
It takes time to cancel the new DC offset.

On the other hand, in addition to the configuration of FIG. 1, the DC offset compensating circuit 1a shown in FIG. 3 changes the output rate of the up / down counter 21 according to the fluctuation of the DC offset to the normal rate Rc ( = Rad / N), a DC offset fluctuation determining unit (N value setting unit) 15 for changing the value to a value Rc2 is provided.

The DC offset fluctuation judging unit 15 detects, for example, when the power supply management circuit detects that a circuit for inputting a signal to the filter 3 or a circuit such as the filter 3 or the ADC 5 has been turned on, or in these circuits. When the return from the sleep state is detected, it is determined that the DC offset changes greatly.

In this case, the DC offset fluctuation determining section 15
Changes the output rate of the up / down counter 21 to Rc2 for a certain period of time by decreasing N in order to quickly cancel the new DC offset. As a result, the DC offset estimated value output by the integration circuit 23 changes faster and approaches a new DC offset more quickly.
Therefore, the followability of the DC offset compensation circuit 1a is improved.

For example, normally, when N = 512, if the value is changed to N = 128, the output rate of the up / down counter 21 increases by four times. Is also quadrupled.

Here, while the output rate of the up / down counter 21 is increased to Rc2, the integration processing unit 12
Is wide (four times in the above numerical example), the DC offset estimation value fluctuates due to the effect of the low frequency component of the signal input to the filter 3, and the output signal waveform of the ADC 5 There is a risk of distortion.

On the other hand, the DC offset fluctuation determining section 15 according to the present embodiment returns the output rate of the up / down counter 21 to the normal value Rc when the elapse of a predetermined time is detected by the timer. Thereby, the filter 3
The tracking performance can be improved while preventing the fluctuation of the estimated DC offset value in the normal state caused by the low frequency component of the signal input to the input terminal.

In this embodiment, since the output rates Rc and Rc2 of the up / down counter 21 are fixed both in the case where the DC offset greatly fluctuates and in the normal state, it is necessary to accurately determine the return frequency. Can be. Therefore, the output errors Rc and Rc2 can be set so that the estimation error of the DC offset amount caused by the aliasing component can be accurately evaluated, and the necessary estimation accuracy can be obtained.

In the above description, the case where the integration processing unit 12 includes the moving average circuit 22 has been described. However, the integration processing unit 12 does not include the moving average circuit 22, and the output value of the up / down counter 21 is used as the integration circuit. Even when the DC offset is directly input to the counter 23, the up-down counter 2 is used both when the DC offset greatly fluctuates and during normal operation.
Since the output rates Rc and Rc2 are fixed, the estimation error of the DC offset caused by the aliasing component can be accurately evaluated, and the output rates Rc and Rc2 can be set so that the required estimation accuracy is obtained. .

Further, in the above description, the case where M is fixed and N is reduced to improve the followability is described. However, by fixing N and M is reduced, the followability can be improved. However, when N and M in the normal state are the same as each other and the tracking performance at the time of output rate rise is the same (when N × M is the same), it is better to adjust N to improve the tracking performance. The output rate (sampling rate) Rc2 of the down counter 21 increases. Also, N and M at the time of output rate increase are the same, and N ×
Assuming that M is the same as each other, adjusting N can set the sampling rate Rc of the up / down counter 21 in the normal state to be higher. Therefore, as described above,
The configuration for adjusting N is better than the configuration for adjusting M,
It is possible to prevent aliasing components from being mixed into the DC offset estimation value, and to obtain a more accurate DC offset estimation value.

In the following, the DC offset compensating circuit 1
The configuration example of each section will be described in detail. That is, in the present embodiment, the ADC 5 outputs a two's complement digital value, and the MSB (Most Significant Bit) of the ADC 5 indicates the sign of the output value. Therefore, a signal indicating the MSB is input to the up / down counter 21. The up / down counter 21 counts up when the MSB is “0”, and counts down when the MSB is “0”. Further, the DC offset compensating circuit 1 according to the present embodiment is provided with a code detector 13 for detecting that the output value of the ADC 5 is a specific code indicating “0”. When the zero determination signal output from the code detector 13 indicates “0”, the count value is maintained regardless of the value of the MSB. Thus, the up / down counter 21 can count up only when the output value of the ADC 5 is larger than 0, and can count down only when the output value is smaller than 0.

Further, the DC offset compensating circuit 1 according to the present embodiment counts the synchronization signal input to the ADC 5 and outputs the ADC 5 by a counter or the like which resets its own count value when the number reaches a predetermined number. A control circuit 14 is provided for instructing the up / down counter 21 to reset 0 every time the value is output N times. Thus, the up / down counter 21 operates at the predetermined period (A
The count value is set to 0 every N times the sampling period of DC5).
Can be reset.

The up / down counter 21 according to the present embodiment also outputs a digital value in two's complement notation, like the ADC 5. Further, the up / down counter 21 includes a circuit similar to the code detector 13, and can output a zero determination signal. Therefore, the count value M
By the signal indicating SB and the zero determination signal, ｛−1,
It can output three values of 0, +1}.

On the other hand, the moving average circuit 22 outputs a value proportional to the moving average of the output of the up / down counter 21. Here, assuming that the output value at the sampling point i in the output sequence of the up / down counter 21 is U (i), the latest M output values U up to the sampling point n are obtained.
(I) Moving average value A based on U (i−M + 1)
(I) is represented by the following equation (5): A (i) = [U (i) + U (i-1) +... + U (i-M + 1)] / M (5) Becomes

Here, each output value U (i) to U (i−M +
1) is any one of {-1, 0, +1}, so that the moving average A
Possible values of (i) are ｛-1, − (M−1) / M,
.., -1 / M, 0, 1 / M,..., 1}, and the moving average circuit 22 calculates {−M · Vr, − (M−1) as a value proportional to the moving average value.・ Vr, ...,-V
r, 0, + Vr,... (M−1) · Vr, M · Vr｝ may be output.

Therefore, the moving average circuit 22 according to the present embodiment outputs the output value without calculating the division (/ M) of the above equation (5) so that the output value can be output at the sampling time point i.
The output value O (i) of the moving average circuit 22 is calculated by the following equation (6).
As shown in the following, the calculation is performed as follows: O (i) = [U (i) + U (i-1) +... + U (i-M + 1)]. Vr (6) The proportional constant in this case is Vr /
M.

The voltage Vr is the minimum quantized DC voltage of the DC offset estimation voltage. The lower the voltage Vr is, the more accurately the DC offset estimation amount can be expressed. This increases the time it takes to reduce the tracking performance. Therefore, the value of the voltage Vr is set so as to balance the accuracy and the followability when estimating the DC offset according to the accuracy and the follow-up performance required for the system including the ADC 5.

Here, for example, in the configuration example shown in FIG.
In order to hold the MSB of and the value of the zero determination signal,
Each of them has M stages of shift registers 31 and 32.

In this configuration example, the shift register 31
Are realized by an M-bit shift register, and the MSB is input from the up / down counter 21 to the first-stage latch circuit of the shift register 31. In addition, a clock signal having the same rate as the output rate Rc of the up / down counter 21 is applied to each latch circuit (none of which is shown) constituting the shift register 31 from, for example, the control circuit 14 or the like. The pulse application timing of the clock signal is determined by the up / down counter
Is set so as to include the data fetch timing of the first-stage latch circuit during the period of outputting the value (more precisely, the MSB thereof) counted based on the N outputs of the latch circuit. Acquires the MSB of the up / down counter 21 or the output of the preceding latch circuit at the data fetch timing and holds it until the next data fetch timing. Thereby, the shift register 31 outputs the output rate Rc of the up / down counter 21.
At the same output rate Rc as the output of each latch circuit, the MSB of the up-down counter 21 for the latest M times
Can be output.

Similarly, the shift register 32 is also realized by an M-bit shift register, and each latch circuit of the shift register 32 controls the value of the zero determination signal of the up / down counter 21 or the latch of the preceding stage at the data fetch timing. The output of the circuit is obtained and held until the next data fetch timing. Thus, the shift register 32 determines the output rate R of the up / down counter 21.
At the same output rate Rc as c, the value of the zero determination signal of the up-down counter 21 for the latest M times can be output as the output of each latch circuit. It should be noted that the clock signal applied to the shift register 32 is
The output rate is the same as the output rate Rc.
It is set so that the zero determination signal of the value counted based on the output of N times of 5 is taken in.

Further, the moving average circuit 22a has a voltage ｛−M · Vr, − (M−
1) Vr, ..., -Vr, 0, + Vr, ... (M-1)
Vr, M · Vr}, a switch 34 for selecting one of these voltages and outputting the selected voltage to the integration circuit 23 shown in FIG. A logic circuit 35 for controlling the switch 34 is provided so as to output the voltage O (i) represented by the above equation (6) based on the output of each latch circuit.

The logic circuit 35 may be constituted by, for example, a logic circuit so as to output a truth table derived from a combination of an output of each latch circuit and a control signal to the switch 34. If j is an integer from 1 to M based on the output of each latch circuit and an up / down counter that is reset before the operation of the output value O (i) starts, if U (i−j + 1) is positive A logic circuit instructing the up / down counter to count up, and instructing a countdown when U (i−j + 1) is negative, and, for example, j instructing the logic circuit by the output rate Rad of the ADC 5 by 1 And a control circuit that changes from M to M. The count value of the up / down counter in the logic circuit 35 is increased / decreased by M times within a cycle shorter than the output cycle of the up / down counter 21.
May be maintained.

As a result, the moving average circuit 22a calculates the most recent M outputs (MSB, value of the zero determination signal) of the up / down counter 21 = ｛(0,0), (0,1), (1,
0)}, the output value U (i) = {− 1, 0, +1}
And a value O (i) proportional to the moving average value A (i) of the output value U (i) can be output to the integration circuit 23 as a voltage signal.

In the above description, both shift registers 31.
32 is an M-stage shift register, and a logic circuit 35
Described the case where the switch 34 is controlled based on the output of each stage of the shift registers 31 and 32. However, each is configured by an M-1 stage shift register, and the logic circuit 35 The switch 34 may be controlled based on the input and the output of each stage of the shift registers 31 and 32. In this case, shift register 3
The number of stages of 1.32 can be reduced by one, and the integration circuit 23
Is provided with an output value advanced by one sample point from the configuration of the M stages.

In the above description, the power supply 33 and the switch 34
And the voltage ｛−M · Vr, − (M−1) ·
Vr, ...,-Vr, 0, + Vr, ... (M-1) Vr,
Although the voltage specified by the logic circuit 35 is output from M · Vr｝, the voltage specified by the logic circuit 35 may be output by, for example, a DA converter.

Further, when simplification of the configuration is particularly required, the output of the moving average circuit 22a is binarized or ternary, and is limited to, for example, ternary {-Vr, 0, + Vr}. Good. In this case, although the accuracy of estimating the DC offset is reduced, the number of voltages output from the power supply 33 can be reduced and the amount of operation of the logic circuit 35 can be reduced, so that the circuit configuration can be greatly simplified.

In the above description, the moving average circuit 22a
Calculates the output value O (i) based on equation (6),
That is, the logic circuit 35 of the moving average circuit 22a
M output values U (i-M) of the up-down counter 21
+1) to U (i) have been described,
Other configurations may be used as long as a value proportional to the moving average value A (i) can be output.

For example, when the above equations (5) and (6) are transformed into a recurrence equation, as shown in the following equations (7) and (8), A (i) = A (i-1) ) + [U (i) -U (iM)] / M (7) O (i) = O (i-1) + [U (i) -U (iM)]. Vr (8) .

Therefore, the logic circuit 35 shown in FIG.
Can be configured by an up-down counter that holds the accumulated value of U (i) -U (iM). In this case, the logic circuit 35 obtains U (i) from the input to the first-stage latch circuit of both shift registers 31 and 32, and U (i−) from the last-stage latch output of both shift registers 31 and 32.
M). Further, the logic circuit 35 includes U (i)
Is "+1", the up / down counter counts up, and if "-1", it counts down. The logic circuit 35 counts up if U (iM) is "+1", and counts down an up-down counter if U (iM) is "-1". In this case, the up / down counter of the logic circuit 35 is counted up / down / maintained twice every output cycle of the up / down counter 21.

Thus, the up / down counter has:
The accumulated value of U (i) -U (iM) is held as a count value. Therefore, based on the count value, the switch 3
By switching 4, the moving average circuit 22a can output a value O (i) proportional to the moving average value A (i).

As another configuration example, accumulation may be performed by a switched-capacitor type integration circuit, such as a moving average circuit 22b shown in FIG. More specifically, the moving average circuit 22b includes M-stage shift registers 41 and 42, like the two shift registers 31 and 32 shown in FIG.
A power supply 43 that outputs three voltages of Vr, 0, and + Vr, a switch 44 that selects and outputs one of the three voltages output by the power supply 43, and both shift registers 41 and 42
Based on the input to the first-stage latch circuit and the output of the last-stage latch circuit of both shift registers 41 and 42.
A logic circuit 45 for controlling the switch 44 and a switched-capacitor-type integration circuit 46 for accumulating the output of the switch 44 are provided. Note that the switch 44, the logic circuit 45, and the switched-capacitor-type integration circuit 46 correspond to the calculating means described in the claims.

In this embodiment, the logic circuit 45
Is the first of the output periods of the up / down counter 21.
In the period, when U (i) is "+1" based on the input to the first-stage latch circuits of both shift registers 41 and 42, switch 44 selects voltage Vr. Also, U
If (i) is "0", the switch 44 selects the voltage 0 (ground level), and if "-1", the switch 44 selects the voltage -Vr. Further, the logic circuit 45 sets U (iM) to "+1" based on the outputs of the last-stage latch circuits of both the shift registers 41 and 42 in the remaining second period of the output cycle of the up / down counter 21. ", 0," -1 "
The switch 44 selects the voltage + Vr, the voltage 0, and the voltage −Vr according to which of Further, the moving average circuit 22b according to the present embodiment is provided with a sample-and-hold circuit 47 for holding the output value of the switched-capacitor type integration circuit 46. Thereby, the switch 44
And the sampling rate (2 · Rc) of the switched capacitor type integrator 46 is equal to the original sampling rate R
c, and the moving average circuit 22b can output an output value O (i) proportional to the moving average value at the sampling rate Rc.

The switched capacitor type integrating circuit 46
The configuration example and operation of the operational amplifier 51 will be described in more detail. For example, the switched-capacitor-type integrating circuit 46 includes an operational amplifier 51 having a non-inverting input terminal grounded, and an inverting output terminal and an output terminal of the operational amplifier 51. A feedback capacitor (holding means) 52, an input capacitor 53 having one end grounded, and a switch 54 for selectively connecting the other end of the input capacitor 53 to one of the switch 44 and one of the inverting input terminals of the operational amplifier 51. Is provided.

In the above configuration, immediately before the sampling time point i, the switched capacitor type integrator 46
The output value O proportional to the moving average value at the sampling time point (i-1) is calculated as the amount of charge stored in the feedback capacitor 52.
(I-1) is accumulated.

In this state, when the up / down counter 21 outputs the output value U (i) as a combination of the MSB and the value of the zero determination signal at the sampling time i, the logic circuit 45 outputs
The switch 44 is switched. Thereby, U (i) × V
The voltage of r is applied to the switched-capacitor type integration circuit 46. On the other hand, the switch 54 of the switched-capacitor-type integrator 46 is connected to the switch 4 at least partially while the switch 54 is applied with the voltage of U (i) × Vr.
4 and the input capacitor 53 are connected. As a result, charges proportional to the voltage of U (i) × Vr are accumulated in the input capacitor 53.

Further, while the voltage of U (i) × Vr is being input to the switched-capacitor-type integrator circuit 46, for example, at the time when one-fourth of the sampling period has elapsed from the sampling time i, the switch 54 For example, switching is performed based on an instruction from the logic circuit 45 or the like, and the input capacitor 53 is connected to the feedback capacitor 52 while retaining the charge. Thereby, the feedback capacitor 5
In 2, charges corresponding to the voltage of O (i−1) + U (i) × Vr are accumulated.

On the other hand, at the time when the second period is started, for example, at the time when half the sampling period has elapsed from the sampling time i, the logic circuit 45
U (i−M) is obtained from the output of the last-stage latch circuit of the shift registers 41 and 42, and the switch 44 outputs a voltage of −U (i−M) × Vr according to the instruction of the logic circuit 45. Further, the switch 54 is switched to the switch 44 side, and a charge corresponding to a voltage of −U (i−M) × Vr is accumulated in the input capacitor 53. Further, for example, 3/4 of the sampling period from the sampling point i
When the voltage of −U (i−M) × Vr is being input, for example, when the switch 54
The input capacitor 53 is connected to the feedback capacitor 52 while retaining the charge. As a result, the feedback capacitor 52 has O (i-1) + U
The charge corresponding to the voltage of (i) × Vr−U (i−M) × Vr is accumulated, and the switched-capacitor type integration circuit 46
The voltage is output.

The sample-and-hold circuit 47 operates, for example, at 3/4 of the sampling period from the sampling point i.
, And the switched-capacitor-type integrator 46 performs O (i−1) + U (i) × Vr−, for example, any time from the time when the time has elapsed to the time immediately before the sampling time (i + 1).
At the time when the voltage of U (i−M) × Vr is being output, the output of the switched capacitor type integration circuit 46 is sampled and held until the next sampling time. Thus, the moving average circuit 22b can output the output value O (i) proportional to the moving average value at the same output rate Rc as the up / down counter 21.

In the above configuration, the power supply 43 provided in the moving average circuit 22b outputs 2M + 1 voltage values す べ き −M · Vr, − (M−1) · V to be output by the moving average circuit 22b.
r, ...,-Vr, 0, + Vr, ... (M-1) Vr, M
・ Three voltage values {−Vr, 0, + V less than Vr}
Although only r 回路 is output, the moving average circuit 22
b can output 2M + 1 types of voltage values. Therefore, by adopting the configuration of FIG. 5, when the power supply cannot be shared with other circuits, and the circuits for the power supplies 33 and 43 are newly required, the circuit can be simplified as compared with the configuration of FIG.

The moving average circuit 22b shown in FIG.
Since +1 voltage values can be output, in the configuration of FIG. 4, the moving average circuit 22a rounds the output value O (i) proportional to the moving average value, and outputs the outputtable voltage values as ｛−Vr, 0,
Unlike the configuration in which the value is limited to three values of + Vr｝, the circuits for the power supplies 33 and 43 can be simplified without lowering the followability.

In the above description, U (i), U (i-M)
Switch 4 to calculate the term corresponding to each of
4 and the switched-capacitor-type integrating circuit 46 operate at a rate twice the output rate Rc of the up / down counter 21, but the logic circuit 45 performs the operation of {U (i) −U
(I−M)｝ / 2 is calculated, and 3 of {−1, 0, +1} is calculated.
The value may be rounded, and a voltage corresponding to this value may be supplied to the switched capacitor type integrator circuit 46 at a rate of Rc. In this case, the output rate of the switched-capacitor-type integration circuit 46 becomes Rc, so that the sample-and-hold circuit 47 can be omitted.

On the other hand, the integrating circuit 23
A circuit for integrating the output value O (i) of (22a / 22b) to obtain an estimated DC offset value,
As long as (i) can be integrated, a switched-capacitor-type integration circuit similar to the switched-capacitor-type integration circuit 46 of the moving average circuit 22b may be used, or an operational amplifier having a non-inverting input terminal grounded and an inverting input terminal of the operational amplifier. And an integration circuit including a feedback capacitor provided between the output terminal and a resistor provided between the input terminal of the integration circuit 23 and the inverting input terminal of the operational amplifier.

The integrating circuit 23 is realized by a digital circuit such as an accumulator (accumulator) including a register and an adding circuit. A DA converter is provided after the integrating circuit 23, and the subtracting circuit of the filter 3 is provided. 11, the subtraction amount may be instructed. In this case, the moving average circuit 22 (22
a.22b) may output a digital value to the integration circuit 23. For example, as in the moving average circuit 22a shown in FIG.
In the case of a configuration that outputs a value proportional to (i), the power supply 33 and the switch 34 may be deleted, and the output of the logic circuit 35 may be provided to the integration circuit 23.

Furthermore, when simplification of the circuit scale is particularly required, it is preferable that the moving average circuit 22 (22a) binarize and output the output value O (i) of the moving average circuit 22 (22a). In this configuration, since the integration circuit 23 can be configured by an up-down counter instead of an accumulator, the circuit scale can be reduced. Furthermore, the dynamic range of the integrating circuit 23 (range in which overflow does not occur) is reduced as compared with the case where more bits are input without binarization or ternarization, and the number of bits when storing the integration result is reduced. Less.
As a result, the number of bits (the number of register stages) of the integration circuit 23 can be reduced, and the circuit scale can be significantly reduced.

The up / down counter 21 may have any configuration as long as it can count up or down N times without overflowing. Where N
Is equal to a power of two, the up-down counter 21
The number of bits required for the operation increases. Specifically, for example, if N = 512, the up-down counter 21
May take a count value of -512 to +512. Here, with a bit width of 10 bits, -511 to +
Since it is only possible to count up to 511, in order to count completely, the up / down counter 21 needs to have a bit width of at least 11 bits. here,
In order to increase the bit width of the up / down counter 21 by one bit, a sequential circuit such as a flip-flop circuit and a logic circuit such as an AND gate and an OR gate are required, so that the circuit scale increases. On the other hand, if the output rate Rc (= Rad / N) is reduced without changing M,
Since N × M becomes low, the low frequency component of the signal passing through the filter 3 may affect the DC offset estimation value. Therefore, when N is a power of 2 and is sufficiently large, if n is an integer of 1 or more, the up / down counter 21 actually counts while keeping the output rate at Rc = Rad / N. What is necessary is just to set the number Nc of outputs of the ADC 5 to N−n.

In this configuration, the up / down counter 21
, The number of bits of the up / down counter 21 can be reduced, and the circuit size can be reduced. For example, when N = 512, Nc = 5
By setting to 11, the bit width of the up / down counter 21 can be reduced to 10 bits, and the circuit scale can be reduced. Even in this case, since the up / down counter 21 outputs the three values {-1, 0, +1}, the output does not change even if the actual count value is reduced by several. Therefore, the circuit scale can be reduced without lowering the DC offset estimation accuracy. In order to suppress a decrease in accuracy, n is optimally 1.

In each of the above configurations, the up-down counter 21 outputs “+1” when the positive value of the counted output values of the ADC 5 is larger than the negative value, and outputs the value “+1”. If the number is larger, "-1" is output, and if the number is the same, "0" is output. Therefore, instead of the up / down counter 21, the MSB of the output value of the ADC 5 and the output value of the code detector 13 are respectively set to N
And a majority circuit that determines whether the output of the ADC 5 in the N-sample period has a large number of positive values or a large number of negative values based on the output of each stage of the shift register. Good. Up / down counter 21
If the same function (input / output) can be realized, the same effect can be obtained.

If the improvement of the estimation accuracy of the DC offset is prioritized over the reduction of the circuit scale, the up / down counter 21 sets the moving average circuit 22 (22a ·
To 22b), not only the values of the MSB and the zero determination signal, but also a plurality of upper bits or all bits may be output. Further, when it is required to further improve the estimation accuracy of the DC offset, an addition / subtraction circuit may be used instead of the up / down counter 21 and addition / subtraction may be performed using a plurality of upper bits or all outputs of the ADC 5. In these cases, the moving average circuit 22 (22a, 22b) is provided with a shift register having a bit width corresponding to the output bit width of the up / down counter 21 instead of the shift registers 31 and 32 or the shift registers 41 and 42. For example, it is necessary to hold M output values. In addition, the number of voltages output from the power supply 33 and the operation of the logic circuit 35, or the operation of the logic circuit 45 and the cycles of the switch 44 and the switched-capacitor-type integrator 46 are determined by the moving average circuit 22 (22a and 22b) by M Based on these output values, the setting is made so that O (i) shown in the above-described equations (6) and (8) can be output. According to these configurations, the estimated amount of the DC offset can be accurately calculated, and similarly to the above-described configurations, there is no need to separately provide a narrow-band low-pass filter, so that the circuit scale can be reduced.

In each of the above-described configurations, the up-down counter 21 maintains the count value when the output value of the ADC 5 is “0”. If the width is small, ADC5
Does not always output 0, and the output value of ADC5 is 0.
Is extremely low. In this case, the code detector 13
, The DC offset can be estimated with substantially the same estimation accuracy. Further, in this case, by setting the actually counted number Nc to an odd number, the output value of the up / down counter 21 can be limited to two values of {-1, + 1}. Therefore, the circuit configuration of the moving average circuit 22 (22a · 22) can be simplified. Specifically, in the moving average circuit 22a (22b) shown in FIG. 4 (FIG. 5), the shift register 32 (42) can be omitted, and 0 output can be omitted from the power supply 33 (43). Further, with the simplification, the circuit scale of the logic circuit 35 (45) can be reduced. Even when Nc is an even number, if the frequency of the output value of the up / down counter 21 is extremely low, the output value 0 is regarded as “+1” or “−1”, and May be limited to the two values {-1, + 1}.

In each of the above configurations, the DC offset compensation circuit 1 (1a) applies the voltage indicating the DC offset estimation value to the subtraction circuit 11 in the filter 3 to subtract the DC offset estimation value. If the additional band component of the filter 3 in the signal input to the filter 3 via the input terminal T1 is sufficiently small, the filter 3 may be deleted. In this case, the signal input from the input terminal T1 is
The signal is applied to the ADC 5 via the subtraction circuit 11.

In each of the above configurations, the ADC 5 has been described as an example of a circuit subject to DC offset compensation.
It is not limited to this. The present invention can be applied to any circuit that causes a DC offset. For example, as shown in FIG. 6, when the analog circuit 7 is to be compensated, the signal input from the input terminal T1 is
Is applied to the analog circuit 7 via the.

Here, unlike the ADC 5, the analog circuit 7 does not output a digital value. Accordingly, the DC offset compensating circuit 1b is provided with a quantizing circuit (comparator) 16 for quantizing the output value of the analog circuit 7 into a binary or ternary value.
Counts according to the output of the quantization circuit 16. For example, in the case of a configuration for performing quantization to binary, the quantization circuit 16
It is composed of a comparator that compares the voltage 0 (ground level) with the output of the analog circuit 7 and determines whether the output of the analog circuit 7 is positive or negative. On the other hand, up-down counter 2
When 1 is positive, the count value is counted up, and when negative, the count value is counted down.

In the case of a ternary quantization configuration, the quantization circuit 16 is composed of two comparators for comparing -Vz and + Vz with the output of the analog circuit 7, respectively. Is ｛−Vz or less, −
From Vz to + Vz, it is determined which of the three ranges from + Vz to｝ is included. On the other hand, the up / down counter 21 counts down when a signal indicating −Vz or less is output, and counts down when a signal indicating + Vz or more is output. Note that from −Vz to + Vz
In the case between, the count value is maintained.

Regardless of the quantization, the quantization circuit 16 includes a latch circuit for holding the output when the output value cannot be held for a time sufficient for input to the up / down counter 21. You may.

Regardless of the presence or absence of the latch circuit, the up / down counter 21 counts up / down / maintains at the sampling rate Rc × N. Therefore, the up / down counter 21 performs time sampling at the sampling rate Rc × N. The output rate R
At c, an output value U (i) is output. On the other hand, the moving average circuit 22 applies a value O (i) proportional to the moving average value to the integrating circuit 23 based on the output value U (i) of the up / down counter 21, and the integrating circuit 23 2
A value proportional to the integral value of the output of the second output is applied to the subtraction circuit 11 as a DC offset estimated value. This allows the ADC
DC offset can be compensated in the same manner as in the case where 5 is the compensation target.

In each of the above configurations, if a DA converter is provided in a signal path before the ADC 5 and the analog circuit 7, it is preferable to arrange the subtraction circuit 11 in front of the DA converter and perform subtraction in the digital domain. . In this case, since the subtraction is performed in the digital domain, unlike the case where the subtraction is performed in the analog domain, unnecessary components such as thermal noise do not enter the input terminal of the DC offset estimation amount.
Therefore, mixing of unnecessary components can be prevented, and the accuracy of DC offset compensation can be improved.

In this case, since the subtraction is performed in the digital domain, similarly to the case where the integration circuit 23 is implemented by a digital circuit, for example, the logic circuit 35 is provided with a digital value like the moving average circuit 22a shown in FIG. Moving average value A
In the case of a configuration that outputs a value proportional to (i), the power supply 33 and the switch 34 may be deleted, and the output of the logic circuit 35 may be provided to the integration circuit 23. In this case, the integrating circuit 23 as an accumulator converts the accumulated value into a digital subtraction circuit 11.
To indicate the amount of subtraction.

[0112]

As described above, in the DC offset compensation circuit according to the present invention, when the predetermined integer of 1 or more is N and the integer of 2 or more is M, the sample of the discrete time output of the circuit to be compensated is Integrating means for integrating the discrete time output over N × M times of the cycle and outputting the output every N times of the sample cycle; and integrating the output of the integrating means to obtain a signal indicating the DC offset amount. And output means for outputting.

According to the above configuration, the integrating means outputs the integration result of N times the sample period, despite outputting the result of integrating the discrete time output over N × M times the sample period. Since the output is made in a cycle, the output rate of the integrating means is
The result of integrating the discrete time output over N × M times the sample period is M times as large as that of an integrating circuit that outputs the result every N × M times of the sample period. Therefore, despite having the same low-pass type frequency characteristics as the integration circuit of the comparative example, the amount of attenuation at the Nyquist frequency can be increased and the aliasing component can be reduced as compared with the comparative example. As a result,
There is provided an effect that the DC offset amount can be estimated with sufficient accuracy even though the filter circuit is not provided in the preceding stage of the integrating means and the circuit is relatively small.

The DC offset compensation circuit according to the present invention
As described above, when a predetermined integer equal to or greater than 1 is N, the sample period of the discrete time output of the compensation target circuit is N
A first integrating means for outputting an output value proportional to a value obtained by integrating substantially N discrete time outputs, and an output of the first integrating means when a predetermined integer of 2 or more is M Storage means for storing the latest M or M-1 of the values, and an output proportional to a value obtained by integrating the M output values of the first integration means with reference to the storage of the storage means. A second integration means for outputting a value in a cycle shorter than M times an output cycle of the first integration means, and an output for integrating the output of the second integration means and outputting a signal indicating the DC offset amount Means.

According to this configuration, each output of the second integrating means depends on the M outputs of the first integrating means, but has a cycle shorter than M times the output cycle of the first integrating means. Is output. Therefore, when compared with a configuration in which the second integration means outputs an output value at a cycle M times the output cycle of the first integration means, the Nyquist The attenuation at the frequency can be increased. As a result, there is an effect that the DC offset amount can be estimated with sufficient accuracy despite the relatively small circuit scale without providing a filter circuit for reducing aliasing components.

The DC offset compensation circuit according to the present invention
As described above, when a predetermined integer equal to or greater than 1 is set to N instead of the above-described first integration circuit, approximately N times of the discrete time output is obtained at every N times of a fixed sampling period of the discrete time output. This is a configuration in which first integration means for outputting an output value obtained by converting a value obtained by integrating the two values into a binary value or a ternary value is provided.

In this configuration, although rough quantization such as binarization or ternarization is performed, each output of the second integration means depends on the M outputs of the first integration means. Are output in a cycle shorter than M times the output cycle of the first integration means. Therefore, as described above, even if the second integrator has the same low-pass frequency characteristic as compared with a configuration in which the second integrator outputs an output value at a period M times the output period of the first integrator, Regardless, the amount of attenuation at the Nyquist frequency can be increased. As a result, there is an effect that the DC offset amount can be estimated with sufficient accuracy despite the relatively small circuit scale without providing a filter circuit for reducing aliasing components.

A DC offset compensating circuit according to the present invention
As described above, in addition to each of the above configurations, the second integration means outputs an output value in an output cycle of the first integration means.

In this configuration, the output rate of the second integration means is increased by a factor M compared to a configuration in which the second integration means outputs an output value at a period M times the output cycle of the first integration means. Can be. As a result, the amount of attenuation at the Nyquist frequency can be set to be larger, and the effect that the aliasing component can be further reduced can be obtained.

A DC offset compensating circuit according to the present invention
As described above, in each of the above-described configurations, the second integrating means holds the output value of the immediately preceding second integrating means and the second integrating means calculates the next output value of the second integrating means. (1) arithmetic means for adding a value proportional to the current output value of the integration means to the value held by the holding means, reading the oldest output value from the storage means, and subtracting from the value held by the holding means; It is a configuration provided with.

According to this configuration, the calculating means adds a value proportional to the current output value of the first integrating means to the output value of the second integrating means immediately before being held by the holding means, and A value proportional to the oldest output value of the means is subtracted to calculate the next output value of the second integrating means. Therefore, the amount of calculation can be reduced as compared with a configuration in which M output values of the first integration means are added and an output value proportional to the addition result is output for each output cycle of the second integration means. There is an effect that the circuit scale of the calculation means can be reduced.

The DC offset compensation circuit according to the present invention
As described above, in addition to the above configuration, the second integration means is configured to provide a binarized or ternary output value to the output means. According to this configuration, since the output of the second integration means is binarized or ternary, the circuit scale of the second integration means itself and the circuit scale of the output means at the subsequent stage can be significantly reduced. As a result, there is an effect that a DC offset compensation circuit having a small circuit scale can be realized.

A DC offset compensating circuit according to the present invention
As described above, in addition to the above configuration, the configuration is provided with the N value setting means for changing the value of N. According to this configuration, there is an effect that the following speed can be changed when the DC offset compensation circuit estimates the DC offset amount, depending on the value of the value set as N.

A DC offset compensating circuit according to the present invention
As described above, when the power of the circuit is turned on or when the circuit is restored from the halt state, the N value setting means sets the N value for a fixed time.
Is set to a value smaller than the normal value, and is returned to the normal value after the predetermined time has elapsed.

According to the above configuration, the N-value setting means sets the value of N to a value smaller than the normal value for a fixed time when the power is turned on or when returning from the sleep state. Without distortion, it is possible to surely compensate for the DC offset of the circuit when the power is turned on or when returning from the sleep state.

A DC offset compensating circuit according to the present invention
When the circuit outputs an analog signal, the estimating unit calculates a result obtained by discrete-time sampling the analog signal,
This is a configuration including a comparator that outputs the discrete-time output.

According to the above configuration, the comparator converts the analog signal into a discrete time and discrete value output. Therefore, even if the circuit for which the DC offset is to be compensated outputs the analog signal, the comparator converts the analog signal into a discrete value. There is an effect that the DC offset can be compensated without any trouble.

[Brief description of the drawings]

FIG. 1 illustrates an embodiment of the present invention, and is a block diagram illustrating a main configuration of a DC offset compensation circuit and a circuit that compensates for a DC offset by the DC offset compensation circuit.

FIG. 2 is a graph showing a frequency characteristic of a transfer function of a circuit including an up-down counter and a moving average circuit provided in the DC offset compensation circuit.

FIG. 3 illustrates another embodiment of the present invention, and is a block diagram illustrating a main configuration of a DC offset compensation circuit and a circuit that compensates for a DC offset by the DC offset compensation circuit.

FIG. 4 is a block diagram illustrating a configuration example of a moving average circuit provided in the DC offset compensation circuit.

FIG. 5 is a circuit diagram showing another configuration example of the moving average circuit.

FIG. 6 is a block diagram showing a modification of the DC offset compensating circuit, and showing a main configuration of a circuit for outputting an analog signal and a DC offset compensating circuit for the circuit.

FIG. 7 is a block diagram illustrating a related art, showing a main configuration of a DC offset compensating circuit and a circuit for compensating for a DC offset by the DC offset compensating circuit.

[Explanation of symbols]

1. 1a DC offset compensation circuit 5 AD converter (circuit) 7 Analog circuit (circuit) 11 Subtraction circuit (subtraction means) 12 Integration processing section (estimation means) 15 DC offset fluctuation determination section (N value setting means) 16 Quantization Circuit (comparator) 21 Up / down counter (integrating means, first integrating means) 22 · 22a / 22b Moving average circuit (integrating means, second integrating means) 23 Integrating circuit (output means) 31 · 32 · 41 · 42 Shift register (Storage means) 44 Switch (arithmetic means) 45 Logic circuit (arithmetic means) 46 Switched capacitor type integration circuit (arithmetic means) 52 Feedback capacitor (holding means)

Claims (9)

[Claims] An estimating means for estimating a DC offset amount based on a discrete time output of a circuit to be compensated for a DC offset, and a DC offset provided on a signal path of the circuit and estimated by the estimating means. A DC offset compensating circuit having a subtracting means for subtracting an amount, wherein the estimating means is such that when a predetermined integer of 1 or more is N and an integer of 2 or more is M, Integrating means for integrating the discrete-time output over N × M times of the above, and outputting the signal every N times the sample period; integrating the output of the integrating means to output a signal indicating the DC offset amount A DC offset compensating circuit, comprising: 2. An estimating means for estimating a DC offset amount based on a discrete time output of a circuit to be compensated for a DC offset, and a DC offset disposed on a signal path of the circuit and estimated by the estimating means. A DC offset compensating circuit having a subtracting means for subtracting an amount, wherein the estimating means, where N is an integer equal to or greater than a predetermined one, every N times a fixed sample period of the discrete time output. A first integrating means for outputting an output value proportional to a value obtained by integrating approximately N time outputs;
A storage means for storing the latest M or M-1 of the output values of the integration means; and a value obtained by integrating M output values of the first integration means with reference to the storage of the storage means. A second integration means for outputting an output value proportional to the following in a cycle shorter than M times the output cycle of the first integration means; a signal indicating the DC offset amount by integrating the output of the second integration means A DC offset compensating circuit comprising: 3. An estimating means for estimating a DC offset amount based on a discrete time output of a circuit to be compensated for a DC offset, and a DC offset disposed on a signal path of the circuit and estimated by the estimating means. A DC offset compensating circuit having a subtracting means for subtracting an amount, wherein the estimating means, where N is an integer equal to or greater than a predetermined one, every N times a fixed sample period of the discrete time output. A first integrating means for outputting a binary or ternary output value obtained by integrating a value obtained by integrating approximately N pieces of time output; and a first integer when M is a predetermined integer of 2 or more.
A storage means for storing the latest M or M-1 of the output values of the integration means; and a value obtained by integrating M output values of the first integration means with reference to the storage of the storage means. A second integration means for outputting an output value proportional to the following in a cycle shorter than M times the output cycle of the first integration means; a signal indicating the DC offset amount by integrating the output of the second integration means A DC offset compensating circuit comprising: 4. The DC offset compensation circuit according to claim 2, wherein said second integration means outputs an output value in an output cycle of said first integration means. 5. The second integration means includes a holding means for holding the output value of the immediately preceding second integration means, and a current value of the first integration means when calculating the next output value of the second integration means. Computing means for adding a value proportional to the output value of the storage means to the value held by the holding means, reading the oldest output value from the storage means, and subtracting from the value held by the holding means. 5. The DC offset compensation circuit according to claim 2, wherein: 6. The DC offset compensating circuit according to claim 2, wherein said second integrating means supplies a binarized or ternary output value to said output means. 7. The DC offset compensation circuit according to claim 1, further comprising N value setting means for changing the value of N. 8. The N value setting means sets the value of N to a value smaller than a normal value for a certain time when the power of the circuit is turned on or when the circuit returns from a halt state. The DC offset compensating circuit according to claim 7, wherein the DC offset is restored to the normal value. 9. The circuit according to claim 8, wherein said circuit outputs an analog signal, and said estimating means includes a comparator which outputs a result obtained by sampling the analog signal in discrete time as the discrete time output. Terms 1, 2, 3,
The DC offset compensation circuit according to 4, 5, 6, 7 or 8.