JP2001004681A - Charge detector - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce thermal noise and an offset so as to detect charge with high precision by providing a circuit in which a reset switch separate from a reset switch connecting an output terminal and a negative input terminal of an operational amplifier together and a separate capacitor element are connected in series. SOLUTION: A charge input terminal 101 is connected to the ground potential via a capacitor C1 and to a negative input terminal in an operational amplifier circuit 130. The input terminal 101 and an output terminal of the circuit 130 are connected together via a first reset switch 104. A feedback circuit constructed of a second reset switch 105 and aΦRS2 feedback capacitor element C2 is connected to the reset switch 104 in parallel. A reset pulse θ RS1 is impressed to a control terminal 114 in the first reset switch 104, while a second reset pulse ϕRS% is impressed to a control terminal 115 in the second reset switch 105. A capacitor element C3 is connected between a terminal 200 connecting the switch 105 and the feedback capacitor element C2 together and a ground electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge detection device, and more particularly to a signal charge detection device that requires high-precision signal charge detection used in a solid-state imaging device, a comparator for an analog-to-digital converter (ADC), and the like. Related to the device.

[0002]

2. Description of the Related Art Conventionally, as a signal charge detecting device as described above, a change in an input voltage signal is injected into a circuit as a signal charge via a capacitor, and an input voltage is input using the injected signal charge. A method of calculating the amount of change in the above has been proposed and put into practical use.

[0003] In recent years, in a CMOS circuit which has been remarkably developed, a capacitive element can be easily formed in a semiconductor process. Therefore, an analog circuit using the capacitive element is actively developed and used.

[0004] For example, Japanese Patent Application Laid-Open No.
Japanese Patent Application Publication No. 02118 discloses a comparator circuit configured to inject electric charge into a MOS inverter circuit via a capacitor, and further discloses a method of reducing noise of the comparator circuit.

A further application example is disclosed in Japanese Patent Application Laid-Open No. 58-10 / 1983.
No. 4524 discloses an AD converter using the above comparator circuit.
A method for configuring C is disclosed.

[0006]

However, in these conventional techniques, there is a problem that thermal noise generated when initializing (resetting) the electric charge accumulated in the input capacitance element is large, and this is alleviated. To do so, it was necessary to increase the size of the capacitive element for human input.

Therefore, there is a problem that the input capacitance of the circuit becomes large and power consumption at the time of driving is large, and that it is difficult to reduce the area when the circuit is integrated on a chip.

Hereinafter, the above-mentioned problem will be described more clearly by taking the comparator circuit used in the above-mentioned conventional technique as an example.

FIG. 3 shows the configuration of a typical conventional charge detection device.

As shown in FIG. 3, the charge input terminal 101 is connected to the ground potential point via a capacitor C1 and to the negative input terminal (-) of the operational amplifier circuit 130.

The negative input terminal (-) of the operational amplifier circuit 130, that is, the charge input terminal 101, and the output terminal of the operational amplifier circuit 130 are connected via a reset switch 104.

The control terminal 1 of the reset switch 104
14 is applied with a first reset pulse ΦRS1.

The reference voltage VREF is input to the positive electrode (+) side of the operational amplifier circuit 130.

The operational amplifier circuit 130 is disclosed in Japanese Unexamined Patent Publication Nos. 57-202118 and 5
There is no difference in basic operation even if the inverter circuit disclosed in JP-A-8-104527 is used.

Next, the operation of the conventional charge detecting device shown in FIG. 3 will be described with reference to a timing chart shown in FIG.

FIG. 4 shows the reset pulse ΦRS1 applied to the control terminal 114 of the reset switch 104 and the potential VIN of the charge input terminal 101 in a time-series manner along the operation sequence.

Here, for the sake of simplicity, the reset switch 104 is assumed to be closed when the reset pulse ΦRS1 has a positive logic.

First, in an initial state before time t1, the potential VIN of the charge input terminal 101 is an arbitrary potential.

When the reset pulse ΦRS1 is input at time t1 and the reset switch 104 is closed, the output terminal of the operational amplifier 130 and the negative input terminal (-) are short-circuited, so that the operational amplifier circuit 130 operates as an analog buffer circuit. Become like

For this reason, the potential VI of the charge input terminal 101
N is set to the reference voltage VREF after a finite ramping period.

Next, when ΦRS1 changes at time t2 and the reset switch 104 opens, the charge input terminal 101
It becomes a floating state in a C manner, and becomes a state in which charge can be stored.

Thereafter, by injecting the signal charge into the charge input terminal 101, a negative potential is output to the output terminal of the operational amplifier 130 when the injected charge is positive, and when the injected charge is negative, , A positive potential is output to the output terminal of the operational amplifier 130.

That is, the present charge detecting device operates as a negative output charge detecting comparator.

However, the conventional charge detecting device shown in FIG. 3 generates thermal noise ΔVIN due to the switching operation by the reset switch 104.

The thermal noise ΔVIN is equal to the charge input terminal 10
A noise voltage is generated for a capacitance value of 1 with respect to the ground, and a noise voltage represented by Expression (1) is generated as a noise average.

ΔVIN (t = t2) = SQRT (kT / C1) (1) where k is a Boltzmann multiplier and T is an absolute temperature.

Since this noise voltage is generated at random, it determines the noise detection limit of the charge detection device and causes a deterioration in detection accuracy.

Further, at the moment when the reset switch 104 is closed, the parasitic capacitance component existing between the control terminal of the reset switch 104 and the charge input terminal 101 and the charge forming the channel of the reset switch 104 cause the reset operation. Will be pushed out to the charge input terminal 101.

This is called a feed-through phenomenon. If this is present, an offset charge is equivalently generated, so that the initial potential of the charge input terminal 101 at the time of resetting deviates from a balance point as a comparator. There's a problem.

The present invention has been made in view of the above circumstances, and in order to solve the problems in the conventional charge detection device, the offset caused by thermal noise and feedthrough generated when resetting the potential of the charge input terminal. To reduce
It is an object of the present invention to provide a charge detection device capable of detecting charges with high accuracy.

[0031]

According to the present invention, in order to solve the above-mentioned problems, (1) an input terminal of a capacitive element is connected to a negative input terminal of an operational amplifier, and an output terminal of the operational amplifier and the operational amplifier are connected to each other. A charge detection device having a reset switch in a feedback circuit connecting a negative input terminal of the operational amplifier, a reset switch separate from the reset switch connecting the output terminal of the operational amplifier and the negative input terminal of the operational amplifier in parallel with the feedback circuit. And a charge detection device comprising at least one circuit in which a capacitance element different from the above-mentioned capacitance element is connected in series.

According to the present invention, in order to solve the above-mentioned problems, (2) an operational amplifier, a first capacitive element having one end connected to the negative input terminal of the operational amplifier and the other end grounded, A first feedback circuit connecting the output terminal of the operational amplifier and the negative input terminal and having a first reset switch in the middle, and a second reset circuit connecting the output terminal and the negative input terminal of the operational amplifier and connected in series in the middle A second feedback circuit having a switch and a second capacitance element; a third capacitance element having one end connected to an intermediate point between the second reset switch and the second capacitance element and the other end grounded; Is provided.

According to the present invention, in order to solve the above problems, (3) at the time of resetting, the first reset switch and the second reset switch are simultaneously turned on for a first predetermined time. Control means for turning off the first reset switch later and turning off the reset switch after a second predetermined time longer than the first predetermined time is further provided (1). ) Or (2).

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a connection diagram showing a schematic configuration of an embodiment of the charge detection device according to the present invention.

As shown in FIG. 1, the charge input terminal 101 is connected to the ground potential via the capacitor C1 and to the negative input terminal (-) of the operational amplifier circuit 130.

The negative input terminal (-) of the operational amplifier circuit 130, that is, the charge input terminal 101 and the operational amplifier circuit 1
The output terminal 30 is connected via a first reset switch 104.

A feedback circuit composed of a second reset switch 105 and a feedback capacitor C2 is connected in parallel with the first reset switch 104.

Then, a first reset pulse ΦRS1 is applied to the control terminal 114 of the first reset switch 104, and the control terminal 11 of the second reset switch 105 is
5, a second reset pulse ΦRS2 is applied.

The capacitor C3 is connected between the terminal 200 connecting the second reset switch 105 and the feedback capacitor C2 and the ground electrode.

The reference voltage VREF is inputted to the positive electrode (+) side of the operational amplifier circuit 130.

The above is the configuration of one embodiment of the charge detection device according to the present invention.

Next, the operation and the driving method of one embodiment of the charge detection device according to the present invention will be described with reference to the timing chart shown in FIG.

FIG. 2 shows reset pulses ΦRS1 and ΦRS2 applied to the control terminal 114 of the first reset switch 104 and the control terminal 115 of the second reset switch 105, and the potential VIN of the charge input terminal 101 in accordance with the operation sequence. Are shown in chronological order.

Here, for simplicity of explanation, the first reset switch 104 and the second reset switch 10
5 is to be closed when the reset pulses ΦRS1 and ΦRS2 are each positive logic.

First, in the initial state before time t1, the potential VIN of the charge input terminal 101 is at an arbitrary potential.

At time t1, reset pulses ΦRS1 and ΦRS1
When RS2 is input, the first reset switch 104
When both the second reset switch 105 and the second reset switch 105 are closed, the output terminal of the operational amplifier 130 and the negative input terminal (-) are short-circuited.

As a result, the operational amplifier circuit 130 operates as an analog buffer circuit.
The potential VIN of 01 is set to the reference voltage VREF after a finite ramping period.

Next, at time t2, the reset pulse ΦRS1
Is changed and the first reset switch 104 is opened, a thermal noise is generated at the potential VIN of the charge input terminal 101 due to the switching operation by the first reset switch 104.

This thermal noise is generated with respect to the capacitance value of the charge input terminal 101 with respect to the ground.

Since the second reset switch 105 is closed at time t2, the capacitance C2 can be equivalently regarded as the ground capacitance.

Accordingly, the thermal noise Δ generated at time t1
VIN (t = t1) is as follows: ΔVIN (t = t1) = SQRT (kT / (C1 + C2)) (2)

Here, k is a Boltzmann multiplier, and T is an absolute temperature.

In an actual circuit, an offset-like potential change is added to this due to the effect of field through caused by opening and closing of the first reset switch 104. However, for the sake of simplicity, the operation will be described below. Omitted.

Incidentally, the thermal noise generated at time t2 is input to the negative input terminal (-) of the operational amplifier circuit 130, and the operational amplifier circuit 130 transfers the generated noise charge to the feedback capacitance C2.
And the terminal potential VIN of the charge input terminal 101 is returned to the reference voltage VREF again after a finite ramping period.

Next, the terminal potential VI of the charge input terminal 101
After N is sufficiently stabilized at the reference voltage VREF, the reset pulse ΦRS2 is changed at time t3 to open the second reset switch 105 and complete the reset operation of the charge input terminal 101.

By this reset operation, the terminal 200 located between the capacitor C2 and the second reset switch 105
Thermal noise shown in equation (3) is generated, and this thermal noise
2 to the charge input terminal 101.

ΔV200 (t = t3) = SQRT (kT / (1 / ((1 / C1) + (1 / C2)) + C3)) (3) The capacitance C2 and the capacitance C1 are connected in series. From the above relationship, finally, the time t
3, the fluctuation ΔVIN (t = t3) of the terminal potential VIN of the charge input terminal 101 is expressed by Expression (4).

ΔVIN (t = t3) = (C2 / (C2 + C1)) ΔV200 (t = t3) = SQRT (kT / ((C1 + C2) × C1 / C2 + (C1 + C2) × (C1 + C2) × C3 / (C2 × C2) ))) (4) The above is the reset operation according to the embodiment of the present invention.
After the time t3, the charge accumulation operation starts, and the signal charge is input to the charge input terminal 101.

Next, the features of this embodiment will be described.

In the conventional reset circuit, since reset noise is generated for the storage capacitor C, SQRT (kT / (C
1 + C2)) occurs when the charge input terminal is reset. In the present embodiment, the noise voltage generated at time t2 is corrected using a feedback circuit, and then the feedback system is closed. It is possible to suppress noise fluctuation at the time of reset to the value shown in Expression (4).

For simplicity of explanation, Cl >> C2, C3 >>
> C2, and the storage capacitance C of the charge input terminal 101 = C1 +
If 1 / (1 / C2 + 1 / C3) is ~ C1 + C2,
The suppression ratio is expressed by Expression (5) from Expression (4) / Expression (2).

Suppression ratio = (Noise voltage of conventional method) / (Noise voltage of this embodiment) 実 施 SQRT (1 / (C1 / C2 + C1 × C3 / (C2 × C2))) (5) As an example, C1: C2 = 5: 1, C3: C2 = 10: 1
In this case, the suppression ratio is about 1/13.

Also, the offset of the initial potential due to the feed-through of the reset switch 104, which is omitted in the above description for simplicity of description, can be suppressed as shown in the equation (5), similarly to the reset noise.

Therefore, according to the present invention, not only the thermal noise generated when the charge input terminal is reset, but also the reset switch 104
This also has an effect on the suppression of the offset amount by the feedthrough.

As described above with reference to the embodiments, the present invention relates to a charge detecting device for detecting charges by inputting charges to a storage capacitor, in which a charge input terminal is connected to a negative input terminal of an operational amplifier. And a first reset switch is provided between the output terminal of the operational amplifier and the charge input terminal.

A feedback circuit in which a feedback capacitor and a second reset switch are connected in series is provided in parallel with the first reset switch.

At the time of resetting the charge input terminal, the first reset switch and the second reset switch are closed at the same time, the first reset switch is opened, and then the second reset switch is opened. To

As a result, the charge detection device of the present invention can suppress the reset noise generated in the switching operation and the fluctuation of the reset potential due to the feed-through of the reset switch, and can initialize the charge input terminal with high accuracy. At the same time, highly accurate charge detection becomes possible.

The present specification described in the above-described embodiment includes, in addition to claims 1 to 3 set forth in the appended claims, the invention as shown in Appendix 1 below. I have.

(Supplementary Note 1) In a charge detection device for inputting a charge to a storage capacitor connected to a charge input terminal and detecting a signal charge stored in the capacitor using an operational amplifier, A first reset switch provided between an output terminal of the operational amplifier having a negative input terminal connected to the terminal and the charge input terminal; a feedback capacitor provided in parallel with the first reset switch; And a feedback circuit in which a reset switch is connected in series. When the charge input terminal is reset, the first reset switch and the second reset switch are simultaneously closed, and then the first reset switch is opened. Later, by opening the second reset switch, reset noise generated in the switching operation of the first reset switch, A charge detection device configured to suppress feedthrough of a reset switch.

In the above-described embodiment, an example in which one feedback circuit in which a capacitor and a reset switch are connected in series is added to the conventional charge detection device, but the present invention is not limited to this. Instead, even if two or more feedback circuits are added, a charge detection device having the same effect can be configured using the concept of the present invention.

[0073]

Therefore, as described above, according to the present invention, it is possible to reduce the thermal noise and the offset due to the feed-through generated when resetting the potential of the charge input terminal, and to detect the charge with high accuracy. Charge detecting device can be provided.

[Brief description of the drawings]

FIG. 1 is a connection diagram illustrating a schematic configuration of an embodiment of a charge detection device according to the present invention.

FIG. 2 is a timing chart for explaining an operation and a driving method of an embodiment of the charge detection device according to the present invention.

FIG. 3 is a schematic configuration diagram of a conventional charge detection device.

FIG. 4 is a timing chart for explaining an operation and a driving method of a conventional charge detection device.

[Explanation of symbols]

 Reference numeral 101: a charge input terminal of the charge detection device; 104, a first reset switch; 105, a second reset switch; 130, an operational amplifier circuit. C1: capacitance, C2: feedback capacitance, 114: control terminal C3: capacitance.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H03M 1/08 H03M 1/08 A F term (Reference) 2G035 AA08 AA20 AB01 AC16 AD13 AD20 AD23 AD47 AD52 AD65 5J022 AA01 BA02 CA07 CA10 CF01 CF02 CF07 5J069 AA01 AA25 AA48 AA51 CA13 CA41 FA17 FA18 HA29 HA39 HA40 KA02 KA17 KA22 MA11 SA08 TA01 TA06 5J091 AA01 AA25 AA48 AA51 CA13 CA41 FA17 FA18 HA29 HA39 HA40 KA02 TA22 KA17 TA22

Claims (3)

[Claims] An input terminal of a capacitive element is connected to a negative input terminal of an operational amplifier, and the charge detection device has a reset switch in a feedback circuit connecting an output terminal of the operational amplifier and a negative input terminal of the operational amplifier. In parallel with the feedback circuit, a reset switch separate from the reset switch connecting the output terminal of the operational amplifier and the negative input terminal of the operational amplifier, and a circuit in which a capacitive element separate from the capacitive element is connected in series, A charge detection device comprising at least one charge detection device. 2. An operational amplifier, a first capacitive element having one end connected to the negative input terminal of the operational amplifier and the other end grounded, and a first intermediate element connecting the output terminal and the negative input terminal of the operational amplifier.
A second feedback switch having a second reset switch and a second capacitive element connected in series between the output terminal and the negative input terminal of the operational amplifier. And a third capacitance element, one end of which is connected between the second reset switch and the second capacitance element and the other end of which is grounded. 3. At the time of reset, the first reset switch and the second reset switch are simultaneously turned on, and after a first predetermined time, the first reset switch is turned off, and the first reset switch is turned off. 3. The charge detecting device according to claim 1, further comprising control means for turning off the second reset switch after a second predetermined time longer than the predetermined time.