JP2009077172A - Analog-to-digital converter, and imaging apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an ADC which alleviates blunting of a counter clock and collapse of Duty ratio to attain high speed drive of an image sensor. <P>SOLUTION: The counter clock is divided using a frequency divider 5, ramp wave is generated by a DAC 2 based on the divided counter clock, and after blunting the ramp wave by a LPF 7, input in a comparator 8. In the comparator, the blunted ramp wave is compared with pixel output, and comparison time of the comparator is counted by a counter 9. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an analog-to-digital converter (ADC) and an imaging apparatus including such an ADC. Specifically, the present invention relates to an ADC that converts an analog value into a digital value by converting an analog signal into time, and an imaging apparatus including such an ADC.

  A CCD (Charge Coupled Device) type or CMOS (Complementary Metal-Oxide Semiconductor) type solid-state imaging device (image sensor) has an imaging unit in which a large number of pixel transistors are arrayed, and corresponds to the signal charge accumulated in the imaging unit. In general, a method of converting an analog electrical signal read from the imaging unit into a digital signal by an ADC and outputting the digital signal to the outside is adopted (for example, Patent Documents). 1, see Patent Document 2.).

Hereinafter, an example of a conventional ADC will be described with reference to the drawings. FIG. 5 is a schematic diagram for explaining the configuration of the conventional ADC, and FIG. 6 is a schematic diagram for explaining the principle of the conventional ADC.
A conventional ADC 101 shown in FIG. 5 is connected to a counter clock supply line 102 to which a counter clock is supplied, a digital-to-analog converter (DAC (Digital to Analog Converter)) 103 connected to the counter clock supply line, and the DAC. Comparator 104 and a counter 105 connected to the comparator and counter clock supply line.

  The DAC 103 described above is a ramp wave whose output value decreases at a constant rate at the rising timing and falling timing of the counter clock (see “counter clock” in FIG. 6) input via the counter clock supply line 102. (Analog signal) is output (refer to “DAC output (ramp wave)” in FIG. 6).

  The comparator 104 receives a pixel output (refer to “pixel output value” in FIG. 6) and a ramp wave, which are analog signals read from the imaging unit (pixel) 106, and the pixel output and the ramp wave. When the relationship of “(Ramp wave)> (pixel output)” is satisfied, a high level (H level) signal is output, and when the relationship of “(Ramp wave) <(pixel output)” is satisfied It is configured to output a low level (L level) signal (see “Comparator output” in FIG. 6).

  Further, the counter 105 is a DDR (Double Date Rate) counter, that is, a counter that employs a configuration that counts at both the rising timing and falling timing of the input counter clock ("counter output" in FIG. 6). Reference is made), and the count is stopped when the output signal from the comparator becomes L level.

  In the ADC configured as described above, the count is stopped at the timing when the output of the comparator is inverted from the H level signal to the L level signal, that is, the timing when the ramp wave becomes smaller than the pixel output, and the counter value is changed to the pixel value. The analog value (pixel output) is converted into a digital value (counter value) by converting the pixel output (electric signal) into time by outputting as an output digital value.

  In the conventional ADC configuration described above, the DAC has the same frequency as the counter so that a ramp wave whose output value decreases at a constant rate at the rising timing and falling timing of the counter clock can be output. The counter clock is input.

JP 2000-152082 A JP 2002-232291 A

  By the way, in recent years, the number of pixels of an image sensor has been increased and high-speed reading has been progressing. For this reason, the driving speed of the image sensor has also been increased. As the driving speed of the image sensor increases, the counting operation of the counter increases, and it is inevitably necessary to increase the frequency of the counter clock.

However, when the frequency of the counter clock is increased, the problem of the dullness of the counter clock and the problem of the duty ratio occur.
That is, because it is necessary to input a counter clock having the same frequency to the DAC and the counter, the counter clock supply line is routed over a long distance in the image sensor, and the time constant is determined by the wiring load of the counter clock supply line. Will become bigger. For this reason, if the counter clock becomes dull in the path from the counter clock generator to the DAC and reaches the DAC, and the degree of dullness of the counter clock becomes excessive, the counter clock does not reach the DAC sufficiently. Such a problem can be considered. Further, there may be a problem that the duty ratio of the counter clock is destroyed on the path from the counter clock generator to the DAC.

  Note that when a DDR counter is used as the counter, the duty ratio of the counter clock is collapsed, resulting in a problem that the linearity of the ramp wave is deteriorated.

Hereinafter, the deterioration of the linearity of the ramp wave due to the destruction of the duty ratio of the counter clock will be described in detail.
FIG. 7 is a schematic circuit diagram for explaining a phenomenon in which the linearity of the ramp wave generated by the DAC is deteriorated when the duty ratio of the counter clock is lost when the DDR counter is used as the DAC configuration. In the circuit shown by 5, five identical current sources are formed, and the current source can be controlled by the DDR counter. Further, the counter clock CK is input to the DDR counter, and the DAC current source is controlled by the output of the DDR counter. Note that the output part of the DAC is terminated with a resistor R [Ω], and the output Ramp_Out of the DAC is I _total × R [V].

In the DAC configured as described above, the DDR counter advances counting at both the rising and falling timings of the counter clock CK, and the current source is turned off by the counter value, and control is performed in this manner. Thus, when the count advances by 1, I _total decreases by I _unit [A] corresponding to one current source, and the voltage of Ramp_Out also decreases by I _unit × R [V].

Here, when the rising and falling edges of the counter clock CK are at regular intervals (that is, when the H level period and the L level period of the counter clock are equal), the current source is turned off by the count. Since the timing at which the current source is turned off is constant, the ramp wave decreases at regular intervals (see the graph indicated by symbol A in FIG. 7), but the rising edge of the counter clock. If the falling edge is not at a constant interval (that is, when the H level period and the L level period of the counter clock are different), the current source is turned off when the current source is turned off for the count. Since the timing for setting the state is not a constant interval, the ramp wave does not decrease at a constant interval (refer to the graph indicated by symbol B in FIG. 7).
That is, as described above, the duty ratio of the counter clock CK collapses, and the linearity of the ramp wave is deteriorated when the H level period and the L level period are different.

  As described above, the actual situation is that the high-speed driving of the image sensor cannot be sufficiently achieved due to the problem of the dull counter clock and the duty ratio.

  Japanese Patent Laid-Open No. 2006-50231 discloses a technique for increasing the time resolution by gradually increasing the rate of reduction of the ramp wave as the count of the counter progresses. The driving frequency of the image sensor cannot be lowered, and the image sensor cannot be driven at high speed.

  The present invention has been made in view of the above points, and an object of the present invention is to provide an ADC capable of realizing high-speed driving of an image sensor and an imaging measure using such an ADC.

  In order to achieve the above object, an AD converter according to the present invention is connected to a counter clock supply line to which a predetermined counter clock is supplied and the counter clock supply line, and divides the inputted counter clock. A frequency divider, a reference signal generating unit that generates a reference signal for converting an analog signal into a digital signal based on a frequency-divided clock generated by the frequency divider, and a reference generated by the reference signal generating unit Smoothing means for smoothing the signal, a comparison unit for comparing the analog signal to be converted with the smoothed reference signal, and the counter clock supply line, and the comparison based on the input counter clock And a counter unit that holds a count value at the time when the comparison process in the unit is completed.

  In order to achieve the above object, an imaging apparatus according to the present invention includes an imaging unit that generates an analog signal corresponding to incident light, and an analog digital that converts the analog signal generated by the imaging unit into a digital signal. In the imaging device including the converter, the analog-digital converter is connected to the counter clock supply line to which a predetermined counter clock is supplied, and the frequency division for dividing the input counter clock is connected to the counter clock supply line A reference signal generation unit that generates a reference signal for converting an analog signal into a digital signal based on a frequency-divided clock generated by the frequency divider, and a reference signal generated by the reference signal generation unit Smoothing means for smoothing, a comparison unit for comparing the analog signal to be converted with the smoothed reference signal, and the counter clock It is connected to the line, and a counter unit that holds the count value when the comparison processing is completed in the comparison unit on the basis of the input counter clock.

Here, even if the frequency of the input signal input to the reference signal generation unit is lowered by smoothing the reference signal generated by the reference signal generation unit by the smoothing means, the resolution of the smoothed reference signal is reduced. There will be almost no difference.
Even if the frequency of the input signal input to the reference signal generation unit is lowered, there is almost no difference in the resolution of the smoothed reference signal, so that it is based on the divided clock divided by the frequency divider. The reference signal can be generated, and as a result, the influence of the dull counter clock can be reduced.

  Further, the duty ratio can be improved by dividing the counter clock by the frequency divider.

  Hereinafter, [1] even if the frequency of the input signal input to the reference signal generator is lowered by smoothing the reference signal, the resolution of the smoothed reference signal is hardly different, [2 A detailed explanation will be given of the fact that the influence of the dullness of the counter clock can be reduced by generating the reference signal based on the divided clock, and that the duty ratio can be improved by dividing the frequency. Do.

[1] The resolution of the smoothed reference signal is hardly different. FIG. 8A shows a ramp wave (an example of a reference signal) generated by a DAC (an example of a reference signal generator). The ramp wave shown here has its output value decreased at a constant rate at the rising and falling timings of the counter clock (see the ramp wave indicated by the symbol a in FIG. 8A). The resolution of the ramp wave generated by the DAC is lowered as the frequency of the counter clock input to the DAC is lowered. Specifically, when the resolution of the counter clock input to the DAC is lowered by 1 bit, the resolution of the ramp wave is reduced. The resolution is also reduced by 1 bit (see the ramp wave indicated by the symbol b in FIG. 8A), and when the resolution of the counter clock input to the DAC is reduced by 2 bits, the resolution of the ramp wave is also reduced by 2 bits (in FIG. 8A). (See the ramp wave indicated by the symbol c.)

On the other hand, FIG. 8B shows a ramp wave in which the ramp wave generated by the DAC is blunted by an LPF (Low Pass Filter) (an example of a smoothing means). The ramp wave shown here is not related to the rising or falling timing of the counter clock due to the ramp time becoming dull when the LP output is inserted into the DAC output line and the ramp constant becomes dull. It always decreases at a constant rate (see symbol a in FIG. 8B).
The resolution of the ramp wave, which has been dulled to a certain extent, regardless of the rising or falling timing of the counter clock, is almost the same even if the frequency of the counter clock input to the DAC is lowered. Specifically, even if the resolution of the counter clock input to the DAC is lowered by 1 bit, there is no difference in the resolution of the ramp wave that has been dulled (see the ramp wave output value indicated by the symbol b in FIG. 8B). Even if the resolution of the counter clock input to the DAC is lowered by 2 bits, there is no difference in the resolution of the ramp wave that has been dulled (see the ramp wave output value shown in the middle number c in FIG. 8C).

  Therefore, as described above, even if the frequency of the input signal input to the reference signal generator is lowered by smoothing the reference signal, the resolution hardly changes.

[2] The effect of reducing the dullness of the counter clock First, as a value indicating the degree of dullness of the counter clock, a time constant that is a value indicating the primary frequency response in the linear type is known. When a rectangular wave as shown by _VIN is input to the RC circuit as shown by 9 (a), _VOUT after passing through the RC circuit becomes a dull waveform, and the degree of this dullness is the load of the circuit ( In the case of the circuit shown in FIG. 9, the value determined by R and C) and indicating the degree thereof is a time constant, and the relationship of the following [Equation 1] is established for the time constant τ.

[1 set]

_Here, the rise of _{V OUT,} when the time from the start of rising waveform and _{t UP, V out_UP} is represented by the following [expression _{2], V OUT_UP = V DD (} 1 at time _{t UP} = tau Since −e ⁻¹ ) ≈0.632 V _DD , it can be said that the time constant τ reaches about 63.2% of the steady value of the waveform. Further, in order to be ^{_{V OUT_UP = V DD (1-}} e -2) ≒ 0.865V DD at time _t UP = 2.tau, and thus reaching about 90% of the steady-state value of the waveform.
On the other _hand, the fall of _{V OUT,} when the time from the start of waveform lowered and _{t DOWN, V OUT_DOWN} is represented by the following [Equation _{3], V OUT_DOWN = V DD (} e at time _{t DOWN} = tau ⁻¹ ) ≈0.368V _DD .

[2 sets]

[3 formulas]

  Although the RC circuit is described as an example here, the relational expression of the time constant τ also changes in the RL circuit and the RLC circuit, but the time constant τ is a steady value of the waveform at the time t = τ. The value reaches approximately 63.2% of the value, and when the load due to the circuit or wiring increases, the value also increases. That is, as described above, the time constant τ can be said to be a value indicating the degree of waveform dullness determined by the circuit and wiring load.

  In the case of the counter clock, the time constant applied to the counter clock is determined by the wiring load and circuit load on the path of the counter clock, but the time constant τ does not depend on the frequency. In addition, even if the counter clock is divided, that is, even if the frequency of the counter clock is lowered, the time constant applied to the counter clock does not change, and it can be said that the waveform dullness is the same. In other words, since the time constant applied to the counter clock does not change even when the frequency is divided (divided by 2) as shown in FIG. 9B, the waveform becomes dull in the same way.

  Therefore, since one period is longer when the frequency is divided than when the frequency is not divided, by generating the reference signal based on the frequency-divided clock, it becomes difficult to see the influence of the dullness of the counter clock due to the time constant. is there.

[3] The duty ratio can be improved by dividing the frequency The duty ratio is the ratio of the H level period to the L level period in one cycle of the clock, and the length of one cycle is T, H When the length of the level period is H, it can be represented by Duty ratio = H / T × 100 (%) (see FIG. 10).

  FIG. 11 shows a circuit configuration and timing chart generally known as the principle of a frequency divider that divides a clock by two. The frequency divider shown here has a two-stage flip-flop (FF) configuration. The inverted output XQ of the second stage FF is input to the input D of the first stage FF, and the inverted signal of the first stage CK is input to the second stage CK.

  As for the operation of the FF, when the XCLR is at the L level, the FF is reset, Q is fixed at the L level, and XQ is fixed at the H level. On the other hand, during the period when XCLR is at the H level, the data of the input D is fetched and held according to the state of CK. Further, during the period when CK is at the L level, the data of the input D is taken and output to Q as it is, and the data of FF is determined at the rising edge of CK. On the other hand, during the period when CK is at the H level, data determined at the rising edge of CK is continuously output from Q, and XQ outputs an inverted signal of Q.

When the FF operates as described above, timings T1 to T4 after XCLR is in the H level period in the timing chart shown in FIG. 11A will be described.
First, since CK becomes L level at the timing of T1, the first stage FF takes in the signal xout and the output ff1_out becomes H level. Next, since CK becomes H level at the timing of T2, the first-stage FF determines data at the rising edge of CK. Since xout at the rising edge of CK is at the H level, the H level data is determined. While the CK is at the H level, the H level determined at the rising edge of the CK is continuously output. In the second-stage FF, since the inverted signal of the first-stage CK is contained in CK, the ff1_out signal is taken into the FF during the CK H-level period, and the H level is output from Divider_out. At that time, xout becomes an L level because of an inverted signal of Divider_out. Next, at the timing of T3, since CK becomes L level, the first stage FF takes in xout and ff1_out becomes L level, and the second stage FF determines data at the falling edge of CK ff1_out = Continue to output H level data. Next, at the timing of T4, CK becomes H level, and the first stage output ff1_out continues to output xout = L level determined at the rising edge of CK, and the second stage output takes in ff1_out = L level and Divider_out = L level. Is output. In this way, the timings T1 to T4 are repeated, and as a result, a clock obtained by dividing CK is output to Divider_out.

FIG. 11B shows an operation timing chart in the case where a clock having a corrupted duty ratio is input to the frequency divider shown in FIG. 11, and from FIG. 11B, the timing is similar to the above at the timings T1 to T4. When the operation is performed, it can be seen that Divider_out after passing through the frequency divider has a waveform with an improved duty ratio even when the clock has a corrupted duty ratio.
In the case of the frequency divider having the configuration shown in FIG. 11, the data is changed in synchronization with only the rising edge of CK in the second stage FF, so that the duty ratio is broken. However, if there is no jitter (or is negligibly small), the length of one cycle is the same, and if only focusing on either the rise or fall of CK, the rise or fall of CK is always constant. Therefore, the Divider_out timing is constant, that is, the duty ratio can be improved by dividing the frequency with a frequency divider.

  In the ADC of the present invention and an image pickup apparatus including such an ADC, the influence of the dull counter clock can be reduced, the duty ratio can be improved, and the image sensor can be driven at high speed. .

Hereinafter, embodiments of the present invention will be described with reference to the drawings to facilitate understanding of the present invention.
FIG. 1 is a schematic diagram for explaining an example of an imaging apparatus to which the present invention is applied. FIG. 2 is a schematic diagram for explaining the principle of an ADC in an example of an imaging apparatus to which the present invention is applied.
An imaging apparatus 1 to which the present invention is applied includes an imaging unit (pixel) 2 that generates an analog signal corresponding to input light, and an ADC 3 that converts the analog signal generated by the imaging unit into a digital signal.

  The ADC 3 includes a counter clock supply line 4 to which a counter clock is supplied, a frequency divider 5 connected to the counter clock supply line, a DAC 6 connected to the frequency divider, an LPF 7 connected to the DAC, an LPF, It comprises a connected comparator 8 and a counter 9 connected to the comparator and counter clock supply line.

  The above-described frequency divider 5 is a general-purpose frequency divider having a circuit configuration as shown in FIG. 11, for example, and is a counter clock input via a counter clock (see “counter clock” in FIG. 2). Can be divided by two. Here, the case where the frequency is divided by 2 is described as an example, but it is needless to say that the frequency may be divided by 3 or by 4.

  Further, the output value of the DAC 6 decreases at a constant rate at the rising timing and the falling timing of the counter clock divided by two (referred to as “divided clock” in FIG. 2) inputted through the frequency divider 3. (See “DAC output (ramp wave)” in FIG. 2).

  Further, the LPF 7 is connected to the DAC output line to increase the time constant of the DAC output line, and the ramp wave is always reduced at a constant rate regardless of the rising timing or falling timing of the counter clock divided by two. (See “Ramp wave after LPF” in FIG. 2).

  The comparator 8 also outputs a ramp wave (hereinafter referred to as “post-LPF ramp wave”) that has passed through a pixel output (see “pixel output value” in FIG. 2) that is an analog signal read from the imaging unit (pixel) 2 and LPF. When the relationship between the pixel output and the ramp wave after LPF satisfies the relationship “(ramp wave after LPF)> (pixel output)”, an H level signal is output, and “(after LPF When the relationship of “ramp wave) <(pixel output)” is satisfied, an L level signal is output (see “Comparator output” in FIG. 2).

  The counter 9 is a DDR counter and is configured to stop counting when the output signal from the comparator becomes L level (see “counter output” in FIG. 2). In this embodiment, the DDR counter is described as an example, but it is needless to say that the type of the counter is not particularly limited.

  Here, in this embodiment, a DAC that outputs a ramp wave whose output decreases at a constant rate at the rising timing and falling timing of the counter clock divided by two is taken as an example, and the output signal from the comparator The case where the count of the counter stops at the timing when the signal becomes L level is described as an example, but the output is constant at the rising and falling timings of the counter clock obtained by dividing the DAC by two. It is also possible to output a ramp wave that increases in step, and stop the counter counting at the timing when the output signal from the comparator becomes H level.

  In an example of the imaging apparatus to which the present invention is applied, a counter clock divided by the DAC can be used by inserting an LPF into the DAC output line. For this reason, even if the frequency of the counter clock is increased, wiring is performed. It becomes difficult to see the influence of dullness due to time constants such as the above, and it is possible to reduce problems caused by increasing the frequency of the counter clock.

  In addition, a clock with an improved duty ratio can be used for the DAC, and problems of duty ratio collapse due to external factors such as a circuit and temperature can be reduced.

  Furthermore, since the DAC can be designed with a resolution lower than that of the counter, the design can be made smaller than the conventional circuit configuration, that is, the circuit configuration in which the resolution of the DAC and the counter is the same, thereby reducing the circuit area. The effect of improving the profitability by reducing the power consumption by reducing the circuit and circuit reduction can be expected.

  By the way, when LPF is inserted in the DAC output line, settling at the time of ramp wave reset may be a problem. In other words, after the counter finishes counting, it is necessary to return the ramp wave output to the initial count level in preparation for the next count. This operation is called ramp wave reset, but LPF is inserted into the DAC output line. In this case, the load on the DAC output line increases, so that the settling time becomes long, and there may be a case where the settling cannot be performed within the required specification time.

  Therefore, as a modification of the imaging device to which the present invention is applied, it is preferable that the LPF is disconnected from the DAC output line and the charge can be charged (precharged) by another voltage source or current source when the ramp wave is reset ( (See FIG. 3 (a)).

  Specifically, as shown in FIG. 3B, the connection destination of the LPF capacitor is configured to be switchable by a switch circuit, and the counter clock is counted and the DAC output decreases or increases over time. Sometimes a capacitor is connected to the DAC output line to perform the LPF function. On the other hand, when the count of the counter is completed and the ramp wave is reset, the potential of the node connected to the DAC output line of the capacitor using the precharge circuit 10 is separated from the DAC output line by the ramp wave. The operation of charging or extracting the charge is performed until the potential becomes the same as the reset potential. Note that any precharging method may be used as long as an operation of charging or extracting charges from the capacitor can be performed at the time of resetting.

  In a modification of the imaging device to which the present invention is applied, by using a circuit having a precharge function, it is possible to reduce the load on the DAC output by disconnecting the capacitor of the LPF at the time of resetting, and putting the LPF into the DAC output may cause a problem. Settling problems during reset can be reduced.

  As described above, in the imaging apparatus to which the present invention is applied, it is difficult to see the influence of the dullness of the counter clock input to the DAC, and the problem of the duty ratio collapse of the counter clock input to the DAC can be reduced. Therefore, as a practical example of the imaging apparatus to which the present invention is applied, the path from the counter clock generator to the counter can be shortened to suppress the influence of the dullness of the counter clock input to the counter and the duty ratio collapse. A configuration is considered preferred.

  That is, it is considered preferable to arrange a counter clock supply line from the counter clock generator to the counter and then arrange a counter clock supply line to the DAC. Specifically, [1] counter clock generator ( A configuration in which a counter clock is input to a counter from a counter clock supply line (not shown), the counter clock is divided by a frequency divider arranged immediately after the counter, and the divided counter clock is input to the DAC ( (See FIG. 4A.) Or [2] A counter clock is input from the counter clock generator (not shown) to the counter via the counter clock supply line, and then placed immediately before the DAC from the counter. Configuration in which a counter clock is input to the frequency divider and the counter clock frequency-divided by the frequency divider is input to the DAC (FIG. 4B) Ether.) Is considered.

  Here, when a frequency divider is inserted on the counter side (in the case of FIG. 4A), the influence of dullness of the counter clock due to a load such as wiring can be reduced, and power consumption can be further reduced. It can be planned. On the other hand, when a frequency divider is inserted on the DAC side (in the case of FIG. 4B), a clock in which the duty ratio is almost unchanged can be input to the DAC.

It is a schematic diagram for demonstrating an example of the imaging device to which this invention is applied. It is a schematic diagram for demonstrating the principle of ADC in an example of the imaging device to which this invention is applied. It is a schematic diagram for demonstrating settling at the time of the reset of a ramp wave. It is a schematic diagram for demonstrating the practical example of the imaging device to which this invention is applied. It is a schematic diagram for demonstrating the structure of the conventional ADC. It is a schematic diagram for demonstrating the principle of conventional ADC. It is a schematic diagram for demonstrating the deterioration of the linearity of a ramp wave. It is a schematic diagram for demonstrating the ramp wave shape at the time of passing through LPF. It is a mimetic diagram for explaining dullness of a counter clock. It is a schematic diagram for demonstrating Duty ratio. It is a schematic diagram for demonstrating a frequency divider.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Imaging device 2 Imaging part (pixel)
3 ADC
4 Counter clock supply line 5 Divider 6 DAC
7 LPF
8 Comparator 9 Counter 10 Precharge circuit

Claims (4)

A counter clock supply line to which a predetermined counter clock is supplied;
A frequency divider that is connected to the counter clock supply line and divides the input counter clock;
A reference signal generation unit that generates a reference signal for converting an analog signal into a digital signal based on a frequency-divided clock generated by the frequency divider;
Smoothing means for smoothing the reference signal generated by the reference signal generation unit;
A comparison unit for comparing the analog signal to be converted and the smoothed reference signal;
An analog-digital converter, comprising: a counter unit connected to the counter clock supply line and holding a count value at the time when the comparison process in the comparison unit is completed based on the input counter clock. Electrical signal supply means for supplying a predetermined electrical signal to the capacitor of the smoothing means;
2. The analog according to claim 1, further comprising a connection switching unit that disconnects the capacitor from the reference signal generation unit when the reference signal generation unit is reset, and connects the capacitor and the electric signal supply unit. Digital converter. An imaging unit that generates an analog signal according to incident light;
In an imaging apparatus including an analog-digital converter that converts an analog signal generated by the imaging unit into a digital signal,
The analog-digital converter is
A counter clock supply line to which a predetermined counter clock is supplied;
A frequency divider that is connected to the counter clock supply line and divides the input counter clock;
A reference signal generation unit that generates a reference signal for converting an analog signal into a digital signal based on a frequency-divided clock generated by the frequency divider;
Smoothing means for smoothing the reference signal generated by the reference signal generation unit;
A comparison unit for comparing the analog signal to be converted and the smoothed reference signal;
An imaging apparatus comprising: a counter unit connected to the counter clock supply line and holding a count value at the time when the comparison process in the comparison unit is completed based on the input counter clock. Electrical signal supply means for supplying a predetermined electrical signal to the capacitor of the smoothing means;
The imaging according to claim 3, further comprising: a connection switching unit that disconnects the capacitor from the reference signal generation unit when the reference signal generation unit is reset, and connects the capacitor and the electric signal supply unit. apparatus.

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