JP4859176B2 - Microprocessor and I / O port replacement method - Google Patents

Description

  The present invention relates to a microprocessor including a control circuit, a numerical operation unit, a predetermined register, and an I / O port.

  Generally, a processor includes an I / O port, and data is input / output from / to the outside through the I / O port. As a method for inputting / outputting data through an I / O port, a method using an I / O dedicated instruction and a method using a memory access instruction by mapping an I / O port to a memory space (memory mapped I / O) There is.

  Here, in the method using the I / O dedicated instruction, is the I / O transfer instruction used to transfer data between the I / O port and the general-purpose register when performing input / output to / from the I / O port? Alternatively, an I / O direct control command that directly controls the value of the I / O port is used.

  For example, the ATEL AT90S4414 microprocessor is provided with an IN instruction that transfers from the I / O port to the general-purpose register and an OUT instruction that transfers from the general-purpose register to the I / O port as I / O transfer instructions. ing.

  Also, as an I / O direct control instruction, an SBIC / SBIS instruction that skips the next instruction according to the bit value of the I / O port, and an SBI / S bit that directly sets the bit value of the I / O port to “1” or “0”. CBI instructions are available.

  On the other hand, in the method using the memory access instruction, a part of the area on the memory is used as an I / O port. This is referred to as “memory mapped I / O”. In this memory mapped I / O, when a memory access is performed to a memory address to which the I / O is mapped, input / output to the I / O port is performed.

  For example, in the Z80 microprocessor of Zilog, an AND operation is performed on the contents of the memory address indicated by the A register and the HL register by an AND A, (HL) instruction. Here, when the memory address 0xff00 is mapped to the I / O port and the HL register is 0xff00 and AND A, (HL) is executed, the result of ANDing the A register and the I / O port is the A register. Is assigned to

As shown in this example, in memory mapped I / O, an instruction for reading from a memory can be used as an instruction for reading from an I / O port. Similarly, an instruction for writing to the memory can be used as an instruction for writing to the I / O port.
JP 11-045223 A

  However, in the method using the I / O dedicated instruction described above, when the processor processes data through the I / O port, the number of execution cycles is larger than when processing data and flags in the general-purpose register. For example, an ATEL AT90S4414 microprocessor having an I / O dedicated instruction provides an ADD instruction for performing addition between general-purpose registers, but does not provide an I / O port. For this reason, it is necessary to once transfer to the general-purpose register using the I / O transfer instruction, and the number of execution cycles is increased by executing the I / O transfer instruction as compared with the operation instruction of the general-purpose register.

  In the microprocessor, a conditional branch instruction is used when processing is changed according to data. However, conditional branch instructions for I / O ports are limited to general-purpose registers and conditional branch instructions. For this reason, it is necessary to transfer from the I / O port to the general-purpose register once, and the number of execution cycles increases.

  On the other hand, even in the memory mapped I / O method, access to a memory or cache memory takes longer than access to a general-purpose register. Therefore, when input / output to / from the I / O port is performed using a memory access instruction, the number of execution cycles is increased as compared with an operation instruction between general-purpose registers.

  Thus, conventionally, when the processor performs processing, if input data or output data is in the I / O port, the number of execution cycles is greater than if input data or output data is in the general-purpose register. In particular, when a process including input / output of an I / O port is required with a very short number of cycles, the number of execution cycles cannot be made sufficiently small.

  Further, even when interrupt processing including input / output to / from an I / O port is required with a very short cycle number, the number of execution cycles cannot be reduced as in the case described above.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to enable a processor to realize predetermined processing for an I / O port with a very short number of execution cycles.

  It is another object of the present invention to realize predetermined processing for an I / O port with an extremely short number of execution cycles even during interrupt processing.

The present invention is a microprocessor including a register and an I / O port, the designation means for designating the register to which the I / O port is replaced, and the I / O port is designated by the designation means Permission means for permitting whether or not to replace with the register; replacement means for replacing the I / O port with the register when permitted by the permission means; and the I / O port with the register by the replacement means. when replaced, have a calculating means for calculating read data from the I / O ports, the replacement unit may perform different replaced by the interrupt processing time and normal processing.

The present invention also relates to an I / O port replacement method in a microprocessor including a register and an I / O port, the designation step for designating the register in which the I / O port is replaced, and the I / O A permission step for permitting whether or not to replace a port with the register designated in the designation step; a substitution step for replacing the I / O port with the register when permitted in the permission step; and a substitution step if the I / O port is replaced in the register, the data is read from the I / O ports possess a calculating step of calculating, in the substitution step differs between the interrupt processing time and normal processing It is characterized by performing replacement .

According to the present invention, the number of execution cycles can be reduced when the arithmetic means of the processor reads and processes the data of the I / O port .

  Also, during interrupt processing, predetermined processing for an I / O port can be realized with a very short number of execution cycles.

  The best mode for carrying out the invention will be described below in detail with reference to the drawings.

  In the present embodiment, the number of execution cycles of the processor is reduced by mapping the I / O port in the processor to a register or flag used for numerical operation or the like instead of mapping it to the memory.

  FIG. 1 is a diagram illustrating an example of a configuration of a processor capable of mapping an I / O port to a general-purpose register in the present embodiment. The processor shown in FIG. 1 has an arithmetic operation block between registers having the same configuration as that of a conventional processor, an I / O port 102, and an I / O port map block capable of mapping the I / O port in this embodiment to a general-purpose register. And various control signals.

  The above-described inter-register operation block includes a register file 100, a flag register 101, a numerical operation unit (ALU) 108, and a control circuit 109.

  The I / O port map block includes a register 103, a bit register 104, comparators 105a and 105b, determination units 106a and 106b, selection circuits (multiplexers) 107a and 107b, and gates 110 and 111.

  Here, an I / O port map register number for mapping an I / O port to a general-purpose register is written in the register 103 by an I / O port map register number write signal 141 from the control circuit 109. An I / O port map valid bit is written in the bit register 104 by an I / O port map valid bit write signal 142 from the control circuit 109. The comparators 105 a and 105 b compare the I / O port map register number from the register 103 with the operand register number control signals 121 a and 121 b from the control circuit 109. The determiners 106a and 106b output the results of the comparators 105a and 105b when the I / O port map valid bit 104 is “1”.

  The selection circuits 107a and 107b select the register file 100 or the I / O port 102 based on the I / O port map validity determinations 126a and 126b, and read the operand register. The gates 110 and 111 determine whether to write data to the register file 100 or the I / O port 102 based on the I / O port map validity determinations 126 a and 126 b and the register file write control signal 120 from the control circuit 109. select.

  The ALU function selection control signal 123 and the control signal of the flag input signal 127 will be described later.

  Here, in order to simplify the explanation, the register file 100 has four registers R0 to R3, the flag register 101 has a Z bit indicating whether the operation result is zero, and a carry has occurred during the operation. It is assumed that there is a C bit indicating whether or not.

  First, the operation of the processor when the I / O port is not mapped to the general-purpose register will be described as an example where XOR R1 and R3 are specified in the instruction. In this example, “0” is stored in the I / O port map valid bit 104 indicating that the I / O port is not mapped to the general-purpose register. Since the instructions are XOR R1 and R3, the control circuit 109 outputs “1” and “3” to the operand register number control signals 121a and 121b in order to read R1 and R3 of the register file 100, respectively. In addition, a value indicating the XOR function is output to the ALU function selection control signal 123 in order to perform the XOR operation. Further, in order to write the operation result to the register file 100, “1” is output to the register file write control signal 120.

  At this time, R1 is read as operand 1 from the register file 100, and is input to the I / O port map read selection 107a via 122a. Similarly to R1, R3 is read from the register file 100 as operand 2, and is input to the I / O port map read selection 107b via 122b.

  Since the I / O port map valid bit 104 is “0”, the outputs of the I / O port map comparators 105a and 105b constituting the I / O port map judgment circuit and the I / O port map validity judgments 106a and 106b. The signals 126a and 126b are both “0”. Therefore, R1 and R3 input from 122a and 122b are output to the output signals 137a and 137b of the I / O port map read selections 107a and 107b, respectively.

The numerical operation unit 108 performs the XOR operation designated by the ALU function selection control signal 123 on R1 and R3 input as the output signals 137a and 137b, and outputs the result as the operation result 124. Here, the output 125 to the flag register 101, the operation result to output a "1" or "0" to the Z bit depending on whether zero. In this case, “0” is always output to the C bit of the output 125.

  Next, when the register file write control signal 120 is “1”, the calculation result 124 is written to the register file 100 if the selection input signal 126 a is “0”, and the I / O port 102 if it is “1”. Is written to. When the register file write control signal 120 is “0”, neither the register file 100 nor the I / O port 102 is written.

  In the example of the instruction XOR R1, R3, the register file write control signal 120 is “1”, but since the operand 1 is not mapped to the I / O port, the selection input signal 126a becomes “0”, and the operation result is It is written in the register file 100. Of the register file 100, the register to be written is R1 specified by the operand register number control signal 121a. The output 125 of the numerical operation unit 108 is recorded in the Z bit and C bit of the flag register 101. Thus, if the I / O port is not mapped to a general purpose register, instructions XOR R1, R3 are executed.

  Next, the processor operation when the I / O port is mapped to the general-purpose register, the I / O port 102 is mapped to the general-purpose register R1, XOR R1 and R3 are specified in the instruction, and XOR PA , R3 is executed as an example. In this example, since the I / O port 102 is mapped to the general-purpose register R1, the I / O port map valid bit 104 stores “1” indicating that the map is valid. Also, the I / O port map register number 103 is different from the first example in that “1” indicating R1 is stored.

  On the other hand, since the instructions are the same, the signal output from the control circuit 109 is the same as in the previous example. That is, since the instruction is XOR R1, R3, the control circuit 109 outputs “1” and “3” to the operand register number control signals 121a and 121b in order to read R1 and R3 of the register file 100. In addition, a value indicating the XOR function is output to the ALU function selection control signal 123 in order to perform the XOR operation. Further, in order to write the operation result to the register file 100, “1” is output to the register file write control signal 120.

  At this time, R1 is read as operand 1 from the register file 100, and is input to the I / O port map read selection 107a via 122a. Similarly to R1, R3 is read from the register file 100 as operand 2, and is input to the I / O port map read selection 107b via 122b.

  Since the I / O port map valid bit 104 is “1”, the operand register number control signals 121a and 121b are respectively compared with the I / O port map register number 103 as the selection input signals 126a and 126b. In this example, since the operand register number control signals 121a and 121b are “1” and “3”, respectively, and the I / O port map register number 103 is “1”, the selection input signals 126a and 126b are “1” and “1”, respectively. “0”. For this reason, PA and R3 are output to the output signals 137a and 137b of the I / O port map read selections 107a and 107b.

  The numerical operation unit 108 performs the XOR operation specified by the ALU function selection control signal 123 on PA and R3 input as the output signals 137a and 137b, and outputs the result as the operation result 124. The calculation result 124 is written to the I / O port 102 because the register file write control signal 120 is “1” and the selection input signal 126 a is “1”.

  As described above, when the I / O port 102 is mapped to the general-purpose register R1, if XOR R1, R3 is specified in the instruction, XOR PA, R3 is actually executed. This allows I / O ports to be mapped to general purpose registers.

  Next, a procedure for software to rewrite the I / O port map register number 103 and the I / O port map valid bit 104 will be described.

  First, when the software instructs to rewrite the I / O port map register number 103, the control circuit 109 outputs a general register number for mapping the I / O port and a write permission signal to the I / O port map register number write signal 141. To do. As a result, the I / O port map register number 103 is updated. Similarly to 103, when the software instructs to rewrite the I / O port map valid bit 104, the control circuit 109 writes the I / O port map valid or invalid in the I / O port map register number write signal 141. Output permission signal. As a result, the I / O port map valid number 104 is updated. In this way, the I / O port map register number 103 and the I / O port map valid bit 104 can be rewritten from software.

  FIG. 2 is a diagram illustrating an example of a configuration of a processor capable of mapping an I / O port to a flag register. Components having the same functions as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 2, based on the output signal 129 of the I / O port map valid bit 130, the selection circuit 131 selects either the output signal 128 of the flag register 101 or the PA of the I / O port 101. Output.

  Here, for the sake of simplicity of explanation, as shown in FIG. 3, the flag register 101 indicates a Z bit 201 indicating whether or not the operation result is zero, and whether or not a carry occurs during the operation. It is assumed that C bit 202 exists. The Z bit 201 is set at the bit 1 position, and the C bit is set at the bit 0 position.

  In addition, as shown in FIG. 4, the I / O port map valid bit 130 stores a value that designates whether to read the flag register 101 for each bit or the value of the I / O port 102 for each bit. ing. In the example shown in FIG. 4, “0” is stored in the I / O port map valid bit 130 when reading the flag register 101 and “1” is read when reading the value of the I / O port 102. And

  First, the operation of the processor when the I / O port 102 is not mapped to the flag register 101 is the BNZ instruction (branch if the Z bit of the flag = 0), the Z bit is 0, the C bit is 1, and the I / O port A case where 102 is 0x2 will be described as an example.

  When the BNZ instruction is executed, as the control signal from the control circuit 109, the register file write control signal 120 is 0 (not written to the register file), and the ALU function selection signal 123 is the input F as it is as the flag output 125. Output to. Operand register number control signals 121a and 121b are arbitrary values. Since the Z bit 201 of the flag register 101 is “0” and the C bit 202 is “1”, the output 128 of the flag register 101 is 0x1. Since the I / O port 102 is not mapped to the flag register 101, the I / O map registers 203 and 204 are both “0”, and the output 129 of the I / O map register is 0x0.

  Here, since the selection signal 129 of the selection circuit 131 is 0x0, the output 128 of the flag register is output to the output of the selection circuit 131. That is, in this example, 0x1 is output. Therefore, since the input value of the flag of the control circuit 109 is 0x1, and the value of the first bit corresponding to the Z bit is “0”, the branch is executed.

  Next, the operation of the processor when the I / O port 102 is mapped to the flag register 101 will be described. In the BNZ instruction (branch if the Z bit of the flag = 0), the Z bit is 0, the C bit is 1, and the I / O port 102 is 0x2 (the value mapped to the Z bit of the flag is 1). The case where the I / O map register is 0x02 (maps bit 1 of the I / O port 102 to the Z bit of the flag) will be described as an example.

  When executing the BNZ instruction, the difference from the previous unmapped example is that the output 129 of the I / O port map valid bit is 0x2, and the control signal from the control circuit 109 is This is the same as the example in.

  Here, since the selection signal 129 of the selection circuit 131 is 0x2, the bit 1 of the PA of the I / O port 102 is output to the Z-bit output of the selection circuit 131, and the flag register 101 outputs to the C-bit output. The C bit is output. In this example, since bit 1 of PA is “1” and C bit of flag register 101 is “1”, 0x3 is output as output 131 of selection circuit 131. Therefore, since the input value of the flag of the control circuit 109 is 0x3 and the bit 1 corresponding to the Z bit is “1”, the branch is not executed.

  Thus, when bit 1 of PA of I / O port 102 is mapped to the Z bit of flag register 101, if a BNZ instruction is specified as an instruction, an instruction that actually branches if PA [1] = 0 Is executed. Further, it is possible to switch whether to map the I / O port 102 to the flag register 101 according to the value of the I / O map register.

  Further, as in the example shown in FIG. 1, when the software instructs to rewrite the I / O port map valid bit 130, the control circuit 109 maps the I / O port to the I / O port map register number write signal 141. Outputs enable / disable and write enable signal. As a result, the I / O port map valid number 104 is updated. In this manner, the I / O port map valid bit 130 can be rewritten from software.

  FIG. 5 is a diagram illustrating an example of a configuration of a processor that can map an I / O port to a general-purpose register and can switch a map at the time of an interrupt. Note that FIG. 5 is obtained by adding a configuration that can switch the map at the time of interruption to the configuration shown in FIG.

  As shown in FIG. 5, an additional interrupt processing level signal 301 output from the control circuit 109 is added. The interrupt level signal 301 is “1” when interrupt processing is in progress, and is “0” when interrupt processing is not in progress. Also, the I / O port map register number 103 and the I / O port map valid bit 104 shown in FIG. 1 are prepared for each interrupt processing level, and the I / O port map register numbers 103a and 103b, the I / O port map are provided. It is effective bits 104a and 104b. Then, selection circuits 302a and 302b for switching between an I / O port map register number and an I / O port map valid bit by an interrupt processing level signal 301 are added.

  The I / O port map register number write signal 141 is written by designating one of the I / O port map register numbers 103a and 103b. Similarly, the I / O port map valid bit write signal 142 is written by designating one of the I / O port map valid bits 104a and 104b.

  In FIG. 5, when the interrupt processing level signal 301 is “0”, the selection circuits 302a and 302b use 103a as the I / O port map register number and 104a as the I / O port map valid bit. On the other hand, when the interrupt processing level signal 301 is “1”, the selection circuits 302a and 302b use 103b as the I / O port map register number and 104b as the I / O port map valid bit.

  As a result, the general-purpose register that maps the I / O port can be changed during interrupt processing and normal processing. This eliminates the need for a transfer instruction between the I / O port during interrupt processing and the general-purpose register or an instruction for changing the map at the start / end of interrupt processing. Can be shortened.

  FIG. 6 is a diagram illustrating an example of a configuration of a processor that can map an I / O port to a flag register and can switch a map at the time of an interrupt. Note that FIG. 6 is obtained by adding a configuration that can switch the map at the time of interruption to the configuration shown in FIG.

  As shown in FIG. 6, an additional interrupt processing level signal 301 output from the control circuit 109 is added. The interrupt level signal 301 is “1” when interrupt processing is in progress, and is “0” when interrupt processing is not in progress. Also, an I / O port map valid bit 130 shown in FIG. 2 is prepared for each interrupt processing level, and becomes I / O port map valid bits 130a and 130b. Then, a selection circuit 302 for switching between an I / O port map register number and an I / O port map valid bit by an interrupt processing level signal 301 is added.

  The I / O port map register number write signal 141 is written by designating either of the I / O port map valid bits 130a and 130b.

  In FIG. 6, when the interrupt processing level signal 301 is “0”, the selection circuit 302 uses the I / O port map valid bit 130 a. On the other hand, when the interrupt processing level signal 301 is “1”, the selection circuit 302 uses 130b as the I / O port map valid bit.

  As a result, the flag register that maps the I / O port can be changed during interrupt processing and normal processing. This eliminates the need for a transfer instruction between the I / O port during the interrupt processing and the general-purpose register and an instruction for changing the map at the start / end of the interrupt process, thereby reducing the number of execution cycles required for the interrupt process. can do.

  According to the embodiment described above, the I / O port can be mapped to the general purpose register or the flag register, and the map to the I / O port and the general purpose register or the flag register can be changed from software. Therefore, processing including input / output of the I / O port can be realized with a very short number of cycles.

  Furthermore, since a general-purpose register or flag register that maps an I / O port can be changed during interrupt processing, processing including input / output of the I / O port can be realized with a very short number of cycles in interrupt processing.

  Even if the present invention is applied to a system composed of a plurality of devices (for example, a host computer, an interface device, a reader, a printer, etc.), it is applied to an apparatus (for example, a copier, a facsimile machine, etc.) composed of a single device. It may be applied.

  In addition, a recording medium in which a program code of software for realizing the functions of the above-described embodiments is recorded is supplied to the system or apparatus, and the computer (CPU or MPU) of the system or apparatus stores the program code stored in the recording medium. Read and execute. It goes without saying that the object of the present invention can also be achieved by this.

  In this case, the program code itself read from the recording medium realizes the functions of the above-described embodiment, and the recording medium storing the program code constitutes the present invention.

  As a recording medium for supplying the program code, for example, a floppy (registered trademark) disk, a hard disk, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like is used. be able to.

  In addition, by executing the program code read by the computer, not only the functions of the above-described embodiments are realized, but also the following cases are included. That is, when the OS (operating system) running on the computer performs part or all of the actual processing based on the instruction of the program code, and the functions of the above-described embodiments are realized by the processing.

  Further, the program code read from the recording medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. After that, based on the instruction of the program code, the CPU of the function expansion board or function expansion unit performs part or all of the actual processing, and the function of the above-described embodiment is realized by the processing. Needless to say.

It is a figure which shows an example of the structure of the processor which can map the I / O port in this embodiment to a general purpose register. It is a figure which shows an example of a structure of the processor which can map an I / O port to a flag register. FIG. 3 is a diagram illustrating a configuration of a flag register 101 illustrated in FIG. 2. FIG. 3 is a diagram showing a configuration of an I / O port map valid bit 130 shown in FIG. 2. It is a figure which shows an example of a structure of the processor which can map an I / O port to a general purpose register and can switch a map at the time of interruption. FIG. 3 is a diagram illustrating an example of a configuration of a processor that can map an I / O port to a flag register and can switch a map at the time of an interrupt.

Explanation of symbols

100 register file 101 flag register 102 I / O port 103 I / O port map register number 104 I / O port map valid bit 105 I / O port map comparator 106 I / O port map valid judgment 107 I / O port map read Selection 108 Numerical arithmetic unit (ALU)
109 Control Circuit 110 I / O Port Map Write Selection 111 I / O Port Map Write Selection 130 I / O Port Map Valid Bit 131 I / O Port Map Read Selection 302 Selection Circuit

Claims (10)

A microprocessor including a register and an I / O port;
Designating means for designating the register in which the I / O port is replaced;
Permission means for permitting whether to replace the I / O port with the register designated by the designation means;
A replacement unit that replaces the I / O port with the register when permitted by the permission unit;
Wherein when the I / O port is replaced in the register, have a calculating means for calculating read data from the I / O port by said replacement means,
The microprocessor according to claim 1, wherein the replacement means performs different replacements in interrupt processing and normal processing . A microprocessor including a register and an I / O port;
Designating means for designating the register in which the I / O port is replaced;
Permission means for permitting whether to replace the I / O port with the register designated by the designation means;
A replacement unit that replaces the I / O port with the register when permitted by the permission unit;
Arithmetic means for reading and calculating data from the I / O port when the replacement means replaces the I / O port with the register;
The microprocessor is characterized in that the register is at least one of flag registers. Specifying means for specifying one flag in the flag register;
3. The microprocessor according to claim 2, wherein the replacement unit replaces the I / O port with the specified flag register when the permission unit permits. A control circuit for controlling the designation by the designation means and the permission by the permission means;
Wherein the control circuit, any one of claims 1 to 3, characterized in that the designation or the I / O ports of the register replacing the I / O ports can be changed to permit or not to replace the register The microprocessor according to item . 5. The microprocessor according to claim 4 , wherein the calculation means reads and calculates data from the register in accordance with an instruction from the control circuit. It said calculating means, when reading data from the I / O ports, the microprocessor according to any one of claims 1 to 5, characterized in that to read the data without passing through the register. The register includes a microprocessor according to any one of claims 1 to 6, characterized in that at least one of the general purpose registers. A specifying means for specifying one register in the general-purpose register;
8. The microprocessor according to claim 7 , wherein the replacement unit replaces the I / O port with the specified register when permitted by the permission unit. An I / O port replacement method in a microprocessor including a register and an I / O port, comprising:
A designation step for designating the register in which the I / O port is replaced;
A permission step for permitting whether or not to replace the I / O port with the register designated in the designation step;
A replacement step of replacing the I / O port with the register if permitted in the permission step;
Wherein when the I / O ports in a substitution step is replaced in the register, it possesses a calculating step of calculating reads data from the I / O ports,
In the replacement step, the I / O port replacement method is characterized in that different replacement is performed during interrupt processing and during normal processing . An I / O port replacement method in a microprocessor including a register and an I / O port, comprising:
A designation step for designating the register in which the I / O port is replaced;
A permission step for permitting whether or not to replace the I / O port with the register designated in the designation step;
A replacement step of replacing the I / O port with the register if permitted in the permission step;
A calculation step of reading and calculating data from the I / O port when the I / O port is replaced with the register in the replacement step;
The I / O port replacement method, wherein the register is at least one of flag registers.

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