JP4851738B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a plurality of guard regions formed in a first conductivity type growth layer.

  FIG. 8 shows a cross-sectional structure of a conventional semiconductor device 2 (MOSFET). The substrate 201 is made of a silicon single crystal containing n-type impurities at a high concentration, and a growth layer 202 made of a silicon epitaxial layer containing n-type impurities is formed on one main surface of the substrate 201 by epitaxial growth. Has been. Inside the growth layer 202, a base region 203 containing a p-type impurity is formed in the vicinity of the surface.

  A plurality of rectangular active grooves 204 having an elongated cross section are arranged in parallel to each other so as to divide the base region 203. A buried region 205 containing a p-type impurity is formed inside the active trench 204. In the base region 203, a source region 206 containing an n-type impurity is formed adjacent to each active trench 204 on one side or both sides thereof. The source region 206 is exposed on the surface of the growth layer 202. In the base region 203 between the adjacent active trenches 204, two source regions 206 face each other, and an ohmic region 207 containing a p-type impurity at a high concentration is formed between the two source regions 206. ing. Similar to the source region 206, the ohmic region 207 is exposed on the surface of the growth layer 202.

  A gate insulating film 208 is formed in the active trench 204 in contact with the base region 203. The region surrounded by the gate insulating film 208 is filled with a gate electrode 209 made of a polysilicon material. Around the active groove 204 and the base region 203, a plurality of quadrangular guard grooves 210 having an elongated cross section are formed. When the semiconductor device 2 is viewed in plan, the guard groove 210 is formed so as to surround the active groove 204 and the base region 203. The guard grooves 210 are concentrically arranged, and are formed such that the intervals between the adjacent guard grooves 210 are equal, the widths of the guard grooves 210 are equal, and the depths of the guard grooves 210 are also equal.

  A gate insulating film is not formed on the inner periphery of the guard trench 210, and a silicon single crystal containing p-type impurities is grown on the bottom and side surfaces of the guard trench 210 by an epitaxial growth method. Is filled with a guard region 211 made of the silicon single crystal.

  An oxide film 214 is formed by thermal oxidation on the growth layer 202 in the region where the guard groove 210 is formed. An insulating film 215 made of, for example, PSG (Phospho Silicate Glass) is formed on the guard region 211, the oxide film 214, the gate insulating film 208, the gate electrode 209, and a part of the source region 106. The insulating film 215 is patterned, and the surfaces of the source region 206 and the ohmic region 207 are exposed at the bottom of the opening. A source electrode 216 made of a metal thin film is formed on the surface of these exposed regions and on the insulating film 215. A drain electrode 217 made of a metal thin film is formed on the main surface of the substrate 201 opposite to the side on which the growth layer 202 is formed.

  The base region 203 is in contact with the gate insulating film 208 at a position below the source region 206. If the contacted region is called an inversion region, a channel is formed in the inversion region when the semiconductor device 2 is energized, and a current flows. That is, when a positive voltage higher than the threshold voltage is applied to the gate electrode 209 in a state where the source electrode 216 is connected to the ground potential and a positive voltage is applied to the drain electrode 217, the inversion region of the base region 203 becomes n. An inversion layer is formed by inverting the mold, the source region 206 and the growth layer 202 are connected by the inversion layer, and a current flows.

  In this state, when the voltage applied to the gate electrode 209 is equal to or lower than the threshold voltage because the gate electrode 209 is connected to the source electrode 216 or the like, the inversion layer disappears and no current flows. In this state, the pn junction between the base region 203 and the growth layer 202 is reverse-biased, and a depletion layer extends inside the base region 203, both inside the buried region 205 and inside the growth layer 202. .

  In general, a ring-shaped semiconductor region having the same conductivity type as the base region and concentrically surrounding the base region is called a guard ring. In this conventional semiconductor device 2, the guard region 211 functions as a guard ring. When the depletion layer extending in the lateral direction in the growth layer 202 reaches the guard region 211, the depletion layer further extends outward from the guard region 211, and the depletion layer successively reaches the concentric guard region 211 and spreads. . Thereby, the spread of the depletion layer becomes larger than the case where the guard region 211 does not exist, and the electric field strength inside the growth layer 202 is relaxed.

  In this specification, assuming that {100} includes all of the following plane orientations, the substrate 201 having a {100} plane orientation is used. The surface orientation of the surface of the growth layer 202 grown on the surface of the substrate 201 and the bottom surface of the guard groove 210 is also {100}. The substrate 201 is formed with a mark that indicates the direction of the {100} plane of the surface by a notch (orientation flat) or the like.

  In order to excavate the guard groove 210 by an etching method, when the resist film having the pattern of the guard groove 210 is formed, the direction in which the pattern of the guard groove 210 extends and the mark of the substrate 201 are aligned. The pattern is formed to extend in the direction of the {100} plane. The side surfaces of the guard groove 210 are formed perpendicular to the main surface of the substrate 201, and the side surfaces are formed to be parallel to each other or orthogonal to each other. Therefore, a surface having a surface orientation of {100} is exposed on the inner peripheral side surface of the guard groove 210 actually formed by etching.

  Since the same {100} plane as the surface of the growth layer 202 is exposed at the bottom surface of the guard groove 210, the {100} plane is exposed at all of the bottom surface and side surfaces inside the guard groove 210. As a result, the silicon single crystal constituting the guard region 211 grows uniformly, and the inside of the guard groove 210 is completely filled with the silicon single crystal constituting the guard region 211. In this case, when the semiconductor device 2 is viewed in a plan view and the four sides of the guard groove 210 are connected at a right angle, the surface of the pn junction formed between the guard region 211 and the growth layer 202 is bent at a right angle. As a result, the withstand voltage is lowered.

Therefore, conventionally, in order to prevent a decrease in breakdown voltage, the four corner portions of the guard groove 210 are bent with a constant radius of curvature, and the surface portion of the pn junction at the boundary between the guard region 211 and the growth layer 202 is bent at a right angle. It is formed so that there is no. Patent Documents 1 to 4 describe techniques related to the peripheral structure of a semiconductor device.
Japanese Patent No. 3628613 JP 2004-128293 A JP-A-1-272151 JP-A 63-227063

  In the conventional semiconductor device 2 shown in FIG. 8, when the corners of the guard groove 210 are rounded, the surface orientation of the side surfaces constituting the four sides of the guard groove 210 extending linearly is {100}. However, the plane orientation does not become {100} at the bent portions of the four corners connecting the side surfaces. For example, the surface orientation of the side surface of the middle portion of the bent portion is {110}. Therefore, there is a difference in the growth rate of the silicon single crystal constituting the guard region 211 between the linear part of the four sides of the guard groove 210 and the part bent at a certain radius of curvature, and the guard groove 210 is uniformly filled. There was a problem that it was impossible to do. If the guard region 211 cannot be uniformly filled and voids are present inside, there is a problem that the breakdown voltage is lowered at that portion, resulting in a failure.

  The present invention has been made in view of the above-described problems. The guard groove is uniformly filled, and the peripheral area required to obtain the same withstand voltage is reduced, so that the size and cost are reduced. An object of the present invention is to provide a semiconductor device capable of achieving the above.

The present invention has been made to solve the above problems, and the invention according to claim 1 includes a first conductivity type growth layer and a second conductivity type base region formed in the growth layer. A plurality of square ring-shaped guard grooves surrounding at least one portion, a second conductivity type guard region formed inside the guard groove, and an outer peripheral portion of the four corners in contact with the outer periphery of the guard region. A ring-shaped second conductivity type outer peripheral side auxiliary diffusion region and a ring-shaped second conductivity type inner peripheral side auxiliary diffusion region in contact with the inner periphery of the guard region, and the plurality of guard grooves are concentric The distance between the adjacent guard grooves increases from the inside to the outside, the width of the guard groove increases from the inside to the outside, and the depth of the guard groove increases from the inside to the outside. Deeper toward Ri, among the plurality of rectangular rings formed inside the guard region of the guard groove shape, the impurity concentration of the first conductivity type of the two widths of the growth layer sandwiched guard region and the growth layer adjacent the Is obtained by adding one half of the width of one of the two adjacent guard areas to one half of the width of the other of the two adjacent guard areas. The semiconductor device is characterized in that the value is equal to the product of the value and the impurity concentration of the second conductivity type in the two adjacent guard regions .

  According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the inner peripheral side auxiliary diffusion region has rounded inner peripheral portions at four corners.

  According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the product of the width of the guard region and the impurity concentration of the second conductivity type in the guard region is the guard region and It is characterized by being equal to the product of the width of the growth layer sandwiched between other guard regions and the impurity concentration of the first conductivity type in the growth layer.

  According to a fourth aspect of the present invention, in the semiconductor device according to any one of the first to third aspects, {100} planes are exposed on the side and bottom surfaces of the four sides of the guard groove, and the guard The region is formed of a semiconductor single crystal grown by an epitaxial growth method on the side surface and the bottom surface of the guard groove.

  According to a fifth aspect of the present invention, in the semiconductor device according to any one of the first to fourth aspects, the outer peripheral side auxiliary diffusion region and the inner peripheral side auxiliary diffusion region are formed from the surface of the growth layer. It is formed by diffusing impurities of two conductivity types.

  According to a sixth aspect of the present invention, in the semiconductor device according to any one of the first to fifth aspects, the outer peripheral side auxiliary diffusion region and the inner peripheral side auxiliary diffusion region are shallower than the guard region. It is formed.

  According to a seventh aspect of the present invention, in the semiconductor device according to any one of the first to sixth aspects of the present invention, the portion surrounded by the guard groove includes the base region of the second conductivity type, and the A MOS transistor cell having a first conductivity type source region formed in a base region, a gate insulating film in contact with the base region, and a gate electrode in contact with the gate insulating film is disposed. To do.

  According to an eighth aspect of the present invention, in the semiconductor device according to any one of the first to seventh aspects, a shot forming a Schottky junction with the growth layer in a portion surrounded by the guard groove. A key electrode is formed.

  According to the present invention, it is possible to obtain an effect that the guard groove is uniformly filled and the area of the peripheral portion required to obtain the same withstand voltage as in the prior art can be reduced, and the size and cost can be reduced.

  The best mode for carrying out the present invention will be described below with reference to the drawings. FIG. 1 shows a cross-sectional structure of a semiconductor device 1a (MOSFET) according to the first embodiment of the present invention, and FIG. 2 shows a planar structure. FIG. 1 shows a cross section taken along line X-X ′ of FIG. 2. The substrate 101 is made of a silicon single crystal containing n-type impurities at a high concentration, and a growth layer 102 made of a silicon epitaxial layer containing n-type impurities is formed on one main surface of the substrate 101 by epitaxial growth. Has been. Inside the growth layer 102, a base region 103 containing a p-type impurity is formed in the vicinity of the surface. The base region 103 is formed by diffusing p-type impurities from the surface of the growth layer 102.

  A plurality of rectangular active grooves 104 having an elongated cross section are arranged in parallel to each other so as to divide the base region 103. A buried region 105 containing a p-type impurity is formed inside the active trench 104. In the base region 103, a source region 106 containing an n-type impurity is formed adjacent to each active trench 104 on one side or both sides thereof. The source region 106 is exposed on the surface of the growth layer 102. The source region 106 is formed by diffusing n-type impurities from the surface of the growth layer 102.

  In the base region 103 between the adjacent active trenches 104, the two source regions 106 face each other, and a p-type impurity is higher than the base region 103 at a substantially central position between the two source regions 106. An ohmic region 107 included in the concentration is formed. Like the source region 106, the ohmic region 107 is exposed on the surface of the growth layer 102. The ohmic region 107 is also formed by diffusing p-type impurities from the surface of the growth layer 102.

  A gate insulating film 108 is formed in the active trench 104 in contact with the base region 103. A region surrounded by the gate insulating film 108 is filled with a gate electrode 109 made of a polysilicon material. Around the active groove 104 and the base region 103, a plurality of quadrangular guard grooves 110 having an elongated cross section are formed. As shown in FIG. 2, the guard groove 110 is formed so as to surround the cell region of the MOS transistor in which the active groove 104 and the base region 103 are formed. Each guard groove 110 has a quadrangular ring shape arranged concentrically, and the interval between adjacent guard grooves 110 increases from the inside toward the outside, and the width of the guard groove 110 increases from the inside to the outside. The guard groove 110 is formed so as to increase in depth from the inside toward the outside.

  No gate insulating film is formed on the inner periphery of the guard groove 110, and a silicon single crystal containing p-type impurities is grown on the bottom and side surfaces of the guard groove 110 by an epitaxial growth method. Is filled with a guard region 111 made of the silicon single crystal. The guard region 111 forms a pn junction with the growth layer 102, and the base region 103 and the active groove 104 are concentrically surrounded by the pn junction. The guard region 111 is not in contact with the base region 103 and is placed at a floating potential.

  An inner peripheral side auxiliary diffusion region 112 is adjacent to the inner peripheral side of each guard groove 110, and an outer peripheral side auxiliary diffusion region 113 is adjacent to the outer peripheral side. As shown in FIG. 2, the inner peripheral side auxiliary diffusion region 112 and the outer peripheral side auxiliary diffusion region 113 are both formed in a ring shape. The inner peripheral side auxiliary diffusion region 112 and the outer peripheral side auxiliary diffusion region 113 are in contact with the guard region 111 and are formed to have the same potential as the guard region 111. The four corners of the inner peripheral side auxiliary diffusion region 112 and the outer peripheral side auxiliary diffusion region 113 are bent with a predetermined radius of curvature, and are formed so as to round the inner periphery and outer periphery of the guard region 111.

  An oxide film 114 is formed by thermal oxidation on the growth layer 102, the inner peripheral side auxiliary diffusion region 112, and the outer peripheral side auxiliary diffusion region 113 in the region where the guard groove 110 is formed. On the guard region 111, the oxide film 114, the gate insulating film 108, the gate electrode 109, and a part of the source region 106, an insulating film 115 made of, for example, PSG is formed. The insulating film 115 is patterned, and the surfaces of the source region 106 and the ohmic region 107 are exposed at the bottom of the opening. A source electrode 116 made of a metal thin film such as aluminum is formed on the surface of these exposed regions and the insulating film 115. On the main surface of the substrate 101 opposite to the side on which the growth layer 102 is formed, a drain electrode 117 made of a metal thin film such as a nickel alloy is formed.

  The surface orientation of the surface of the substrate 101 and the growth layer 102 made of silicon single crystal is {100}, and the {100} plane is exposed on the bottom surface of each guard groove 110. Further, when the semiconductor device 1a is viewed in plan, the four corner portions of each guard groove 110 intersect with each other at right angles, and {100} is provided on both the vertical side surface and the lateral side surface of each guard groove 110. The surface is exposed. Therefore, in the guard region 111, there are no defects at the four corners, the epitaxial growth is uniform, and the inside of the guard groove 110 is filled without voids.

  The base region 103 is in contact with the gate insulating film 108 at a position below the source region 106. When the contacted region is called an inversion region, a channel is formed in the inversion region when the semiconductor device 1a is energized, and a current flows. That is, when a positive voltage equal to or higher than the threshold voltage is applied to the gate electrode 109 in a state where the source electrode 116 is connected to the ground potential and a positive voltage is applied to the drain electrode 117, the inversion region of the base region 103 becomes n. An inversion layer is formed by inverting the mold, the source region 106 and the growth layer 102 are connected by the inversion layer, and a current flows.

  In this state, when the voltage applied to the gate electrode 109 becomes equal to or lower than the threshold voltage because the gate electrode 109 is connected to the source electrode 116 or the like, the inversion layer disappears and no current flows. In this state, the pn junction between the base region 103 and the growth layer 102 is reverse-biased, and a depletion layer extends both inside the base region 103 and inside the growth layer 102, and also in the buried region 105. The depletion layer begins to spread.

  When the buried region 105 is connected to the base region 103, a depletion layer spreads in the growth layer 102 from both the base region 103 and the buried region 105, and a depletion layer begins to spread in the buried region 105. . When the amount of p-type impurity in buried region 105 is substantially equal to the amount of n-type impurity in growth layer 102 located between adjacent buried regions 105, the depletion layer spreads. When the growth layer 102 located between adjacent buried regions 105 becomes fully depleted, the interior of the buried region 105 is completely depleted at the same time, and is a region having a constant depth below the bottom of the base region 103. Is fully filled with a depletion layer, and it is known that the breakdown voltage is increased.

  On the other hand, when the depletion layer extending in the lateral direction from the buried region 105 and the base region 103 reaches the inner peripheral auxiliary diffusion region 112 and the guard region 111, the guard region 111 and the guard region 111 are similarly formed as described above. A depletion layer spreads in the growth layer 102 from the inner peripheral side auxiliary diffusion region 112 and the outer peripheral side auxiliary diffusion region 113 that are in contact with each other. When the voltage between the drain electrode 117 and the source electrode 116 increases and the depletion layer spreading from the inner guard region 111 side contacts the inner peripheral auxiliary diffusion region 112 of the outer guard region 111, the guard region 111. A depletion layer spreads in the growth layer 102 from the inner peripheral side auxiliary diffusion region 112 and the outer peripheral side auxiliary diffusion region 113 in contact with the guard region 111. As described above, the depletion layer sequentially spreads from the inner guard region 111, the inner peripheral auxiliary diffusion region 112 in contact with the guard region 111, and the outer peripheral auxiliary diffusion region 113 toward the outer guard region 111. The electric field strength near the surface of the growth layer 102 is relaxed.

  When the semiconductor device 1a is viewed in a plan view, the four sides of the guard region 111 intersect substantially at right angles, and the four corners of the guard region 111 are not rounded, but at the four corner positions on the outer periphery of the guard region 111, Four corner portions of the outer peripheral side auxiliary diffusion region 113 to which roundness is given are connected. Therefore, the electric field strength is significantly reduced at the four corners of the guard region 111 as compared to the case where the outer peripheral side auxiliary diffusion region 113 is not formed. Further, the inner peripheral side of the guard region 111 is connected to the inner peripheral side auxiliary diffusion region 112, and the inner peripheral side auxiliary diffusion region 112 with roundness is also provided inside the four corners of the inner periphery of the guard region 111. Since it is connected, the electric field is also relaxed in this part.

  Further, the {100} plane of the semiconductor crystal is exposed at the bottom and side surfaces of each active groove 104 and guard groove 110, and the buried region 105 and the guard region 111 grow from the same plane orientation. Therefore, the buried region 105 and the guard region 111 are free from defects and the breakdown voltage is improved.

  Next, the guard groove 110 and the guard region 111 of the semiconductor device 1a according to the present embodiment will be described. As described above, the distance between the adjacent guard grooves 110 increases from the inside toward the outside, the width of the guard groove 110 increases from the inside to the outside, and the depth of the guard groove 110 increases from the inside to the outside. It is getting deeper towards. When the growth layer 102 is etched to form the guard groove 110, the etching rate varies depending on the width of the opening of the mask material patterned into the shape of the guard groove 110 due to the microloading effect. Since the etching rate increases as the width of the opening increases, the depth of the guard groove 110 increases as the width of the guard groove 110 increases.

  In addition, due to the microloading effect, the speed of epitaxial growth when the guard region 111 is formed becomes faster as the outer guard groove 110, so that the guard groove 110 is formed in the same time as the time required to fill the inner active groove 104. Can be filled. With the structure as described above, the area of the peripheral portion (region where the guard groove 110 is formed) necessary to obtain a breakdown voltage comparable to that of the conventional structure can be made smaller than that of the conventional structure.

In the semiconductor device 1a according to the present embodiment, the so-called super junction (super-junction) in which the n-type region (growth layer 102) and the p-type region (the buried region 105 and the guard region 111) are alternately repeated in the growth layer 102 is provided. Bonding) structure. When the amount of impurities in the n-type region of the portion sandwiched between adjacent p-type regions is equal to the amount of impurities in the p-type region adjacent to the n-type region, a reverse voltage is applied. Both the n-type region and the p-type region are completely depleted, and the breakdown voltage is improved. In order to equalize the impurity amounts in both regions, the impurity concentration of the growth layer 102 is Nd, the lateral width is Wm, the impurity concentration of the buried region 105 or the guard region 111 is Na, and the lateral width is Wt. Then, Nd × Wm = Na × Wt holds, and the amount of impurities (Nd × Wm and Na × Wt) in each region needs to be 2.0 × 10 ¹² cm ⁻² or less.

The results of numerical calculation are shown below. Using the conventional structure and the structure of the present invention as models, the spread of the depletion layer when a reverse voltage was applied was calculated by the finite element method. In the conventional structure (FIG. 3), the thickness of the substrate 51 is 350 μm, and the n-type impurity concentration is 2.20 × 10 ¹⁹ cm ⁻³ . The thickness of the growth layer 52 was 23 μm and the n-type impurity concentration was 4.60 × 10 ¹⁵ cm ⁻³ . The center position of the active groove 54 having the outermost gate electrode 53 is set as a reference (origin) of the distance. The guard groove 55 has a width of 1.6 μm and a depth of 16 μm. The interval between adjacent guard grooves 55 is 4.0 μm. The p-type impurity concentration of the guard region 56 is 1.15 × 10 ¹⁶ cm ⁻³ .

Further, in order to make the other conditions except the guard groove the same as the structure of the present invention, the inner peripheral side auxiliary diffusion region 57 and the outer peripheral side auxiliary diffusion region 58 are provided, and the inner peripheral side auxiliary diffusion region 57 and the outer peripheral side are provided. The auxiliary diffusion region 58 had a width of 0.3 μm, a depth of 1.2 μm, and a p-type impurity concentration of 2.81 × 10 ¹⁷ cm ⁻³ . The guard groove 55 outside the outermost active groove 54 is not provided with an inner peripheral side auxiliary diffusion region. A base region 59 provided outside the active groove 54 is in contact with the source electrode 60. When a reverse voltage of 357.0 V is applied between the source electrode 60 and the drain electrode 61, a depletion layer extending from the boundary between the growth layer 52 and the guard region 56 toward the inside of the growth layer 52 is depleted. There were 25 guard grooves 55 on the inner side of the position where the boundary with the part of the non-grown growth layer 52 is exposed at the surface of the growth layer 52. Therefore, the distance from the origin to the 25th guard groove 55 was 140 μm.

In contrast, in the structure of the present invention (FIG. 4), the thickness of the substrate 11 and the n-type impurity concentration, the thickness of the growth layer 12 and the n-type impurity concentration are the same as those in the conventional structure. The center position of the active groove 14 having the outermost gate electrode 13 is set as a reference (origin) of the distance. The width and depth of the guard groove 15 are as shown in FIG. 5A for each region shown in FIG. 4, and the p-type impurity concentration of the guard region 16 is 1.15 × 10 ¹⁶ cm ⁻³ . Further, the interval between the adjacent guard grooves 15 is as shown in FIG. In FIG. 5B, for example, the distance between the adjacent guard grooves 15 in the area A is 4 μm, and the distance between the outermost active groove 14 in the area A and the innermost guard groove 15 in the area B is also 4 μm. It is shown. The width, depth, and p-type impurity concentration of the inner peripheral side auxiliary diffusion region 17 and the outer peripheral side auxiliary diffusion region 18 are the same as those of the conventional structure of FIG. The guard groove 15 outside the outermost active groove 14 is not provided with an inner peripheral side auxiliary diffusion region. A base region 19 provided outside the active groove 14 is in contact with the source electrode 20.

  When a reverse voltage of 362.0 V is applied between the source electrode 20 and the drain electrode 21, a depletion layer extending from the boundary between the growth layer 12 and the guard region 16 toward the inside of the growth layer 12 is depleted. The position where the boundary with the portion of the non-grown growth layer 12 is exposed on the surface of the growth layer 12 is just outside the 19th guard groove 15 as counted from the inside. Accordingly, there are 19 guard grooves 15 on the inner side of this position, and the distance from the origin to the 19th guard groove 15 is 123 μm. Therefore, the area of the peripheral structure necessary for obtaining a comparable breakdown voltage can be made smaller than that of the conventional structure. Thereby, size reduction and cost reduction can be achieved.

  In addition, within the range that satisfies the conditional expression of the super junction structure described above, the width of each guard groove 110 may be widened from the inside toward the outside, or the interval between the guard grooves 110 may be widened. As in the present embodiment, the width of the plurality of guard grooves 110 may be expanded as a unit, or the interval between the guard grooves 110 may be increased. In addition, the inner peripheral side auxiliary diffusion region 112 and the outer peripheral side auxiliary diffusion region 113 are less than the guard region 111 so as not to affect the conditions of the super junction structure that should be established between the growth layer 102 and the guard region 111. It is desirable to form it shallowly.

  Next, a second embodiment of the present invention will be described. FIG. 6 shows a cross-sectional structure of the semiconductor device 1b (Schottky barrier diode) according to the present embodiment, and FIG. 7 shows its planar structure. FIG. 6 shows a cross section taken along line Y-Y 'of FIG. Also in the semiconductor device 1b according to the present embodiment, a plurality of ring-shaped guard grooves 110 are formed concentrically in the n-type growth layer 102, as in the semiconductor device 1a according to the first embodiment. The interior of 110 is filled with a guard region 111 in which a p-type semiconductor crystal is epitaxially grown. The surface orientations of the side surface and the bottom surface of the guard groove 110 are {100}.

  Although the four corners of the guard region 111 are not rounded, the inner peripheral side auxiliary diffusion region 112 and the outer peripheral side auxiliary diffusion region 113 are connected to the inner peripheral side and the outer peripheral side of each guard region 111, and the guard region 111 At the four corner positions of the inner periphery and the outer periphery of 111, the rounded portions of the inner periphery side auxiliary diffusion region 112 and the outer periphery side auxiliary diffusion region 113 are arranged. The structures of the guard region 111, the inner peripheral side auxiliary diffusion region 112, and the outer peripheral side auxiliary diffusion region 113 are the same as those in the first embodiment.

  An active groove 120 having a rectangular cross section is formed in a non-contact manner with the guard groove 110 in a region inside the innermost auxiliary diffusion region 112 at the innermost periphery in the growth layer 102. Inside the active groove 120, a pressure resistant region 121 of the same p-type and the same material as the guard region 111 is formed. The upper end portion of the breakdown voltage region 121 is located at the same height as the surface of the growth layer 102, and the Schottky electrode 122 is formed on the surface of the breakdown voltage region 121 exposed on the surface of the growth layer 102 and on the surface of the growth layer 102. Has been. The Schottky electrode 122 forms an ohmic junction with the breakdown voltage region 121, and is formed with a metal thin film such as molybdenum or platinum that forms the Schottky junction with the growth layer. A back electrode 123 is formed on the main surface of the substrate 101 opposite to the side on which the growth layer 102 is formed.

  The outer peripheral edge portion of the Schottky electrode 122 is positioned on the inner side of the innermost auxiliary diffusion region 112 on the innermost periphery, and the Schottky electrode 122 has an inner auxiliary diffusion region 112, an outer auxiliary diffusion region 113, And it is formed so as not to contact the guard region 111.

  When the Schottky electrode 122 is applied with a positive voltage as an anode electrode and the back electrode 123 is applied with a negative voltage as a cathode electrode, the Schottky junction between the growth layer 102 and the Schottky electrode 122 is forward-biased. . When a voltage is applied between the Schottky electrode 122 and the back electrode 123 in a direction in which the Schottky junction is forward biased, the pn junction formed between the breakdown voltage region 121 and the growth layer 102 is also forward biased. .

  However, since the voltage at which the pn junction is forward-biased and the current starts to flow is larger than the voltage at which the Schottky junction is forward-biased and the current starts to flow, between the Schottky electrode 122 and the back electrode 123, Current flows only through the junction. Conversely, when a negative voltage is applied to the Schottky electrode 122 and a positive voltage is applied to the back electrode 123, both the Schottky junction and the pn junction are reverse-biased, and no current flows.

  In this state, a depletion layer spreads in the growth layer 102 from the Schottky junction between the Schottky electrode 122 and the growth layer 102 and the pn junction between the breakdown voltage region 121 and the growth layer 102. When the depletion layer reaches the guard region 111 and the inner peripheral side auxiliary diffusion region 112, the depletion layer spreads outward from the guard region 111, the inner peripheral side auxiliary diffusion region 112, and the outer peripheral side auxiliary diffusion region 113. In the semiconductor device 1b, the Schottky electrode 122 is a cathode electrode and the back electrode 123 is an anode electrode. However, the Schottky electrode may be an anode electrode and the back electrode may be a cathode electrode. Since the semiconductor device 1b according to the present embodiment has the same peripheral structure as that of the semiconductor device 1a according to the first embodiment, the area of the peripheral structure necessary to obtain a breakdown voltage comparable to that of the conventional structure is larger than that of the conventional structure. Can be reduced, and downsizing and cost reduction can be achieved.

  As described above, the embodiments of the present invention have been described in detail with reference to the drawings. However, the specific configuration is not limited to these embodiments, and includes design changes and the like without departing from the gist of the present invention. . For example, the values relating to the dimensions and physical properties of the respective structures shown in the drawings are examples, and are not limited to the above. In addition, a structure in which the p-type and the n-type are reversed from the above is also included in the present invention. Further, the semiconductor device of the present invention includes an IGBT (Insulated Gate Bipolar Transistor).

1 is a schematic cross-sectional view showing a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. 1 is a plan view showing a planar structure of a semiconductor device according to a first embodiment of the present invention. It is a schematic cross section which shows the model structure used for the numerical calculation in the 1st Embodiment of this invention. It is a schematic cross section which shows the model structure used for the numerical calculation in the 1st Embodiment of this invention. It is a reference figure which shows the model structure used for the numerical calculation in the 1st Embodiment of this invention. It is a schematic cross section which shows the cross-section of the semiconductor device by the 2nd Embodiment of this invention. It is a top view which shows the planar structure of the semiconductor device by the 2nd Embodiment of this invention. It is a schematic cross section which shows the cross-section of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a, 1b, 2 ... Semiconductor device, 11, 51, 101, 201 ... Substrate, 12, 52, 102, 202 ... Growth layer, 13, 53, 109, 209 ... Gate electrode, 14 , 54, 104, 120, 204 ... active groove, 15, 55, 110, 210 ... guard groove, 16, 56, 111, 211 ... guard region, 17, 57, 112 ... inner circumference Side auxiliary diffusion region, 18, 58, 113 ... Outer peripheral side auxiliary diffusion region, 20, 60, 116, 216 ... Source electrode, 21, 61, 117, 217 ... Drain electrode, 19, 59, 103 , 203 ... base region, 105, 205 ... buried region, 106, 206 ... source region, 107, 207 ... ohmic region, 108, 208 ... gate insulating film, 114, 214 ..Oxidation , 115, 215 ... insulating film, 121 ... voltage region, 122 ... Schottky electrode, 123 ... rear surface electrode

Claims (7)

A first conductivity type growth layer;
A plurality of square ring-shaped guard grooves surrounding a portion having one or more second conductivity type base regions formed in the growth layer;
A second conductivity type guard region formed in the guard groove;
A ring-shaped second conductivity type outer peripheral side auxiliary diffusion region in contact with the outer periphery of the guard region and rounded outer peripheral portions of the four corners;
A ring-shaped second conductivity type inner peripheral side auxiliary diffusion region in contact with the inner periphery of the guard region;
Have
The plurality of guard grooves are arranged concentrically, the interval between the adjacent guard grooves increases from the inside toward the outside, and the width of the guard grooves increases from the inside to the outside, the guard grooves The depth of becomes deeper from the inside to the outside,
Of the guard regions formed in the plurality of square ring-shaped guard grooves, the product of the width of the growth layer sandwiched between two adjacent guard regions and the impurity concentration of the first conductivity type in the growth layer Is a value obtained by adding one half of the width of one of the two adjacent guard areas to one half of the width of the other of the two adjacent guard areas. A semiconductor device characterized by being equal to the product of the impurity concentration of the second conductivity type in the two adjacent guard regions .   The semiconductor device according to claim 1, wherein the inner peripheral side auxiliary diffusion region has rounded inner peripheral portions at four corners.   {100} planes are exposed on the side and bottom surfaces of the four sides of the guard groove, and the guard region is formed of a semiconductor single crystal grown by epitaxial growth on the side and bottom surfaces of the guard groove. The semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor device.   4. The outer peripheral side auxiliary diffusion region and the inner peripheral side auxiliary diffusion region are formed by diffusing impurities of a second conductivity type from the surface of the growth layer. The semiconductor device according to any one of the items.   5. The semiconductor device according to claim 1, wherein the outer peripheral side auxiliary diffusion region and the inner peripheral side auxiliary diffusion region are formed shallower than the guard region. In the part surrounded by the guard groove,
The base region of the second conductivity type;
A first conductivity type source region formed in the base region;
A gate insulating film in contact with the base region;
A gate electrode in contact with the gate insulating film;
The semiconductor device according to claim 1, wherein a cell of a MOS transistor having the following characteristics is arranged.   7. The semiconductor according to claim 1, wherein a Schottky electrode that forms a Schottky junction with the growth layer is formed in a portion surrounded by the guard groove. 8. apparatus.

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