JP4849711B2 - Manufacturing method of semiconductor integrated circuit device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device manufacturing technique, and is particularly effective when applied to the manufacture of a semiconductor integrated circuit device having a step of depositing a silicon nitride film on a substrate using a thermal CVD (Chemical Vapor Deposition) method. Regarding technology.
[0002]
[Prior art]
In an LSI manufacturing process that has recently been miniaturized and highly integrated, an element isolation trench (SGI) is formed in a silicon substrate by utilizing the etching rate difference between a silicon oxide film and a silicon nitride film. Alternatively, a contact hole is formed in a self-aligned manner with respect to a gate electrode of a MISFET (Metal Insulator Semiconductor Field Effect Transistor). Such a method for forming an element isolation trench (SGI) is described in, for example, Japanese Patent Application Laid-Open No. 11-16999. A method for forming a self-aligned contact (SAC) is described in, for example, Japanese Patent Application Laid-Open No. 11-17147.
[0003]
A silicon nitride film used in the above-described element isolation groove forming process and self-aligned contact forming process is generally monosilane (SiH). _Four ) And ammonia (NH _Three ) And the source gas as a source gas. As the CVD apparatus, a hot wall type batch type thermal CVD apparatus that heat-treats a plurality of (for example, about 100) semiconductor wafers at once is used. A hot wall type thermal CVD apparatus employs a method of indirectly heating a semiconductor wafer (radiant heating by a heater outside the tube wall), and the inner wall of the chamber (reaction chamber) and the entire atmosphere in the chamber are the source. It is structured to be heated to a temperature above the gas decomposition temperature. In the case of a batch type thermal CVD apparatus, since it is necessary to uniformly diffuse the source gas into a large volume chamber, the film is usually formed under a reduced pressure condition of 0.13 kPa (1 Torr) or less. A CVD method is employed.
[0004]
[Problems to be solved by the invention]
The present inventors examined a technique for forming a silicon nitride film using a thermal CVD method. The following is an overview.
[0005]
A hot wall type batch-type thermal CVD apparatus widely used for forming a silicon nitride film has a structure that heats the entire atmosphere in the chamber (reaction chamber), so that reaction products are also formed on the inner wall of the chamber. Which accumulates and causes contamination of the wafer. Moreover, in order to remove this deposit, the complicated operation | work which cleans the inner wall of a chamber frequently is needed.
[0006]
In addition, since the batch type thermal CVD apparatus performs film formation under a reduced pressure condition of 0.13 kPa (1 Torr) or less as described above, the film formation rate becomes slow. In order to compensate for this, about 100 wafers are processed in a lump. However, if the chamber volume increases as the diameter of the wafer increases, it takes a lot of time to uniformly diffuse the source gas. Is required, and the deposition throughput is reduced. Furthermore, in the batch method in which a large number of wafers are processed at a time, if the wafer diameter increases, it becomes difficult to ensure film thickness uniformity within the wafer surface, and dislocations may occur in the wafer. Also occurs.
[0007]
Recently, as a measure for preventing a reduction in threshold voltage of a miniaturized MISFET, the gate electrode of the n-channel type MISFET is made of n-type polycrystalline silicon, and the gate electrode of the p-channel type MISFET is made of p-type polycrystalline silicon. However, the adoption of a so-called dual gate CMOS (or CMIS (Complementary Metal Insulator Semiconductor)) structure in which both are surface channel types is being promoted.
[0008]
In this case, when a high-temperature heat treatment is applied in the process after forming the gate electrode, the p-type impurity (boron) in the gate electrode made of p-type polycrystalline silicon diffuses into the semiconductor substrate (well) through the gate oxide film. There is a risk of changing the threshold voltage of the MISFET. Therefore, when depositing a silicon nitride film in the process after the formation of the gate electrode, it is necessary to precisely control the temperature condition of the film formation, but it is difficult to set the precise temperature condition with the above-described batch type thermal CVD apparatus. It is.
[0009]
A plasma CVD method is known as a method for depositing a silicon nitride film at a relatively low temperature that does not change the characteristics of the MISFET. However, since there is a problem of damage to the gate oxide film due to plasma and a problem of charge-up, the side wall spacer It is difficult to apply the silicon nitride film for silicon and the silicon nitride film for self-aligned contact.
[0010]
On the other hand, a single wafer thermal CVD apparatus that processes wafers one by one in a chamber can reduce the volume of the chamber as compared with the batch thermal CVD apparatus described above, and therefore it is easy to set precise temperature conditions. Even in a large-diameter wafer, in-plane film thickness uniformity can be improved. In addition, the source gas can be diffused uniformly and quickly even under conditions of quasi-atmospheric pressure of 1.3 kPa (10 Torr) to 93 kPa (700 Torr), which is higher than that of a batch type thermal CVD apparatus, improving the film formation rate. It can also be made. Furthermore, since the wafer processing flow can be continued by processing the wafers one by one, the cycle time of the wafer process can be shortened and the number of in-process lots can be reduced.
[0011]
In addition, the single wafer thermal CVD apparatus employs a cold wall method in which only the wafer and the vicinity thereof are heated in order to compensate for a decrease in throughput caused by processing the wafers one by one, so that the wafer is deposited on the inner wall of the chamber. There is less possibility of wafer contamination due to reaction products, and the work of cleaning the inner wall of the chamber is reduced.
[0012]
From the examination results as described above, the present inventors have particularly developed a silicon nitride film that requires high film thickness uniformity for sidewall spacers or self-aligned contacts on a large-diameter wafer having a diameter of about 20 cm to 30 cm. In the case of film formation, it was concluded that it is effective to use a cold wall type single wafer thermal CVD apparatus.
[0013]
However, the present inventors have found a new problem in the process of considering the introduction of a cold wall type single wafer thermal CVD apparatus into the memory LSI manufacturing process currently under development.
[0014]
In general, a memory LSI includes a memory mat and a peripheral circuit in one chip. Among these, in the memory mat, in order to realize a large storage capacity, MISFETs constituting the memory cell are arranged very densely, but in the peripheral circuit, MISFETs are arranged sparsely compared to the memory mat. The Therefore, when the gate electrode of the MISFET is formed on the wafer, each of the plurality of chip areas partitioned on the wafer has a sparse area (peripheral circuit) and a dense area (memory mat) of the gate electrode pattern density. Will occur.
[0015]
However, when a silicon nitride film is deposited on such a wafer by a thermal CVD method, the thickness of the silicon nitride film on the memory mat is larger than that of the silicon nitride film on the peripheral circuit in each of the plurality of chip regions. There was a phenomenon of thinning by about 30%. This is because the area where the gate electrode is dense (memory mat) has a larger effective surface area per wafer unit area than the sparse area (peripheral circuit), and the supply amount of the source gas is relatively short. This is thought to be because the amount of film deposition decreases.
[0016]
When the above problem (non-uniform film thickness) occurs, by performing dry etching on the silicon nitride film, sidewall spacers are formed on the sidewalls of the gate electrode of the memory mat and the gate electrode of the peripheral circuit, When forming a contact hole in a self-aligned manner with respect to a gate electrode or an element isolation region, if a thick silicon nitride film deposited on a peripheral circuit is completely etched, not only a thin silicon nitride film deposited on a memory mat Since the surface of the base (gate oxide film or substrate) is also removed, the characteristics of the MISFET constituting the memory cell are deteriorated.
[0017]
In general, monosilane (SiH _Four ) And ammonia (NH _Three ) Is used as a source gas, and the film formation mechanism of the silicon nitride film by the thermal CVD method is represented by the following formula (1):
3SiH _Four + 4NH _Three → Si _Three N _Four + 12H ₂ (1)
Monosilane (SiH _Four ) And ammonia (NH _Three ) And silicon nitride (Si _Three N _Four ) Is considered to be an endothermic reaction. In this reaction, the formation rate of silicon nitride is monosilane (SiH _Four ) Is considered to be rate-controlled.
[0018]
Therefore, when a silicon nitride film is deposited on a wafer having a mixture of sparse and dense patterns as described above, the flow ratio of monosilane to ammonia (SiH _Four / NH _Three ) And by supplying a sufficient amount of monosilane to the memory mat having a large effective surface area, it is presumed that the difference in film thickness of the silicon nitride film between the memory mat and the peripheral circuit can be reduced.
[0019]
However, when the present inventors deposited a silicon nitride film on a wafer using a cold-wall type single-wafer thermal CVD apparatus, the flow rate of monosilane was increased based on the above assumption. Contrary to expectation, the film thickness difference between the memory mat and the peripheral circuit was not reduced. Therefore, the present inventors have pursued the cause and derived the following conclusion.
[0020]
In the case of a hot wall type batch CVD apparatus in which the entire atmosphere in the chamber is heated, the source gas introduced into the chamber is heated to a temperature equal to or higher than the decomposition temperature of monosilane and ammonia before reaching the surface of the wafer. Therefore, pyrolyzed gas is supplied to the surface of the wafer. On the other hand, in the case of a cold wall type single wafer thermal CVD apparatus in which only the stage (susceptor) on which the wafer is mounted is heated, only the wafer and its vicinity become high temperature, so monosilane and ammonia in the source gas are Even if it is introduced into the chamber, it is not immediately pyrolyzed, but is pyrolyzed only after reaching the vicinity of the surface of the wafer. For this reason, ammonia having a decomposition temperature as high as about 250 ° C. compared with monosilane has a relatively low decomposition rate, and as a result, the amount of nitrogen atoms supplied to the surface of the wafer is insufficient. That is, in this case, even if the supply amount of monosilane is increased, the deposition rate of the silicon nitride film on the memory mat cannot be improved.
[0021]
Thus, when using the conventional hot wall type batch type CVD apparatus, monosilane (SiH _Four The film formation mechanism of non-uniform film formation due to the supply rate-determining is the case where the silicon nitride film is formed using a cold wall type single wafer thermal CVD apparatus. It has been clarified by the present inventors that it is not applicable to the above.
[0022]
An object of the present invention is to form silicon nitride in a sparse region and a dense region when a silicon nitride film is deposited on a semiconductor wafer having a sparse region and a dense region by a thermal CVD method. An object of the present invention is to provide a technique capable of reducing a film thickness difference between films.
[0023]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0024]
[Means for Solving the Problems]
Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
[0025]
A method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a first silicon nitride film on a main surface of a semiconductor substrate by a thermal CVD method using a first source gas containing a silane-based gas and an ammonia gas. (B) forming a plurality of first patterns having a sparse pattern density and a dense area on the main surface of the semiconductor substrate; and (c) a silane-based gas and ammonia. Depositing a second silicon nitride film on a main surface of the semiconductor substrate on which the plurality of first patterns are formed by a thermal CVD method using a second source gas containing a gas, The first source gas and the second source gas are different in flow rate ratio between the silane-based gas and the ammonia gas.
[0026]
The method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a first silicon nitride film on a main surface of a semiconductor wafer by a thermal CVD method using a first source gas containing a silane-based gas and an ammonia gas. (B) forming a plurality of first patterns having a sparse pattern density and a dense pattern on the main surface of the semiconductor wafer; and (c) a silane-based gas and ammonia. Depositing a second silicon nitride film on a main surface of the semiconductor wafer on which the plurality of first patterns are formed by a thermal CVD method using a second source gas containing a gas, The second source gas has a larger flow rate ratio of the ammonia gas to the silane-based gas than the first source gas.
[0027]
The method for manufacturing a semiconductor integrated circuit device according to the present invention includes: (a) a first silicon nitride film on a main surface of a semiconductor wafer by a thermal CVD method using a first source gas containing a silane-based gas and an ammonia gas. (B) forming a plurality of gate electrodes having a sparse pattern density and a dense pattern on the main surface of the semiconductor wafer; and (c) a silane-based gas and an ammonia gas. Depositing a second silicon nitride film on a main surface of the semiconductor wafer on which the plurality of gate electrodes are formed by a thermal CVD method using a second source gas including: (d) the first Forming a sidewall spacer made of the second silicon nitride film on each side wall of the plurality of gate electrodes by anisotropically etching the second silicon nitride film. The second source gas, the flow rate ratio of the ammonia gas to the silane gas is greater than the first source gas.
[0028]
In the present application, the term “semiconductor integrated circuit device” is not limited to those manufactured on a single crystal silicon substrate. Film Transistor) includes those made on other substrates such as liquid crystal manufacturing substrates. A wafer refers to a single crystal silicon substrate (generally substantially disk-shaped), an SOI substrate, a glass substrate, other insulating, semi-insulating, or semiconductor substrates used in the manufacture of a semiconductor integrated circuit device or a composite substrate thereof.
[0029]
The chip or the chip area is a unit integrated circuit area shown in FIG. 1 corresponding to a portion to be divided after the previous process of the wafer is completed.
[0030]
The sub-atmospheric reduced pressure region generally refers to a pressure range of 1.3 kPa to 93 kPa. In addition, the quasi-normal pressure region refers to a pressure range from 106 kPa to 133 kPa in the present application, and includes the normal pressure and the quasi-normal pressure region.
[0031]
A cold wall type single wafer thermal CVD apparatus is a cold wall type heat treatment furnace that generally heats a wafer to a temperature higher than that of an outer peripheral wall (resistance heating, high frequency induction heating, or lamp heating), and does not directly use plasma or the like. This is a CVD apparatus that performs film formation on a wafer basis.
[0032]
In addition, the gas atmosphere can include a reaction gas such as a source gas, a carrier gas, a dilution gas, and other additive gases. Further, when referring to each gas composition, addition of other elements is allowed unless otherwise specified.
[0033]
Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), unless otherwise specified and clearly limited to a specific number in principle. It is not limited to the specific number, and may be a specific number or more. Furthermore, in the following embodiments, the constituent elements (including element steps) are not necessarily essential unless explicitly stated or apparently essential in principle. Not too long.
[0034]
Similarly, in the following embodiments, when referring to the shapes and positional relationships of components and the like, the shapes and the like of the components are substantially the same unless explicitly stated or otherwise apparent in principle. Including those that are approximate or similar to. The same applies to the above numerical values and ranges.
[0035]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0036]
(Embodiment 1)
FIG. 1 is a block diagram of a silicon chip 1A on which an SRAM (Static Random Access Memory) of this embodiment is formed. The silicon chip 1A on which the SRAM is formed is used by being incorporated in a portable electronic device or the like, and on its main surface, a storage unit divided into a plurality of memory mats and an input / output circuit (input) A peripheral circuit including a buffer decoder, an output circuit), a control circuit, a reference voltage generation circuit (step-down power supply circuit), and the like are formed.
[0037]
FIG. 2 is an equivalent circuit diagram of the memory cells formed in the storage unit. The SRAM memory cell includes a pair of driving MISFETs (Qd) arranged at the intersections between a pair of complementary data lines (DL, / DL) and a word line (WL). ₁ , Qd ₂ ), A pair of load MISFETs (Qp ₁ , Qp ₂ ) And a pair of transfer MISFETs (Qt) ₁ , Qt ₂ ). MISFET for driving (Qd ₁ , Qd ₂ ) And transfer MISFET (Qt) ₁ , Qt ₂ ) Is composed of an n-channel type MISFET and a load MISFET (Qp). ₁ , Qp ₂ ) Is composed of a p-channel type MISFET. That is, the memory cell is configured as a complete CMOS type using four n-channel MISFETs and two p-channel MISFETs. The complete CMOS memory cell has a feature of low power consumption because it has less standby leakage current than a load resistance memory cell using four n-channel MISFETs and two high resistance load elements. I have.
[0038]
Of the six MISFETs constituting the memory cell, the driving MISFET Qd ₁ And load MISFETQp ₁ Is the first inverter (INV ₁ ) For driving MISFETQd ₂ And load MISFETQp ₂ Is the second inverter (INV ₂ ). These pair of inverters (INV ₁ , INV ₂ ) Constitutes a flip-flop circuit as an information storage unit which is cross-coupled in the memory cell and stores 1-bit information.
[0039]
One input / output terminal of the flip-flop circuit is connected to the transfer MISFET Qt. ₁ The other input / output terminal is connected to one of the source and drain of the MISFET Qt for transfer. ₂ Is connected to one of the source and drain. MISFETQt for transfer ₁ The other of the source and drain is connected to the data line DL, and the transfer MISFET Qt ₂ The other of the source and drain is connected to the data line / DL. One end of the flip-flop circuit (two load MISFETs Qp ₁ , Qp ₂ Is connected to a power supply voltage (Vcc) of 3.3 V, for example, and the other end (two drive MISFETs Qd). ₁ , Qd ₂ For example, one of the source and the drain is connected to a GND voltage of 0 V, for example.
[0040]
FIG. 3 is a plan view showing the gate electrode pattern of each of the six MISFETs constituting the memory cell. In addition, the rectangular area | region which connected the 4 + mark shown in the figure with the straight line has shown the area | region for one memory cell.
[0041]
Six MISFETs (driving MISFETs Qd constituting the memory cell) ₁ , Qd ₂ , MISFET Qp for load ₁ , Qp ₂ And transfer MISFETQt ₁ , Qt ₂ ) Is formed in the active region (Ln, Lp) surrounded by the element isolation trench 4 on the main surface of the substrate 1. MISFET Qd for driving composed of n-channel type ₁ , Qd ₂ And transfer MISFETQt ₁ , Qt ₂ Is formed in the active region Lp in which the p-type well is formed and is a p-channel type load MISFET Qp ₁ , Qp ₂ Is formed in the active region Ln in which the n-type well is formed.
[0042]
MISFETQt for transfer ₁ , Qt ₂ Has a gate electrode 9A configured integrally with the word line WL. The gate electrode 9A is composed of an n-type polycrystalline silicon film doped with phosphorus (P) and a Co (cobalt) silicide layer formed thereon.
[0043]
Flip-flop circuit first inverter (INV ₁ MISFETQd for driving constituting) ₁ And load MISFETQp ₁ Has an integrally configured gate electrode. Of these gate electrodes, driving MISFET Qd ₁ The portion used as the gate electrode (gate electrode 9B) is composed of an n-type polycrystalline silicon film doped with phosphorus and a Co silicide layer formed thereon, and the load MISFET Qp ₁ The portion used as the gate electrode (gate electrode 9C) is composed of a p-type polycrystalline silicon film doped with boron (B) and a Co silicide layer formed thereon.
[0044]
Similarly, the second inverter (INV of the flip-flop circuit) ₂ MISFETQd for driving constituting) ₂ And load MISFETQp ₂ Has an integrally configured gate electrode, and is a driving MISFET Qd. ₂ The portion used as the gate electrode (gate electrode 9B) is composed of an n-type polycrystalline silicon film doped with phosphorus and a Co silicide layer formed thereon, and the load MISFET Qp ₂ The portion used as the gate electrode (gate electrode 9C) is composed of a p-type polycrystalline silicon film doped with boron and a Co silicide layer formed thereon.
[0045]
On the other hand, peripheral circuits such as an input / output circuit (input buffer decoder, output circuit), a control circuit, and a reference voltage generation circuit (step-down power supply circuit) are configured by complementary MISFETs that combine an n-channel MISFET and a p-channel MISFET. Has been. The gate electrode of the n-channel type MISFET is composed of an n-type polycrystalline silicon film doped with phosphorus and a Co silicide layer formed thereon, and the gate electrode of the p-channel type MISFET is a p-type polycrystalline silicon film doped with boron. It consists of a crystalline silicon film and a Co silicide layer formed thereon.
[0046]
Next, a manufacturing method of the MISFET constituting the SRAM memory cell and the peripheral circuit will be described with reference to FIGS.
[0047]
First, as shown in FIG. 4, a substrate (silicon wafer) 1 made of p-type single crystal silicon having a specific resistance of, for example, about 1 to 10 Ωcm is thermally oxidized at about 850 ° C., and a film thickness of about 10 nm is formed on the surface. After the thin silicon oxide film 2 is formed, a silicon nitride film 3 having a thickness of about 120 nm is deposited on the silicon oxide film 2 by a CVD method. The silicon nitride film 3 is used as a mask when the substrate 1 in the element isolation region is etched to form a groove. Further, since the silicon nitride film 3 has the property of being hardly oxidized, it is also used as a mask for preventing the surface of the lower substrate 1 from being oxidized. The silicon oxide film 2 below the silicon nitride film 3 relieves stress generated at the interface between the substrate 1 and the silicon nitride film 3 and causes defects such as dislocations on the surface of the substrate 1 due to the stress. Form to prevent.
[0048]
FIG. 5 is a schematic view of a cold wall type single wafer thermal CVD apparatus 100 used for depositing the silicon nitride film 3.
[0049]
A stage 102 on which a silicon wafer (substrate) 1 is mounted is provided at the center of the chamber 101 of the single wafer thermal CVD apparatus 100. Inside the stage 102, a heater (not shown) for heating the silicon wafer 1 is provided. Above the stage 102, monosilane (SiH _Four ) And ammonia (NH _Three ) Source gas consisting of nitrogen (N ₂ A shower head that supplies the surface of the silicon wafer 1 together with a carrier gas such as) is provided. In addition, a temperature control mechanism (not shown) that sets the inner wall of the chamber 101 to a temperature lower than the temperature of the stage 102 and the silicon wafer 1 is provided outside the chamber 101.
[0050]
The single wafer thermal CVD apparatus 100 that processes the silicon wafers one by one in one chamber 101 can easily ensure precise temperature conditions as compared with the batch thermal CVD apparatus, and can form a film on the wafer surface. It is characterized by good thickness uniformity. In particular, a cold wall type CVD apparatus that forms a film by lowering the inner wall temperature of the chamber 101 below the temperature of the stage 102 or the silicon wafer 1 forms a film by reacting most of the source gas on the surface of the silicon wafer 1. In addition, since a film is hardly deposited on the inner wall of the chamber 101 having a low temperature, film formation with high throughput becomes possible.
[0051]
On the other hand, in the case of a hot wall type CVD apparatus that forms a film by heating the entire interior of the chamber to a uniform temperature, a film is deposited not only on the wafer surface but also on the inner wall surface of the chamber 101. . Therefore, it takes a long time for the film deposited on the wafer surface to have a desired thickness, and it is necessary to periodically remove the film deposited on the inner wall surface of the chamber 101.
[0052]
In this embodiment, the temperature of the silicon wafer 1 is set to 750 ° C., the inner wall temperature of the chamber 101 is set to 30 ° C., monosilane flow rate = 20 sccm, ammonia flow rate = 1400 sccm, nitrogen flow rate = 3600 sccm, gas pressure = 36 kPa (275 Torr). A silicon nitride film 3 is deposited under conditions. The silicon nitride film 3 has a substantially uniform film thickness over the entire surface of the substrate (silicon wafer) 1 because the surface of the underlying silicon oxide film 2 is flat.
[0053]
Next, as shown in FIG. 6, after selectively removing the silicon nitride film 3 in the element isolation region and the silicon oxide film 2 therebelow by dry etching using a photoresist film (not shown) as a mask, A groove 4a having a depth of about 350 to 400 nm is formed in the substrate 1 in the element isolation region by dry etching using the silicon nitride film 3 as a mask.
[0054]
Next, as shown in FIG. 7, a silicon oxide film 5 is deposited on the substrate 1 including the inside of the groove 4a. The silicon oxide film 5 is deposited with a film thickness (for example, about 450 to 500 nm) thicker than the depth of the groove 4 a so that the inside of the groove 4 a is completely filled with the silicon oxide film 5. The silicon oxide film 5 is made of, for example, oxygen and tetraethoxysilane ((C ₂ H _Five ) _Four Si) is deposited by a plasma CVD method using a source gas.
[0055]
Next, after the substrate 1 is thermally oxidized at about 1000 ° C. and densification (baking) is performed to improve the film quality of the silicon oxide film 5 embedded in the groove 4a, chemical mechanical polishing is performed as shown in FIG. The element isolation trench 4 is formed by polishing the silicon oxide film 5 on the upper portion of the trench 4a using the (CMP) method and planarizing the surface. This polishing is performed using the silicon nitride film 3 covering the surface of the substrate 1 in the active region as a stopper, and the end point is when the height of the surface of the silicon oxide film 5 becomes the same as that of the silicon nitride film 3. . Thereafter, the silicon nitride film 3 covering the surface of the substrate 1 in the active region is removed with hot phosphoric acid.
[0056]
Next, as shown in FIG. 9, an n-type impurity (for example, phosphorus) is ion-implanted into a part of the substrate 1, and a p-type impurity (boron) is ion-implanted into another part. The impurity is diffused by heat treatment at a temperature of 0 ° C., thereby forming the n-type well 6 in a part of the substrate 1 and the p-type well 7 in the other part.
[0057]
Next, after the surface of the substrate 1 is cleaned by wet etching using hydrofluoric acid, the substrate 1 is thermally oxidized at about 800 to 850 ° C. as shown in FIG. 7, clean gate oxide film 8 is formed on each surface, and then gate electrodes 9 </ b> A to 9 </ b> E are formed on top of gate oxide film 8. For the gate electrodes 9A to 9E, a polycrystalline silicon film having a thickness of about 200 nm to 250 nm is deposited on the gate oxide film 8 by CVD, and then an n-type impurity (phosphorus) is ionized in a part of the polycrystalline silicon film. After the implantation, p-type impurities (boron) are ion-implanted into the other part, and the polycrystalline silicon film is formed by dry etching using the photoresist film as a mask.
[0058]
The gate electrode 9A is made of an n-type polycrystalline silicon film doped with phosphorus, and a transfer MISFET Qt constituting a part of the memory cell. ₁ , Qt ₂ Used as a gate electrode and a word line WL. The gate electrode 9B is also made of an n-type polycrystalline silicon film, and is a driving MISFET Qd that forms part of the memory cell. ₁ , Qd ₂ Used as a gate electrode. The gate electrode 9C is made of a p-type polycrystalline silicon film doped with boron, and a load MISFET Qp constituting a part of the memory cell. ₁ , Qp ₂ Used as a gate electrode.
[0059]
The gate electrode 9D is made of an n-type polycrystalline silicon film doped with phosphorus, and is used as a gate electrode of an n-channel MISFET (Qa) constituting a part of the peripheral circuit. The gate electrode 9E is made of a p-type polycrystalline silicon film doped with boron, and is used as a gate electrode of a p-channel type MISFET (Qb) constituting a part of the peripheral circuit.
[0060]
Six MISFETs (driving MISFETs Qd constituting the memory cell) ₁ , Qd ₂ , MISFET Qp for load ₁ , Qp ₂ And transfer MISFETQt ₁ , Qt ₂ ) Are extremely densely arranged, the gate electrodes 9A to 9C are arranged close to each other. On the other hand, since the MISFETs constituting the peripheral circuit are arranged sparsely, the gate electrodes 9D and 9E are arranged apart from each other. For this reason, when the gate electrodes 9A to 9E are formed on the main surface of the silicon wafer (substrate) 1, each of the plurality of chip regions divided on the main surface of the wafer has a dense gate electrode pattern (memory mat). And a sparse area (peripheral circuit).
[0061]
Next, as shown in FIG. 11, phosphorus or arsenic (As) is ion-implanted into the p-type well 7 to form n with a low impurity concentration. ^- P-type semiconductor region 10 is formed and boron is ion-implanted into n-type well 6 to form a low impurity concentration p. ^- After forming the type semiconductor region 11, a silicon nitride film 12 having a thickness of about 50 nm is deposited on the main surface of the substrate 1 by a CVD method.
[0062]
For the deposition of the silicon nitride film 12, the cold wall type single wafer thermal CVD apparatus 100 shown in FIG. 5 is used.
[0063]
Here, when various parameters when the silicon nitride film 12 is deposited are changed, the gate electrode pattern is deposited on the silicon nitride film 12 deposited on a dense region (memory mat) and on a sparse region (peripheral circuit). FIG. 12 shows the results of measuring how the film thickness difference with the silicon nitride film 12 changes. Eight types of line graphs shown in the figure are, in order from the left, A: annealing time of ammonia, B: temperature of the inner wall of the chamber 101, C: distance from the stage 102 to the shower head 103, D: gas pressure in the chamber 101, E: wafer temperature, F: nitrogen flow rate, G: ammonia flow rate, and H: monosilane flow rate. The vertical axis indicates how much the difference in film thickness of the silicon nitride film 12 changes when each of these eight types of parameters is set to the three types shown in FIG. 13 (two types only for the annealing time of ammonia). This indicates that the larger the numerical value, the smaller the film thickness difference.
[0064]
From this figure, it can be seen that the gas pressure (D), the ammonia flow rate (G), and the monosilane flow rate (H) in the chamber 101 greatly contribute to fluctuations in the film thickness difference of the silicon nitride film 12. Further, as the gas pressure (D) in the chamber 101 is increased or the ammonia flow rate (G) is increased, the difference in film thickness of the silicon nitride film 12 becomes smaller. Conversely, as the monosilane flow rate (H) is increased, silicon nitride is increased. It can be seen that the film thickness difference of the film 12 increases.
[0065]
FIG. 14 shows the difference in film thickness of the silicon nitride film 12 when the gas pressure in the chamber 101 is set to 26 kPa (200 Torr) and 46 kPa (350 Torr), respectively, and the flow rate ratio (%) of ammonia and monosilane is changed. The result of measuring whether it changes to is shown. From this figure, it can be seen that the difference in film thickness of the silicon nitride film 12 decreases as the ammonia flow rate ratio increases.
[0066]
From the above measurement results, in order to reduce the film thickness difference between the silicon nitride film 12 deposited in the dense region (memory mat) and the silicon nitride film 12 deposited in the sparse region (peripheral circuit). It is effective to increase the flow ratio of ammonia to monosilane and to increase the gas pressure in the chamber 101.
[0067]
Specifically, the ratio of the thickness of the silicon nitride film 12 deposited in the dense region (memory mat) to the thickness of the silicon nitride film 12 deposited in the region (peripheral circuit) where the gate electrode pattern is sparse is 80. In order to set the gas pressure to 46 kPa (350 Torr), it is desirable to set the flow rate ratio of ammonia to monosilane to at least 40 times or more. Further, in order to make the film thickness ratio 85% or more (film thickness difference 15% or less), the flow rate ratio of ammonia to monosilane is at least 100 times or more, and the film thickness ratio is 90% or more (film). In order to make the thickness difference 10% or less, it is desirable that the flow rate ratio is at least 250 times or more.
[0068]
In this embodiment, the temperature of the silicon wafer 1 is set to 750 ° C. (the heater set temperature is 800 ° C., and the wafer top surface temperature is generally lower by about 50 ° C. than the heater set temperature), and the inner wall temperature of the chamber 101 is set to 25 ° C. By setting and depositing the silicon nitride film 12 under the conditions of monosilane flow rate = 10 sccm, ammonia flow rate = 5000 sccm, nitrogen flow rate = 5000 sccm, gas pressure = 46 kPa (350 Torr), the gate electrode pattern has a dense region (memory mat). The film thickness of the silicon nitride film 12 can be made almost uniform in a sparse region (peripheral circuit).
[0069]
Next, as shown in FIG. 15, the silicon nitride film 12 is anisotropically dry etched to form sidewall spacers 12A on the sidewalls of the gate electrodes 9A to 9E. In this embodiment, since the thickness of the silicon nitride film 12 can be made substantially uniform between the memory mat and the peripheral circuit, the sidewall spacer 12A is formed without removing the gate oxide film 8 and the substrate 1 of the memory mat. can do.
[0070]
Next, as shown in FIG. 16, phosphorus or arsenic (As) is ion-implanted into the p-type well 7 to increase the n impurity concentration. ⁺ Type semiconductor regions (source, drain) 13 are formed, and boron is ion-implanted into the n-type well 6 to form a high impurity concentration p. ⁺ A type semiconductor region (source, drain) 14 is formed. Subsequently, n is performed by wet etching using hydrofluoric acid. ⁺ Type semiconductor region (source, drain) 13 and p ⁺ After removing the gate oxide film 8 on each surface of the type semiconductor region (source, drain) 14, a Co film is deposited on the substrate 1 by a sputtering method, and gate electrodes 9A to 9E, n are formed by a silicide reaction by heat treatment. ⁺ Type semiconductor region (source, drain) 13 and p ⁺ After the Co silicide layer 15 is formed on each surface of the type semiconductor region (source, drain) 14, the unreacted Co film is removed by wet etching. Through the steps so far, the drive MISFET Qd, the load MISFET Qp, and the transfer MISFET Qt are formed in the memory mat, and the n-channel MISFET Qa and the p-channel MISFET Qb are formed in the peripheral circuit.
[0071]
Next, as shown in FIG. 17, a silicon nitride film 16 having a thickness of about 50 nm is deposited on the main surface of the substrate 1 by a CVD method. The silicon nitride film 16 is deposited using the cold wall type single wafer thermal CVD apparatus 100 shown in FIG. The film forming conditions are the same as those of the silicon nitride film 12 used for forming the sidewall spacer 12A. Thereby, the film thickness of the silicon nitride film 16 can be made substantially uniform in a region where the gate electrode pattern is dense (memory mat) and a region where the gate electrode pattern is sparse (peripheral circuit).
[0072]
Next, as shown in FIG. 18, after depositing a silicon oxide film 17 on the silicon nitride film 16 by plasma CVD using, for example, oxygen and tetraethoxysilane as source gases, a photoresist film (not shown) is formed. ) As a mask, the silicon oxide film 17 and the silicon nitride film 16 are sequentially dry-etched to obtain n ⁺ Type semiconductor region (source, drain) 13, p ⁺ Contact holes 20 to 29 are formed above the type semiconductor region (source, drain) 14 and the gate electrode 9B.
[0073]
The dry etching of the silicon oxide film 17 is performed under the condition that the etching speed of the silicon oxide film 17 is higher than the etching speed of the silicon nitride film 16 using the silicon nitride film 16 as an etching stopper. The etching of the silicon nitride film 16 is performed under the condition that the etching rate is higher than the etching rate of the silicon oxide film 5 embedded in the element isolation trench 4. Thereby, the contact holes 20 to 25 of the memory mat can be formed in self-alignment with the gate electrodes 9A to 9C and the element isolation trench 4, respectively. In this embodiment, since the film thickness of the silicon nitride film 16 can be made substantially uniform between the memory mat and the peripheral circuit, the silicon oxide film 5 and the substrate 1 embedded in the element isolation groove 4 of the memory mat are scraped. The contact holes 20 to 29 can be formed without any problems.
[0074]
Next, as shown in FIG. 19, the metal film deposited on the silicon oxide film 17 is patterned to form first-layer wirings 30-39.
[0075]
(Embodiment 2)
A second embodiment of the present invention will be described based on FIGS. 20 to 24 and FIGS. The contents of the description and drawings in the above embodiment are substantially the same except when there are alternative drawings and when different descriptions are given, and will not be described repeatedly.
[0076]
As described in the above embodiment, the ratio of the thickness of the silicon nitride film in the dense region to the thickness of the silicon nitride film in the sparse region in the chip region is large (that is, the thickness of the silicon nitride film). To reduce the difference, the flow rate ratio between ammonia and monosilane (NH _Three / SiH _Four It is important to control the deposition pressure. In this embodiment, this flow rate ratio (NH _Three / SiH _Four ) And the film forming pressure were further examined in detail.
[0077]
FIG. 20 shows the film formation pressure dependence of the film thickness ratio (hereinafter referred to as the sparse / dense film thickness ratio) and the NH / semiconductor film thickness ratio maximizing for each film formation pressure. _Three / SiH _Four The measurement result of the film formation pressure dependence of the flow rate ratio is shown.
[0078]
FIG. 21 is a schematic view of the cold wall type single wafer thermal CVD apparatus 100 used for this measurement. The basic structure of this device is the same as the device shown in FIG. 5 of the above embodiment. The volume of the chamber 101 is about 6 liters, and a resistance heating type heater is built in the stage 102. A pressure gauge (BARATRON type 624) 104 for measuring a film forming pressure and an exhaust pipe 107 including a mechanical booster pump 105 and a dry pump 106 are attached to the side wall of the chamber 101. The wafer 1 is a silicon wafer having a diameter of 20 cm in which gate electrodes (9A to 9E) as shown in FIG. 10 are formed in each chip region.
[0079]
As shown in the figure, the film thickness ratio of the sparse / dense part (indicated by a dashed line) and NH _Three / SiH _Four It was found that the flow rate ratio (shown by the solid line) has an optimum value within a certain range with respect to the film forming pressure. In other words, in order to make the thickness ratio of the dense / dense part more than a certain value, the film formation pressure and NH _Three / SiH _Four It is necessary to control the flow rate ratio within a certain range.
[0080]
Next, FIG. 22 shows the results of detailed measurement of conditions in which the thickness ratio of the silicon nitride film is 85% or more (film thickness difference 15% or less) and 95% or more (film thickness difference 5% or less).
[0081]
As the wafer, a 20 cm wafer in which each chip area was divided into blocks as shown in FIG. 1 was used. As shown in FIGS. 23A and 23B, a gate electrode is formed in the memory cell of each chip region, and a part of the peripheral circuit is for film thickness inspection having an outer dimension of about 100 μm × 100 μm. A pad 40 is formed. The evaluation of the thickness ratio of the sparse / dense portion is performed by depositing a silicon nitride film having a thickness of 100 nm on the wafer using the cold wall type single wafer thermal CVD apparatus shown in FIG. This was done by measuring the ratio of the film thickness to the film thickness on the memory array. The wafer temperature during film formation is 750 ° C. (generally, a suitable range is from 650 ° C. to 800 ° C., but a possible range by slightly changing other conditions is 600 ° C. to 850 ° C. The temperature of the inner wall of the chamber 101 was set to 30 ° C., respectively. The supply sequence of the source gas (ammonia + monosilane) at this time is shown in FIG. 24A, and the pressure change of the source gas is shown in FIG.
[0082]
From the above measurement results, NH _Three / SiH _Four It has been found that by setting the flow rate ratio to about 150 times to about 750 times and the film forming pressure to be in the range of about 37 kPa (280 Torr) to about 50 kPa (380 Torr), the dense portion film thickness ratio becomes 85% or more. Also preferably NH _Three / SiH _Four The flow rate ratio is about 200 times to about 650 times, and the film forming pressure is in the range of about 39 kPa (295 Torr) to about 49 kPa (365 Torr), more preferably NH. _Three / SiH _Four It has been found that by setting the flow rate ratio in the range of about 300 times to about 550 times and the film forming pressure in the range of about 41 kPa (310 Torr) to about 47 kPa (350 Torr), the dense part thickness ratio is further increased. That is, it has been found that the uniformity is further increased. In particular, NH _Three / SiH _Four By setting the flow rate ratio to around 450 times and the film forming pressure to around 44 kPa (330 Torr), the dense part thickness ratio could be 95% or more.
[0083]
The above film formation pressure and NH _Three / SiH _Four The optimum range of the flow rate ratio can be applied not only to a wafer having a diameter of 20 cm but also to a wafer having other dimensions. However, since the surface area changes as the wafer dimensions change, it is necessary to increase or decrease the flow rate of the source gas according to the surface area. For example, a wafer having a diameter of 30 cm has a surface area of 2.25 times that of a wafer having a diameter of 20 cm. Therefore, the flow rate of the source gas needs to be increased by, for example, 2.25 times. _Three / SiH _Four The flow rate ratio may be the same.
[0084]
Further, the cold wall type single wafer thermal CVD apparatus used for forming the silicon nitride film is not limited to the one shown in FIG. 21 and uses variously modified details without departing from the gist of the present invention. can do. For example, although the apparatus shown in FIG. 21 employs a method of heating a wafer with a resistance heating type heater built in the stage 102, the wafer may be heated by a lamp heating method. The lamp heating method has an advantage that the temperature raising / lowering characteristics are superior to the resistance heating method. On the other hand, the resistance heating method has a feature that less contamination is generated from the heat source than the lamp heating method.
[0085]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.
[0086]
In the above embodiment, nitrogen gas is used as the carrier gas or the dilution gas, but an inert gas such as argon can be used instead or as a part thereof. In addition, the gas atmosphere can include a reaction gas such as a source gas, a carrier gas, a dilution gas, and other additive gases.
[0087]
Further, regarding the pressure of the gas atmosphere, not only the quasi-atmospheric pressure reduction region exemplified in the first and second embodiments but also a safety problem needs to be taken, but a merit can be expected from the film forming speed and the like. It is possible even in a pressure region or a sub-normal pressure region.
[0088]
In the above-described embodiment, the case where the present invention is applied to the manufacture of SRAM has been described. However, the present invention is not limited to this. On each semiconductor wafer having a sparse pattern density and a dense area in each chip area The present invention can be applied to all semiconductor integrated circuit devices having a step of depositing a silicon nitride film by thermal CVD.
[0089]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed by the present application will be briefly described as follows.
[0090]
According to the present invention, a silicon nitride film having a uniform thickness can be deposited on the main surface of a semiconductor wafer having a sparse pattern density and a dense pattern.
[Brief description of the drawings]
FIG. 1 is a block diagram of a semiconductor chip on which an SRAM according to an embodiment of the present invention is formed.
FIG. 2 is an equivalent circuit diagram of an SRAM memory cell according to an embodiment of the present invention.
FIG. 3 is a plan view showing a gate electrode pattern of a MISFET constituting an SRAM memory cell according to an embodiment of the present invention;
FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an SRAM according to an embodiment of the present invention;
FIG. 5 is a schematic view of a cold wall type single wafer thermal CVD apparatus used for manufacturing an SRAM according to an embodiment of the present invention.
FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an SRAM according to an embodiment of the present invention;
FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an SRAM according to an embodiment of the present invention;
FIG. 8 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an SRAM according to an embodiment of the present invention;
FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing an SRAM according to an embodiment of the present invention.
FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing an SRAM according to an embodiment of the present invention;
FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing an SRAM according to an embodiment of the present invention.
FIG. 12 is a graph showing the relationship between various parameters when depositing a silicon nitride film and the difference in film thickness density of the silicon nitride film.
FIG. 13 is a diagram showing various parameters and the amount of change when depositing a silicon nitride film.
FIG. 14 is a graph showing a relationship between a monosilane / ammonia flow rate ratio and a difference in film thickness density of a silicon nitride film.
FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing an SRAM according to an embodiment of the present invention;
FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing an SRAM which is an embodiment of the present invention;
FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate, illustrating a method for manufacturing an SRAM according to an embodiment of the present invention;
FIG. 18 is a cross sectional view of the essential part of the semiconductor substrate, showing a method for manufacturing an SRAM according to an embodiment of the present invention.
FIG. 19 is a cross sectional view of the essential part of the semiconductor substrate, showing a method for manufacturing an SRAM according to an embodiment of the present invention.
FIG. 20 shows the dependence of the film thickness ratio on the density of the dense part and the film thickness on which the film thickness ratio of the dense part is maximized with respect to each film pressure. _Three / SiH _Four It is a graph which shows the film-forming pressure dependence of a flow rate ratio.
FIG. 21 shows the film thickness ratio of the dense part and the NH in FIG. _Three / SiH _Four It is the schematic of the cold wall type single wafer type thermal CVD apparatus used for measuring the film-forming pressure dependence of a flow rate ratio.
FIG. 22 shows NH for increasing the film thickness ratio of the silicon nitride film to 85% or more and 95% or more. _Three / SiH _Four It is a graph which shows two-dimensional distribution of a flow rate ratio and film-forming pressure.
23A is an enlarged view of the main part of the wafer used in the measurement of FIG. 22, and FIG. 23B is a sectional view of the same.
24A is a diagram showing a source gas (ammonia + monosilane) supply sequence used in the measurement of FIG. 22, and FIG. 24B is a diagram showing a change in pressure of the source gas.
[Explanation of symbols]
1 Silicon wafer (substrate)
1A silicon chip
2 Silicon oxide film
3 Silicon nitride film
4 Element isolation groove
4a groove
5 Silicon oxide film
6 n-type well
7 p-type well
8 Gate oxide film
9A-9E Gate electrode
10 n ^- Type semiconductor region
11 p ^- Type semiconductor region
12 Silicon nitride film
12A Sidewall spacer
13 n ⁺ Type semiconductor region (source, drain)
14 p ⁺ Type semiconductor region (source, drain)
15 Co silicide layer
16 Silicon nitride film
17 Silicon oxide film
20-29 contact hole
30-39 wiring
40 Film thickness inspection pad
100 single wafer thermal CVD system
101 chamber
102 stages
103 shower head
104 Pressure gauge
105 Mechanical booster pump
106 Dry pump
107 exhaust pipe
DL, / DL complementary data line
INV ₁ , INV ₂ Inverter
Ln, Lp Active region
Q ₁ ~ Q ₆ MISFET
Qd ₁ , Qd ₂ MISFET for driving
Qp ₁ , Qp ₂ MISFET for load
Qt ₁ , Qt ₂ MISFET for transfer
WL Word line

Claims (20)

A source gas containing monosilane gas and ammonia gas is supplied in the vicinity of the main surface of the semiconductor wafer heated to a temperature equal to or higher than the thermal decomposition temperature of the monosilane gas and ammonia gas, and the monosilane gas and the ammonia gas are supplied to the main surface of the semiconductor wafer. A method for manufacturing a semiconductor integrated circuit device comprising a step of depositing a silicon nitride film on a main surface of the semiconductor wafer placed in a gas atmosphere containing the monosilane gas and the ammonia gas by thermally decomposing in the vicinity. ,
A method of manufacturing a semiconductor integrated circuit device, wherein a flow rate ratio of the ammonia gas to the monosilane gas is 150 to 750 times, and a pressure of the gas atmosphere is 37 kPa to 50 kPa. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the flow rate ratio of the ammonia gas to the monosilane gas is 200 to 650 times, and the pressure of the gas atmosphere is 39 to 49 kPa. Device manufacturing method. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the flow rate ratio of the ammonia gas to the monosilane gas is 300 to 550 times, and the pressure of the gas atmosphere is 41 kPa to 47 kPa. Device manufacturing method. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein the main surface of the semiconductor substrate is partitioned into one or more chip regions, and each of the chip regions includes a sparse pattern density region and a dense region. A method of manufacturing a semiconductor integrated circuit device, comprising: 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1 , wherein a cold wall type single wafer thermal CVD apparatus is used. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5 , wherein a flow ratio of the ammonia gas to the monosilane gas is 200 to 650 times, and a pressure of the gas atmosphere is 39 to 49 kPa. Device manufacturing method. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5 , wherein a flow rate ratio of the ammonia gas to the monosilane gas is 300 to 550 times, and a pressure of the gas atmosphere is 41 kPa to 47 kPa. Device manufacturing method. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 5 , wherein the wafer has a diameter of 200 mm or more. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6 , wherein the wafer has a diameter of 200 mm or more. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 7 , wherein the diameter of the wafer is 200 mm or more. A source gas containing monosilane gas and ammonia gas is supplied in the vicinity of the main surface of the semiconductor wafer heated to a temperature equal to or higher than the thermal decomposition temperature of the monosilane gas and ammonia gas, and the monosilane gas and the ammonia gas are supplied to a cold wall type single wafer. On the main surface of the semiconductor wafer placed in a gas atmosphere in a sub-atmospheric pressure-reduced region containing the monosilane gas and ammonia gas by being thermally decomposed in the vicinity of the main surface of the semiconductor wafer in a reaction chamber of a thermal CVD apparatus A method of manufacturing a semiconductor integrated circuit device comprising a step of depositing a silicon nitride film on the substrate,
A method for manufacturing a semiconductor integrated circuit device, wherein a flow rate ratio of the ammonia gas to the monosilane gas is set to 100 times or more. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 11 , wherein the diameter of the wafer is 200 mm or more. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 12 , wherein a flow rate ratio of the ammonia gas to the monosilane gas is 250 times or more. 12. The method of manufacturing a semiconductor integrated circuit device according to claim 11 , wherein a flow rate ratio of the ammonia gas to the monosilane gas is 250 times or more. A source gas containing monosilane gas and ammonia gas is supplied in the vicinity of the main surface of the semiconductor wafer heated to a temperature equal to or higher than the thermal decomposition temperature of the monosilane gas and ammonia gas, and the monosilane gas and the ammonia gas are supplied to a cold wall type single wafer. On the main surface of the semiconductor wafer placed in a gas atmosphere in a sub-atmospheric pressure-reduced region containing the monosilane gas and ammonia gas by being thermally decomposed in the vicinity of the main surface of the semiconductor wafer in a reaction chamber of a thermal CVD apparatus A method of manufacturing a semiconductor integrated circuit device comprising a step of depositing a silicon nitride film on the substrate,
A method of manufacturing a semiconductor integrated circuit device, wherein a flow rate ratio of the ammonia gas to the monosilane gas is 150 to 750 times, and a pressure of the gas atmosphere is 37 kPa to 50 kPa. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 15 , wherein the flow rate ratio of the ammonia gas to the monosilane gas is 200 to 650 times, and the pressure of the gas atmosphere is 39 to 49 kPa. Device manufacturing method. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 15 , wherein the flow rate ratio of the ammonia gas to the monosilane gas is 300 to 550 times, and the pressure of the gas atmosphere is 41 to 47 kPa. Device manufacturing method. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 15 , wherein the diameter of the wafer is 200 mm or more. 17. The method of manufacturing a semiconductor integrated circuit device according to claim 16 , wherein the wafer has a diameter of 200 mm or more. 18. The method of manufacturing a semiconductor integrated circuit device according to claim 17 , wherein the diameter of the wafer is 200 mm or more.

Images