JP2001102444A - Manufacturing method of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an insulating film from being formed on an interface between bit lines, a wiring and an Si substrate. SOLUTION: A Ti film 101 is formed on a silicon oxide film 31 and inside a connection hole 34 through a sputtering method, and then a silicide layer 42 is formed through a thermal treatment. Then, a TiN film 102 is formed on the Ti film 101, and successively, a TiN film 103 is formed thereon through an inorganic CVD method where a mixed gas of titanium tetrachloride and ammonia is used. Then, an after treatment is carried out making NH3 gas or NH3 gas and carrier gas (helium; He) flow, and successively, a pure water treatment is carried out through a sheet-type cleaning device, by which Cl is removed from the above TiN film 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique therefor, and more particularly, to the inside of a connection hole formed on a semiconductor substrate by a CVD method using a metal source containing a halogen element and a capacitor insulation. The present invention relates to a technique effective when applied to reduce a heat-resistant connection resistance when a titanium nitride (TiN) film is formed on an upper electrode of the film.

[0002]

2. Description of the Related Art As the aspect ratio (depth / diameter of a connection hole) of a connection hole formed on a semiconductor substrate increases with miniaturization and high integration of an LSI, a conductive film for wiring is connected to the connection hole. Conventionally, a technique of embedding a plug into a connection hole having a high aspect ratio has been used because it becomes difficult to deposit the plug inside the connection hole.

On the other hand, as described in, for example, JP-A-8-204144, in order to prevent a reaction between a metal wiring layer in a miniaturized connection hole and its underlying film, a nitride film is formed as a reaction barrier film. Titanium films are used.

The titanium nitride film is formed by CVD (Chemical V).
When deposited by the apor deposition method, it is widely used as a plug material to be embedded in a connection hole having a high aspect ratio because of good coverage. For example, Japanese Patent Application Laid-Open No. 9-45770 discloses a technique in which a TiN film is formed by CVD in a connection hole formed in an insulating film, and a tungsten film or a tungsten compound is formed on the TiN film. .

[0005]

SUMMARY OF THE INVENTION Titanium nitride (TiN)
When a film is deposited by a CVD method, a source gas containing a halogen element such as titanium tetrachloride (TiCl ₄ ) is generally used. This is because the TiN film formed using this source gas has a good step coverage,
This is because the film can be formed at a low temperature of about 50 ° C., so that there is an advantage that the characteristics of the element are not deteriorated.

However, since a TiN film (CVD-TiN film) formed using a source gas containing a halogen element contains a halogen element such as chlorine generated by decomposition of the source gas, Heat treatment of CV
The halogen element segregates at the interface between the lower portion of the connection hole in which the D-TiN film is embedded and the silicon film, and acts as a catalyst to form an insulating film such as a silicon oxide film at the interface. There is a problem that the connection resistance increases due to the covering.

Further, as described in Japanese Patent Application Laid-Open No. 9-45770, a method of forming a tungsten film or a tungsten compound film on a titanium nitride film buried in a contact hole involves the use of a tungsten film such as a tungsten nitride film. Although the tungsten film has a higher ability to trap the halogen element than the compound film, the tungsten film has a smaller effect of trapping the halogen element as a whole, and the silicon film under the connection hole during the heat treatment is generally small. The halogen element acts as a catalyst for oxidizing, and an insulating film is formed. Further, there is a problem that the tungsten film has poor adhesion to the underlying film and is easily peeled off.

An object of the present invention is to provide a technique for preventing an insulating film such as a silicon oxide film from being formed at an interface between silicon and a lower portion of a connection hole in which a CVD-TiN film is buried.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

A method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps.

(A) A step of forming an insulating film on a main surface of a semiconductor substrate and forming a connection hole in the insulating film.

(B) forming a titanium film containing a small amount of nitrogen by a sputtering method on the surface of the insulating film including the inside of the connection hole;

(C) heat treating the semiconductor substrate to form a titanium silicide layer at the bottom of the connection hole.

(D) forming a titanium nitride film on the surface of the titanium film by a sputtering method;

(E) forming a titanium nitride film on the surface of the titanium nitride film by a CVD method using a mixed gas of titanium tetrachloride and ammonia;

(F) After forming the titanium nitride film by the CVD method, an ammonia gas or an ammonia gas and a carrier gas capable of reacting with residual chlorine in the titanium nitride film are supplied to the surface of the titanium nitride film; Removing the residual chlorine by reacting the gas with the residual chlorine.

(G) a step of removing the residual chlorine by cleaning the surface of the titanium nitride film so that the residual chlorine reacts with a cleaning solution.

(H) After forming a tungsten film on the titanium nitride film formed by the inorganic CVD method by a CVD method, patterning is performed by using a photoresist film as a mask to form bit lines and wirings. Process.

According to the above manufacturing method, the chlorine in the titanium nitride film is removed by reacting the chlorine in the TiN film with the ammonia gas to remove the chlorine from the TiN film and performing a pure water treatment. Is dissolved in water in the form of hydrochloric acid or the like and is removed from the titanium nitride film. By these treatments, the chlorine concentration in the titanium nitride film is reduced, and even when a high-temperature heat treatment is performed, an insulating layer is not formed at the interface between the bit line and the wiring and the Si substrate, thereby increasing the connection resistance. Can be reduced. As a result, the yield and reliability of the semiconductor integrated circuit device can be improved.

Further, since the bit line is composed of the tungsten film, the titanium nitride film and the titanium film, the sheet resistance can be reduced, so that the information reading speed and the writing speed can be improved. Since the line and the wiring of the peripheral circuit can be formed simultaneously in one step, the manufacturing steps of the DRAM can be shortened.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(First Embodiment) FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to the present embodiment is formed.
As shown, a semiconductor chip 1 made of single crystal silicon
X direction (long side direction of semiconductor chip 1A) on the main surface of A
And a large number of memory arrays MARY are arranged in a matrix along the Y direction (the short side direction of the semiconductor chip 1A). Memory arrays M adjacent to each other along the X direction
A sense amplifier SA is arranged between ARY. A word driver W is provided at the center of the main surface of the semiconductor chip 1A.
D, control circuits such as data line selection circuits, input / output circuits,
Bonding pads and the like are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM. As shown, the memory array of this DRAM (MA
RY) includes a plurality of word lines W arranged in a matrix.
L (WLn-1, WLn, WLn + 1...), A plurality of bit lines BL, and a plurality of memory cells (MC) arranged at their intersections. One memory cell for storing one bit of information is composed of one information storage capacitor C
And one memory cell selecting MI connected in series
SFET Qs. M for memory cell selection
One of a source and a drain of the ISFET Qs is electrically connected to the information storage capacitor C, and the other is a bit line BL.
Is electrically connected to One end of the word line WL is connected to a word driver WD, and one end of the bit line BL is
It is connected to the sense amplifier SA.

Hereinafter, a method of manufacturing a semiconductor integrated circuit device according to the present embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 3, a p-type semiconductor substrate 1 is wet-oxidized at about 850 ° C. to form a thin silicon oxide film 2 on the surface thereof. The silicon nitride film 3 is deposited by a (Chemical Vapor Deposition) method.

Next, the silicon nitride film 3, the silicon oxide film 2, and the semiconductor substrate 1 are dry-etched using the photoresist film 4 patterned by photolithography as a mask, so that the trench 5a is formed in the semiconductor substrate 1 in the element isolation region. To form

Next, as shown in FIG. 4, in order to remove a damaged layer formed on the inner wall of the groove 5a by the above-mentioned etching, the semiconductor substrate 1 is wet-oxidized at about 850 to 900 ° C. to remove the inner wall of the groove 5a. Then, a thin silicon oxide film 6 is formed.

Next, after a silicon oxide film 7 is deposited on the semiconductor substrate 1 by a thermal CVD method, the semiconductor substrate 1 is kept at 1000 ° C.
By performing dry oxidation to a degree, sintering (burning) for improving the film quality of the silicon oxide film 7 embedded in the groove 5a is performed.

Next, as shown in FIG. 5, a silicon nitride film 8 is deposited on the silicon oxide film 7 by the CVD method. Next, the silicon nitride film 8 is dry-etched using the photoresist film 9 patterned by photolithography as a mask, so that the upper portion of the groove 5a having a relatively large area such as the boundary between the memory array and the peripheral circuit region is formed. Only the silicon nitride film 8 is left. When the silicon nitride film 8 remaining on the groove 5a is planarized by polishing the silicon oxide film 7 by a CMP method in the next step, the silicon oxide film 7 inside the groove 5a having a relatively large area is removed. It is formed in order to prevent a phenomenon (dishing) that is polished deeper than the silicon oxide film 7 inside the groove 5a having a relatively small area.

Next, as shown in FIG. 6, the silicon oxide film 7 is formed by a CMP method using the silicon nitride films 3 and 8 as stoppers.
Is polished and left inside the groove 5a to form the element isolation groove 5.

Next, as shown in FIG. 7, after removing the silicon nitride films 3 and 8 by wet etching using hot phosphoric acid, an n-type semiconductor substrate 1 in a region (memory array) where a memory cell is to be formed is formed. An n-type semiconductor region 10 is formed by ion-implanting an impurity, for example, phosphorus (P), and a p-type impurity, for example, boron (B) is formed in a part of the memory array and the peripheral circuit region (a region for forming an n-channel MISFET). Is ion-implanted to form a p-type well 11, and an n-type impurity, for example, P is ion-implanted into another part of the peripheral circuit region (a region where a p-channel MISFET is formed) to form an n-type well 12. . Following the ion implantation, an impurity for adjusting the threshold voltage of the MISFET, for example, boron fluoride (BF ₂ ) is added to the p-type well 11.
Then, ions are implanted into the n-type well 12. The n-type semiconductor region 10 is formed to prevent noise from entering the p-type well 11 of the memory array from the input / output circuit and the like through the semiconductor substrate 1.

Subsequently, after the silicon oxide film 2 on each surface of the p-type well 11 and the n-type well 12 is removed using a hydrofluoric acid (HF) cleaning solution, the semiconductor substrate 1 is wet-oxidized at about 850 ° C. Then, a clean gate oxide film 13 is formed on each surface of the p-type well 11 and the n-type well 12.

Although not particularly limited, after the gate oxide film 13 is formed, the semiconductor substrate 1 is subjected to a heat treatment in an NO (nitrogen oxide) atmosphere or an N ₂ O (nitrogen oxide) atmosphere to thereby form the gate oxide film. Nitrogen may be segregated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 (oxynitriding treatment). When the gate oxide film 13 is thinned to about 7 nm, the semiconductor substrate 1
Distortion generated at the interface between the two due to the difference in thermal expansion coefficient between the two causes the generation of hot carriers. Nitrogen segregated at the interface with the semiconductor substrate 1 alleviates this distortion, so that the above oxynitridation can improve the reliability of the ultra-thin gate oxide film 13.

Next, as shown in FIG.
The gate electrodes 14A, 14B, 14C are formed on the top of the gate electrode 3. The gate electrode 14A is a MISFE for selecting a memory cell.
T and a word line W in a region other than the active region.
Used as L. The width of the gate electrode 14A (word line WL), that is, the gate length is the memory cell selection M
It has a minimum dimension within an allowable range where the short channel effect of the ISFET can be suppressed and the threshold voltage can be secured to a certain value or more. The adjacent gate electrode 14A (word line W
The distance between L) is constituted by the minimum dimension determined by the resolution limit of photolithography. The gate electrode 14B and the gate electrode 14C are formed of an n-channel MISFE of a peripheral circuit.
Each part of the T and p channel MISFETs is formed.

The gate electrode 14A (word line WL) and the gate electrodes 14B and 14C are formed by forming a polycrystalline silicon film doped with an n-type impurity such as P on the semiconductor substrate 1.
Then, a tungsten nitride (WN) film and a tungsten (W) film are deposited thereon by a sputtering method, and a silicon nitride film 15 is further deposited thereon by a CD method.
After deposition by the VD method, these films are formed by patterning these films by photolithography. The WN film functions as a barrier layer that prevents the W film and the polycrystalline silicon film from reacting during the high-temperature heat treatment to form a high-resistance silicide layer at the interface between them. As the barrier layer, a TiN film or the like can be used in addition to the WN film.

When a part of the gate electrode 14A (word line WL) is made of low-resistance metal (W), its sheet resistance can be reduced, so that word line delay can be reduced. Further, the gate electrode 14 (word line WL) is
Since the word line delay can be reduced without backing with wiring or the like, the number of wiring layers formed above the memory cell can be reduced by one.

Subsequently, dry etching residues and photoresist residues remaining on the surface of the semiconductor substrate 1 are removed using an etching solution such as hydrofluoric acid. When this wet etching is performed, the gate electrode 14A (word line WL)
In addition, the gate oxide film 13 in a region other than below the gate electrodes 14B and 14C is shaved, and at the same time, the gate oxide film 13 below the gate side wall is also isotropically etched to produce an undercut. The breakdown voltage of the device decreases. Therefore, the film quality of the shaved gate oxide film 13 is improved by wet oxidizing the semiconductor substrate 1 at about 900 ° C.

Subsequently, a p-type impurity, for example, B is ion-implanted into the n-type well 12 to form a p ^- type semiconductor region 17 in the n-type well 12 on both sides of the gate electrode 14C. Also, an n ⁻ -type semiconductor region 18 is formed in the p-type well 11 on both sides of the gate electrode 14B by ion-implanting an n-type impurity, for example, P, in the p-type well 11, and is formed in the p-type well 11 on both sides of the gate electrode 14A. An n-type semiconductor region 19 is formed.
As a result, the memory cell selecting MISF
ETQs are formed.

Next, as shown in FIG. 9, after a silicon nitride film 20 is deposited on the semiconductor substrate 1 by the CVD method, the silicon nitride film 20 of the memory array is covered with a photoresist film, and the silicon nitride film of the peripheral circuit region is formed. By performing anisotropic etching of the film 20, side wall spacers 20a are formed on the side walls of the gate electrodes 14B and 14C. In this etching, an etching gas that increases the etching rate of the silicon nitride film 20 with respect to the silicon oxide film is used in order to minimize the shaving amount of the silicon oxide film 7 buried in the gate oxide film 13 and the element isolation trench 5. Use to do. Further, in order to minimize the amount of the silicon nitride film 15 shaved on the gate electrodes 14B and 14C, the amount of over-etching is minimized.

Subsequently, after removing the photoresist film,
A p-type impurity such as B
Is ion-implanted to form p + of a p-channel type MISFET.
A semiconductor region 22 (source, drain) is formed, and an n-type impurity, for example, As is added to the p-type well 11 in the peripheral circuit region.
N-channel MISFE by ion implantation of (arsenic)
A T n + type semiconductor region 23 (source, drain) is formed. As a result, the LDD (Lightly Do
p-channel MISFETQ with ped Drain) structure
The p and n channel type MISFETs Qn are formed.

Next, as shown in FIG.
SOG (spin-on-glass) with a thickness of about 300 nm on top
After spin coating the film 24, the semiconductor substrate 1 is heated at 800 ° C.
The heat treatment is performed for about one minute, and the SOG film 24 is sintered (sintered).

Subsequently, after depositing a silicon oxide film 25 on the SOG film 24, the silicon oxide film 25 is
The surface is flattened by polishing by the P method. The silicon oxide film 25 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. As described above, in the present embodiment, the gate electrode 14A (word line WL) and the gate electrodes 14B,
SOG film 24 with good flatness even immediately after film formation on top of 4C
Is applied, and a silicon oxide film 2 deposited on the
5 is flattened by a CMP method. Thereby, the gate electrode 1
4A (word line WL) improves the gap fill property of a minute gap between the gate electrodes 14A (word line WL).
L) and planarization of the insulating film on the gate electrodes 14B and 14C can be realized.

Subsequently, a silicon oxide film 26 is deposited on the silicon oxide film 25. This silicon oxide film 26
Is deposited in order to repair fine scratches on the surface of the silicon oxide film 25 generated when the silicon oxide film 25 is polished by the CMP method.
The silicon oxide film 26 is deposited by, for example, a plasma CVD method using O ₃ and TEOS as a source gas. A PSG (Phospho Silicate Glass) film or the like may be deposited on the silicon oxide film 25 instead of the silicon oxide film 26.

Next, as shown in FIG. 11, the silicon oxide films 26, 25 and SO on the n-type semiconductor region 19 (source, drain) of the MISFET Qs for memory cell selection are dry-etched using a photoresist film as a mask.
The G film 24 is removed. This etching is performed on the silicon oxide films 26 and 25 and the SOG on the silicon nitride film 20.
The etching is performed under such a condition that the etching rate of the film 24 is increased, so that the n-type semiconductor region 19 and the silicon nitride film 20 covering the upper part of the element isolation groove 5 are not completely removed.

Subsequently, the MISFE for selecting a memory cell is formed by dry etching using the photoresist film as a mask.
By removing the silicon nitride film 15 and the gate oxide film 13 above the n-type semiconductor region 19 (source, drain) of TQs, a connection hole 28 is formed above one of the n-type semiconductor region 19 (source, drain). And a connection hole 29 is formed in the other upper part.

This etching is performed under such conditions that the etching rate of the silicon nitride film 20 with respect to the silicon oxide film (the gate oxide film 13 and the silicon oxide film 7 in the element isolation trench 5) is increased. The element isolation groove 5 is prevented from being cut deeply. This etching is performed under such conditions that the silicon nitride film 20 is anisotropically etched, and the gate electrode 14A (word line W
The silicon nitride film 20 is left on the side wall of L). As a result, the connection holes 28 and 29 having a fine diameter equal to or smaller than the resolution limit of the photolithography are formed in self-alignment with the gate electrode 14A (word line WL). Connection hole 2
8 and 29 are formed in a self-aligned manner with respect to the gate electrode 14A (word line WL).
0 may be anisotropically etched to form a sidewall spacer on the side wall of the gate electrode 14A (word line WL).

Next, as shown in FIG. 12, after removing the photoresist film, the surface of the substrate exposed at the bottoms of the connection holes 28 and 29 is etched using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. Removal of dry etching residues and photoresist residues. At this time, the connection holes 28, 2
The SOG film 24 exposed on the side wall 9 is also exposed to the etchant. However, since the SOG film 24 has a reduced etching rate with respect to the hydrofluoric acid-based etchant by sintering at about 800 ° C., The sidewalls of the connection holes 28 and 29 are not largely undercut by the etching process. As a result, it is possible to reliably prevent a short circuit between the plugs embedded in the connection holes 28 and 29 in the next step.

Subsequently, plugs 30 are formed inside the connection holes 28 and 29. The plug 30 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 26 by a CVD method, and polishing the polycrystalline silicon film by a CMP method to form a connection hole. It is formed by leaving inside of 28 and 29.

Subsequently, after a silicon oxide film 31 having a thickness of about 200 nm is deposited on the silicon oxide film 26, the semiconductor substrate 1 is heat-treated at about 800.degree. The silicon oxide film 31 is formed, for example, by plasma CVD using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.
It is deposited by the method. By this heat treatment, n-type impurities in the polycrystalline silicon film forming plug 30 are removed from connection holes 28, 2
9 diffuses into the n-type semiconductor region 19 (source, drain) of the memory cell selecting MISFET Qs, and the n-type semiconductor region 19 is reduced in resistance.

Subsequently, the silicon oxide film 31 above the connection hole 28 is removed by dry etching using a photoresist film as a mask to expose the surface of the plug 30.

Next, as shown in FIG. 13, after removing the photoresist film, the silicon oxide film 3 in the peripheral circuit region is subjected to dry etching using the photoresist film as a mask.
1, 26, 25, SOG film 24 and gate oxide film 13
Is removed, the n-channel MISFET Qn
The connection holes 34 and 35 are formed above the n + -type semiconductor region 23 (source and drain), and the p-channel MISFET is formed.
Connection holes 36 and 37 are formed above the p + type semiconductor region 22 (source, drain) of Qp.

Next, after removing the photoresist film, the bit lines BL and first layer wirings 38 and 39 of the peripheral circuit are formed on the silicon oxide film 31. Bit line B
In order to form the L and first layer wirings 38 and 39, as shown in FIG. 14, which shows an enlarged view of the vicinity of the connection hole 34, first, the semiconductor substrate having the connection hole formed therein is washed with an HF aqueous solution and the bottom of the connection hole is formed. Is removed to expose a clean Si surface.
Thickness 7 containing a trace amount of nitrogen on top of silicon oxide film 31
A Ti film 101 of about 0 nm is deposited by a sputtering method, and the semiconductor substrate 1 is heat-treated at about 650 ° C. for 1 minute to form a titanium silicide layer 42. Then, Ti
A TiN film 102 having a thickness of about 20 nm is deposited on the upper part of the film by a sputtering method.
Depending on the pressure and timing, a gas mixture of titanium tetrachloride (TiCl ₄ ), ammonia (NH ₃ ) and helium (He) (TiCl ₄ / NH ₃ = 1/2 to 1) is formed on the TiN film.
/ 50) as a raw material at a temperature of 450 to 750 ° C., preferably 550 to 650 ° C., and a pressure of about 5 to 4000 Pa by an inorganic CVD method (inorganic TiN-CVD) to a thickness of 3
A 0 nm TiN film 103 is formed. This TiN-CV
Although it is possible to form the Tin film 103 having good step coverage by the film forming conditions of D, the film contains about 4% of chlorine atoms or chlorine ions. At the time of forming a tantalum oxide (Ta ₂ O ₅ ) film 61 to be described later, Ta ₂ O ₅
A heat treatment at 800 ° C. is applied for crystallization annealing of the film. At this time, Cl in the TiN film 103 is segregated at the interface between the bit line BL, the first layer wirings 38 and 39 and the Si substrate, and acts as a catalyst to form silicon oxide (SiO ₂ ) or the like on the interface. Since a thin insulating film layer is formed and the bottom of the connection hole is covered with the insulating layer, the connection resistance increases. Therefore, as shown in FIG.
In the step of forming the TiN film 103 by the iN-CVD method, after stopping the TiCl ₄ and terminating the film formation, NH ₃ gas, or NH ₃ gas and carrier gas (helium; H)
e) to carry out post-processing, so that the TiN film 10
3 reacts with the NH ₃ to form the TiN film 1.
03 is removed from the Cl. At this time, the Cl is reacted with the NH _3, and a time (S) for removing the Cl is removed.
Step 4) needs to be 60 seconds or longer, preferably 90 seconds or longer. Further, the carrier gas is not limited to He, and it is also possible to use nitrogen (N ₂ ), argon (Ar), or a mixed gas thereof. continue,
By performing pure water treatment with the single wafer type cleaning apparatus (conceptual diagram) shown in FIG. 16, the Cl in the TiN film 103 is dissolved in water in the form of hydrochloric acid (HCl) or the like, and the TiN film 10 is dissolved.
3 is removed. By these processes, the TiN film 1 is formed.
03, the bit line BL and the first line are formed even when a high-temperature heat treatment is performed after the formation of the connection hole.
Since no insulating layer is formed at the interface between the layer wirings 38 and 39 and the Si substrate, an increase in connection resistance can be reduced. In an experiment conducted by the inventor, as shown in Table 1, the n + -type semiconductor region 23 (source, drain) of the n-channel type MISFET Qn and the bit line BL and the first layer The contact resistance with the wiring 38 is 35
Although it was MΩ, the contact resistance could be reduced to 180Ω when the pure treatment was performed. Further, the p + -type semiconductor region 22 (source, drain) of the p-channel type MISFET Qp and the first layer wiring 3 when the pure processing is not performed
The contact resistance between 8 and 39 was 92 MΩ,
When the pure treatment was performed, the contact resistance could be reduced to 1.3 kΩ.

[0054]

[Table 1]

Subsequently, after depositing a W film by the CVD method, depositing a silicon nitride film 40 by the CVD method,
These films are patterned using the photoresist film 41 as a mask.

After depositing a Ti film on the silicon oxide film 31, the semiconductor substrate 1 is heat-treated at about 650 ° C., whereby the Ti film reacts with the Si substrate, and the n-channel type M
A low-resistance TiSi ₂ (titanium silicide) layer 42 is formed on the surface of the n + -type semiconductor region 23 (source, drain) of the ISFET Qn and the surface of the p + -type semiconductor region 22 (source, drain) of the p-channel MISFET Qp. You. Although not shown, the memory cell selection M
Upper connection hole 28 in n-type semiconductor region 19 of ISFET Qs
A TiSi ₂ (titanium silicide) layer 42 is also formed on the surface of the plug 30 embedded in the substrate. This gives n +
The connection resistance of the wiring (bit line BL, first layer wirings 38 and 39) connected to the type semiconductor region 23 and the p + type semiconductor region 22 can be reduced. Further, since the bit line BL is made of the W film / TiN film / Ti film, the sheet resistance can be reduced, so that the information reading speed and the writing speed can be improved, and the bit line BL and the peripheral circuit can be connected to each other. Since the first layer wirings 38 and 39 can be formed simultaneously in one step, the manufacturing steps of the DRAM can be shortened. Further, the first of the peripheral circuits
In the case where the layer wirings (38, 39) are formed of the same layer as the bit line BL, the first layer wiring is formed of the upper layer of the memory cell.
MISFET of peripheral circuit compared to the case of wiring
(N channel MISFET Qn, p channel MIS
FET Qp) and the connection hole (34-
Since the aspect ratio of 37) is reduced, the connection reliability of the first layer wiring is improved.

The bit line BL is used to reduce the parasitic capacitance formed between the bit line BL and the adjacent bit line BL as much as possible to improve the information reading speed and the writing speed.
The gap is formed so as to be longer than the width. The interval between the bit lines BL is, for example, about 0.24 μm, and the width is, for example, about 0.22 μm.

Next, after removing the photoresist film 41, as shown in FIG.
After a silicon nitride film is deposited on the upper portions and the side walls of the first layer wirings 38 and 39 by the CVD method, the silicon nitride film is anisotropically etched to form a sidewall spacer 43.

Subsequently, the bit line BL and the first layer wiring 3
The SOG film 44 is spin-coated on the upper portions 8 and 39. Next, the semiconductor substrate 1 is heat-treated at 800 ° C. for about 1 minute to obtain SO 2.
The G film 44 is sintered (burned).

Subsequently, after a silicon oxide film 45 is deposited on the SOG film 44, the silicon oxide film 45 is
The surface is flattened by polishing by the P method. The silicon oxide film 45 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. As described above, in the present embodiment, the SOG film 44 having good flatness is applied on the bit lines BL and the first layer wirings 38 and 39 immediately after the film formation, and the silicon oxide film 45 deposited on the SOG film 45 is further formed thereon. Is flattened by a CMP method. Thereby, the gap fill property of the minute gap between the bit lines BL is improved, and the flattening of the insulating film on the bit lines BL and the first layer wirings 38 and 39 can be realized. Further, since heat treatment at a high temperature for a long time is not performed, the MISFE forming the memory cell and the peripheral circuit is not required.
It is possible to achieve high performance by preventing the characteristic deterioration of T, and to reduce the resistance of the bit line BL and the first layer wirings 38 and 39.

Subsequently, a silicon oxide film 46 is deposited on the silicon oxide film 45. This silicon oxide film 46
Is deposited in order to repair fine scratches on the surface of the silicon oxide film 45 generated when polished by the CMP method.
The silicon oxide film 46 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 18, the silicon oxide films 46 and 45 over the connection holes 29 are formed by dry etching.
The SOG film 44 and the silicon oxide film 31 are removed to form a through hole 48 reaching the surface of the plug 30.

Subsequently, a dry etching residue and a photoresist residue on the surface of the plug 30 exposed at the bottom of the through hole 48 are removed by using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride.

Next, the plug 4 is inserted into the through hole 48.
9 is formed. The plug 49 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 46 by a CVD method, and then etching back the polycrystalline silicon film to form a through hole 48. It is formed by leaving it inside.

Next, as shown in FIG. 19, after a silicon nitride film 51 is deposited on the silicon oxide film 46 by the CVD method, the silicon nitride film 51 in the peripheral circuit region is removed by dry etching. The silicon nitride film 51 remaining in the memory array is used as an etching stopper when etching a silicon oxide film between the lower electrodes in a step of forming a lower electrode of the information storage capacitor element described later.

Subsequently, for example, ozone (O ₃ ) and tetraethoxysilane (TEO) are formed on the silicon nitride film 51.
S), a silicon oxide film 53 is deposited by a plasma CVD method using a source gas, and the silicon oxide film 53 and the silicon nitride film 51 are removed by dry etching. A groove 55 is formed. At the same time, a strip-shaped long groove 59 surrounding the memory array is formed around the memory array.

Subsequently, a polycrystalline silicon film 56 doped with an n-type impurity (for example, P (phosphorus)) is deposited on the silicon oxide film 53 by a CVD method. This polycrystalline silicon film 56 is used as a lower electrode material of the information storage capacitor.

Next, as shown in FIG. 20, an SOG film 57 having a thickness sufficient to bury the groove 55 and the long groove 59 is deposited on the polycrystalline silicon film 56, and then the SOG film is heat-treated at about 400 ° C. After baking the film 57, the SOG film 5
7 is etched back to expose the polycrystalline silicon film 56 above the silicon oxide film 53, and then the polycrystalline silicon film 56 is etched back, so that the inside (groove and bottom) of the groove 55 and the long groove 59 is formed. The polycrystalline silicon film 56 is left. At this time, the SOG film 57 that has not been etched back also remains inside the groove 55 and the long groove 59.

Next, as shown in FIG. 21, the silicon oxide film 53 in the peripheral circuit region is covered with a photoresist film 58,
SOG inside groove 55 using hydrofluoric acid based etchant
The lower electrode 60 of the information storage capacitor is formed by wet-etching the film 57 and the silicon oxide film 53 in the gap between the grooves 55. At this time, since the silicon nitride film 51 is formed at the bottom of the gap of the groove 55, even if the silicon oxide film 53 in the gap is completely removed, the silicon oxide film 46 thereunder is not removed by the etching solution. Absent.

Next, as shown in FIG. 22, the photoresist film 58 covering the peripheral circuit region is removed, and then the semiconductor substrate 1 is removed to prevent oxidation of the polycrystalline silicon film 56 forming the lower electrode 60. 800 ° C in an ammonia atmosphere
After the surface of the polycrystalline silicon film 56 is nitrided by performing a heat treatment at a temperature of about 200 ° C., a Ta ₂ O ₅ (tantalum oxide) film 61 is deposited on the lower electrode 60 by a CVD method, and then the semiconductor substrate 1 is heat treated at about 800 ° C. Then, the defect of the Ta ₂ O ₅ film 61 is repaired. This Ta ₂ O ₅ film 61 is used as a material of a capacitive insulating film of the information storage capacitor.

Subsequently, first, C is formed on the Ta ₂ O ₅ film 61.
A TiN film is formed by a VD method. The TiN-CVD film uses a mixed gas (TiCl ₄ / NH ₃ = 1/2 to 1/50) of titanium tetrachloride (TiCl ₄ ) and ammonia (NH ₃ ) as a source gas and has a temperature of 400 ° C. to 650 ° C. , Preferably at a temperature of 400 to 500 ° C and a pressure of about 5 to 3000 Pa
Deposit by D method. Although the step coverage is good and good withstand voltage characteristics of the capacitive insulating film can be obtained by the CVD-TiN film forming conditions, the film contains about 5% of chlorine atoms or chlorine ions. After stopping the TiCl ₄ in the TiN-CVD film forming step and terminating the film formation, the post-treatment is performed by flowing NH 3 or NH 3 gas and a carrier gas, so that the Cl in the TiN film and the NH 3 To remove from the TiN film. Subsequently, by performing pure water treatment, the C in the TiN film is removed.
1 is dissolved in water in the form of hydrochloric acid (HCl) or the like and removed from the TiN film. After the TiN-CVD film is formed, a TiN film is further formed by a sputtering method.

After the TiN film 62 is deposited, the TiN film 6 is dry-etched using the photoresist film 63 as a mask.
2 and Ta ₂ O ₅ film 61 are patterned to form an upper electrode made of TiN film 62 and Ta ₂ O ₅ film 6.
1 is formed, and an information storage capacitance element C composed of a lower electrode 60 made of a polycrystalline silicon film 56 is formed. Thereby, the MISFET for memory cell selection
A DRAM memory cell composed of Qs and an information storage capacitor C connected in series thereto is substantially completed.

Next, after removing the photoresist film 63, as shown in FIG. 23, the information storage capacitor is formed by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. A silicon oxide film 64 is deposited on the element C, and a high aspect ratio through hole 66 is formed on the first layer wiring 38.

Subsequently, a TiN film 71 having a thickness of 5 to 50 nm, preferably about 50 nm is deposited on the silicon oxide film 64 including the inside of the through hole 66. This TiN
The film 71 is formed of a mixed gas (TiCl ₄ / NH ₃ = 1/2) of titanium tetrachloride (TiCl ₄ ) and ammonia (NH ₃ ).
~ 1/50) as a source gas at a temperature of 400 ° C to 65 ° C.
Deposition is performed by a thermal CVD method at 0 ° C., preferably 600 ° C. or more and a pressure of about 5 to 3000 Pa. Since the TiN film 71 has good step coverage, the film thickness becomes substantially uniform between the bottom of the through hole 66 and the opening. Since titanium tetrachloride is used as the source gas in the TiN film 71, about 5% of chlorine is taken into the film. The TiN-CVD
After stopping the TiCl ₄ in the film forming process and terminating the film formation, NH 3 or an NH 3 gas and a carrier gas are flowed to perform post-processing, whereby the ClN in the TiN film is removed.
And the NH3 are reacted to remove from the TiN film. Subsequently, by performing pure water treatment, the Cl in the TiN film is dissolved in water in the form of hydrochloric acid (HCl) or the like, and
Removed from the membrane.

Next, as shown in FIG.
After the W film 72 is deposited on the upper surface of the silicon oxide film 64 by a CVD method, the W film 72 and the TiN film 71 on the silicon oxide film 64 are etched back and left only inside the through hole 66, thereby forming the TiN film 71 and the W film. A plug 73 made of a laminated film with the plug 72 is formed. W film 72 on top of silicon oxide film 64
To remove the TiN film 71, a chemical mechanical polishing (CMP) method may be used.

Subsequently, a TiN film 74 is deposited on the silicon oxide film 64 including the surface of the plug 73 by a sputtering method.

Subsequently, after an Al alloy film 75 and a Ti film 76 are deposited on the TiN film 74 by a sputtering method,
Dry etching with photoresist film as mask
The i film 76, the Al alloy film 75 and the TiN film 74 are patterned to form a second layer wiring 7 on the silicon oxide film 64.
7, 78 are formed.

(Embodiment 2) The method of manufacturing a semiconductor integrated circuit device according to the second embodiment is similar to that of the semiconductor integrated circuit device according to the first embodiment except that TiCl After stopping the _four gases and terminating the film formation, post-processing is performed by flowing NH ₃ gas at a pressure higher than the pressure at the time of film formation, for example, 133 Pa, as shown in FIG. In this case, since Cl can be removed in a shorter time, the throughput can be improved. Other members and manufacturing steps are the same as in the first embodiment. Therefore, description of the same members and manufacturing steps as those of the first embodiment will be omitted.

(Embodiment 3) The method of manufacturing a semiconductor integrated circuit device according to the third embodiment is directed to the method of manufacturing the semiconductor integrated circuit device according to the first or second embodiment.
In the step of forming the TiN film 103 by the D method, TiN
The pure water treatment after the formation of the film 103 is performed using warm water. In this case, the Cl.
, The margin of the process can be expanded. For example, even when the thickness of the TiN film 103 is increased, the bit line BL and the first-layer wirings 38 and 3
No insulating layer is formed at the interface between the silicon substrate 9 and the Si substrate, and an increase in connection resistance can be reduced.

(Embodiment 4) A method of manufacturing a semiconductor integrated circuit device according to Embodiment 4 is directed to a method of manufacturing an inorganic TiN-CV of a semiconductor integrated circuit device according to Embodiment 1 or 2.
In the step of forming the TiN film 103 by the D method, TiN
The processing after the formation of the film 103 is performed using an NH ₃ aqueous solution. In this case, the Cl removal efficiency is improved as compared with the case of using normal-temperature hot water, so that the process margin can be expanded. For example, even when the thickness of the TiN film 103 is increased, the bit line BL and the first Since no insulating layer is formed at the interface between the layer wirings 38 and 39 and the Si substrate, an increase in connection resistance can be reduced.

(Fifth Embodiment) A method of manufacturing a semiconductor integrated circuit device according to a fifth embodiment is directed to a method of manufacturing the semiconductor integrated circuit device according to the first, second, third, or fourth embodiment. TiN film 1 by inorganic TiN-CVD method
In the film forming step 03, pure water treatment after the formation of the TiN film 103 is performed using a batch-type cleaning apparatus, and a larger number of substrates are cleaned at once than in the case of using a single-wafer-type cleaning apparatus. Therefore, the throughput can be improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, in Embodiment 1, the inorganic T
In the process of forming a TiN film by the iN-CVD method,
After completion of the stop forming a Cl _4, NH ₃ gas, or by flowing the NH ₃ gas and the carrier gas has been exemplified a case in which the post-processing, hydrazine, monomethyl hydrazine, dimethyl hydrazine, N ₂ plasma or NH, ₃ Plasma may be used.

[0084]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, Cl in the TiN film formed by the inorganic TiN-CVD method is removed, and an insulating layer is formed at the interface between the bit line and the wiring and the Si substrate even when a high-temperature heat treatment is performed. Instead, an increase in connection resistance can be reduced.

[Brief description of the drawings]

FIG. 1 is an overall plan view of an example of a semiconductor chip on which a semiconductor integrated circuit device according to a first embodiment of the present invention is formed.

FIG. 2 is an equivalent circuit diagram of the semiconductor integrated circuit device according to the first embodiment;

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of First Embodiment.

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of First Embodiment;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of First Embodiment.

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of First Embodiment.

FIG. 7 is an essential part cross sectional view of the semiconductor substrate, showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1.

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of First Embodiment.

9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1. FIG.

10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1. FIG.

11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1. FIG.

12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of First Embodiment; FIG.

13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1. FIG.

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of First Embodiment;

FIG. 15 is a diagram showing a film formation flow by inorganic TiN-CVD in the method for manufacturing a semiconductor integrated circuit device of the first embodiment.

FIG. 16 is a conceptual diagram of a single-wafer cleaning apparatus that performs a pure water treatment in the method for manufacturing a semiconductor integrated circuit device according to the first embodiment.

17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1. FIG.

18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1. FIG.

19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1. FIG.

20 is an essential part cross sectional view of the semiconductor substrate, showing an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1. FIG.

21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of Embodiment 1. FIG.

FIG. 22 is an essential part cross sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of the first embodiment.

23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of First Embodiment; FIG.

24 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating an example of a method for manufacturing a semiconductor integrated circuit device of First Embodiment; FIG.

FIG. 25 is a diagram showing a film formation flow by inorganic TiN-CVD in the method for manufacturing a semiconductor integrated circuit device of the second embodiment.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 1A semiconductor chip 2 silicon oxide film 3 silicon nitride film 4 photoresist film 5 element isolation groove 5a groove 6 silicon oxide film 7 silicon oxide film 8 silicon nitride film 9 photoresist film 10 n-type semiconductor region 11 p-type well 12 n-type well 13 gate oxide film 14A to 14C gate electrode 15 silicon nitride film 17 p ^- type semiconductor region 18 n ^- type semiconductor region 19 n-type semiconductor region 20 silicon nitride film 20a sidewall spacer 22 p ⁺ type semiconductor region 23 n ⁺ Type semiconductor region 24 SOG film 24a, 24b SOG film 25 Silicon oxide film 26 Silicon oxide film 27 Photoresist film 28 Connection hole 29 Connection hole 30 Plug 31 Silicon oxide film 32 Photoresist film 34-37 Connection hole 38, 39 First layer Wiring 40 Silicon nitride 41 the photoresist film 42 TiSi ₂ layer 43 sidewall spacers 44 SOG film 45 a silicon oxide film 46 a silicon oxide film 48 through hole 49 plug 51 silicon film 53 a silicon oxynitride film 55 groove 56 polycrystalline silicon film 57 SOG film 59 elongated groove 60 bottom Electrode 61 Ta ₂ O ₅ (tantalum oxide) film 62 TiN film (upper electrode) 63 photoresist film 64 silicon oxide film 66 through hole 71 TiN film 72 W film 73 plug 74 TiN film 75 Al alloy film 76 Ti film 77, 78 Second layer wiring 101 Ti film 102 TiN film 103 TiN film BL Bit line C Information storage capacitor MARY Memory array Qn N-channel MISFET Qp P-channel MISFET Qs MISFET for memory cell selection SA Sense Flop WD word driver

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Naoki Fukuda 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Hiroshi Sakuma 6--16 Shinmachi, Ome-shi, Tokyo 3 Inside the Hitachi, Ltd. Device Development Center (72) Inventor Yoshitaka Nakamura 6-16, Shinmachi, Ome-shi, Tokyo 3 Inside the Hitachi Ltd. Device Development Center (72) Inventor Takuya Fukuda 6-16, Shinmachi, Ome-shi, Tokyo Address 3 F-term in Device Development Center, Hitachi, Ltd. (Reference) 4M104 AA01 BB25 CC01 DD04 DD08 DD16 DD23 DD37 DD45 DD79 DD84 DD90 FF18 FF23 GG10 GG16 HH15 5F033 HH18 HH19 HH33 JJ18 JJ19 JJ33 KK11 MM08Q09 QQ37 QQ70 QQ73 QQ74 QQ92 QQ93 RR04 RR09 SS04 SS15 SS22 TT02 TT08 VV16 XX0 9 5F083 AD10 GA27 JA39 JA40 JA56 KA05 MA04 MA05 MA06 MA19 MA20 PR03 PR09 PR13 PR21 PR22 PR23 PR40 PR43 PR44 PR45 PR46 PR53 PR54 PR55 PR56

Claims (8)

[Claims] (A) forming an insulating film having a connection hole on a semiconductor substrate; and (b) using a mixed gas of titanium tetrachloride and ammonia on the surface of the insulating film including the inside of the connection hole. Forming a titanium nitride film by a CVD method,
(C) After forming the titanium nitride film by the CVD method, a gas capable of reacting with the residual chlorine in the titanium nitride film is supplied to the surface of the titanium nitride film, and the gas reacts with the residual chlorine. Removing the residual chlorine, (d) cleaning the surface of the titanium nitride film, thereby reacting the residual chlorine with a cleaning liquid to remove the residual chlorine,
A method for manufacturing a semiconductor integrated circuit device, comprising: 2. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the gas supplied to the titanium nitride film is ammonia, hydrazine, monomethylhydrazine, dimethylhydrazine, nitrogen plasma or ammonia plasma. Of manufacturing a semiconductor integrated circuit device. 3. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein a pressure of the gas supplied to the titanium nitride film is higher than a pressure of the ammonia gas used for forming the titanium nitride film. A method for manufacturing a semiconductor integrated circuit device. 4. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein pure water or an aqueous ammonia solution is used for cleaning the surface of the titanium nitride film. 5. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein the surface of the titanium nitride film is cleaned using pure water or an aqueous ammonia solution at a temperature higher than room temperature. Device manufacturing method. 6. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein a batch-type cleaning device is used for cleaning the surface of the titanium nitride film. 7. A DRAM comprising a memory cell selecting MISFET and an information storing capacitive element connected in series to the memory cell, wherein the information storing capacitive element is arranged above the memory cell selecting MISFET. (A) a MISFE for selecting a memory cell in a memory array on a main surface of a semiconductor substrate.
MIS for forming peripheral circuits in the peripheral circuit region
After forming the FET, the memory cell selecting MISFE
Forming an insulating film on the T and the MISFET forming the peripheral circuit; (b) forming a connection hole in the insulating film above the semiconductor region of the MISFET forming the peripheral circuit; Forming a titanium nitride film by a CVD method using a mixed gas of titanium tetrachloride and ammonia on the surface of the insulating film including the inside of the connection hole; (d) forming a titanium nitride film by the CVD method; Supplying a gas capable of reacting with the residual chlorine in the titanium nitride film to the surface of the titanium nitride film, and reacting the gas with the residual chlorine to remove the residual chlorine; and (e) removing the residual chlorine. Removing the residual chlorine by reacting the residual chlorine with a cleaning solution by cleaning the surface; (f) forming a metal film on the surface of the insulating film including the inside of the connection hole;
Forming a wiring electrically connected to the semiconductor region through the connection hole by patterning the metal film; (g) the memory cell selecting MISFE
Forming a lower electrode on the upper portion of T, and then forming a capacitive insulating film on the lower electrode; (h) forming an upper electrode on the upper portion of the capacitive insulating film after heat treating the capacitive insulating film; Forming a capacitance element for information storage constituted by the lower electrode, the capacitance insulating film, and the upper electrode. 8. The method for manufacturing a semiconductor integrated circuit according to claim 7, wherein a heat treatment temperature of said capacitance insulating film is 700 ° C. or higher.