JPH1174354A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent an Al wiring, which is formed on the upper part of a through hole filled with a CVD(Chemical Vapor Deposition)-TiN (Titanium Nitride) film, from being corroded. SOLUTION: A TiN film 71 and a W film 72 are deposited on the upper part of a silicon oxide film 64 being included in the interior of a through hole 66 by a CVD method, thereafter the films 72 and 71 on the upper part of the film 64 are etched back to leave the films 72 and 71 only in the interior of the hole 66, and a plug 73 is formed. Then, after a TiN film 74, an Al alloy film 75 and a Ti film 76 are deposited on the upper part of the film 64 including the surface of the plug 73 by a sputtering method, the films 76, 75 and 74 are patterned to form second layer wirings 77 and 78.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly, to a method of connecting upper and lower wirings formed on a semiconductor substrate by a CVD method using a metal source containing a halogen element. The present invention relates to a technique effective for preventing corrosion of an upper wiring when a titanium nitride (TiN) film is formed inside a through hole to be formed or on an upper electrode of a capacitor insulating film.

[0002]

2. Description of the Related Art As the aspect ratio (through-hole depth / diameter) of through-holes connecting upper and lower wirings formed on a semiconductor substrate increases with the miniaturization and higher integration of LSIs, Since it becomes difficult to deposit a conductive film for wiring in a through-hole, a technique of embedding a plug in a through-hole having a high aspect ratio has been conventionally used.

On the other hand, as described in, for example, JP-A-8-204144, titanium nitride is used as a reaction barrier layer in order to prevent a reaction between a metal wiring layer in a miniaturized contact hole and its underlying film. Membranes are used.

The titanium nitride film is formed by CVD (Chemical Vapor).
When deposited by the por deposition method, it is widely used as a plug material to be embedded in a high-aspect-ratio through-hole because of good coverage. For example,
Japanese Patent Application Laid-Open No. 9-45770 discloses a technique in which a TiN film is formed by CVD in a through hole formed in an interlayer insulating film, and a tungsten film or a tungsten compound is formed on the TiN film.

On the other hand, there has been developed a technique of depositing a TiN film as an upper electrode on a tantalum oxide film which is a capacitive insulating film of a capacitive element by a CVD method. For example, JP-A-9-219
No. 501 discloses a technique of forming a TiN film as a top electrode by a CVD method on a tantalum oxide film which is a capacitive insulating film.

[0006]

When a TiN film is deposited by the CVD method, titanium tetrachloride (TiCl4) is generally used.
A source gas containing a halogen element such as is used.
This is because the TiN film formed by using this source gas has an advantage that it has good step coverage and can be formed at a low temperature of about 450 ° C. so that the characteristics of the element are not deteriorated.

However, since a TiN film formed using a source gas containing a halogen element contains a halogen element such as chlorine generated by decomposition of the source gas, the CVD-TiN film is embedded. When an Al (aluminum) wiring is formed above the through hole, there is a problem that the halogen element reacts with the Al to cause corrosion of the wiring.

When depositing a TiN film by the CVD method,
Generally, a source gas containing a halogen element such as titanium tetrachloride (TiCl ₄ ) is used. This is because the TiN film formed by using this source gas has an advantage that it has good step coverage and can be formed at a low temperature of about 450 ° C. so that the characteristics of the element are not deteriorated.

However, since a TiN film formed using a source gas containing a halogen element contains a halogen element such as chlorine generated by the decomposition of the source gas, the CVD-TiN film is embedded. When an Al (aluminum) wiring is formed above the through-hole, or when a CVD-TiN film is formed on the upper electrode of the capacitive insulating film and A
When forming the l wiring, there is a problem that a halogen element and Al react to cause wiring corrosion.

[0010] As described in Japanese Patent Application Laid-Open No. 9-45770, a method of forming a tungsten film or a tungsten compound film on a titanium nitride film embedded in a through hole involves forming a tungsten compound film such as a tungsten nitride film. Although the tungsten film has a higher ability to trap a halogen element than the tungsten film, the effect of trapping the halogen element is generally small, and the halogen element penetrates into the aluminum wiring layer on the tungsten film. Then, aluminum is corroded by the halogen element. Further, there is a problem that the tungsten film has poor adhesion to the underlying film and is easily peeled off.

An object of the present invention is to provide a technique for preventing corrosion of an Al wiring formed above a through hole in which a CVD-TiN film is embedded.

Another object of the present invention is to provide a technique for preventing corrosion of an Al wiring formed on an upper electrode when the upper electrode of the capacitive insulating film is formed of a CVD-TiN film. .

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0014]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

[0015] Between the titanium nitride film formed using a gas containing halogen as a source gas and the second conductive film, a metal atom which binds to a halogen element and has a capability of trapping halogen is higher than that of tungsten. A high film is also provided. As described above, by providing a film that traps a halogen element having a corrosive effect on the second conductive film such as aluminum between the titanium nitride film and the second conductive film such as aluminum, Can be prevented from diffusing into the second conductive film, and corrosion of the second conductive film can be prevented.

The trap film containing a metal atom bonded to a halogen element and having a higher capability of trapping halogen than tungsten is, for example, a titanium film, a titanium nitride film, a tantalum film, a tantalum film formed by a sputtering method. Examples include a tantalum nitride film, a titanium film, a titanium nitride film, a tantalum film, and a tantalum nitride film formed by a CVD method using a gas containing no halogen as a constituent element as a source gas. These films may be used as a single layer or a stacked film of two or more layers. When used as a single layer, a titanium film formed by a sputtering method has the highest ability to trap a halogen element. In the case of using a titanium film formed by sputtering and a titanium nitride film formed by sputtering, the titanium film has a better trapping ability. The effect is high. It is preferable that the above-described trap film is provided with a thickness of 5 nm or more, preferably a single layer or a stacked layer, more preferably 20 nm or more. However, 120nm
If it exceeds, the resistance increases, which is not preferable for practical use.
By providing such a trap layer, adhesion between the titanium nitride film containing a halogen element and the interlayer insulating film is improved.
Further, the trap film has a binding energy of 1 with the halogen.
It is composed of a film containing atoms exceeding 11 Kcal / mol. The larger the binding energy is, the greater the effect of trapping the halogen is, and in practice, it should be more than 111 Kcal / mol.

The trap film may be provided immediately below the second conductive film, or one or more other films may be provided between the second conductive film and the trap film. Second
The effect of preventing corrosion of the conductive film is the same. As a source gas for the titanium nitride film, chlorine, as well as fluorine, bromine,
Even when a gas containing iodine as a constituent element is used, a trap film such as a titanium film has an excellent ability to trap halogen. Specific examples of the halogen-containing source gas include, for example, titanium tetrachloride and titanium tetraiodide. When titanium tetrachloride is used, it is the most corrosive to metals, particularly titanium tetrachloride. When is used as a source gas, it is meaningful to provide a trap film.

The second conductive film is a film that can be corroded, and is made of an aluminum film, an aluminum alloy film, a copper film, a copper alloy film, or the like.

This trap film has a CV at the opening of the insulating film.
After a halogen element-containing titanium nitride film is formed by the method D, it is formed on the opening. Specifically, after depositing a first conductive film including a titanium nitride film formed by a CVD method using a gas containing halogen as a source gas on the insulating film from the opening of the insulating film on the base, A plug is formed inside the opening by removing the first conductive film above the insulating film, and a second titanium nitride film having a lowermost layer formed by a sputtering method on the insulating film including the plug surface; Second
Is deposited, and the second conductive film is patterned to form a wiring layer. The first conductive film is formed of the C
In addition to a single layer of a titanium nitride film formed by the VD method, a stacked film of a titanium nitride film and a tungsten film formed by the above-described CVD method may be used. Also, MISFET
A titanium nitride film formed by a CVD method using a gas containing halogen as a constituent element as a source gas on the insulating film through an opening of the insulating film on the substrate provided with the storage capacitor element; After the conductive film is deposited, the first conductive film on the insulating film is removed to form a plug inside the opening, and the lowermost layer is formed on the insulating film including the plug surface by the sputtering method. A second conductive film including the second titanium nitride film is deposited, and the second conductive film is patterned to form a wiring layer. Also in this case, the first conductive film is
In addition to a single layer of a titanium nitride film formed by the CVD method, a stacked film of a titanium nitride film and a tungsten film formed by the CVD method may be used.

In a semiconductor device using a copper wiring layer which is particularly susceptible to corrosion, by providing a trapping film such as tantalum or tantalum nitride between the halogen-containing titanium nitride film and the copper wiring layer, the corrosion of copper is reduced. Can be reduced.

Further, one electrode of the storage capacitor portion is formed by CVD.
When a titanium nitride film formed by a method is used, the above-described trap film such as a titanium film formed by a sputtering method is formed on the titanium nitride film. Conventionally, polycrystalline silicon has been mainly used for the electrodes of the storage capacitor portion.
It was necessary to raise the temperature to 50 ° C. However, CVD using a source gas containing halogen as a constituent element
By using the titanium nitride film formed by the method, it is possible to lower the film formation temperature. The deposition temperature of the titanium nitride film by the above-mentioned CVD method is 400 ° C. to 600 ° C.

FIG. 56 shows the relationship between the chlorine concentration in the titanium nitride film and the film formation temperature when titanium tetrachloride is used as the source gas. As shown in the figure, the lower the deposition temperature, the higher the chlorine concentration in the titanium nitride film.
When the film is formed at a temperature of 00 ° C. or lower, the degree of corrosion of the wiring layer around the storage capacitor portion increases. Therefore, particularly when the titanium nitride film is formed at a temperature of 500 ° C. or lower, the effect of preventing the corrosion of the wiring layer becomes more remarkable by providing the trap film of the present invention. Note that, in addition to the case where a halogen-containing titanium nitride film is formed as a storage electrode, the case where a titanium nitride film is formed after forming an aluminum wiring layer is preferably performed at 500 ° C. or lower, and is formed at a low temperature. This increases the halogen content in the titanium nitride film.

Alternatively, after forming a titanium nitride film using a source gas containing halogen as a constituent element, annealing is performed in an inert gas such as a nitrogen gas or a rare gas.
Corrosion of the conductive film can be prevented. That is, halogen can be removed from the titanium nitride film by annealing. This annealing is performed at 400 ° C. to 800 ° C.
Annealing is performed at a temperature equal to or higher than 0 ° C., preferably equal to or higher than a temperature of a process for forming a TiN film by a CVD method. Immediately after the formation of the titanium nitride film, if the annealing is performed in the same apparatus as the film forming apparatus without exposure to the air, the titanium nitride film is not exposed to the air, so that surface oxidation of the titanium nitride film can be prevented. Although the cleaning step may be omitted, the cleaning may be performed before or after the annealing, but it is preferable to perform the cleaning after the annealing. The cleaning is most effective for removing chlorine by using warm water of 40 ° C. or higher.

Further, if water enters the chlorine in the titanium nitride film in some processing step, the chlorine easily moves in the device, so that the amount of chlorine moving toward the wiring layer increases, and the wiring layer is easily corroded. Become. It is considered that this is because chlorine in the titanium nitride film is ionized by contact with water, and the ionized chlorine is more easily moved for a bonding species. Therefore, by forming a titanium nitride film with a source gas containing halogen as a constituent element and then forming a high-density plasma CVD insulating film having a high water blocking effect, it is possible to prevent water from entering the titanium nitride film. it can. This insulating film is a silicon-rich insulating film having a refractive index of 1.46 or more. Examples of the step of water penetration include a cleaning step after dry etching and a step of forming an inorganic SOG film. In this inorganic SOG film forming step, inorganic SOG
After the application of the OG film, steam baking for baking in steam is performed. Therefore, by forming the high-density plasma CVD insulating film under the inorganic SOG film, it becomes possible to reduce the corrosion of the wiring layer. In addition, high density plasma CV
In addition to the D insulating film, the organic SOG film has a blocking effect against water, though not as much as the high density plasma CVD insulating film.
A G film may be formed.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM of the present embodiment is formed. As shown in the drawing, the main surface of the semiconductor chip 1A made of single crystal silicon has X
A large number of memory arrays MARY are arranged in a matrix along the direction (the long side direction of the semiconductor chip 1A) and the Y direction (the short side direction of the semiconductor chip 1A). A sense amplifier SA is arranged between memory arrays MARY adjacent to each other along the X direction. In the center of the main surface of the semiconductor chip 1A, control circuits such as a word driver WD and a data line selection circuit, input / output circuits, and bonding pads are arranged.

FIG. 2 is an equivalent circuit diagram of the DRAM. As shown, the memory array of this DRAM (MA
RY) includes a plurality of word lines W arranged in a matrix.
L (WLn-1, WLn, WLn + 1...), A plurality of bit lines BL, and a plurality of memory cells (MC) arranged at their intersections. One memory cell for storing one bit of information is composed of one information storage capacitor C
And one memory cell selecting MI connected in series
SFET Qs. M for memory cell selection
One of a source and a drain of the ISFET Qs is electrically connected to the information storage capacitor C, and the other is a bit line BL.
Is electrically connected to One end of the word line WL is connected to a word driver WD, and one end of the bit line BL is
It is connected to the sense amplifier SA.

Next, a method of manufacturing the DRAM of this embodiment will be described in the order of steps with reference to FIGS.

First, as shown in FIG. 3, a p-type semiconductor substrate 1 having a specific resistance of about 10 Ωcm is wet-oxidized at about 850 ° C. to form a thin silicon oxide film 2 having a thickness of about 10 nm on its surface. CV is formed on the silicon oxide film 2
A silicon nitride film 3 having a thickness of about 140 nm is deposited by a D (Chemical Vapor Deposition) method. Silicon oxide film 2
Is formed to alleviate the stress applied to the substrate when sintering (burning) a silicon oxide film embedded in the element isolation groove in a later step. Since the silicon nitride film 3 has the property of being hardly oxidized, it is used as a mask for preventing the oxidation of the substrate surface below (the active region).

Next, as shown in FIG. 4, the silicon nitride film 3, the silicon oxide film 2 and the semiconductor substrate 1 are dry-etched using the photoresist film 4 as a mask, so that the semiconductor substrate 1 in the element isolation region is deeply etched. 300-400
A groove 5a of about nm is formed. In order to form the groove 5a, the silicon nitride film 3 is dry-etched using the photoresist film 4 as a mask, the photoresist film 4 is removed, and then the silicon oxide film 2 and the semiconductor substrate are etched using the silicon nitride film 3 as a mask. 1 may be dry-etched.

Next, after removing the photoresist film 4,
As shown in FIG. 5, in order to remove a damaged layer formed on the inner wall of the groove 5a by the above-described etching, the semiconductor substrate 1 is wet-oxidized at about 850 to 900 ° C. to form a film having a thickness of about 10 nm on the inner wall of the groove 5a. A thin silicon oxide film 6 is formed.

Next, as shown in FIG. 6, after a silicon oxide film 7 having a thickness of about 300 to 400 nm is deposited on the semiconductor substrate 1, the semiconductor substrate 1 is dry-oxidized at about 1000.degree. Silicon oxide film 7 embedded in
(Sintering) is performed to improve the film quality. The silicon oxide film 7 is deposited by, for example, a thermal CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 7, a silicon nitride film 8 having a thickness of about 140 nm is deposited on the silicon oxide film 7 by the CVD method, and then, as shown in FIG. Then, the silicon nitride film 8 is dry-etched to leave the silicon nitride film 8 only on the upper portion of the groove 5a having a relatively large area such as the boundary between the memory array and the peripheral circuit region. When the silicon nitride film 8 remaining on the groove 5a is planarized by polishing the silicon oxide film 7 by a CMP method in the next step, the silicon oxide film 7 inside the groove 5a having a relatively large area is removed. It is formed in order to prevent a phenomenon (dishing) that is polished deeper than the silicon oxide film 7 inside the groove 5a having a relatively small area.

Next, after removing the photoresist film 9,
As shown in FIG. 9, the element isolation groove 5 is formed by polishing the silicon oxide film 7 by a CMP method using the silicon nitride films 3 and 8 as stoppers and leaving the silicon oxide film 7 inside the groove 5a.

Next, after removing the silicon nitride films 3 and 8 by wet etching using hot phosphoric acid, as shown in FIG. 10, an n-type semiconductor substrate 1 in a region (memory array) where a memory cell is to be formed is formed. An n-type semiconductor region 10 is formed by ion-implanting an impurity, for example, P (phosphorus), and a p-type impurity, for example, B (boron) is formed in a part of a memory array and a peripheral circuit region (a region for forming an n-channel MISFET). Is ion-implanted to form a p-type well 11, and an n-type impurity, for example, P (phosphorus) is ion-implanted into another part of the peripheral circuit region (a region where a p-channel MISFET is formed). To form Following this ion implantation, impurities for adjusting the threshold voltage of the MISFET, for example, BF ₂ (boron fluoride) are ion-implanted into the p-type well 11 and the n-type well 12.
The n-type semiconductor region 10 is formed to prevent noise from entering the p-type well 11 of the memory array from the input / output circuit and the like through the semiconductor substrate 1.

Next, the p-type well 11 and the n-type well 1
After removing the silicon oxide film 2 on each surface of the semiconductor substrate 1 using a HF (hydrofluoric acid) -based cleaning solution, the semiconductor substrate 1 is wet-oxidized at about 850 ° C. to form a p-type well 11 and an n-type well 1.
Then, a clean gate oxide film 13 having a thickness of about 7 nm is formed on each surface of No. 2.

Although not particularly limited, after the gate oxide film 13 is formed, the semiconductor substrate 1 is subjected to a heat treatment in an NO (nitrogen oxide) atmosphere or an N ₂ O (nitrogen oxide) atmosphere to form the gate oxide film. Nitrogen may be segregated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 (oxynitriding treatment). When the thickness of the gate oxide film 13 is reduced to about 7 nm, distortion generated at the interface between the semiconductor substrate 1 and the semiconductor substrate 1 due to a difference in thermal expansion coefficient becomes apparent, and hot carriers are generated. Nitrogen segregated at the interface with the semiconductor substrate 1 relaxes this distortion.
The above oxynitriding process can improve the reliability of the ultra-thin gate oxide film 13.

Next, as shown in FIG. 11, gate electrodes 14A, 14B and 14C are formed on the gate oxide film 13. The gate electrode 14A is provided with a memory cell selecting MISF.
It forms a part of the ET, and is used as a word line WL in a region other than the active region. The width of the gate electrode 14A (word line WL), that is, the gate length is the minimum dimension (for example, within an allowable range) in which the short channel effect of the memory cell selecting MISFET can be suppressed and the threshold voltage can be secured to a certain value or more. (About 0.24 μm). The distance between the adjacent gate electrodes 14A (word lines WL) is the minimum dimension (for example, 0.2) determined by the resolution limit of photolithography.
2 μm). The gate electrode 14B and the gate electrode 14C constitute each part of the n-channel MISFET and the p-channel MISFET of the peripheral circuit.

For the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C, a polycrystalline silicon film having a thickness of about 70 nm doped with an n-type impurity such as P (phosphorus) is formed on the semiconductor substrate 1 by the CVD method. Then, a WN (tungsten nitride) film having a thickness of about 50 nm and a W film having a thickness of about 100 nm are deposited thereon by sputtering, and a silicon nitride film 15 having a thickness of about 150 nm is further formed thereon by CVD. After deposition by a method, these films are formed by patterning these films using the photoresist film 16 as a mask. The WN film functions as a barrier layer that prevents the W film and the polycrystalline silicon film from reacting during the high-temperature heat treatment to form a high-resistance silicide layer at the interface between them. As the barrier layer, a TiN film or the like can be used in addition to the WN film.

When a part of the gate electrode 14A (word line WL) is made of low-resistance metal (W), the sheet resistance can be reduced to about 2 to 2.5 Ω / □, so that the word line delay is reduced. Can be reduced. Also, the gate electrode 1
Since the word line delay can be reduced without backing 4 (word line WL) with an Al wiring or the like, the number of wiring layers formed above the memory cells can be reduced by one.

Next, after removing the photoresist film 16, the semiconductor substrate 1 is etched using an etching solution such as hydrofluoric acid.
Dry etching residues and photoresist residues remaining on the surface of the substrate are removed. When this wet etching is performed, the gate oxide film 13 in a region other than the region under the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C is formed.
At the same time that the gate oxide film 1 under the gate sidewall is removed.
3 is also isotropically etched and an undercut occurs, so that the breakdown voltage of the gate oxide film 13 is reduced as it is. Therefore, the film quality of the shaved gate oxide film 13 is improved by wet oxidizing the semiconductor substrate 1 at about 900 ° C.

Next, as shown in FIG.
A p ^- type semiconductor region 17 is formed in the n-type well 12 on both sides of the gate electrode 14C by ion implantation of a p-type impurity, for example, B (boron) into the gate electrode 14C. In addition, the p-type well 11 has n
An n ^- type semiconductor region 18 is formed in the p-type well 11 on both sides of the gate electrode 14B by ion-implanting a p-type impurity, for example, P (phosphorus), and an n ^- type semiconductor region 19 is formed in the p-type well 11 on both sides of the gate electrode 14A. To form As a result, the memory cell selecting MISFET Qs is formed in the memory array.

Next, as shown in FIG.
After a silicon nitride film 20 having a thickness of about 50 to 100 nm is deposited thereon by the CVD method, the silicon nitride film 20 of the memory array is covered with a photoresist film 21 as shown in FIG. 20 is anisotropically etched to form sidewall spacers 20a on the side walls of the gate electrodes 14B and 14C. In this etching, an etching gas that increases the etching rate of the silicon nitride film 20 with respect to the silicon oxide film is used in order to minimize the shaving amount of the silicon oxide film 7 buried in the gate oxide film 13 and the element isolation trench 5. Use to do. Further, in order to minimize the amount of the silicon nitride film 15 shaved on the gate electrodes 14B and 14C, the amount of over-etching is minimized.

Next, after removing the photoresist film 21, as shown in FIG. 15, the n-type well 1 in the peripheral circuit region is formed.
2 is ion-implanted with a p-type impurity, for example, B (boron) to form ap ⁺ -type semiconductor region 22 of a p-channel MISFET.
(Source, drain) are formed, and an n-type impurity, for example, As (arsenic) is ion-implanted into the p-type well 11 in the peripheral circuit region to form an n ⁺ -type semiconductor region 23 (source, drain) of the n-channel MISFET. I do. This allows
A p-channel MISFET Qp and an n-channel MISFET Qn having an LDD (Lightly Doped Drain) structure are formed in the peripheral circuit region.

Next, as shown in FIG.
After spin coating an SOG (spin-on-glass) film 24 having a thickness of about 300 nm on the semiconductor substrate 1,
The heat treatment is performed for about a minute, and the SOG film 24 is sintered (sintered).

Next, as shown in FIG.
After a silicon oxide film 25 having a thickness of about 600 nm is deposited on the upper surface of the silicon oxide film 25, the silicon oxide film 25 is polished by a CMP method to flatten the surface. The silicon oxide film 25 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. As described above, in the present embodiment, the SOG film 24 with good flatness is applied to the upper portion of the gate electrode 14A (word line WL) and the gate electrodes 14B and 14C even immediately after the film formation, and the oxidation deposited on the SOG film 24 is further deposited thereon. The silicon film 25 is planarized by the CMP method. Thereby, the gap fill property of the fine gap between the gate electrodes 14A (word lines WL) is improved, and the flattening of the insulating film on the gate electrodes 14A (word lines WL) and the gate electrodes 14B and 14C is realized. be able to.

Next, as shown in FIG. 18, a silicon oxide film 26 having a thickness of about 100 nm is formed on the silicon oxide film 25.
Is deposited. The silicon oxide film 26 is deposited in order to repair fine scratches on the surface of the silicon oxide film 25 generated when the silicon oxide film 25 is polished by the CMP method. Silicon oxide film 2
6 is deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. On top of the silicon oxide film 25, a PSG (Phospho Silicate Glas
s) A film or the like may be deposited.

Next, as shown in FIG. 19, the silicon oxide films 26, 25 on the n-type semiconductor region 19 (source, drain) of the memory cell selection MISFET Qs are dry-etched using the photoresist film 27 as a mask. The SOG film 24 is removed. This etching is performed under such a condition that the etching rates of the silicon oxide films 26 and 25 and the SOG film 24 with respect to the silicon nitride film 20 are increased, and the silicon nitride film covering the n-type semiconductor region 19 and the upper part of the element isolation trench 5 is formed. 20 is not completely removed.

Subsequently, as shown in FIG. 20, the n-type semiconductor region 19 of the MISFET Qs for selecting a memory cell is dry-etched using the photoresist film 27 as a mask.
By removing the silicon nitride film 15 and the gate oxide film 13 above the (source, drain), a contact hole 28 is formed in one upper part of the n-type semiconductor region 19 (source, drain) and in the other upper part. Contact hole 2
9 is formed.

This etching is performed under the condition that the etching rate of the silicon nitride film 20 with respect to the silicon oxide film (the gate oxide film 13 and the silicon oxide film 7 in the element isolation trench 5) is increased. The element isolation groove 5 is prevented from being cut deeply. This etching is performed under such conditions that the silicon nitride film 20 is anisotropically etched, and the gate electrode 14A (word line W
The silicon nitride film 20 is left on the side wall of L). As a result, the contact holes 28 and 29 having a fine diameter smaller than the resolution limit of photolithography are formed in the gate electrode 1.
4A (word line WL) is formed in a self-aligned manner.
In order to form the contact holes 28 and 29 in a self-aligned manner with respect to the gate electrode 14A (word line WL), the silicon nitride film 20 is anisotropically etched in advance to form a sidewall on the side wall of the gate electrode 14A (word line WL). A spacer may be formed.

Next, after the photoresist film 27 is removed, dry etching residues and photoresist residues on the substrate surface exposed at the bottoms of the contact holes 28 and 29 are etched using an etching solution such as a mixture of hydrofluoric acid and ammonium fluoride. And so on. At that time, the contact hole 28,
The SOG film 24 exposed on the side wall of the S.sub.29 is also exposed to the etching solution. However, the SOG film 24 has a reduced etching rate with respect to a hydrofluoric acid-based etching solution by the above-described sintering at about 800.degree. The sidewalls of the contact holes 28 and 29 are not largely undercut by the etching process. As a result, it is possible to reliably prevent a short circuit between plugs embedded in the contact holes 28 and 29 in the next step.

Next, as shown in FIG. 21, plugs 30 are formed inside the contact holes 28 and 29. The plug 30 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 26 by CVD.
After the deposition by the method, the polycrystalline silicon film is polished by the CMP method and is formed by being left inside the contact holes 28 and 29.

Next, as shown in FIG. 22, a silicon oxide film 31 having a thickness of about 200 nm is formed on the silicon oxide film 26.
Is deposited, the semiconductor substrate 1 is heat-treated at about 800 ° C. The silicon oxide film 31 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. By this heat treatment,
An n-type impurity in the polycrystalline silicon film forming the plug 30 is supplied from the bottom of the contact holes 28 and 29 to the n-type semiconductor region 19 (source,
Drain) and the resistance of the n-type semiconductor region 19 is reduced.

Next, as shown in FIG. 23, the surface of the plug 30 is exposed by removing the silicon oxide film 31 above the contact hole 28 by dry etching using the photoresist film 32 as a mask. Next, after removing the photoresist film 32, as shown in FIG. 24, the silicon oxide films 31, 26, 25 and the SOG film 24 in the peripheral circuit region are dry-etched using the photoresist film 33 as a mask.
By removing the gate oxide film 13 and contact holes 34 and 35 above the n ⁺ -type semiconductor region 23 (source and drain) of the n-channel MISFET Qn, the p ⁺ -type semiconductor region 22 of the p-channel MISFET Qp Contact holes 36 and 37 are formed above (source, drain).

Next, after removing the photoresist film 33, as shown in FIG. 25, the bit lines BL and the first layer wirings 38 and 39 of the peripheral circuit are formed on the silicon oxide film 31. In order to form the bit line BL and the first layer wirings 38 and 39, first, a film thickness 5
A Ti film of about 0 nm is deposited by a sputtering method, and the semiconductor substrate 1 is heat-treated at about 800 ° C. Next, a TiN film having a thickness of about 50 nm is deposited on the Ti film by a sputtering method, and a W film having a thickness of about 150 nm and a silicon nitride film 40 having a thickness of about 200 nm are further deposited thereon by a CVD method. These films are patterned using the photoresist film 41 as a mask.

After depositing a Ti film on the silicon oxide film 31, the semiconductor substrate 1 is subjected to a heat treatment at about 800 ° C., so that the Ti film reacts with the Si substrate and the n-channel type M
A low-resistance TiSi ₂ (titanium silicide) layer 42 is formed on the surface of the n ⁺ type semiconductor region 23 (source, drain) of the ISFET Qn and the surface of the p ⁺ type semiconductor region 22 (source, drain) of the p-channel MISFET Qp. You. Although not shown, the memory cell selection M
The surface of the plug 30 buried in the contact hole 28 above the n-type semiconductor region 19 of the ISFET Qs
An Si ₂ (titanium silicide) layer 42 is formed. Thereby, the wiring (bit line BL, first layer wiring 3) connected to n ⁺ type semiconductor region 23 and p ⁺ type
8, 39) can be reduced.
Further, since the bit line BL is formed of the W film / TiN film / Ti film, the sheet resistance can be reduced to 2 Ω / □ or less, so that the information reading speed and the writing speed can be improved, and the bit rate can be improved. Since the line BL and the first-layer wirings 38 and 39 of the peripheral circuit can be formed simultaneously in one step, the manufacturing steps of the DRAM can be shortened. Furthermore, the first layer wiring (3
8 and 39) are formed of the same layer wiring as the bit line BL, the MISFETs of the peripheral circuits (n-channel MISFETs Qn and p Channel type MISFET Qp)
Contact holes (34 to 3) for connecting
Since the aspect ratio of 7) is reduced, the connection reliability of the first layer wiring is improved.

The bit line BL is used to reduce the parasitic capacitance formed between the bit line BL and the adjacent bit line BL as much as possible to improve the information reading speed and the writing speed.
The gap is formed so as to be longer than the width. The interval between the bit lines BL is, for example, about 0.24 μm, and the width thereof is, for example, about 0.22 μm.

Next, after removing the photoresist film 41, as shown in FIG. 26, sidewall spacers 43 are formed on the side walls of the bit lines BL and the side walls of the first layer wirings 38 and 39.
To form The side wall spacer 43 is formed by depositing a silicon nitride film on the bit line BL and the first layer wirings 38 and 39 by the CVD method, and then anisotropically etching the silicon nitride film.

Next, as shown in FIG.
Then, an SOG film 44 having a thickness of about 300 nm is spin-coated on the first layer wirings 38 and 39. Next, the semiconductor substrate 1 is heat-treated at 800 ° C. for about 1 minute to sinter (bake) the SOG film 44. The SOG film 44 is made of BPSG
Since the reflow property is higher than that of the film and the gap fill property between fine wirings is excellent, it is possible to satisfactorily fill gaps between the bit lines BL miniaturized to the resolution limit of photolithography. The SOG film 44 is made of B
Since high reflow properties can be obtained without performing high-temperature and long-time heat treatment required for the PSG film, the MISFET (n) of the source and drain of the memory cell selection MISFET Qs formed under the bit line BL and the peripheral circuit Channel type MISFETQn, p channel type MISFETQ
Thermal diffusion of impurities contained in the source and drain of p) can be suppressed to achieve a shallow junction. Further, the gate electrode 14A (word line WL) and the gate electrodes 14B, 1
Since deterioration of the metal (W film) constituting 4C can be suppressed, the memory cells of the DRAM and the M constituting the peripheral circuit can be suppressed.
High performance of the ISFET can be realized. Also,
T forming bit line BL and first layer wirings 38 and 39
Wiring resistance can be reduced by suppressing deterioration of the i film, TiN film, and W film.

Next, as shown in FIG.
After a silicon oxide film 45 having a thickness of about 600 nm is deposited on the upper surface of the substrate, the silicon oxide film 45 is polished by a CMP method to flatten the surface. The silicon oxide film 45 is deposited by, for example, a plasma CVD method using ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

As described above, in the present embodiment, the SOG film 44 having good flatness is applied to the bit line BL and the first layer wirings 38 and 39 immediately after the film formation, and the oxidation The silicon film 45 is planarized by the CMP method. Thereby, the gap fill property of the minute gap between the bit lines BL is improved, and the flattening of the insulating film on the bit lines BL and the first layer wirings 38 and 39 can be realized. Further, since heat treatment at a high temperature for a long time is not performed, the MISFE forming the memory cell and the peripheral circuit is not required.
It is possible to achieve high performance by preventing the characteristic deterioration of T, and to reduce the resistance of the bit line BL and the first layer wirings 38 and 39.

Next, as shown in FIG. 29, a silicon oxide film 46 having a thickness of about 100 nm is formed on the silicon oxide film 45.
Is deposited. The silicon oxide film 46 is deposited to repair fine scratches on the surface of the silicon oxide film 45 generated when the silicon oxide film 45 is polished by the CMP method. Silicon oxide film 4
6 is deposited by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas.

Next, as shown in FIG. 30, the silicon oxide films 46 and 45 over the contact holes 29 are removed by dry etching using the photoresist film 47 as a mask.
After removing the film 44 and the silicon oxide film 31, the plug 30
Is formed to reach the surface of the substrate. This etching is performed on the silicon oxide films 46, 45, 31 and SO
The etching is performed under such a condition that the etching rate of the silicon nitride film with respect to the G film 44 becomes small.
To prevent the silicon nitride film 40 and the sidewall spacers 43 on the upper portion from being etched deeply. As a result, the through hole 48 is formed in self alignment with the bit line BL.

Next, after the photoresist film 47 is removed, a dry etching residue or a photoresist residue on the surface of the plug 30 exposed at the bottom of the through hole 48 is etched using an etching solution such as a mixed solution of hydrofluoric acid and ammonium fluoride. And so on. At this time, the SOG film 44 exposed on the side wall of the through hole 48 is also exposed to the etching solution.
Since the etching rate of the OG film 44 with respect to the hydrofluoric acid-based etchant is reduced by the sintering at about 800 ° C., the side wall of the through hole 48 is not largely undercut by the wet etching process. Accordingly, a short circuit between the plug buried in the through hole 48 and the bit line BL in the next step can be reliably prevented. Also, since the plug and the bit line BL can be sufficiently separated from each other,
An increase in the parasitic capacitance of the bit line BL can be suppressed.

Next, as shown in FIG. 31, a plug 49 is formed inside the through hole 48. The plug 49 is formed by depositing a polycrystalline silicon film doped with an n-type impurity (for example, P (phosphorus)) on the silicon oxide film 46 by a CVD method, and then etching back the polycrystalline silicon film to form a through hole 48. It is formed by leaving it inside.

Next, as shown in FIG. 32, a silicon nitride film 51 having a thickness of about 100 nm is formed on the silicon oxide film 46.
Is deposited by the CVD method, and the silicon nitride film 51 in the peripheral circuit region is removed by dry etching using the photoresist film 52 as a mask. The silicon nitride film 51 remaining in the memory array is used as an etching stopper when etching a silicon oxide film between the lower electrodes in a step of forming a lower electrode of the information storage capacitor element described later.

Next, after removing the photoresist film 52, as shown in FIG. 33, for example, ozone (O ₃ ) and tetraethoxysilane (T
A silicon oxide film 53 having a thickness of about 1.3 μm is deposited by a plasma CVD method using EOS) as a source gas, and the silicon oxide film 53 and the silicon nitride film 51 are removed by dry etching using a photoresist film 54 as a mask. Thereby, a groove 55 is formed above the through hole 48 in which the plug 49 is embedded. At the same time, a strip-shaped long groove 59 surrounding the memory array is formed around the memory array. FIG. 34 is a plan view of a principal part of the semiconductor substrate 1 showing the pattern of the groove 55 and the pattern of the long groove 59. FIG.

Next, after removing the photoresist film 54, as shown in FIG. 35, a film thickness 60 doped with an n-type impurity (for example, P (phosphorus)) is formed on the silicon oxide film 53.
A polycrystalline silicon film 56 of about nm is deposited by a CVD method.
This polycrystalline silicon film 56 is used as a lower electrode material of the information storage capacitor.

Next, as shown in FIG. 36, an SOG film 57 having a thickness (for example, about 300 to 400 nm) sufficient to bury the groove 55 and the long groove 59 is deposited on the polycrystalline silicon film 56. After baking the SOG film 57 by a heat treatment at about 400 ° C., as shown in FIG.
7 is etched back to expose the polycrystalline silicon film 56 above the silicon oxide film 53, and then the polycrystalline silicon film 56 is etched back, so that the inside (groove and bottom) of the groove 55 and the long groove 59 is formed. The polycrystalline silicon film 56 is left. At this time, the SOG film 57 that has not been etched back also remains inside the groove 55 and the long groove 59.

Next, as shown in FIG. 38, the silicon oxide film 53 in the peripheral circuit region is covered with a photoresist film 58,
SOG inside groove 55 using hydrofluoric acid based etchant
The lower electrode 60 of the information storage capacitor is formed by wet-etching the film 57 and the silicon oxide film 53 in the gap between the grooves 55. At this time, since the silicon nitride film 51 is formed at the bottom of the gap of the groove 55, even if the silicon oxide film 53 in the gap is completely removed, the silicon oxide film 46 thereunder is not removed by the etching solution. Absent.

One end of the photoresist film 58 covering the silicon oxide film 53 in the peripheral circuit region is disposed at the boundary between the memory array and the peripheral circuit region, that is, above the long groove 59. Therefore, when the above-mentioned wet etching is performed, the SOG film 57 inside the long groove 59 is also removed, but the lower electrode material (polycrystalline silicon film 56) on the inner wall of the long groove 59 serves as an etching stopper.
No side wall is cut off. Further, since the surface of the silicon oxide film 53 in the peripheral circuit region is covered with the photoresist film 58, the surface is not scraped.
As a result, a step between the memory array and the peripheral circuit region is eliminated, and the peripheral circuit region is also flattened.

Next, in order to prevent the photoresist film 58 covering the peripheral circuit region from being removed and to prevent the polycrystalline silicon film (56) constituting the lower electrode 60 from being oxidized, the semiconductor substrate 1 is placed in an ammonia atmosphere at 800.degree. After nitriding the surface of the polycrystalline silicon film (56) by heat treatment at about
As shown in FIG. _2, a Ta ₂ O ₅ (tantalum oxide) film 61 having a thickness of about 20 nm is deposited on the lower electrode 60 by a CVD method, and then the semiconductor substrate 1 is heat-treated at about 800 ° C.
The defect of the a ₂ O ₅ film 61 is repaired. This Ta ₂ O ₅ film 6
Reference numeral 1 is used as a material for a capacitive insulating film of an information storage capacitor.

Next, as shown in FIG. 40, a TiN film is first formed on the Ta ₂ O ₅ film 61 by a CVD method to a thickness of 50 to 100 nm.
Form. The CVD-TiN film is made of titanium tetrachloride (TiC
l ₄ ) and ammonia (NH ₃ ) mixed gas (TiCl
₄ / NH ₃ = 1/2 to 1/50) as the source gas,
Temperature 400 ° C to 650 ° C, preferably 400 to 500
It is deposited by a thermal CVD method at a temperature of about 5 ° C. and a pressure of about 5 to 3000 Pa.
Although the step coverage is good and good withstand voltage characteristics of the capacitive insulating film can be obtained by the CVD-TiN film forming conditions, the film contains about 5% of chlorine atoms or chlorine ions.

After forming the CVD-TiN film, a TiN film is further formed to a thickness of 50 to 100 nm by a sputtering method. The laminated structure of sputtered TiN / CVD-TiN is CVD-T
About 5% of chlorine or chlorine ions contained in the iN film can be trapped by the upper sputtered TiN film, and when formed in a subsequent process due to chlorine in the CVD-TiN film. Corrosion of the Al wiring used can be prevented.

After the TiN film 62 is deposited, the TiN film 6 is dry-etched using the photoresist film 63 as a mask.
2 and Ta ₂ O ₅ film 61 are patterned to form an upper electrode made of TiN film 62 and Ta ₂ O ₅ film 6.
1 is formed, and an information storage capacitance element C composed of a lower electrode 60 made of a polycrystalline silicon film 56 is formed. Thereby, the MISFET for memory cell selection
A DRAM memory cell composed of Qs and an information storage capacitor C connected in series thereto is substantially completed.

Next, after removing the photoresist film 63, as shown in FIG. 41, the information storage capacitor is formed by a plasma CVD method using, for example, ozone (O ₃ ) and tetraethoxysilane (TEOS) as a source gas. A silicon oxide film 64 having a thickness of about 100 nm is deposited on the upper part of the element C, and the silicon oxide film 64, the silicon oxide film 53, and the silicon oxide films 46, 45 in the peripheral circuit region are dry-etched using the photoresist film 65 as a mask. By removing the SOG film 44 and the silicon nitride film 40, a through hole 66 having a high aspect ratio is formed above the first layer wiring 38.

Next, after removing the photoresist film 65, as shown in FIG. 42, a TiN film 71 having a thickness of 5 to 50 nm, preferably about 50 nm is formed on the silicon oxide film 64 including the inside of the through hole 66. Is deposited. This TiN
The film 71 is formed of a mixed gas (TiCl ₄ / NH ₃ = 1/2) of titanium tetrachloride (TiCl ₄ ) and ammonia (NH ₃ ).
~ 1/50) as a source gas at a temperature of 400 ° C to 65 ° C.
Deposition is performed by a thermal CVD method at 0 ° C., preferably 600 ° C. or more and a pressure of about 5 to 3000 Pa. Since the TiN film 71 has good step coverage, the film thickness becomes substantially uniform between the bottom of the through hole 66 and the opening. Since titanium tetrachloride is used as the source gas in the TiN film 71, about 5% of chlorine is taken into the film.

Next, as shown in FIG.
After a W film 72 having a thickness of about 500 nm is deposited on the upper surface of the silicon oxide film 64 by a CVD method,
By etching back the iN film 71 and leaving it only inside the through hole 66, a plug 73 made of a laminated film of the TiN film 71 and the W film 72 is formed. Silicon oxide film 6
In order to remove the W film 72 and the TiN film 71 on the upper part of the substrate 4, a chemical mechanical polishing (CMP) method may be used.

Next, as shown in FIG. 44, a TiN film 74 having a thickness of about 50 nm is deposited on the silicon oxide film 64 including the surface of the plug 73 by a sputtering method. Subsequently, as shown in FIG. 45, an Al alloy film 75 having a thickness of about 500 nm and a Ti film 76 having a thickness of about 50 nm were deposited on the TiN film 74 by a sputtering method, and the photoresist film was used as a mask. Ti film 76, A by dry etching
l alloy film 75 and TiN film 74 are patterned,
Second layer wirings 77 and 78 are formed on the silicon oxide film 64.

The second-layer wiring 7 thus formed
Reference numerals 7 and 78 denote TiN films in which a TiN film 71 constituting a part of the plug 73 (deposited by the CVD method) and an Al alloy film 75 constituting a part of the second layer wirings 77 and 78 are deposited by the sputtering method. CV because it is separated by the membrane 74
Corrosion of the second layer wirings 77 and 78 due to chlorine contained in the TiN film 71 deposited by the method D can be prevented.

After forming a sputtered Ti film of about 30 nm instead of the sputtered TiN film 74, the sputtered TiN film
Even when the film is formed to a thickness of about 30 nm, the second layer wiring 77 due to chlorine contained in the TiN film 71 deposited by the CVD method,
78 can be prevented. The sputtered Ti film has a better effect of trapping chlorine than sputtered TiN.

In this embodiment, the sputtered titanium nitride film 74 is used, but the sputtered titanium film, the tantalum film,
A tantalum nitride film or the like may be used.

The present invention can be applied to a process of forming a wiring with a conductive film containing an Al film above a through hole in which a plug containing a CVD-TiN film is buried.

(Embodiment 2) This embodiment is an embodiment of a device using a titanium nitride film containing a halogen element for one electrode of a storage capacitor portion.

FIG. 46 is a sectional view of the storage capacitor portion. Lower electrode 10 made of one polycrystalline silicon film of a capacitor
1 and a capacitor insulating film 102 made of a tantalum oxide film are formed by the same method as in the first embodiment. Although a tantalum oxide film is used as the capacitor insulating film 102 in this embodiment, a ferroelectric film such as BST or PZT may be used. Thereafter, using a mixed gas of titanium tetrachloride and ammonia as a source gas as a source gas, a TiN film having a thickness of 50 nm to 100 nm is deposited by a CVD method to form the upper electrode 103. This TiN film is formed at about 500 ° C. and contains about 4% chlorine. T for the upper electrode 103
The use of the iN film has an advantage that the film can be formed at a lower temperature than the conventional polycrystalline silicon film. Subsequently, chlorine-containing T
An about 30 nm-thick Ti film 104 is deposited on the upper electrode 103 made of the iN film by, for example, a sputtering method to form a chlorine trap layer.

As described above, the T forming the upper electrode 103
Despite the fact that the iN film contains a large amount of chlorine, by forming the Ti film 104 as a chlorine trapping layer on the iN film, corrosion of the wiring layer around the information storage capacitance element C can be effectively prevented. This can be prevented.

(Embodiment 3) On the sputtered Ti film 104 of Embodiment 2 described above,
FIG. 47 shows an example in which an N film 105 is deposited to form a trap layer.
This will be described with reference to FIG. The steps up to the step of forming the capacitance insulating film 102 made of a tantalum oxide film are the same as those in the first and second embodiments. Then, a 40 nm-thick T
An i film 104 is formed, and a TiN film 105 having a thickness of 60 nm is formed on the i film 104 by reactive sputtering in which a nitrogen gas is flown.

As described above, the Ti film 10 formed by the sputtering method
4 and a TiN film 105 formed by sputtering to form a chlorine trapping layer, chlorine can be almost completely trapped, and the corrosion of the wiring layer around the information storage capacitor C is further reduced. Can be prevented.

In this embodiment, the Ti film 104 is formed to a thickness of 40 nm and the TiN film 105 is formed to a thickness of 60 nm by the sputtering method.
The film 105 may be formed to a thickness of 50 to 100 nm to serve as a trap layer.

In this embodiment, the trap layer is formed by laminating the Ti film 104 and the TiN film 105.
For example, a trap layer may be formed by stacking a tantalum film and a tantalum nitride film (TaN). Also in this case, a tantalum film is formed, and a nitrogen gas is flowed from the middle to continue film formation, thereby forming a tantalum nitride film. As described above, when the trap layer is used as a laminated film, the trapping layer may be made of a laminated film of TiN film (upper layer) / Ti film (lower layer) or a laminated film of tantalum nitride film (upper layer) / tantalum film (lower layer). When a film having common constituent elements is used, pattern formation such as film formation and etching can be easily performed.

(Embodiment 4) An example in which a TiN film containing a halogen element is used as the upper electrode 103 of the information storage capacitive element C and the upper part and the side wall are covered with a trap film will be described with reference to FIG. .

First, as in the second embodiment, a lower electrode 101 made of a polycrystalline silicon film, a capacitance insulating film 102 made of a tantalum oxide film, and a halogen element-containing Ti
The information storage capacitor C is formed by the upper electrode 103 made of an N film.
To form Thereafter, a halogen trap layer 106 was formed from the upper portion to the side portion of the upper electrode 103 by using a selective CVD method. By using the selective CVD method as described above, not only the upper portion of the halogen element-containing TiN film but also the
The trap layer 106 can also be formed on the side wall.

The titanium nitride film (upper electrode 103) is formed by the following method in addition to the above-described selective CVD method.
May be provided. First, FIG.
As shown in FIG. 3, CVD using TDMAT (tetraxydimethylaminotitanium) as a source gas is formed on the upper electrode 103.
A TiN film 106a is formed by a method. Subsequently, FIG.
0, the TiN film 1 is formed using the photoresist film 111 covering the upper surface and the side walls of the upper electrode 103 as a mask.
06a is patterned to form the trap layer 10.
6 is formed. Note that a source gas such as TDEAT (tetraxydiethylaminotitanium) may be used as the organic source in addition to TDMAT.

As described above, by forming the trap layer 106 not only on the upper surface of the upper electrode 103 but also on the side walls, diffusion of halogen from the side of the TiN film (upper electrode 103) can be prevented, and information can be prevented. Corrosion of the wiring layer around the storage capacitance element C can be more effectively prevented.

As the trap layer 106, a Ti film or a TiN film formed by a sputtering method, a tantalum or tantalum nitride film, a Ti film formed by a CVD method using a source gas containing no halogen as a constituent element, a tantalum film or a nitride film. Any of tantalum films or a stacked film of these may be used.

(Embodiment 5) A method of removing a halogen element in a halogen-containing CVD-TiN film constituting an upper electrode of an information storage capacitor element will be described with reference to a process flow chart of FIG.

First, a capacitor insulating film made of a tantalum oxide film is formed on the lower electrode, and TiCl _{4 is} formed on the capacitor insulating film.
And NH ₃ as a source gas by the CVD method.
A TiN film is formed at a temperature of ° C. In this TiN film, about 5%
Contains chlorine.

Next, at about 500.degree.
The heat treatment is performed for at least seconds, preferably for about 10 minutes. This heat treatment is performed in the apparatus used for forming the TiN film,
This is performed continuously without exposing the N film to the atmosphere. When this heat treatment is performed at an annealing temperature (400 to 800 ° C., preferably 500 ° C. or more and 650 ° C. or less) higher than the film forming temperature of the CVD-TiN film, chlorine in the TiN film or on the surface is more effectively used. Can be removed. Note that the heat treatment may be performed by an RTA (Rapid Thermal Anneal) method or the like. Further, the heat treatment may be performed using an apparatus different from the apparatus used for forming the TiN film. If the same apparatus is used, annealing can be performed without exposing the film to the atmosphere after film formation, so that there is an effect of preventing surface oxidation. On the other hand, if a different apparatus or chamber is used, productivity (processing capacity) is improved.

The annealing is performed in addition to the above N ₂ , Ar,
It can be performed in an atmosphere of an inert gas such as He. However, it is possible to use a reducing gas such as H ₂ and NH _{3 in} addition to the inert gas.
Although the effect of removing chlorine in the VD-TiN film is large, it is necessary to pay attention to the deterioration of the withstand voltage of the capacitive insulating film.

Thereafter, chlorides such as NH ₄ Cl deposited on the film surface are removed by washing with pure water. As a pure water cleaning method, pure water is supplied to a rotating wafer surface. In some cases, ultrasonic vibration may be applied to pure water, or a brush such as nylon may be used in combination.

After the cleaning, the wafer is dried on a hot plate at 100 to 150 ° C. In addition to the pure water cleaning, an aqueous solution containing 1 to 10% NH ₃ may be used.
The cleaning step is not necessarily required because the annealing treatment alone has an effect of removing chlorine in the film. However, cleaning can remove chlorides adhering to the surface, so that the effect of preventing corrosion is high. Thereafter, a tantalum oxide film and Ti
The N film is patterned to form an information storage capacitor.

By these steps, chlorine in the TiN film can be effectively removed, and if this step is used, it is not necessary to provide the above-described trap layer. However, when the above-described means for providing a trap layer is used in combination with the step of removing chlorine as in the present embodiment, diffusion of chlorine can be almost completely prevented.

(Embodiment 6) A method for preventing corrosion of Al wiring by using a silicon oxide film deposited by a high-density plasma CVD method as an interlayer insulating film will be described with reference to FIGS. 52 and 53. FIG.

In the same manner as in the second embodiment, a capacitor insulating film 102 made of a tantalum oxide film is formed on a lower electrode 101 made of a polycrystalline silicon film. After forming a CVD-TiN film using TiCl ₄ to a thickness of about 100 nm, these films are patterned to form an information storage capacitor.

Next, a 30 nm-thick TiN film 105 is formed as a chlorine trap layer on the upper electrode 103 by a sputtering method. Subsequently, using an ECR plasma CVD apparatus, a mixed gas of SiH ₄ / O ₂ / Ar was introduced to form a plasma, and 13.56M was placed on a sample stage on which a substrate was placed.
A high frequency of Hz is applied to draw Ar ions in the plasma, and the silicon oxide film 107 is formed by a high-density plasma CVD method. Thus, a silicon oxide film 107 having a water blocking property is formed to a thickness of about 400 nm (FIG. 52). In addition, the plasma CVD apparatus is EC
In addition to the R type, a helical type or a helicon type may be used. Note that in this specification, high density means that the number of ions in the plasma is 1 × 10 ¹⁰ (pieces / cm ³ ) or more. However, it is preferable to use a high-density plasma CVD method of 1 × 10 ¹² (pieces / cm ³ ) or more.

After that, the silicon oxide film 1 is formed by the CMP method.
07 is removed by about 300 nm, and a silicon oxide film 107 having a thickness of about 100 nm is left on the information storage capacitor (FIG. 5).
3). This film is a silicon oxide film 64 shown in FIG.
Is equivalent to

When chlorine in the TiN film comes into contact with water that enters in some process, the surrounding wiring layer is easily corroded, but the high density plasma insulating film (silicon oxide film 107) having a high water blocking effect is formed. By forming on the chlorine-containing TiN film, it is possible to prevent water from entering the TiN film and to prevent corrosion of the surrounding wiring layer. This water is generated by, for example, steam baking after applying an inorganic spin-on-glass (SOG) film on the upper layer of the chlorine-containing TiN film, or washing after etching. Therefore,
If there is a high-density plasma silicon oxide film between the inorganic SOG film and the chlorine-containing TiN film, the penetration of water into the TiN film can be prevented, and the effect of corrosion prevention can be obtained.

The high-density plasma silicon oxide film is
It is sufficient that the inorganic SOG film is present between the inorganic SOG film and the halogen-containing TiN film, and when the inorganic SOG film 108 is directly formed on the high-density plasma CVD-silicon oxide film 107 of this embodiment (FIG. 54), Wiring layer 109 is formed on plasma CVD-silicon oxide film 107, and then inorganic SO
The case where the G film 110 is formed (FIG. 55) may be used.
In this embodiment, an example in which the TiN film is applied to the upper electrode of the information storage capacitor is shown. By forming the high-density plasma insulating film on the TiN film, the same water blocking effect as described above can be obtained.

In this embodiment, a high-density plasma CVD insulating film is used as a film having a high blocking effect against water. However, the present invention is not limited to this, and an organic SOG film can be used. However, the organic SOG film has a less blocking effect on water than the high-density plasma CVD insulating film.

Further, in the above-described embodiment, an example has been described in which the halogen in the TiN film diffuses into the wiring layer thereabove. The purpose is achieved by forming a trap film. For example, in a structure in which a tantalum or tantalum nitride film is formed as a trap film on a highly corrosive copper film, an insulating film is further formed thereon, and a halogen-containing TiN film is further provided thereon, the halogen from above is tantalum or It can be trapped by the tantalum nitride film, and the corrosion protection of the underlying copper film can be achieved.

Further, in the above embodiment, tantalum oxide is used as the capacitance insulating film. However, other than this, for example, BaSrTiO ₃ , SrTiO ₃ , BaTiO ₃ , PZ
Z doped with T, B (boron) or F (fluorine)
nO or the like can be applied.
The present invention can be applied to a nonvolatile memory and the like.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

[0114]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

According to the present invention, the A formed on the through hole in which the plug including the CVD-TiN film is embedded is formed.
Since the corrosion of the l-wiring can be reliably prevented, the reliability and manufacturing yield of an LSI having through holes with a high aspect ratio can be particularly improved.

Further, according to the present invention, it is possible to prevent wiring corrosion when forming an Al wiring on a capacitor element having an electrode made of a CVD-TiN film.
The reliability of the Al wiring and the production yield can be improved without deteriorating the breakdown voltage of the capacitor insulating film.

[Brief description of the drawings]

FIG. 1 is an overall plan view of a semiconductor chip on which a DRAM according to an embodiment of the present invention is formed.

FIG. 2 is an equivalent circuit diagram of a DRAM according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 5 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 9 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 10 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 11 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 12 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 13 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 14 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 15 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 16 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 17 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 18 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 19 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 20 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 21 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 22 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 23 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 24 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 25 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 26 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 27 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 28 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 29 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 30 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 31 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 32 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 33 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 34 is a plan view of a principal part of the semiconductor substrate showing a groove pattern and a long groove pattern.

FIG. 35 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 36 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 37 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 38 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 39 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 40 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 41 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 42 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 43 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 44 is a fragmentary cross-sectional view of the semiconductor substrate, illustrating the method for manufacturing the DRAM according to one embodiment of the present invention;

FIG. 45 is an essential part cross sectional view of the semiconductor substrate, illustrating the method of manufacturing the DRAM according to one embodiment of the present invention;

FIG. 46 is a diagram showing a cross section of a storage capacitor section of a DRAM according to another embodiment of the present invention.

FIG. 47 is a diagram showing a cross section of a storage capacitor section of a DRAM according to another embodiment of the present invention.

FIG. 48 is a diagram showing a cross section of a storage capacitor section of a DRAM according to another embodiment of the present invention.

FIG. 49 is a cross-sectional view showing a storage capacitor of a DRAM according to another embodiment of the present invention.

FIG. 50 is a cross-sectional view showing a storage capacitor part of a DRAM according to another embodiment of the present invention.

FIG. 51 is a flowchart showing a process for removing chlorine in a titanium nitride film.

FIG. 52 is a cross-sectional view showing a storage capacitor portion of a DRAM according to another embodiment of the present invention.

FIG. 53 is a cross-sectional view showing a storage capacitor of a DRAM according to another embodiment of the present invention.

FIG. 54 is a cross-sectional view showing a storage capacitor portion of a DRAM according to another embodiment of the present invention.

FIG. 55 is a cross-sectional view showing a storage capacitor of a DRAM according to another embodiment of the present invention.

FIG. 56 is a graph showing a relationship between a deposition temperature of a titanium nitride film by a CVD method and a chlorine concentration in the titanium nitride film.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 semiconductor substrate 1A semiconductor chip 2 silicon oxide film 3 silicon nitride film 4 photoresist film 5 element isolation groove 5a groove 6 silicon oxide film 7 silicon oxide film 8 silicon nitride film 9 photoresist film 10 n-type semiconductor region 11 p-type well 12 n-type well 13 gate oxide film 14A to 14C gate electrode 15 silicon nitride film 16 photoresist film 17 p ^- type semiconductor region 18 n ^- type semiconductor region 19 n-type semiconductor region 20 silicon nitride film 20a sidewall spacer 21 photoresist film 22 p ⁺ type semiconductor region 23 n ⁺ type semiconductor region 24 SOG film 24 a, 24 b SOG film 25 silicon oxide film 26 silicon oxide film 27 photoresist film 28 contact hole 29 contact hole 30 plug 31 silicon oxide film 32 photoresist Strike film 33 photoresist film 34-37 contact hole 38, 39 first layer wiring 40 silicon nitride film 41 photoresist film 42 TiSi ₂ layer 43 sidewall spacer 44 SOG film 45 silicon oxide film 46 silicon oxide film 47 photoresist film 48 Through hole 49 Plug 51 Silicon nitride film 52 Photoresist film 53 Silicon oxide film 54 Photoresist film 55 Groove 56 Polycrystalline silicon film 57 SOG film 58 Photoresist film 59 Long groove 60 Lower electrode 61 Ta ₂ O ₅ (tantalum oxide) film 62 TiN film (upper electrode) 63 photoresist film 64 silicon oxide film 65 photoresist film 66 through hole 67 plug 71 TiN film 72 W film 73 plug 74 TiN film 75 Al alloy film 76 Ti film 77, 78 Layer wiring 101 Lower electrode 102 Capacitive insulating film 103 Upper electrode 104 Ti film 105 TiN film 106 Trap layer 106 a TiN film 107 Silicon oxide film 108 Inorganic SOG film 110 Inorganic SOG film 111 Photoresist film BL Bit line C Information storage capacitor MARY Memory array Qn n-channel type MISFET Qp p-channel type MISFET Qs MISFET for memory cell selection SA sense amplifier WD word driver

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Isamu Isano 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Katsuhiko Tanaka 5--20 Kamimizu Honcho, Kodaira-shi No. 1 Hitachi Semiconductor Co., Ltd. Semiconductor Division (72) Inventor Naoki Fukuda 6-16-16 Shinmachi, Ome-shi, Tokyo Inside Device Development Center Hitachi, Ltd. 3-16, Hitachi, Ltd. Device Development Center, Hitachi, Ltd. (72) Inventor Hiroshi Sakuma 6-16, Shinmachi, Shinmachi, Ome City, Tokyo 3) Hitachi, Ltd. Device Development Center, Ltd. (72) Keizo Kawakita Ome, Tokyo 6-chome, Shinmachi, Yokohama 3 Device Development Center, Hitachi, Ltd. (72) Akiya Satoru Satoru 6-16-16 Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Kensei Hirasawa 6-16-16, Shinmachi, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.

Claims (36)

[Claims] 1. A substrate, a halogen-containing titanium nitride film formed on the substrate, a first conductive film formed on the substrate, the titanium nitride film and the first conductive film A second film formed between the first film and the second film, the second film including a metal atom bonded to a halogen element and having a higher ability to trap the halogen element than tungsten. 2. The semiconductor integrated circuit device according to claim 1, wherein said second film is a titanium film or a tantalum film. 3. The semiconductor integrated circuit device according to claim 1, wherein the second film is a stacked film including a titanium film or a stacked film including a tantalum film. 4. The semiconductor integrated circuit device according to claim 1, wherein the thickness of the second film is 5 nm or more. 5. The semiconductor integrated circuit device according to claim 1, wherein the first conductive film is an aluminum film, an aluminum alloy film, a copper film, or a copper alloy film. Semiconductor integrated circuit device. 6. A base, an insulating film having an opening formed on the base, and a titanium nitride film formed using a source gas containing a halogen element formed in the opening. A third film formed on the titanium nitride film, the third film containing a metal atom bonded to the halogen element and having a higher ability to trap the halogen element than tungsten; and a third film formed on the third film. A semiconductor integrated circuit device having a second conductive film formed thereon. 7. The semiconductor integrated circuit device according to claim 6, wherein said third film is formed from above said titanium nitride film to above said insulating film. 8. The semiconductor integrated circuit device according to claim 6, wherein said third film is a titanium film or a laminated film including said titanium film. 9. The semiconductor integrated circuit device according to claim 6, wherein a tungsten film is formed on the titanium nitride film formed in the opening. Semiconductor integrated circuit device. 10. A base on which a MISFET is formed, and a storage capacitor section comprising a first electrode, a capacitor insulating film, and a second electrode including a titanium nitride film containing a halogen element formed on the base. A fourth film formed on the titanium nitride film, the fourth film including an element having a binding energy with the halogen element exceeding 111 Kcal / mol, and a conductive film formed on the fourth film. A semiconductor integrated circuit device characterized by the above-mentioned. 11. The semiconductor integrated circuit device according to claim 10, wherein said fourth film is formed so as to cover said titanium nitride film. 12. A copper wiring layer formed on a substrate, a film formed on the copper wiring layer and containing an element having a bonding energy of more than 111 Kcal / mol with an insulating film and a halogen element, and the insulating film And a titanium nitride film containing a halogen element formed on the film containing the element. 13. A step of forming an insulating film having an opening on a substrate, and forming a titanium nitride film in the opening by a CVD method using a compound containing a halogen element as a source gas. Forming a third film on the titanium nitride film, the third film containing a metal atom bonded to the halogen element and having a higher ability to trap the halogen element than tungsten. Forming a wiring thereon. A method of manufacturing a semiconductor integrated circuit device, comprising: 14. The method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein the compound containing a halogen element as a constituent element is titanium tetrachloride or titanium tetraiodide. Device manufacturing method. 15. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the step of forming the third film comprises:
A method for manufacturing a semiconductor integrated circuit device, comprising a step of forming a titanium film, a titanium nitride film, a tantalum film, or a tantalum nitride film by a sputtering method. 16. The method of manufacturing a semiconductor integrated circuit device according to claim 13, wherein the step of forming the third film comprises:
A method for manufacturing a semiconductor integrated circuit device, comprising a step of forming a titanium film, a titanium nitride film, a tantalum film, or a tantalum nitride film by a CVD method using a source gas containing no halogen element as a constituent element. 17. The method for manufacturing a semiconductor integrated circuit device according to claim 13, 14, 15 or 16, wherein the titanium nitride film is formed at a temperature of 500 ° C. or less. . 18. The method according to claim 1, wherein the first substrate is provided on a substrate on which the semiconductor element is formed.
Forming a capacitor insulating film on the first electrode, and forming a second electrode on the capacitor insulating film by a CVD method using a source gas containing a halogen element as a second electrode. Forming a film and forming a storage capacitor portion; and forming a third film on the titanium nitride film, the third film containing a metal atom bonded to the halogen element and having a higher ability to trap the halogen element than tungsten. A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming; and a step of forming an insulating film on the third film. 19. The method for manufacturing a semiconductor integrated circuit device according to claim 18, wherein said third film is formed by a selective CVD method. 20. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein the step of forming the third film comprises:
Forming the third film covering the storage capacitor portion, forming a fourth film on the third film on the upper surface and side surfaces of the storage capacitor portion, and using the fourth film as a mask; A method for manufacturing a semiconductor integrated circuit device, comprising: a step of etching and removing the third film so as to leave the third film on the upper surface and the side surface of the storage capacitor portion. 21. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein the step of forming the third film comprises:
A method for manufacturing a semiconductor integrated circuit device, comprising a step of forming a titanium film, a titanium nitride film, a tantalum film, or a tantalum nitride film by a sputtering method. 22. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein the step of forming the third film comprises:
A method for manufacturing a semiconductor integrated circuit device, comprising a step of forming a titanium film, a titanium nitride film, a tantalum film, or a tantalum nitride film by a CVD method using a source gas containing no halogen element as a constituent element. 23. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein the step of forming the third film comprises:
A method for manufacturing a semiconductor integrated circuit device, comprising: a step of forming a titanium film by a sputtering method; and a step of forming a titanium nitride film on the titanium film by a sputtering method. 24. The method of manufacturing a semiconductor integrated circuit device according to claim 18, wherein the step of forming the third film comprises:
A step of forming a tantalum film by a sputtering method,
Forming a tantalum nitride film on the tantalum film by a sputtering method. 25. A step of forming a titanium nitride film at a first temperature on a substrate by a CVD method using a compound containing a halogen element as a constituent gas as a source gas; Removing the halogen element from the titanium nitride film by heating the titanium nitride film in an inert gas. 26. The method for manufacturing a semiconductor integrated circuit device according to claim 25, wherein after the step of removing the halogen element, the base is washed, and the halogen element or the halogen compound on the surface of the titanium nitride film. A method of manufacturing a semiconductor integrated circuit device, further comprising the step of removing a semiconductor integrated circuit device. 27. A step of forming a titanium nitride film on a substrate by a CVD method using a compound containing a halogen element as a constituent gas as a source gas, and a high-density plasma CVD method on the titanium nitride film. Forming a semiconductor integrated circuit device. 28. A method for manufacturing a semiconductor integrated circuit device, comprising: a step of applying an inorganic spin-on-glass film on an insulating film; and a step of steam-baking the inorganic spin-on-glass film. 29. A method comprising: forming a metal wiring on an insulating film; applying an inorganic spin-on-glass film on the metal wiring; and steam-baking the inorganic spin-on-glass film. A method for manufacturing a semiconductor integrated circuit device. 30. A step of forming a titanium nitride film on a substrate by a CVD method using a compound containing a halogen element as a constituent gas as a source gas, and a plasma CVD method or a thermal CVD method on the titanium nitride film. Refractive index is 1.
Forming a 46 or more insulating film. 31. The method for manufacturing a semiconductor integrated circuit device according to claim 30, comprising a step of applying an inorganic spin-on-glass film on the insulating film, and a step of steam-baking the inorganic spin-on-glass film. A method for manufacturing a semiconductor integrated circuit device, comprising: 32. The method of manufacturing a semiconductor integrated circuit device according to claim 30, wherein: a step of forming a metal wiring on the insulating film; and a step of applying an inorganic spin-on-glass film on the metal wiring. Steam baking the inorganic spin-on-glass film. 33. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps (a) to (c): (a) Opening and connecting an insulating film formed on a main surface of a semiconductor substrate Forming a hole, (b) a first conductive film including a first titanium nitride film formed on the insulating film including the inside of the connection hole by a CVD method using a source gas containing a halogen element After the formation of the first insulating film,
Forming a plug inside the connection hole by removing the first conductive film including the titanium nitride film and leaving the inside of the connection hole, (c) forming a plug on the insulating film including the surface of the plug Forming a wiring by depositing a second conductive film including a second titanium nitride film having at least a lowermost layer formed by a sputtering method, and then patterning the second conductive film including the second titanium nitride film; Process. 34. The method of manufacturing a semiconductor integrated circuit device according to claim 33, wherein said second conductive film contains Al. 35. The method for manufacturing a semiconductor integrated circuit device according to claim 33, wherein the first conductive film is further formed by CVD.
A method for manufacturing a semiconductor integrated circuit device, comprising a tungsten film formed by a method. 36. A DRAM in which a memory cell is constituted by a memory cell selecting MISFET and an information storing capacitive element connected in series with the MISFET, and the information storing capacitive element is arranged above the memory cell selecting MISFET. And (a) a memory cell selecting MISFE in a memory array on a main surface of a semiconductor substrate.
Forming a MISFET of a peripheral circuit in a peripheral circuit region, and (b) forming the memory cell selecting MISFE.
Forming a bit line above the T via a first insulating film, and forming a first layer wiring above the MISFET of the peripheral circuit via the first insulating film; (c) above the bit line Forming an information storage capacitor via a second insulating film, (d) depositing a third insulating film on the information storage capacitor, and then forming the third insulating film in a peripheral circuit region; Etching a second insulating film and the first insulating film to form a connection hole above the first layer wiring; and (e) forming a halogen element on the third insulating film including the inside of the connection hole. After forming a first conductive film containing first titanium nitride formed by a CVD method using a source gas containing, a first conductive film containing the first titanium nitride film on the third insulating film is formed.
Forming a plug inside the connection hole by removing the conductive film and leaving the plug only inside the connection hole; (f)
After depositing a second conductive film including a second titanium nitride film having at least a lowermost layer formed by a sputtering method on the third insulating film including the surface of the plug, the second titanium nitride film is removed. Patterning the second conductive film containing
Forming a layer wiring, a method for manufacturing a semiconductor integrated circuit device.