JP4844441B2 - Capacitor circuit, calibration circuit, comparator and voltage comparator - Google Patents

Description

  The present invention relates to a capacitor circuit suitable for use in configuring a calibration circuit for canceling an offset of a comparator (comparator) used when configuring an A / D converter, a voltage comparator, etc., and the capacitor circuit The present invention relates to a calibration circuit using the calibration circuit, a comparator using the calibration circuit, and a voltage comparator using the comparator.

  A comparator is used for the A / D converter and the voltage comparator. The comparator has the function of comparing and determining the magnitude of two analog input voltages and outputting the comparison determination result as a digital value, but usually has an offset due to variations in the characteristics of the elements constituting the comparator. This limits the accuracy of comparison. In order to cancel this offset, conventionally, static offset calibration generally called auto-zero has been generally performed (see, for example, Non-Patent Document 1).

On the other hand, a dynamic offset calibration method (see, for example, Non-Patent Document 2) in which a comparator is operated under the same conditions as in an actual operation mode and an offset is canceled using a D / A converter. There has also been reported a dynamic offset calibration method (see Non-Patent Document 3) in which an offset is canceled by applying negative feedback by a switched capacitor circuit without using a / A converter. In these dynamic offset calibration methods, offset calibration is performed under the same conditions as in the actual operating environment, so that a more accurate comparison / determination operation can be realized.
Sanroku Tsukamoto, Ian Dedic, Toshiaki Endo, Kazu-yoshi Kikuta, Kunihiko Goto, Osamu Kobayashi; A CMOS 6-b, 200 Msample / s, 3 V-supply A / D converter for a PRML read channel LSI, IEEE Journal of Solid -State Circuits, vol.31, pp.1831-1836, November 1996. Yuko Tamba, Kazuo Yamakido; A CMOS 6b 500M Sample / s ADC for a hard disk drive read channel, IEEE International Solid-State Circuits Conference, vol.XLII, pp.324-325, February 1999. Pedro M. Figueiredo, “A 90nm CMOS 1.2V 6b 1GS / s Two-Step Subranging ADC” IEEE International Solid-State Circuits Conference, vol. 49, pp. 568-569, February 2006.

  In the dynamic offset calibration methods described in Non-Patent Documents 2 and 3, the resolution of the D / A converter or the switched capacitor circuit to be corrected is finite, and the offset / offset based on the comparison determination result of the comparator is used. In order to apply feedback for calibration, it was controlled by one gradation / judgment step. For this reason, there is a trade-off relationship between the high accuracy of offset calibration and the number of correction cycles.

  That is, if the minimum step width of correction is reduced in order to increase the accuracy of offset calibration, the number of comparison judgment cycles (= correction period) until reaching the balance point where the offset is canceled becomes the minimum step width. There is a problem that the rise time increases until the actual operation becomes possible, and the correction cannot be completed during one correction period. Conversely, if the minimum step width is increased in order to shorten the correction period, there is a problem that an offset below the correction resolution cannot be canceled.

  In view of this point, the present invention provides a high-precision offset in a short time when used in a calibration circuit for calibrating an offset of a comparator used when configuring an A / D converter, a voltage comparator, or the like. An object is to provide a capacitor circuit capable of performing calibration, a calibration circuit using the capacitor circuit, a comparator using the calibration circuit, and a voltage comparator using the comparator.

  The capacitor circuit of the present invention includes a plurality of switches connected in series between a first connection point and a second connection point, a node on the second connection point side of each of the plurality of switches, and a power source. A switched capacitor circuit having a plurality of capacitors connected to each other, and a switch control circuit for controlling the plurality of switches, wherein the switch control circuit includes a plurality of switches in the first mode. A predetermined switch is turned on, and the remaining switches other than the predetermined switch are repeatedly turned on and off so that adjacent switches are not turned on at the same time. In the second mode, the plurality of switches The plurality of switches are repeatedly turned on and off so that adjacent switches in the switch do not turn on at the same time. In the third mode, the plurality of switches are turned on. Characterized in that a switch control circuit to.

  The calibration circuit of the present invention has a calibration transistor in which a source is connected to a third connection point and a drain is connected to a fourth connection point, and the first connection point is connected to a fifth connection point. The capacitor circuit of the present invention is provided with the second connection point connected to the gate of the calibration transistor.

  In the comparator of the present invention, a first conductive type first transistor having a gate connected to a first analog voltage input terminal, a source connected to a first power supply, and a gate connected to a second analog voltage input terminal. A first conductivity type second transistor having a source connected to the first power source, a drain connected to the drain of the first transistor, a gate connected to a drain of the second transistor, and a source Is connected to the second power source, and the drain is connected to the drain of the second transistor, the gate is connected to the drain of the first transistor, and the source is the second transistor. At least a fourth transistor of the second conductivity type connected to the power source of the first transistor, and an input terminal of the drain of the first transistor or the drain of the third transistor. A first inverter having an output terminal connected to the first comparison determination signal output terminal, and an input terminal connected to either the drain of the second transistor or the drain of the fourth transistor. , A second inverter having an output terminal connected to a second comparison determination signal output terminal, the third connection point connected to a source of the first transistor, and the fourth connection point connected to the first A calibration circuit of the first aspect of the present invention in which the fifth connection point is connected to the second comparison determination signal output terminal, and the third connection point is connected to the drain of the transistor; A calibration according to the second aspect of the present invention, in which the fourth connection point is connected to the drain of the second transistor, and the fifth connection point is connected to the first comparison determination signal output terminal. Those with a ® down circuit.

  The voltage comparator of the present invention monitors the logic of the comparator of the present invention and the comparison determination signal output from the comparator of the present invention to the second comparison determination signal output terminal. A control circuit is provided for setting the comparator of the present invention to the second mode when the first mode is set and then the logic of the comparison determination signal is inverted.

  The capacitor circuit of the present invention is used for a calibration circuit for calibrating an offset of a comparator used when an A / D converter, a voltage comparator, or the like is configured, and the switched capacitor circuit is a calibration circuit. Is used as part of the negative feedback path.

  In the capacitor circuit of the present invention, in the first mode, a plurality of predetermined switches among the plurality of switches are turned on, and the remaining switches are configured such that adjacent switches in the remaining switches are not turned on at the same time. Repeat the on / off operation. As a result, in the first mode, the switched capacitor circuit has a relatively low calibration accuracy but a relatively fast calibration operation, ie, negative feedback for performing offset calibration by so-called coarse adjustment. Can act as part of a path.

  In the second mode, the plurality of switches are repeatedly turned on and off so that adjacent switches in the plurality of switches do not turn on at the same time. As a result, in the second mode, the switched capacitor circuit is not fast in the calibration operation, but has a relatively high calibration accuracy, ie, a negative feedback path for performing offset calibration by so-called fine adjustment. Can function as a part of

  Therefore, when the capacitor circuit according to the present invention is used in the calibration circuit of the comparator to sequentially set the first mode and the second mode, the comparator performs coarse calibration offset calibration and fine adjustment offset calibration. Calibration can be performed in order. Therefore, according to the capacitor circuit of the present invention, highly accurate offset calibration can be performed in a short time.

  The calibration circuit of the present invention performs offset calibration for the comparator by adjusting the current flowing through the calibration transistor, and includes the capacitor circuit of the present invention.・ Calibration can be performed.

  The comparator according to the present invention compares and determines the magnitude of two analog input voltages, and includes the calibration circuit according to the present invention, so that highly accurate offset calibration can be performed in a short time.

  According to the voltage comparator of the present invention, first, the comparator of the present invention is set to the first mode, the offset calibration by coarse adjustment is performed on the comparator of the present invention, and then the comparison determination signal is inverted. Since the comparator of the present invention can be set to the second mode and the offset calibration by fine adjustment can be performed for the comparator of the present invention, the highly accurate offset calibration can be performed in a short time for the comparator of the present invention. .

  FIG. 1 is a circuit diagram showing the main part of an embodiment of the voltage comparator of the present invention. One embodiment of the voltage comparator of the present invention includes a comparator 1, which is an embodiment of the comparator of the present invention, a coarse / fine control circuit 2, and flip-flops 3 and 4.

  The comparator 1 compares and determines the magnitude of the analog input voltage Vip applied to the first analog input terminal 1A and the analog input voltage Vim applied to the second analog input terminal 1B, and outputs a first comparison determination signal. A normal phase comparison determination signal Cop is output to the positive phase comparison determination signal output terminal 1C, which is a terminal, and a positive phase comparison determination signal Cop is complementary to the negative phase comparison determination signal output terminal 1D, which is a second comparison determination signal output terminal. The negative phase comparison determination signal Com is output.

  When the analog input voltage Vip> the analog input voltage Vim, the comparator 1 has the positive phase comparison determination signal Cop at the H level (positive power supply voltage VDD) and the negative phase comparison determination signal Com at the L level (0 V). When the input voltage Vip <the analog input voltage Vim, the normal phase comparison determination signal Cop is at the L level and the negative phase comparison determination signal Com is at the H level.

  The comparator 1 is supplied with a clock signal φC, a calibration instruction signal φRES, and a coarse / fine control signal φS as control signals. The calibration instruction signal φRES is a signal for instructing the comparator 1 to execute offset calibration. The coarse / fine adjustment control signal φS controls the accuracy of the offset calibration in the comparator 1, that is, whether the offset calibration is executed with coarse or fine adjustment.

  The coarse / fine adjustment control circuit 2 receives the calibration instruction signal φRES, the clock signal φC, and the negative phase comparison determination signal Com output from the comparator 1 to generate the coarse / fine adjustment control signal φS. A fine / fine adjustment control signal φS is supplied to the comparator 1 to control whether the offset calibration in the comparator 1 is executed in coarse adjustment or fine adjustment.

  In the flip-flop 3, the normal phase comparison determination signal Cop output from the comparator 1 is applied to the data input terminal D, and the clock signal φC is applied to the clock input terminal CLK. In the flip-flop 4, the anti-phase comparison determination signal Com output from the comparator 1 is applied to the data input terminal D, and the clock signal φC is applied to the clock input terminal CLK.

  FIG. 2 is a circuit diagram showing the configuration of the flip-flop 3, and the flip-flop 4 is similarly configured. The flip-flop 3 includes a capturing unit 7 and a capturing control unit 8 that controls the capturing unit 7.

  The capturing unit 7 includes inverters 9 to 14 and switches 15 to 18. The switches 15 and 16 are controlled to be turned on and off by the switch control signal CK1, and are turned on when the switch control signal CK1 is at the H level and turned off when the switch control signal CK1 is at the L level. The switches 17 and 18 are controlled to be turned on and off by the switch control signal CK2, and are turned on when the switch control signal CK2 is at the H level and turned off when the switch control signal CK2 is at the L level.

  The capture control unit 8 includes inverters 19 and 20. The inverter 19 inverts the clock signal φC applied to the clock input terminal CLK and outputs a switch control signal CK1. The inverter 20 inverts the switch control signal CK1 output from the inverter 19 and outputs a switch control signal CK2.

  FIG. 3 is a timing chart showing the comparison operation timing and reset operation timing of the comparator 1 and the capture operation timing of the flip-flops 3 and 4, where (A) is the clock signal φC and (B) is the positive phase output by the comparator 1. The comparison determination signal Cop and the negative phase comparison determination signal Com, (C) indicate the signal Dop output from the flip-flop 3 to the positive phase output terminal Q and the signal Dom output from the flip-flop 4 to the positive phase output terminal Q. The case of address input voltage Vip> analog input voltage Vim is taken as an example.

  That is, in one embodiment of the voltage comparator of the present invention, the comparator 1 starts the comparison operation in synchronization with the falling edge of the clock signal φC and outputs valid data, and synchronizes with the rising edge of the clock signal φC. Reset operation is started and invalid data is output. The flip-flop 3 captures the normal phase comparison determination signal Cop in synchronization with the rising edge of the clock signal φC, and the flip-flop 4 captures the reverse phase comparison determination signal Com in synchronization with the rise of the clock signal φC.

  FIG. 4 is a circuit diagram showing a configuration of the coarse / fine adjustment control circuit 2. The coarse / fine adjustment control circuit 2 includes flip-flops 22 and 23, an EOR (exclusive OR) circuit 24, and a flip-flop 25.

  The flip-flop 22 is applied with the anti-phase comparison determination signal Com at the data input terminal D, the clock signal φC is applied at the clock input terminal CLK, and takes in the anti-phase comparison determination signal Com in synchronization with the rise of the clock signal φC. The configuration is the same as that of the flip-flop 3 shown in FIG.

  In the flip-flop 23, the output signal S22 of the flip-flop 22 is applied to the data input terminal D, the clock signal φC is applied to the clock input terminal CLK, and the output signal S22 of the flip-flop 22 is synchronized with the rise of the clock signal φC. This is to be taken in and is configured in the same manner as the flip-flop 3 shown in FIG.

  The EOR circuit 24 performs EOR processing on the output signal S22 of the flip-flop 22 and the output signal S23 of the flip-flop 23, and the logical values of the output signal S22 of the flip-flop 22 and the output signal S23 of the flip-flop 23 are the same. In this case, an L level is output, and if the logical values of the output signal S22 of the flip-flop 22 and the output signal S23 of the flip-flop 23 are not the same, an H level is output.

  In the flip-flop 25, the power supply voltage VDD is applied to the data input terminal D, the output signal S24 of the EOR circuit 24 is applied to the clock input terminal CLK, the calibration instruction signal φRES is applied to the reset input terminal RES, and the positive phase output The coarse / fine adjustment control signal φS is output to the terminal Q.

  FIG. 5 is a circuit diagram showing the configuration of the flip-flop 25. The flip-flop 25 includes a capturing unit 27 and a capturing control unit 28 that controls the capturing unit 27.

  The capturing unit 27 includes inverters 29 to 33, a NAND circuit 34, and switches 35 to 38. The switches 35 and 36 are ON / OFF controlled by the switch control signal CK3, and are ON when the switch control signal CK3 is at the H level, and OFF when the switch control signal CK3 is at the L level. The switches 37 and 38 are ON / OFF controlled by a switch control signal CK4. The switches 37 and 38 are ON when the switch control signal CK4 is at an H level, and are OFF when the switch control signal CK4 is at an L level.

  The capture control unit 28 includes inverters 39 and 40. The inverter 39 inverts the clock signal φC applied to the clock input terminal CLK and outputs a switch control signal CK3. The inverter 40 inverts the switch control signal CK3 output from the inverter 39 and outputs the switch control signal CK4.

  FIG. 6 is a timing chart showing the operation of the coarse / fine control circuit 2. (A) is a calibration instruction signal φRES, (B) is a clock signal φC, and (C) is a positive-phase comparison determination output by the comparator 1. The signal Cop and the negative phase comparison determination signal Com, (D) is the output signal S22 of the flip-flop 22, (E) is the output signal S23 of the flip-flop 23, (F) is the output signal S24 of the EOR circuit 24, (G) is The power supply voltages VDD and (H) indicate the coarse / fine adjustment control signal φS output from the flip-flop 25, and the case where the analog input voltage Vip> the analog input voltage Vim is taken as an example.

  That is, in the coarse / fine adjustment control circuit 2, when the calibration instruction signal φRES is at L level, the output of the NAND circuit 34 in the flip-flop 25 is fixed at H level, and the coarse / fine adjustment control signal φS is Fixed to L level.

  On the other hand, when the calibration instruction signal φRES is at the H level, the NAND circuit 34 in the flip-flop 25 functions as an inverter for the output signal of the switch 36 or the switch 38, so that the flip-flop 25 is a D flip-flop. It functions as a group.

  As a result, in the flip-flop 25, when the output signal S24 of the EOR circuit 24 is at L level, the switch control signal CK3 becomes H level and the switch control signal CK4 becomes L level, the switches 35 and 36 are ON, and the switch 37 , 38 are OFF.

  As will be described later, when the calibration instruction signal φRES is at the H level, the comparator 1 performs an offset calibration operation, but starts the comparison operation in synchronization with the falling edge of the clock signal φC, Since the reset operation is started in synchronization with the rise of the signal φC, when the analog input voltage Vip> the analog input voltage Vim, initially, the normal phase comparison determination signal Cop is H level and the negative phase comparison determination signal Com is L Become a level.

  Here, when the normal phase comparison determination signal Cop is at the H level and the negative phase comparison determination signal Com is at the L level, the flip-flop 22 takes in the L level signal and sets the output signal S22 to the L level. As a result, the flip-flop 23 takes in the L level signal, sets the output signal S23 to the L level, and the EOR circuit 24 sets the output signal S24 to the L level.

  As a result, in the flip-flop 25, the switch control signal CK3 is at the H level and the switch control signal CK4 is at the L level, and the switches 35 and 36 are kept on and the switches 37 and 38 are kept off.

  Here, even when the analog input voltage Vip> the analog input voltage Vim, as described later, as a result of the offset calibration by the coarse adjustment in the comparator 1, the normal phase comparison determination signal Cop and the negative phase comparison determination signal Com. Is inverted, and the normal phase comparison determination signal Cop is at the L level and the negative phase comparison determination signal Com is at the H level.

  In this case, the flip-flop 22 takes in the H level signal and sets the output signal S22 to the H level. At this time, since the output signal S23 of the flip-flop 23 is at the L level, the EOR circuit 24 outputs the output signal S22. The signal S24 is set to H level.

  As a result, in the flip-flop 25, the switch control signal CK3 becomes L level and the switch control signal CK4 becomes H level, the switches 35 and 36 are turned off, and the switches 37 and 38 are turned on, and the flip-flop 25 takes in the power supply voltage VDD. The coarse / fine adjustment control signal φS becomes H level, and this state is maintained until the calibration instruction signal φRES becomes L level.

  FIG. 7 is a circuit diagram showing a configuration of the comparator 1. In the comparator 1, calibration circuits 49 and 50, which are one embodiment of the calibration circuit of the present invention, are added to a comparator comprising PMOS transistors 42 and 43, NMOS transistors 44 and 45, inverters 46 and 47, and a switch 48. It is a thing.

  The PMOS transistors 42 and 43 form drive elements. The PMOS transistor 42 has a source connected to the VDD power source, a gate connected to the analog voltage input terminal 1A, and a drain connected to the node 51. The PMOS transistor 43 has a source connected to the VDD power supply, a gate connected to the analog voltage input terminal 1B, and a drain connected to the node 52.

  The NMOS transistors 44 and 45 form load elements. The NMOS transistor 44 has a drain connected to the node 51, a gate connected to the node 52, and a source grounded. The NMOS transistor 45 has a drain connected to the node 52, a gate connected to the node 51, and a source grounded.

  The inverter 46 has its input terminal connected to the node 51 and its output terminal connected to the positive phase comparison determination signal output terminal 1C of the comparator 1, and outputs a positive phase comparison determination signal Cop based on the level of the node 51. To do. Inverter 47 has its input terminal connected to node 52 and its output terminal connected to negative-phase comparison determination signal output terminal 1D of comparator 1, and outputs negative-phase comparison determination signal Com based on the level of node 52. To do.

  The switch 48 is a reset switch and is turned on when the clock signal φC is at the H level and turned off when the clock signal φC is at the L level. Therefore, the comparator 1 is reset when the clock signal φC is at the H level and the switch 48 is turned on, and performs the comparison operation when the clock signal φC is at the L level and the switch 48 is turned off.

  FIG. 8 is a circuit diagram showing a configuration of the calibration circuit 49. The calibration circuit 49 includes a calibration PMOS transistor 55, a switched capacitor circuit 56, and a switch control circuit 57. Note that the switched capacitor circuit 56 and the switch control circuit 57 constitute one embodiment of the capacitor circuit of the present invention.

  The PMOS transistor 55 outputs a calibration current to the drain side, and has a source connected to the power supply voltage input node 58 and a drain connected to the calibration current output node 59. The power supply voltage input node 58 is connected to the VDD power supply, and the calibration current output node 59 is connected to the node 52.

  In the switched capacitor circuit 56, between the negative feedback node 60 and the gate of the PMOS transistor 55, one of the switches 61 to 64 is on the negative feedback node 60 side, and the other node is on the gate side of the PMOS transistor 55. And capacitors 65 to 68 are connected between the other nodes of these switches 61 to 64 and the ground. The negative feedback node 60 is connected to the output terminal of the inverter 46.

  The switch 61 is controlled to be turned on and off by the switch control signal φ4. The switch 61 is turned on when the switch control signal φ4 is at the H level and turned off when the switch control signal φ4 is at the L level. The switch 62 is controlled to be turned on and off by the switch control signal φ3, and is turned on when the switch control signal φ3 is at the H level and turned off when the switch control signal φ3 is at the L level.

  The switch 63 is controlled to be turned on and off by the switch control signal φ2, and is turned on when the switch control signal φ2 is at the H level and turned off when the switch control signal φ2 is at the L level. The switch 64 is controlled to be turned on and off by the switch control signal φ1, and is turned on when the switch control signal φ1 is at the H level and turned off when the switch control signal φ1 is at the L level.

  The switch control circuit 57 includes a calibration instruction signal φRES, a coarse / fine adjustment control signal via a calibration instruction signal input node 69, a coarse / fine adjustment control signal input node 70, a clock signal input node 71, and a power supply voltage input node 58. φS, clock signal φC, and power supply voltage VDD are input to generate switch control signals φ1 to φ4.

  FIG. 9 is a circuit diagram showing a configuration of the switch control circuit 57. The switch control circuit 57 includes a flip-flop 73, inverters 74 to 79, NAND circuits 80 to 88, and a NOR circuit 89.

  FIG. 10 is a circuit diagram showing the configuration of the flip-flop 73. The flip-flop 73 includes a capturing unit 91 and a capturing control unit 92 that controls the capturing unit 91.

  The capturing unit 91 includes inverters 93 to 98 and switches 99 to 102. The switches 99 and 100 are ON / OFF controlled by the switch control signal CK5, and are ON when the switch control signal CK5 is at the H level, and OFF when the switch control signal CK5 is at the L level. The switches 101 and 102 are ON / OFF controlled by the switch control signal CK6, and are ON when the switch control signal CK6 is at the H level, and OFF when the switch control signal CK6 is at the L level.

  The capture control unit 92 includes a NAND circuit 103 and an inverter 104. The NAND circuit 103 performs NAND processing on the calibration instruction signal φRES applied to the clock enable signal input terminal CE and the coarse / fine control signal φS applied to the clock signal input terminal CLK to obtain the switch control signal CK5. Output. The inverter 104 inverts the switch control signal CK5 output from the NAND circuit 103 and outputs the switch control signal CK6.

  FIG. 11 is a timing chart showing the operation of the switch control circuit 57. (A) is the calibration instruction signal φRES, (B) is the clock signal φC, (C) is the coarse / fine adjustment control signal φS, and (D) is (E) is a switch control signal φ4, (F) is a switch control signal φ3, (G) is a switch control signal φ2, and (H) is a switch control signal φ1. Show.

  FIG. 12 is a circuit diagram for explaining the operation of the switch control circuit 57, and shows the case where the calibration instruction signal φRES is at the L level. In this case, the outputs of NAND circuits 85-88 are fixed at the H level, so that switch control signals φ4-φ1 are fixed at the L level. As a result, in the switched capacitor circuit 56, the switches 61 to 64 are fixed to OFF, and offset calibration is not executed.

  FIG. 13 is a circuit diagram for explaining the operation of the switch control circuit 57, and shows a case where the calibration instruction signal φRES is at H level and the coarse / fine adjustment control signal φS is at L level. In this case, NAND circuits 85-88 function as inverters for the output signals of NAND circuits 81-84, respectively.

  When clock signal CLK is at H level, the output signal of inverter 74 is at L level and the output signal of NAND circuit 80 is at H level. On the other hand, when the clock signal CLK is at L level, the output signal of the inverter 74 is H level, the output signal of the NOR circuit 89 is L level, the output signal of the inverter 75 is H level, and the output signal of the NAND circuit 80 is L level. Become a level.

  Here, the flip-flop 73 takes in the coarse / fine adjustment control signal φS in synchronization with the output signal of the NAND circuit 82. However, since the coarse / fine adjustment control signal φS is at the L level, the output signal of the flip-flop 73 is Fixed to L level. As a result, the output signals of the NAND circuits 81 and 84 are fixed at the H level, and the switch control signals φ2 and φ3 are fixed at the H level as shown in FIGS.

  When the clock signal φC becomes H level, the output signal of the NAND circuit 80 becomes H level, the output signal of the NAND circuit 82 becomes L level, and when the clock signal φC becomes L level, the output signal of the NAND circuit 80 becomes L level. The output signal of the NAND circuit 82 is at the H level. Accordingly, the switch control signal φ4 is active as shown in FIG. 11E, that is, repeats the H level and the L level.

  When the clock signal φC becomes H level, the output signal of the inverter 75 becomes L level, the output signal of the NAND circuit 83 becomes H level, and when the clock signal φC becomes L level, the output signal of the inverter 75 becomes H level, NAND The output signal of the circuit 83 becomes L level. Therefore, the switch control signal φ1 is active as shown in FIG. 11H, that is, the H level and the L level are repeated so that the H level does not overlap with the switch control signal φ4.

  FIG. 14 is a circuit diagram for explaining the operation of the switch control circuit 57, and shows a case where the calibration instruction signal φRES is at the H level and the coarse / fine adjustment control signal φS is at the H level. In this case, NAND circuits 85-88 function as inverters for the output signals of NAND circuits 81-84, respectively.

  The flip-flop 73 captures the coarse / fine adjustment control signal φS in synchronization with the output signal of the NAND circuit 80. However, since the coarse / fine adjustment control signal φS is at the H level, the output signal of the flip-flop 73 is H Fixed to level. As a result, the NAND circuit 81 functions as an inverter for the output signal of the NAND circuit 80, and the NAND circuit 84 functions as an inverter for the output signal of the inverter 75.

  When the clock signal φC becomes H level, the output signal of the NAND circuit 80 becomes H level, the output signals of the NAND circuits 81 and 82 become L level, and when the clock signal φC becomes L level, the output signal of the NAND circuit 80 becomes The output signals of the L level and NAND circuits 81 and 82 are at the H level. Therefore, the switch control signals φ2 and φ4 are active, that is, in-phase signals that repeat H level and L level, as shown in FIGS. 11 (G) and 11 (E).

  When the clock signal φC becomes H level, the output signal of the inverter 75 becomes L level, the output signals of the NAND circuits 83 and 84 become H level, and when the clock signal φC becomes L level, the output signal of the inverter 75 becomes H level. The output signals of the NAND circuits 83 and 84 are at the L level. Therefore, the switch control signals φ1 and φ3 are active as shown in FIGS. 11H and 11F, that is, the same phase that repeats the H level and the L level so that the H level does not overlap with the switch control signals φ2 and φ4. Signal.

  FIG. 15 is a circuit diagram showing a configuration of the calibration circuit 50. The calibration circuit 50 includes a PMOS transistor 105 for calibration, a switched capacitor circuit 106, and a switch control circuit 107.

  The PMOS transistor 105 outputs a calibration current to the drain side, and has a source connected to the power supply voltage input node 108 and a drain connected to the calibration current output node 109. The power supply voltage input node 108 is connected to the VDD power supply, and the calibration current output node 109 is connected to the node 51.

  In the switched capacitor circuit 106, between the negative feedback node 110 and the gate of the PMOS transistor 105, the switches 111 to 114 each have one node on the negative feedback node 110 side and the other node on the gate side of the PMOS transistor 105. The capacitors 115 to 118 are connected between the other nodes of the switches 111 to 114 and the ground.

  The capacitance value of the capacitor 115 is the same as that of the capacitor 65, the capacitance value of the capacitor 116 is the same as that of the capacitor 66, the capacitance value of the capacitor 117 is the same as that of the capacitor 67, and the capacitance value of the capacitor 118 is the same as that of the capacitor 68. The negative feedback node 110 is connected to the output terminal of the inverter 47.

  The switch 111 is controlled to be turned on and off by a switch control signal φ8. The switch 111 is turned on when the switch control signal φ8 is at an H level and turned off when the switch control signal φ8 is at an L level. The switch 112 is controlled to be turned on and off by the switch control signal φ7. The switch 112 is turned on when the switch control signal φ7 is at the H level and turned off when the switch control signal φ7 is at the L level.

  The switch 113 is controlled to be turned on and off by a switch control signal φ6. The switch 113 is turned on when the switch control signal φ6 is at the H level and turned off when the switch control signal φ6 is at the L level. The switch 114 is controlled to be turned on and off by a switch control signal φ5. The switch 114 is turned on when the switch control signal φ5 is at an H level and turned off when the switch control signal φ5 is at an L level.

  The switch control circuit 107 includes a calibration instruction signal φRES, a coarse adjustment / fine adjustment control signal via a calibration instruction signal input node 119, a coarse / fine adjustment control signal input node 120, a clock signal input node 121, and a power supply voltage input node 108. φS, clock signal φC, and power supply voltage VDD are input to generate switch control signals φ5 to φ8.

  FIG. 16 is a circuit diagram showing a configuration of the switch control circuit 107. The switch control circuit 107 includes a flip-flop 123, inverters 124 to 129, NAND circuits 130 to 138, and a NOR circuit 139. The flip-flop 123 is configured in the same manner as the flip-flop 73.

  FIG. 17 is a timing chart showing the operation of the switch control circuit 107. (A) is the calibration instruction signal φRES, (B) is the clock signal φC, (C) is the coarse / fine adjustment control signal φS, and (D) is (E) is a switch control signal φ8, (F) is a switch control signal φ7, (G) is a switch control signal φ6, and (H) is a switch control signal φ5. Show.

  Since the switch control circuit 107 is configured in the same manner as the switch control circuit 57, the switch control circuit 107 generates a switch control signal φ5 having the same phase as the switch control signal φ1, and generates a switch control signal φ6 having the same phase as the switch control signal φ2. A switch control signal φ7 having the same phase as the control signal φ3 is generated, and a switch control signal φ8 having the same phase as the switch control signal φ4 is generated.

  FIG. 18 is a diagram showing the operation of one embodiment of the voltage comparator of the present invention. In one embodiment of the voltage comparator of the present invention, when the analog input voltage Vip> the analog input voltage Vim and the calibration instruction signal φRES is set to the H level, the current flowing through the PMOS transistor 43> the PMOS transistor 42 in the comparator 1. It becomes the flowing current.

  As a result, when the clock signal φC becomes L level and the switch 48 is turned OFF, the positive feedback by the NMOS transistors 44 and 45 works, the potential of the node 51 decreases, the potential of the node 52 increases, and the inverter 46 outputs. The normal phase comparison determination signal Cop to be output is at the H level, and the negative phase comparison determination signal Com output from the inverter 47 is at the L level.

  Thus, when the negative phase comparison determination signal Com becomes L level, in the coarse / fine adjustment control circuit 2, the output S22 of the flip-flop 22 is L level, the output S23 of the flip-flop 23 is L level, and the output of the EOR circuit 24 S24 becomes L level, and the coarse / fine adjustment control signal φS becomes L level.

  As a result, the switch control circuit 57 of the calibration circuit 49 activates the switch control signals φ1 and φ4, fixes the switch control signals φ2 and φ3 to the H level, and the switch control circuit 107 of the calibration circuit 50 The control signals φ5 and φ8 are activated, and the switch control signals φ6 and φ7 are fixed at the H level.

  As a result, in the calibration circuit 49, the switches 62 and 63 are fixed to ON, and the switches 61 and 64 repeat ON and OFF operations alternately. In the calibration circuit 50, the switches 112 and 113 are fixed to ON, and the switches 111 and 114 repeat ON and OFF operations alternately.

  Therefore, in this case, the calibration circuit 49 uses the capacitors 65 to 67 in parallel connection, and the calibration circuit 50 uses the capacitors 115 to 117 in parallel connection. , 50 has a low accuracy. That is, in this case, the calibration circuits 49 and 50 execute offset calibration by coarse adjustment for the analog input voltages Vip and Vim.

  The calibration circuits 49 and 50 are configured so that the analog input voltage Vip, while the level of the output signal S22 of the flip-flop 22 and the level of the output signal S23 of the flip-flop 23 in the coarse / fine control circuit 2 are L level. Continue offset calibration with coarse adjustment for Vim.

  Here, the capacitance value of the capacitors 65 and 115 is C4, the capacitance value of the capacitors 66 and 116 is C3, the capacitance value of the capacitors 67 and 117 is C2, the capacitance value of the capacitors 68 and 118 is C1, and the positive phase comparison determination signal Cop The voltage is Vop, the voltage of the negative phase comparison determination signal Com is Vom, the gate voltage of the PMOS transistor 55 is Vg55, and the gate voltage of the PMOS transistor 105 is Vg105.

  Then, during offset calibration by coarse adjustment, the feedback amount ΔV55 of the voltage Vop of the normal phase comparison determination signal Cop to the gate of the PMOS transistor 55 is ΔV55 = (C4 + C3 + C2) (Vop−Vg55) / (C4 + C3 + C2 + C1) and vice versa. The feedback amount ΔV105 of the voltage Vom of the phase comparison determination signal Com to the gate of the PMOS transistor 105 is ΔV105 = (C4 + C3 + C2) (Vom−Vg105) / (C4 + C3 + C2 + C1).

  Thereafter, as a result of offset calibration by coarse adjustment, the current flowing through the PMOS transistor 55 decreases and the current flowing through the PMOS transistor 105 increases in the comparator 1, so that the potential of the node 51 rises and the potential of the node 52 increases. Descends. As a result, the normal phase comparison determination signal Cop is inverted from the H level to the L level, and the negative phase comparison determination signal Com is inverted from the L level to the H level.

  As described above, when the negative phase comparison determination signal Com becomes H level, the output S22 of the flip-flop 22 becomes H level in the coarse / fine adjustment control circuit 2, but at this time, the output signal S23 of the flip-flop 23 becomes high. Is at the L level, the output signal S24 of the EOR circuit 24 is at the H level, the flip-flop 25 takes in the H level signal output from the EOR circuit 24, and sets the coarse / fine adjustment control signal φS to the H level.

  As a result, in the calibration circuit 49, the switch control signals φ1 to φ4 become active, and the switches 61 to 64 repeat the ON and OFF operations so that the adjacent switches are not simultaneously turned ON. The switch control signals φ5 to φ8 are activated, and the switches 111 to 114 are repeatedly turned on and off so that adjacent switches are not turned on at the same time.

  Accordingly, since the charge transfer in the switched capacitor circuits 56 and 106 is fine, the negative feedback in the calibration circuits 49 and 50 is highly accurate. That is, in this case, the calibration circuits 49 and 50 execute offset calibration by fine adjustment on the analog input voltages Vip and Vim.

  Here, at the time of offset calibration by fine adjustment, the feedback amount ΔV55 of the voltage Vop of the positive phase comparison determination signal Cop to the gate of the PMOS transistor 55 is ΔV55 = C4 × C3 × C2 (Vop−Vg55) / {(C4 + C3). (C3 + C2) (C2 + C1)}, and the feedback amount ΔV105 of the voltage Vom of the negative phase comparison determination signal Com to the gate of the PMOS transistor 105 is ΔV105 = C4 × C3 × C2 × (Vom−Vg105) / {(C4 + C3) ( C3 + C2) (C2 + C1)}.

  When the offset calibration is executed for a certain time, the gate voltage Vg55 of the PMOS transistor 55 converges to a substantially constant value, and the gate voltage Vg105 of the PMOS transistor 105 converges to a substantially constant value. When the L level is set, the switch control circuit 57 fixes the switch control signals φ1 to φ4 to the L level, and the switch control circuit 107 fixes the switch control signals φ5 to φ8 to the L level.

  As a result, the offset calibration is completed, and the comparator 1 cancels the offset and stores the threshold voltage of the comparator 1 itself by the accumulated charges of the capacitors 68 and 118. Therefore, after that, the comparison operation can be performed on the analog input voltage in a state where the offset is canceled.

  FIG. 19 is a diagram showing a change in the gate voltage Vg105 of the PMOS transistor 105 in the calibration circuit 50 when the analog input voltage Vip> the analog input voltage Vim and the calibration instruction signal φRES is at the H level. However, C1: C2: C3: C4 = 100: 5: 10: 1.

  Here, assuming that the cycle in which the gate voltages Vg55 and Vg105 of the PMOS transistors 55 and 105 are converted is a conversion cycle, in the example shown in FIG. 19, offset calibration by coarse adjustment is executed up to 7 conversion cycles. As a result of the offset calibration by the coarse adjustment, the logic of the negative phase comparison determination signal Com is inverted, and the calibration mode is switched to the offset calibration by the fine adjustment.

  As described above, in the embodiment of the voltage comparator of the present invention, when the analog input voltage Vip> the analog input voltage Vim and the calibration instruction signal φRES is set to the H level, the same as in the normal comparison operation. The offset calibration of the comparator 1 can be executed at the timing.

  Moreover, while the negative phase comparison determination signal Com is at the L level, the calibration accuracy is not relatively high, but the calibration operation is relatively fast, so that offset calibration by so-called coarse adjustment can be executed, and the negative phase comparison It is possible to perform at high speed until the determination signal Com is inverted to the H level.

  When the negative phase comparison determination signal Com is inverted to the H level, the calibration operation is not relatively fast thereafter regardless of the logic inversion of the negative phase comparison determination signal Com, but the calibration accuracy is relatively high. High offset calibration by so-called fine adjustment can be executed.

  Therefore, according to an embodiment of the voltage comparator of the present invention, the offset calibration of the comparator 1 can be realized with high accuracy without sacrificing the calibration period. That is, high-precision offset calibration can be performed in a short time by performing offset calibration by coarse adjustment at high speed and thereafter performing offset calibration by fine adjustment. Further, when a plurality of cycles of feedback are continuously executed, it is possible to perform correction with a wide range and high accuracy with respect to fluctuation due to leakage or the like.

It is a circuit diagram which shows the principal part of one Embodiment of the voltage comparator of this invention. It is a circuit diagram which shows the structure of the flip-flop with which one Embodiment of the voltage comparator of this invention is provided. 5 is a timing chart showing comparison operation timing and reset operation timing of a comparator and fetch operation timing of a flip-flop in an embodiment of the voltage comparator of the present invention. It is a circuit diagram which shows the structure of the rough adjustment / fine adjustment control circuit with which one Embodiment of the voltage comparator of this invention is provided. It is a circuit diagram which shows the structure of the flip-flop in the coarse / fine adjustment control circuit with which one Embodiment of the voltage comparator of this invention is provided. It is a timing chart which shows operation | movement of the coarse / fine adjustment control circuit with which one Embodiment of the voltage comparator of this invention is provided. It is a circuit diagram which shows the structure of the comparator with which one Embodiment of the voltage comparator of this invention is provided. It is a circuit diagram which shows the structure of one calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided. It is a circuit diagram which shows the structure of the switch control circuit with which one calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided. It is a circuit diagram which shows the structure of the flip-flop in the switch control circuit with which one calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided. It is a timing chart which shows operation | movement of the switch control circuit with which one calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided is provided. It is a circuit diagram for demonstrating operation | movement of the switch control circuit with which one calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided. It is a circuit diagram for demonstrating operation | movement of the switch control circuit with which one calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided. It is a circuit diagram for demonstrating operation | movement of the switch control circuit with which one calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided. It is a circuit diagram which shows the structure of the other calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided. It is a circuit diagram which shows the structure of the switch control circuit with which the other calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided is provided. It is a timing chart which shows operation | movement of the switch control circuit with which the other calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided is provided. It is a figure which shows operation | movement of one Embodiment of the voltage comparator of this invention. It is a figure which shows the change of the gate voltage of the PMOS transistor with which the other calibration circuit in the comparator with which one Embodiment of the voltage comparator of this invention is provided is provided.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... One Embodiment of the comparator of this invention 2 ... Coarse / Fine control circuit 3, 4 ... Flip-flop 7 ... Capture part 8 ... Capture control part 9-14 ... Inverter 15-18 ... Switch 19, 20 ... Inverter 22, DESCRIPTION OF SYMBOLS 23 ... Flip flop 24 ... EOR (exclusive OR) circuit 25 ... Flip flop 27 ... Capture part 28 ... Capture control part 29-33 ... Inverter 34 ... NAND circuit 35-38 ... Switch 39, 40 ... Inverter 42, 43 ... PMOS transistor 44, 45 ... NMOS transistor 46, 47 ... inverter 48 ... switch 49, 50 ... one embodiment of calibration circuit of the present invention 51, 52 ... node 55, 105 ... PMOS transistor 56, 106 ... switched capacitor circuit 57, 107: Switch control circuit 58, 108 ... power supply voltage input node 59, 109 ... calibration current output node 60, 110 ... negative feedback node 61-64, 111-114 ... switch 65-68, 115-118 ... capacitor 69, 119 ... calibration Instruction signal input nodes 70, 120 ... coarse / fine adjustment control signal input nodes 71, 121 ... clock signal input nodes 73, 123 ... flip-flops 74-79, 124-129 ... inverters 80-88, 130-138 ... NAND circuit 89 139: NOR circuit

Claims (4)

A plurality of switches connected in series between the first connection point and the second connection point, and a plurality of switches connected between the node on the second connection point side of each of the plurality of switches and the power source A switched capacitor circuit having a capacitor of
A switch control circuit for controlling the plurality of switches,
In the first mode, the switch control circuit turns on a predetermined switch among the plurality of switches, and prevents the adjacent switches in the remaining switches other than the predetermined switch from being turned on at the same time. The switch is repeatedly turned on and off, and in the second mode, the plurality of switches are repeatedly turned on and off so that adjacent switches in the plurality of switches are not turned on at the same time. A capacitor control circuit that turns off the plurality of switches. A calibration transistor having a source connected to the third connection point and a drain connected to the fourth connection point;
A calibration circuit comprising: the capacitor circuit according to claim 1, wherein the first connection point is connected to a fifth connection point, and the second connection point is connected to a gate of the calibration transistor. . A first transistor of a first conductivity type having a gate connected to a first analog voltage input terminal and a source connected to a first power supply;
A first conductivity type second transistor having a gate connected to a second analog voltage input terminal and a source connected to the first power supply;
A third transistor of the second conductivity type having a drain connected to the drain of the first transistor, a gate connected to the drain of the second transistor, and a source connected to a second power source;
At least a fourth transistor of the second conductivity type having a drain connected to the drain of the second transistor, a gate connected to the drain of the first transistor, and a source connected to the second power supply;
A first inverter having an input terminal connected to either the drain of the first transistor or the drain of the third transistor, and an output terminal connected to the first comparison determination signal output terminal;
A second inverter having an input terminal connected to either the drain of the second transistor or the drain of the fourth transistor and an output terminal connected to a second comparison determination signal output terminal;
The third connection point is connected to the source of the first transistor, the fourth connection point is connected to the drain of the first transistor, and the fifth connection point is connected to the second comparison determination signal. A calibration circuit according to claim 2 connected to an output terminal;
The third connection point is connected to the source of the second transistor, the fourth connection point is connected to the drain of the second transistor, and the fifth connection point is connected to the first comparison determination signal. A comparator comprising the calibration circuit according to claim 2 connected to an output terminal. A comparator according to claim 3;
The comparator according to claim 3 monitors the logic of the comparison determination signal output to the second comparison determination signal output terminal, and at the start of calibration, the comparator according to claim 3 is set to the first mode. Thereafter, when the logic of the comparison determination signal is inverted, a control circuit is provided for setting the comparator according to claim 3 to the second mode.

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