JP4843586B2 - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  A nonvolatile semiconductor memory (EEPROM) that is electrically rewritable using a memory cell having a stacked gate structure in which a floating gate and a control gate are stacked is known. In this type of EEPROM, a tunnel insulating film is used as the first gate insulating film between the floating gate and the semiconductor substrate, and silicon oxide is usually used as the second gate insulating film between the floating gate and the control gate. An ONO film which is a laminated structure film of film (O) / silicon nitride film (N) / silicon oxide film (O) is used.

  Each memory cell is formed in an element formation region partitioned by an element isolation insulating film. In general, the floating gate electrode film is separated in the direction of the control gate line (word line) by slitting the element isolation insulating film. At this stage of slit processing, floating gate isolation in the bit line direction is not performed. A control gate electrode film is deposited on the entire surface of the substrate including the slit processed floating gate electrode film via the ONO film, and the control gate electrode film, the ONO film, and the floating gate electrode film are sequentially etched to form a bit. The control gate and the floating gate are separated in the line direction. Thereafter, source and drain diffusion layers are formed in a self-aligned manner on the control gate.

  In the conventional EEPROM structure described above, the floating gates of the memory cells adjacent in the word line direction are isolated on the element isolation insulating film, but the ONO film formed thereon is continuously disposed in the word line direction. The In this structure, when the memory cell is miniaturized and the separation width (slit width) of the floating gate in the word line direction is narrowed, charge movement may occur through the ONO film when the charge storage states of adjacent floating gates are different. It has become clear. This is because the charge easily moves in the lateral direction on the silicon nitride film of the ONO film or the interface between the silicon nitride film and the silicon oxide film. Therefore, in a miniaturized EEPROM, when memory cells adjacent in the word line direction are in different data states, threshold fluctuations occur due to charge movement, and data destruction may occur in some cases.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a nonvolatile semiconductor memory device and a method for manufacturing the same, which can prevent data destruction due to charge transfer between floating gates and improve reliability. Yes.

  A nonvolatile semiconductor memory device according to an embodiment of the present invention is an element isolation insulating film that separates a semiconductor substrate and an element formation region of the semiconductor substrate, and an upper end portion is higher than an upper surface of the semiconductor substrate. An element isolation insulating film having a recess at an upper end, and a first gate electrode material film formed in the element formation region via a first gate insulating film, the height of the upper surface being the element isolation A first gate electrode material film formed between the upper end of the insulating film and the bottom of the recess, and a second gate electrode material film formed on the first gate electrode material film. And a second gate electrode material film separated from an adjacent second gate electrode material film on the element isolation insulating film, the height of the upper surface being higher than the height of the upper end portion of the element isolation insulating film, The concave portion is formed on the second gate electrode material film. A second gate insulating film formed over the inner surface of, and having a second of the third gate electrode material film formed on the gate insulating film.

  A nonvolatile semiconductor memory device according to another embodiment of the present invention is an element isolation insulating film that separates a semiconductor substrate and an element formation region of the semiconductor substrate, and the height of the upper end portion is higher than that of the upper surface of the semiconductor substrate. An element isolation insulating film having an upper surface and an inclined surface on the upper side, and a recess having a bottom height lower than the lower end of the inclined surface formed on the upper end; and a first gate insulating film in the element formation region, respectively A floating gate formed above the element isolation insulating film, the height of the upper surface being higher than the height of the upper end portion of the element isolation insulating film, and a floating gate separated from an adjacent floating gate on the element isolation insulating film, A second gate insulating film formed from the floating gate to the inner surface of the recess, and a control gate formed on the second gate insulating film.

  A nonvolatile semiconductor memory device according to still another embodiment of the present invention is an element isolation insulating film that separates a semiconductor substrate and an element formation region of the semiconductor substrate, and the height of the upper end portion is the upper surface of the semiconductor substrate. A higher element isolation insulating film and a floating gate formed in each of the element formation regions via a first gate insulating film, the height of the upper surface being higher than the height of the upper end portion of the element isolation insulating film; A floating gate separated from an adjacent floating gate on the element isolation insulating film, and formed at the upper end of the element isolation insulating film such that the bottom has the same height as the lower surface of the floating gate. It has a recess, a second gate insulating film formed from the floating gate to the inner surface of the recess, and a control gate formed on the second gate insulating film.

  A method for manufacturing a nonvolatile semiconductor memory device according to still another embodiment of the present invention includes a step of sequentially depositing a first insulating film and a first gate electrode material film on a semiconductor substrate, and the first gate electrode. A step of sequentially etching the material film, the first insulating film, and the semiconductor substrate to form an element isolation groove; and an upper surface height of the element isolation groove is a height of the upper surface of the first gate electrode material film. A step of forming an element isolation insulating film so as to be higher, a step of depositing a second gate electrode material film on the first gate electrode material film and on the element isolation insulating film, and the second Separating the gate electrode material film on the element isolation insulating film, and forming a recess in the element isolation insulating film whose bottom is lower than the upper surface of the first gate electrode material; and the second gate electrode material film Top and inside of the recess Forming a second insulating film, depositing a third gate electrode material film on the second insulating film, the third gate electrode material film, the second gate insulating film, The gate electrode material film 2 and the first gate electrode material film are sequentially etched to pattern the floating gate made of the first and second gate electrode material films and the control gate made of the third gate electrode material film. And a step of forming a source / drain diffusion layer self-aligned with the control gate.

  According to the present invention, it is possible to provide a nonvolatile semiconductor memory device and a method for manufacturing the same, in which data destruction due to charge transfer between floating gates is prevented and reliability is improved.

  Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1]
FIG. 1 is a layout of a cell array of a NAND type EEPROM according to the first embodiment of the present invention, and FIGS. 2 (a) and 2 (b) are sectional views taken along lines AA 'and BB' in FIG. 1, respectively.

  The memory cell array is formed in the p-type well of the silicon substrate 1. In the silicon substrate 1, an element isolation groove 3 is formed, and an element isolation insulating film 4 is embedded therein, and a stripe-shaped element formation region 2 is partitioned by the element isolation insulating film 3.

  A floating gate 6 is formed in each element formation region 2 via a first gate insulating film 5 which is a tunnel insulating film. The floating gate 6 includes a first polycrystalline silicon (or amorphous silicon) film 6a formed before element isolation and a second polycrystalline silicon (or amorphous silicon) film 6b formed after element isolation. The two-layer structure is separated for each memory cell. A control gate 8 is formed on the floating gate 6 via a second gate insulating film 7. The control gate 8 has a two-layer structure of a polycrystalline silicon (or amorphous silicon) film 8a and a tungsten silicide (WSi) film 8b. The control gate 8 is continuously patterned across the plurality of element formation regions 2 in the cross section of FIG. 2A, which becomes the word line WL.

  The second gate insulating film 7 between the floating gate 6 and the control gate 8 is an ONO film. In this embodiment, the second gate insulating film 7 is arranged on the element isolation insulating film 4 so as to be arranged only on each floating gate 6 in the word line WL direction shown in the cross section of FIG. The slits 13 are separated. Accordingly, a silicon oxide film 9 is formed on the side surface of the floating gate 6, thereby separating it from the control gate 8. Source / drain diffusion layers 12 are formed in the control gate 8 in a self-aligning manner, and a NAND cell unit in which a plurality of memory cells are connected in series is configured.

  A selection gate 13 formed simultaneously with the control gate 8 is disposed on one drain side of the NAND cell unit, and a bit line (BL) 11 is connected to the drain diffusion layer. The selection gate 13 portion has a stacked gate structure similar to the gate portion of the memory cell, but the first-layer gate electrode material film is not separated as a floating gate, but the two layers are integrally short-circuited at a predetermined location as a selection gate. 13 Further, the first gate insulating film 5 'of the select gate 13 is formed thicker than that of the memory cell region. Although the other end source side of the NAND cell unit is not shown, it is configured similarly to the drain side.

  3A, 3B, 8A, and 8B, which are process cross-sectional views corresponding to the cross sections of FIGS. 2A and 2B, show the specific manufacturing process of the EEPROM according to this embodiment. The description will be given with reference.

  As shown in FIGS. 3A and 3B, a silicon oxide film having a thickness of 10 nm is first formed on the silicon substrate 1 as the first gate insulating film 5, and a first film having a thickness of 60 nm, which is a gate electrode material film, is formed thereon. The polycrystalline silicon film 6a is deposited, and a mask material 21 for element isolation processing is further deposited. Note that a thicker gate insulating film 5 ′ is formed in the select gate transistor region than in the cell transistor region. The mask material 21 is a laminated film of a silicon nitride film and a silicon oxide film. The mask material 21 is patterned so as to remain on the element formation region, and the polycrystalline silicon film 6a and the first gate insulating films 5 and 5 ′ are etched using the mask material 21, and the substrate 1 is further etched. A separation groove 3 is formed.

  Thereafter, heating is performed at 1000 ° C. in an O 2 atmosphere, and a silicon oxide film 22 of about 6 nm is formed on the inner wall of the element isolation trench 3 as shown in FIGS. Subsequently, a silicon oxide film is deposited by plasma CVD, and is flattened by CMP processing to be embedded as an element isolation insulating film 4 in the element isolation trench 3. Then, after performing a heat treatment at 900 ° C. in a nitrogen atmosphere at 900 ° C., the mask material 21 is removed. The removal of the silicon nitride film is performed by phosphoric acid treatment at 150 ° C.

  Thereafter, as shown in FIGS. 5A and 5B, a second polycrystalline silicon film 6b doped with phosphorus is deposited as a gate electrode material film by a low pressure CVD method. Subsequently, a second gate insulating film is formed. An ONO film to be the film 7 is deposited. Then, using the resist pattern having an opening on the element isolation insulating film 4 as a mask, the second gate insulating film 7 and the second polycrystalline silicon film 6b are etched by RIE, as shown in FIGS. ), A slit 13 for separating the floating gate 6 on the element isolation insulating film 4 is formed. The slit 13 has a length extending over a plurality of memory cells in the NAND cell unit. The second gate insulating film 7 is also different from the conventional one in that it is simultaneously separated by the slit 13 on the element isolation insulating film 4.

  The side surface of the polycrystalline silicon film 6b exposed by the processing of the slit 13 is protected by forming a silicon oxide film 9 by heating at 1000 ° C. in an O 2 atmosphere. Thereafter, as shown in FIGS. 7A and 7B, a polycrystalline silicon film 8a doped with phosphorus is deposited as a gate electrode material film by a CVD method, and a WSi film 8b is subsequently deposited thereon.

  Next, a resist pattern is formed, and the WSi film 8b, the polycrystalline silicon film 8a, the gate insulating film 7, the polycrystalline silicon films 6b and 6a, and the gate insulating film 5 are sequentially etched by RIE, so that FIG. As shown in b), the control gate 8 is patterned as a continuous word line WL, and the floating gate 6 is separated for each memory cell in the bit line direction. Then, ion implantation is performed to form the source and drain diffusion layers 12 of each memory cell self-aligned with the control gate 8.

  Note that the selection gate line SG is continuously patterned integrally with the upper gate electrode material films 8a and 8b without separating the lower gate electrode material films 6a and 6b on the element isolation insulating film 4. After that, as shown in FIGS. 2A and 2B, an interlayer insulating film 10 is deposited, and contact holes are formed to pattern the bit lines 11.

  As described above, according to this embodiment, the second gate electrode material film made of the ONO film on the floating gate 6 is isolated on the element isolation insulating film 4 simultaneously with the floating gate 6. Therefore, even when the floating gates of adjacent memory cells are close to each other, charge leakage does not occur and data retention characteristics are excellent.

[Embodiment 2]
9A and 9B to FIG. 12A and FIG. 12B show manufacturing steps of another embodiment. Portions corresponding to those of the previous embodiment are denoted by the same reference numerals as those of the previous embodiment, and detailed description thereof is omitted. Also in this embodiment, the second gate insulating film 7 made of the ONO film on the floating gate 6 is separated on the element isolation insulating film 4, but the process is different from the previous embodiment.

  Up to FIGS. 5A and 5B, steps similar to those in the previous embodiment are taken. Thereafter, as shown in FIGS. 9A and 9B, a silicon oxide film 31 is deposited on the second gate insulating film 7, and a slit processing opening 13 ′ is formed on the element isolation insulating film 4. Open. Further, a silicon oxide film 32 is deposited. Then, etch back is performed to leave the silicon oxide film 32 as a side spacer in the opening 13 'as shown in FIGS. In this state, the second gate insulating film 7 and the polycrystalline silicon film 6b are etched by RIE using the silicon oxide films 31 and 32 as a mask. Thus, as in the previous embodiment, the slit 13 for separating the second gate insulating film 7 and the polycrystalline silicon film 6b is processed on the element isolation insulating film 4.

  Thereafter, after the silicon oxide films 31 and 32 are removed by HF, as shown in FIGS. 11A and 11B, a silicon oxide film 33 is deposited on the entire surface by a low pressure CVD method. After being deposited, the silicon oxide film 33 is heated at 1000 ° C. in an O 2 atmosphere to form a dense oxide film free from charge transfer. This silicon oxide film 33 becomes a gate insulating film together with the second gate insulating film 7, and also becomes an insulating film for protecting the side surface of the polycrystalline silicon film 6b.

  Thereafter, as shown in FIGS. 12A and 12B, a polycrystalline silicon film 8a and a WSi film 8b are sequentially deposited, and then patterned in the same manner as in the previous embodiment, so that the control gate 6 and The floating gate 6 is formed, and the source / drain diffusion layer 12 is formed. Also in this embodiment, as in the previous embodiment, the gate insulating film 7 made of the ONO film on the floating gate 6 is cut and separated in the element isolation region. Therefore, excellent data retention characteristics can be obtained.

[Embodiment 3]
FIGS. 13A and 13B to 16A and 16B show the manufacturing steps of still another embodiment. In the previous embodiment, as shown in FIGS. 5A and 5B, the second-layer polycrystalline silicon film 6b and the second gate insulating film 7 are continuously deposited. On the other hand, in this embodiment, as shown in FIGS. 13A and 13B, before the second gate insulating film 7 is deposited on the second-layer polycrystalline silicon film 6b, element isolation insulation is performed. A slit 13 is formed on the membrane 4 for separation. Thereafter, a second gate insulating film 7 is deposited.

  Then, a register pattern (not shown) having the same opening as the slit 13 is formed on the second gate insulating film 6b, and the second gate insulating film 6b is etched by RIE, so that FIG. As shown in b), the slit 13 is separated. Thereafter, as in the previous embodiment, as shown in FIGS. 15A and 15B, a polycrystalline silicon film 8a doped with phosphorus is deposited as a gate electrode material film by a CVD method. Then, a WSi film 8b is deposited.

  Next, a resist pattern is formed, and the WSi film 8b, the polycrystalline silicon film 8a, the gate insulating film 7, the polycrystalline silicon films 6b and 6a, and the gate insulating film 5 are sequentially etched by RIE, so that FIG. As shown in b), the control gate 8 is patterned as a continuous word line WL, and the floating gate 6 is separated for each memory cell in the bit line direction. Then, ion implantation is performed to form the source and drain diffusion layers 12 of each memory cell self-aligned with the control gate 8. Also in this embodiment, since the second gate insulating film 7 on the floating gate 6 is isolated on the element isolation insulating film 4, excellent data retention characteristics can be obtained as in the previous embodiment.

[Embodiment 4]
In the embodiment so far, the second gate insulating film 7 is cut and separated on the element isolation insulating film 4, but in this embodiment, a substantially equivalent effect is obtained without performing cutting and separation. It is. The cross-sectional structure of the cell array in this embodiment is shown in FIGS. 17 (a) and 17 (b) corresponding to FIGS. 2 (a) and 2 (b).

17A and 17B is different from FIGS. 2A and 2B in that the slit 13 for separating the floating gate 6 on the element isolation insulating film 4 is processed by the second gate insulating film 7. The recess 41 is formed by performing recess etching on the element isolation insulating film 4 at the same time. Therefore, the second gate insulating film 7 is disposed along a recess formed on the surface of the element isolation insulating film 4.

  As shown in FIG. 17A, when the width of the slit 13 and thus the width of the recess 41 formed in the element isolation insulating film 4 is a and the depth of the recess 41 is b, the interval between the adjacent floating gates 6 is In effect, a + 2b. By setting this interval to a value at which charge transfer between floating gates can be ignored, excellent data retention characteristics can be obtained as in the previous embodiments.

  A specific manufacturing process of this embodiment will be described with reference to FIGS. 18 to 25, focusing on the cross section of FIG. As shown in FIG. 18, a silicon oxide film of about 8 nm is formed as a first gate insulating film 5 on a silicon substrate 1, and a first polycrystalline silicon film 6a of about 60 nm is deposited thereon by low pressure CVD. . Subsequently, a 150 nm silicon nitride film 21a and a 165 nm silicon oxide film 21b are deposited by low pressure CVD.

  Thereafter, after performing a hydrogen combustion oxidation process at 850 ° C. for 30 minutes, a register pattern is formed by lithography so as to cover the element isolation region, and the silicon oxide film 21b and the silicon nitride film 21a are etched by RIE to form a mask material. Form a pattern. Using this mask material, the polycrystalline silicon film 6a and the gate insulating film 5 are etched by RIE, and the silicon substrate 1 is further etched to form the element isolation trench 3. Thereby, the stripe-shaped element formation region 2 is partitioned.

  Subsequently, after forming a thermal oxide film on the sidewall of the element isolation trench 3, a silicon oxide film 4 is deposited by plasma CVD, and planarized by CMP treatment, as shown in FIG. Embed in. The silicon oxide film 21b is removed with buffered hydrofluoric acid, and the silicon nitride film 21a is further removed by phosphoric acid treatment at 150 ° C. for 30 minutes to obtain the state of FIG.

  Thereafter, as shown in FIG. 21, a second polycrystalline silicon film 6b having a thickness of 100 nm is deposited by a low pressure CVD method. Subsequently, as shown in FIG. 22, a silicon oxide film 42 is deposited to a thickness of about 230 nm by a low pressure CVD method, and a slit processing opening 13 'is formed thereon through lithography and RIE processes. Further, as shown in FIG. 23, a silicon oxide film 43 having a thickness of about 70 nm is deposited by low pressure CVD, and etched back to leave only side walls of the openings 13 'as side spacers.

  Subsequently, using the silicon oxide films 42 and 43 as a mask, the polycrystalline silicon film 6b is etched by RIE to process the slits 13 for separating the floating gate as shown in FIG. Further, the surface of the element isolation insulating film 4 is etched by the RIE method having a large selection ratio with respect to polycrystalline silicon, thereby forming a recess 41 in the element isolation insulating film 4 with the same width as the slit 13.

  Thereafter, the silicon oxide films 42 and 43 are removed by O 2 plasma and HF treatment, and then a second gate insulating film 7 made of 17 nm ONO film is deposited as shown in FIG. A third polycrystalline silicon film 8a and a 50 nm WSi film 8b are sequentially deposited by plasma CVD. Hereinafter, although not shown, the gate portions of the memory cells are separated and the source and drain diffusion layers are formed through the same steps as in the previous embodiment.

  FIG. 26 shows the correlation between the width of the slit separating adjacent floating gates and the number of defective bits generated by charge transfer between the floating gates. The arrows in the figure indicate the range of variation in the number of defective bits, and the curve connects the average values. It can be seen that when the memory cell is miniaturized and densified and the slit width is reduced to 0.14 μm or less, the number of defective bits is extremely increased. According to this embodiment, the substantial slit width can be set to a + 2b by the depth b of the recess of the element isolation insulating film 4 with respect to the slit width a on the plane. Specifically, in the 256 Mbit NAND type EEPROM, when the specification of the number of defective bits is 2 bits / chip, the slit width needs to be at least 0.14 μm. Therefore, in this embodiment, this specification can be satisfied by processing the recess 41 so as to satisfy a + 2b> 0.14 [μm].

  As described above, in the EEPROM according to the embodiment of the present invention, the second gate insulating film between the floating gate and the control gate is placed on the element isolation insulating film between adjacent memory cells with the element isolation insulating film interposed therebetween. Therefore, charge transfer between adjacent floating gates is prevented. Alternatively, even if the second gate insulating film is not completely separated on the element isolation film, a recess is processed on the surface of the element isolation insulating film so that the second gate insulating film continues along the recess. As a result, the distance between adjacent floating gates is substantially increased, and charge transfer between adjacent floating gates is prevented. Therefore, even when the memory cell is miniaturized, data destruction due to charge transfer is prevented.

1 is a layout of an EEPROM memory cell array according to Embodiment 1 of the present invention; It is A-A 'and B-B' sectional drawing of FIG. FIG. 10 is a manufacturing process sectional view of the first embodiment. FIG. 10 is a manufacturing process sectional view of the first embodiment. FIG. 10 is a manufacturing process sectional view of the first embodiment. FIG. 10 is a manufacturing process sectional view of the first embodiment. FIG. 10 is a manufacturing process sectional view of the first embodiment. FIG. 10 is a manufacturing process sectional view of the first embodiment. It is manufacturing process sectional drawing of Embodiment 2 of this invention. It is manufacturing process sectional drawing of the same Embodiment 2. It is manufacturing process sectional drawing of the same Embodiment 2. It is manufacturing process sectional drawing of the same Embodiment 2. It is manufacturing process sectional drawing of Embodiment 3 of this invention. It is manufacturing process sectional drawing of the same Embodiment 3. It is manufacturing process sectional drawing of the same Embodiment 3. It is manufacturing process sectional drawing of the same Embodiment 3. It is sectional drawing corresponding to FIG. 2 (a) (b) of EEPROM by Embodiment 4 of this invention. It is manufacturing process sectional drawing of the same Embodiment 4. It is manufacturing process sectional drawing of the same Embodiment 4. It is manufacturing process sectional drawing of the same Embodiment 4. It is manufacturing process sectional drawing of the same Embodiment 4. It is manufacturing process sectional drawing of the same Embodiment 4. It is manufacturing process sectional drawing of the same Embodiment 4. It is manufacturing process sectional drawing of the same Embodiment 4. It is manufacturing process sectional drawing of the same Embodiment 4. It is a figure which shows the correlation of the number of defective bits and slit width for demonstrating the effect of the same Embodiment 4. FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element formation area, 3 ... Element isolation groove, 4 ... Element isolation insulating film, 5 ... 1st gate insulating film, 6 ... Floating gate, 7 ... 2nd gate insulating film, 8 ... Control Gate: 9 ... Silicon oxide film, 10 ... Interlayer insulating film, 11 ... Bit line, 12 ... Source, drain diffusion layer, 13 ... Slit.

Claims (4)

A semiconductor substrate;
An element isolation insulating film for isolating an element formation region of the semiconductor substrate, the height of the upper end portion being higher than the upper surface of the semiconductor substrate, and an element isolation insulating film having a recess at the upper end portion;
A first gate electrode material film formed in the element formation region via a first gate insulating film, the height of the upper surface being between the upper end of the element isolation insulating film and the bottom of the recess; A first gate electrode material film formed to be positioned;
A second gate electrode material film formed on the first gate electrode material film, wherein the height of the upper surface is higher than the height of the upper end portion of the element isolation insulating film, and is adjacent on the element isolation insulating film; A second gate electrode material film separated from the second gate electrode material film,
A second gate insulating film formed along the recess from above the second gate electrode material film;
Possess a second of the third gate electrode material film formed on the gate insulating film,
A floating gate is formed by the first gate electrode material film and the second gate electrode material film,
The floating gate is not formed in the recess,
In the recess, the second gate insulating film and the element isolation insulating film are in contact with each other . A semiconductor substrate;
An element isolation insulating film for isolating an element formation region of the semiconductor substrate, wherein the upper end portion is higher than the upper surface of the semiconductor substrate, has an inclined surface at the upper part of the side surface, and the bottom portion has the inclined surface. An element isolation insulating film in which a recess lower than the lower end of the upper end is formed;
A floating gate formed in each of the element formation regions via a first gate insulating film, the height of the upper surface being higher than the height of the upper end of the element isolation insulating film, and adjacent to the element isolation insulating film Floating gate separated from the floating gate,
A second gate insulating film formed along the recess from above the floating gate;
Possess a second control gate formed on the gate insulating film,
The floating gate is not formed in the recess,
In the recess, the second gate insulating film and the element isolation insulating film are in contact with each other.
The nonvolatile semiconductor memory device characterized by there. A semiconductor substrate;
An element isolation insulating film for isolating the element formation region of the semiconductor substrate, wherein the upper end portion has a height higher than that of the upper surface of the semiconductor substrate;
A floating gate formed in each of the element formation regions via a first gate insulating film, the height of the upper surface being higher than the height of the upper end of the element isolation insulating film, and adjacent to the element isolation insulating film Floating gate separated from the floating gate ,
A recess formed in the upper portion of the front Symbol isolation insulating film,
A second gate insulating film formed along the recess from above the floating gate;
A control gate formed on the second gate insulating film,
The floating gate is not formed in the recess,
In the recess, the second gate insulating film and the element isolation insulating film are in contact with each other.
The nonvolatile semiconductor memory device characterized by there. Sequentially depositing a first insulating film and a first gate electrode material film on a semiconductor substrate;
Etching the first gate electrode material film, the first insulating film, and the semiconductor substrate sequentially to form an element isolation trench;
Forming an element isolation insulating film in the element isolation trench such that the height of the upper surface is higher than the height of the upper surface of the first gate electrode material film;
Depositing a second gate electrode material film on the first gate electrode material film and on the element isolation insulating film;
The second gate electrode material film is separated on the element isolation insulating film, and a recess is located on the semiconductor substrate side of a portion of the element isolation insulating film farthest from the semiconductor substrate. Forming the step,
Forming a second gate insulating film on the second gate electrode material film and along the recess;
Depositing a third gate electrode material film on the second gate insulating film;
The third gate electrode material film, the second gate insulating film, the second gate electrode material film, and the first gate electrode material film are sequentially etched to form the first and second gate electrode material films. Patterning a control gate composed of a floating gate and the third gate electrode material film;
Source that is self-aligned to the control gate, possess and forming a drain diffusion layer,
The step of forming the second gate insulating film comprises forming the second gate insulating film in contact with the element isolation insulating film in the recess .

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