JP2008103542A - Nonvolatile semiconductor storage device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make compatible both the lowering of the resistance of a gate electrode using a cobalt silicide and the stabilizing of memory cell transistor characteristics. <P>SOLUTION: A barrier film 9 composed of a silicon nitride film is not formed on the upper surface and the side wall of a metal semiconductor alloy layer 8 composed of a cobalt silicide film, and formed along the side wall surface of a polycrystal silicon film of a control gate electrode 6, an integrate insulating film 5 and a floating gate electrode 4. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a nonvolatile semiconductor memory device having a metal semiconductor alloy layer on a gate electrode and a manufacturing method thereof.

A flash memory device (nonvolatile semiconductor memory device) employs a stack structure of a floating gate electrode made of polycrystalline silicon and a control gate electrode as a gate electrode of a memory cell transistor in a memory cell formation region, and accumulates in the floating gate electrode. Information is stored in accordance with the charge that is generated. In order to reduce the resistance value of the control gate electrode, a silicide layer such as tungsten silicide (WSi) is formed as a low resistance metal layer on the control gate electrode. A silicon nitride (SiN) film is formed on the silicide layer. This silicon nitride film functions as a hydrogen barrier film that prevents the characteristics of the memory cell transistor from fluctuating when hydrogen enters the gate insulating film of the memory cell transistor (see, for example, Patent Document 1).
In recent years, for example, in order to further reduce the resistance of a silicide layer, it has been considered to use cobalt (Co) or the like. However, for example, since cobalt is a lower melting point material than tungsten, if a silicon nitride film is formed after forming a cobalt silicide (CoSi ₂ ) film on the control gate electrode, there is a problem that the cobalt silicide film deteriorates. .
Japanese Patent Laid-Open No. 2000-311992 (FIG. 1)

  An object of the present invention is to provide a nonvolatile semiconductor memory device that can stabilize the characteristics of a memory cell transistor while preventing deterioration of a metal semiconductor alloy layer such as silicide, and a manufacturing method thereof.

  One embodiment of the present invention is a semiconductor substrate, and a plurality of gate electrodes formed on the semiconductor substrate with a gate insulating film interposed therebetween, each having a metal semiconductor alloy layer formed thereon, and a plurality of adjacent gate electrodes. A barrier film made of a silicon nitride film formed to cover the semiconductor substrate between the gate electrodes and to cover the sidewall surfaces of the plurality of gate electrodes while exposing the upper surface and sidewall surfaces of the metal semiconductor alloy layer; and a plurality of gates Provided is a nonvolatile semiconductor memory device including an interlayer insulating film formed between electrodes and on the plurality of gate electrodes.

  One embodiment of the present invention includes a step of forming a first gate insulating film over a semiconductor substrate, a step of forming a first semiconductor layer over the first insulating film, and a second step over the first semiconductor layer. Forming the gate insulating film, forming the second semiconductor layer on the second insulating film, and dividing the first and second semiconductor layers and the second gate insulating film into a plurality of parts A step of providing a region, a step of forming a silicon nitride film so as to cover the first and second semiconductor layers and the first and second gate insulating films, and a first step of forming a silicon oxide film on the silicon nitride film Forming a first interlayer insulating film; removing the first interlayer insulating film and the silicon nitride film so as to expose the upper surface and the upper sidewall of the second semiconductor layer; and exposing the upper portion of the exposed second semiconductor layer Forming a metal semiconductor alloy layer on the first interlayer insulating film and To provide a method of manufacturing a nonvolatile semiconductor memory device including the step of forming a second interlayer insulating film to the fine metal semiconductor alloy layer.

  One embodiment of the present invention includes a step of forming a first gate insulating film over a semiconductor substrate, a step of forming a first semiconductor layer over the first gate insulating film, and a step of forming a first gate insulating film over the first semiconductor layer. A step of forming a second gate insulating film, a step of forming a second semiconductor layer on the second gate insulating film, a first semiconductor layer, a second semiconductor layer, and a second gate insulating film. The gate electrode of the select gate transistor and the gate electrode of the memory cell transistor are arranged side by side, and the first and second semiconductor layers and the first and second gate insulating films are formed of a TEOS film so as to cover the first and second semiconductor layers. A step of forming one interlayer insulating film, a step of removing the first interlayer insulating film between adjacent select gate electrodes, and a sidewall surface of the gate electrode of the select gate transistor on the first interlayer insulating film. Along the silicon nitride film Forming a barrier film, forming a second interlayer insulating film made of a BPSG film on the barrier film, and first and second interlayer insulation so that the upper surface and upper side wall of the second semiconductor layer are exposed. Removing the film and the silicon nitride film; forming a metal semiconductor alloy layer on the second semiconductor layer; and a third interlayer insulating film on the first and second interlayer insulating films and the metal semiconductor alloy layer And a method of manufacturing a nonvolatile semiconductor memory device.

  According to the present invention, it is possible to achieve both reduction in resistance of the gate electrode and stabilization of memory cell transistor characteristics by a metal semiconductor alloy layer such as silicide.

(First embodiment)
Hereinafter, a first embodiment in which a nonvolatile semiconductor memory device of the present invention is applied to a NAND flash memory device will be described with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  FIG. 1 shows an equivalent circuit of a part of a memory cell array configured in a memory cell region of a NAND flash memory device, and FIG. 2 shows a schematic plan view of the structure of the memory cell region. . FIG. 3 is a schematic plan view showing a plan view around the bit line contact CB.

  A NAND flash memory device 1 as a semiconductor device includes a memory cell region M in which a memory cell array Ar shown in FIG. 1 and a peripheral circuit region (not shown) in which a peripheral circuit for driving the memory cell array Ar is formed. ).

  In the flash memory device 1 shown in FIG. 1, the memory cell array Ar includes two selection gate transistors Trs and a plurality (for example, 8: 2 to the nth power) connected in series between the selection gate transistors Trs. (N is a positive number)) NAND cell units Su composed of memory cell transistors Trn are arranged in a matrix.

  In one NAND cell unit Su, two select gate transistors Trs and a plurality of memory cell transistors Trn are configured such that adjacent ones share a source / drain region 2a (see FIG. 13).

  The memory cell transistors Trn arranged in the X direction (corresponding to the word line WL direction and the gate width direction) in FIG. 1 are electrically connected by a word line (control gate line) WL. Further, the selection gate transistors Trs arranged in the X direction in FIG. 1 are connected by a selection gate line SL. Further, the select gate transistor Trs is connected to the bit line BL extending in the Y direction (corresponding to the crossing direction in the gate width direction, the gate length direction, and the bit line direction) orthogonally intersecting the X direction in FIG. 1 via the bit line contact CB. It is connected. Although an embodiment in which the X direction and the Y direction are orthogonal to each other is shown, any angle may be used as long as they intersect.

  As shown in FIG. 2, the plurality of NAND cell units Su are separated from each other by an element isolation region Sb having an STI (Shallow Trench Isolation) structure. As shown in FIG. 3, the element isolation region Sb defines an element formation region (active region: active area) Sa extending in the Y direction. The element formation region Sa indicates a region including the source / drain regions and the channel region of the memory cell transistor Trn and the select gate transistor Trs. The memory cell transistor Trn is formed at an intersection of an element formation region Sa extending in the Y direction and a word line WL formed at a predetermined interval in the Y direction and extending in the X direction.

<About the peripheral structure of the bit line contact CB>
Hereinafter, the structure around the bit line contact CB will be described with reference to FIG. FIG. 13 is a longitudinal sectional view taken along line AA shown in FIGS. 2 and 3 schematically showing a partial structure of the memory cell region M. As shown in FIG.

  The memory cell region M of the flash memory device 1 has a structure in which a floating gate electrode and a control gate electrode constituting a gate electrode are stacked on a p-type silicon substrate 2 as a semiconductor substrate. It has a higher aspect ratio structure. Further, the bit line contact CB in the memory cell region M of the flash memory device 1 according to the present embodiment employs a non-self-aligned contact structure.

  As shown in FIG. 13, on the silicon substrate 2, the gate electrode SG constituting the selection gate transistor and the gate electrode MG constituting the memory cell transistor are juxtaposed in a plurality of gate electrode formation regions GC on the silicon substrate 2. ing.

<About the structure of the gate electrode MG of the memory cell transistor>
The gate electrode MG is formed on the floating gate electrode (first gate electrode) 4 (FG) formed on the silicon substrate 2 via the first gate insulating film 3 and on the first gate electrode 4. The inter-gate insulating film 5 and the control gate electrode (second gate electrode) 6 formed on the inter-gate insulating film 5 are configured.

  The first gate insulating film 3 is formed of, for example, a silicon oxide film. The floating gate electrode 4 is formed of polycrystalline silicon doped (introduced) with impurities such as phosphorus and arsenic. The inter-gate insulating film 5 is formed of, for example, an ONO (silicon oxide film (Oxide) -silicon nitride film (Nitride) -silicon oxide film (Oxide)) film.

  The control gate electrode 6 includes a thin polycrystalline silicon film 7a on the lower layer side, a polycrystalline silicon film 7b formed thick on the polycrystalline silicon film 7a, and a metal formed on the polycrystalline silicon film 7b. And a semiconductor alloy layer 8.

  The polycrystalline silicon films 7a and 7b are doped (introduced) with impurities such as phosphorus and arsenic. The metal semiconductor alloy layer (metal silicide layer) 8 is a layer formed by alloying a metal and the polycrystalline silicon film 7b, and cobalt (Co) is applied as the metal.

<About the structure of the gate electrode SG of the selection gate transistor>
The gate electrode SG has substantially the same structure as that of the gate electrode MG constituting the memory cell transistor. The difference is that the control gate electrode 6 and the floating gate electrode 4 are penetrated to be structurally and electrically conductively connected. It is in place.

  Specifically, the selection gate electrode SG is formed on the silicon substrate 2 via the first gate insulating film 3 via the first gate electrode 4, the inter-gate insulating film 5, and the polycrystalline silicon, similarly to the gate electrode MG. The films 7a and 7b and the metal semiconductor alloy layer 8 are formed in order with the same film thickness as the corresponding film of the gate electrode MG. Of these, the through-hole 11 is provided in the inter-gate insulating film 5 and the polycrystalline silicon film 7a. It has been. The polycrystalline silicon film 7b is formed so as to be structurally in contact with the first gate electrode 4 through the through-hole 11, thereby forming the gate electrode SG.

A gate electrode isolation region GV is provided between the plurality of gate electrodes MG-MG arranged in parallel and between MG-SG. A barrier film 9 and an interlayer insulating film 10 are formed in the gate electrode isolation region GV. The barrier film 9 is formed along the outer wall surface of each gate electrode G and along the surface of the silicon substrate 2. The barrier film 9 is made of, for example, a silicon nitride (SiN) film. The interlayer insulating film 10 is made of a BPSG (boro phospho silicate glass) film. The barrier film 9 is formed such that the upper end portion 9a thereof is substantially the same height as the lower surface of the metal semiconductor alloy layer 8. . That is, the barrier film 9 is formed so as to cover the entire side wall of the floating gate electrode 4, the side wall of the inter-gate insulating film 5, the side wall of the control gate electrode, and between the gate electrodes MG-MG and the MG-SG. Yes.

  An interlayer insulating film 13 is formed immediately above each gate electrode SG and MG. The interlayer insulating film 13 is made of, for example, a silicon oxide film made of TEOS (Tetra Ethyl Ortho Silicate: Tetra Ethoxy Silane).

  A source / drain region 2a is formed as a diffusion layer in the surface layer of the silicon substrate 2 between the gate electrodes SG and MG. A contact plug 12 is formed on the diffusion layer 2a between the gate electrodes SG-SG. The contact plug 12 is composed of a poly plug or a metal plug.

  According to the structure according to the present embodiment, the barrier film 9 includes the side wall of the floating gate electrode 4, the side wall of the intergate insulating film 5, the side wall of the control gate electrode, the silicon substrate 2 between the gate electrodes MG-MG and between MG-SG. Since it is formed so as to cover the entire upper surface, it is possible to prevent hydrogen from entering the gate insulating film, and to prevent characteristic variation of the memory cell transistor Trn.

  Hereinafter, the manufacturing method of the structure described above will be described with reference to FIGS. Although the description will focus on the features of the present embodiment, the present invention can achieve the object by solving the problems described in the problem column to be solved by the invention, and the effects described in the effect column of the invention If any of the above is performed, any of the steps described below may be omitted as necessary. Moreover, it may be changed as long as other materials are applicable instead of the material of each functional film, and the film thickness may be appropriately changed.

  For convenience of explanation, 100 is added to the reference numerals assigned to the structural elements for the manufacturing structural elements (referred to as structural elements) corresponding to the constituent elements (referred to as structural elements) of the respective films and layers described above. A reference numeral is attached and described as a manufacturing element code. Therefore, the manufacturing elements shown below correspond to the manufacturing elements with the reference numerals obtained by subtracting 100 from the reference numerals attached to the manufacturing elements.

Since the present embodiment is characterized by the manufacturing process after the formation of the gate electrodes MG and SG, the process for forming the structure shown in FIG. 4 will be schematically described.
<Formation Step of Structure of FIG. 4>
A silicon oxide film 103 is formed on the silicon substrate 102 to a thickness of about 10 [nm] by a thermal oxidation method. Next, an amorphous silicon layer (first semiconductor layer) 104 is formed with a thickness of about 120 [nm] on the silicon oxide film 103 by low pressure CVD. This amorphous silicon layer is transformed into polycrystalline silicon by heat treatment later.

  Next, a plurality of element isolation grooves (not shown) are formed in the amorphous silicon layer 104, the silicon oxide film 103, and the silicon substrate 102, and an element isolation insulating film (not shown) is formed in the element isolation grooves. By embedding, the amorphous silicon layer 104 is divided in the X direction in FIG. Thereby, the silicon oxide film 103 and the amorphous silicon layer 104 are left on the element formation region Sa. Next, an ONO film 105 is formed on the element isolation insulating film (not shown) and the amorphous silicon layer 104 by a low pressure CVD method. Next, an amorphous silicon layer 107a doped with impurities such as phosphorus is deposited on the ONO film 105 by low pressure CVD. Next, in the formation region of the gate electrode SG, a through hole 111 is formed in the amorphous silicon layer 107a and the ONO film 105, and then an amorphous silicon layer 107b doped with impurities such as phosphorus is formed by a low pressure CVD method. Form. The amorphous silicon layers 107a and 107b are transformed into polycrystalline silicon by a subsequent heat treatment step.

  Next, a mask pattern is formed on the amorphous silicon layers 107a and 107b by a photolithography technique, and the layers 107b, 107a, 105, and 104 in the gate electrode isolation region GV are removed. Next, ions are implanted by an ion implantation technique to form a diffusion layer 102a. Next, an HTO (High Temperature Oxide) film (not shown) is formed thinly so as to cover the layers 107b, 107a, 105, and 104 by low pressure CVD. Next, as shown in FIG. 5, a silicon nitride film 109 is formed so as to cover the layers 107b, 107a, 105, 104 and the silicon oxide film 103 between the gate electrodes MG-MG and MG-SG.

  Next, as shown in FIG. 6, an embedded film 110 is formed by HDP (High Density Plasma) -CVD so as to cover the silicon nitride film 109. The buried film 110 is formed of, for example, TEOS, BPSG or the like and is configured as an interlayer insulating film. The silicon nitride film 109 is formed for the purpose of preventing intrusion of impurities from the interlayer insulating film 110 (particularly BPSG) and functions as a barrier film.

  Next, as shown in FIG. 7, the buried film 110 is planarized by a CMP (Chemical Mechanical Polishing) method and dry-etched by an RIE (Reactive Ion Etching) method, so that the upper surface of the amorphous silicon layer 107b is obtained. And the upper sidewalls are exposed.

  Next, as shown in FIG. 8, cobalt is formed on the upper surface and side walls of the amorphous silicon layer 107b by sputtering and alloyed by heat treatment to form a cobalt silicide film 108 as a metal semiconductor alloy layer. Then, the metal film that has not been alloyed is removed.

  Next, as shown in FIG. 9, a silicon oxide film 113 is deposited on the metal silicide film 108 and the interlayer insulating film 110. The silicon oxide film 113 is a film formed by, for example, a dual frequency plasma CVD method.

  Next, as shown in FIG. 10, a resist R is applied and patterned on the silicon oxide film 113 to form holes H1. FIG. 12 is a plan view showing the formation region of the hole H1 at this time. The hole H1 is formed in an elliptical shape, for example, and is formed on the formation region of the bit line contact CB.

  Next, as shown in FIG. 11, using the patterned resist R as a mask, the silicon oxide film 113, the silicon oxide film 110, the silicon nitride film 109, and the silicon oxide film 103 are removed by the RIE method to form a hole H. . The etching conditions at this time are conditions with a low selectivity between the silicon oxide films 110 and 113. Next, a contact plug 12 is embedded in the hole H.

  According to the manufacturing method according to the present embodiment, since the silicon nitride film 109 is formed before the metal silicide film 108 is formed, it is possible to prevent the metal silicide film 108 from being deteriorated due to the influence of heat when the silicon nitride film 109 is formed. At the same time, since the silicon nitride film 109 covers the sidewalls of the amorphous (polycrystalline) silicon layers 107a and 107b and the silicon oxide film 103 between the gate electrodes MG-MG and MG-SG, the gate insulation of the memory cell transistor Trn is performed. It is possible to prevent the characteristics of the memory cell transistor from fluctuating due to hydrogen entering the film. Further, cobalt is formed on the upper surface and the side wall of the amorphous silicon layer 107b, and the alloying process is performed from both the upper surface and the side surface to form the metal silicide film 108. Therefore, the metal silicide film 108 can be formed uniformly.

(Second Embodiment)
FIGS. 14 to 20 show a second embodiment of the present invention. The difference from the previous embodiment is that the main factor of generation of hydrogen entering the gate insulating film is the BPSG film. 9 is provided only between the gate electrodes SG-SG of the selection gate transistor in which the BPSG film is embedded, and BPSG does not contain hydrogen between the gate electrode SG and the gate electrode MG of the memory cell transistor and between the gate electrodes MG-MG. An interlayer insulating film other than the film is buried and the barrier film 9 is not provided. In addition, the order of forming the silicon nitride film 109 and the silicon oxide film 110 is changed. About the same part as the above-mentioned embodiment, the same code | symbol is attached | subjected and description is abbreviate | omitted and only a different part is demonstrated hereafter.

<About structure>
As shown in FIG. 14, the barrier film 9 is not formed between the gate electrode SG and the gate electrode MG, and the barrier film 9 is also formed between the adjacent gate electrodes MG-MG, as compared with the previous embodiment. It has not been. In the present embodiment, only the interlayer insulating film 10 made of a non-BPSG film not containing hydrogen is formed between the gate electrode SG and the gate electrode MG and between the gate electrodes MG-MG. In the present embodiment, the interlayer insulating film 10 is formed of a silicon oxide film made of a TEOS material.

  The relative dielectric constant of the barrier film 9 made of a silicon nitride film is higher than the relative dielectric constant of the interlayer insulating film 10 made of a silicon oxide film. Therefore, if the barrier film 9 is not formed between the select gate electrode SG and the gate electrode MG and between the gate electrodes MG-MG, the relative dielectric constant can be kept low, and the adjacent memory cell transistors The electrical coupling of the floating gate electrode FG can be suppressed.

  A barrier film 9 is formed on the outer periphery of the bit line contact CB and in the vicinity of the contact region with the silicon substrate 2, and an interlayer insulating film 15 made of BPSG is embedded inside the barrier film 9. .

Hereinafter, the manufacturing method will be described with reference to FIGS.
After forming the structure shown in FIG. 4, as shown in FIG. 15, a buried film 110 made of TEOS is formed by HDP-CVD, and the entire surface of the amorphous silicon layer 107b is etched back by RIE. The silicon oxide film 110 between the gate electrodes SG-SG is removed by lithography and wet etching while being exposed. At this time, although not shown, if the HTO film having resistance to the wet etching process is formed on the element isolation insulating film (not shown), the reliability of the element isolation insulating film is maintained.

  Next, as shown in FIG. 16, the silicon nitride film 109 is formed on the silicon substrate 2 between the gate electrode SG-SG from which the upper surface of the silicon oxide film 110, the upper surface of the amorphous silicon layer 107b, and the buried film 110 have been removed. Form. Next, as shown in FIG. 17, a BPSG 115 is formed. This BPSG 115 is a material with better embedding than TEOS material, for example. Therefore, even if the width of the bit line contact CB formation region is narrow, the interlayer insulating film 15 can be configured with good embedding.

Next, as shown in FIG. 18, planarization is performed by CMP, and the entire surface is etched back by RIE to expose the upper surface and upper sidewall of the amorphous silicon layer 107b.
Next, as shown in FIG. 19, cobalt is formed on the upper surface of the amorphous silicon layer 107b and the exposed upper side wall and alloyed to form a metal silicide film 108 on the amorphous silicon layer 107b. It is formed as an alloy layer. Next, as shown in FIG. 20, a silicon oxide film 113 is formed and planarized by a CMP method. Next, as shown in FIG. 14, the silicon oxide film 113, the BPSG 115, and the silicon nitride film 109 are etched by RIE to form holes H up to the silicon substrate 2, and contact plugs 12 are formed in the holes H. Embedded to form. According to the manufacturing method according to the present embodiment, there are substantially the same functions and effects as in the previous embodiment.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
The present invention is not limited to the flash memory device 1 and can be applied to semiconductor devices such as various nonvolatile semiconductor memory devices. Moreover, although the said embodiment was applied to the p-type silicon substrate 2 and 102, you may apply this invention to the semiconductor substrate which consists of another material. In the above embodiment, the first gate insulating film 3 is formed of the silicon oxide film 103, but the present invention may be formed of other insulating materials. In the above embodiment, the floating gate electrode (first gate electrode) 4 is formed of the amorphous silicon layer 104, but the present invention may be formed of other semiconductor materials.

  In the above embodiment, the inter-gate insulating film 5 is formed of an ONO film. However, the present invention relates to NONON (silicon oxide film (Oxide) -silicon nitride film (Nitride) -silicon oxide film (Oxide) -silicon nitride film (Nitride). ) -Silicon oxide film (Oxide)) or other oxide film layer and nitride film layer structure, or a film made of other high dielectric materials may be applied. In the above embodiment, the base layer of the control gate electrode 6 is formed of the polycrystalline silicon film 7 (amorphous silicon layers 107a and 107b). However, the present invention may be formed of other semiconductor materials. In the present invention, the amorphous silicon layer 107a may be formed as necessary. The present invention is not limited to the gate electrode SG of the select gate transistor and the gate electrode MG of the memory cell transistor, but can be applied to the gate electrodes of other transistors.

  In the above embodiment, the cobalt silicide film 108 is used as the metal semiconductor alloy layer 8. However, in the present invention, nickel silicide (NiSi), platinum silicide (PtSi), titanium silicide (TiSi), and tantalum silicide (TaSi) are used as metal semiconductors. It may be used as an alloy layer.

1 is an electrical configuration diagram of a part of a memory cell region showing a first embodiment of the present invention; Schematic plan view of part of the memory cell area Schematic plan view near the contact plug Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 1) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 2) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 3) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 4) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 5) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 6) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 7) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 8) Figure showing mask pattern 2 and 3 is a longitudinal sectional view taken along line AA in FIG. FIG. 13 equivalent view showing the second embodiment of the present invention Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 9) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 10) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 11) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 12) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 13) Sectional drawing in alignment with the AA line of FIG. 2, FIG. 3 in the middle of manufacture (the 14)

Explanation of symbols

  In the drawings, 1 is a flash memory device (nonvolatile semiconductor memory device), 2 and 102 are silicon substrates (semiconductor substrates), 3 is a gate insulating film, 103 is a silicon oxide film (first gate insulating film), and 4, FG Is a floating gate electrode (first gate electrode), 104 is an amorphous silicon layer (first semiconductor layer), 5 is an inter-gate insulating film, 105 is an ONO film (second gate insulating film), and 6 is a control. Gate electrodes (second gate electrodes) 107a and 107b are amorphous silicon layers (second semiconductor layers), SG is a selection gate electrode (gate electrode), MG is a gate electrode of a memory cell transistor, and 8 is a metal semiconductor. Alloy layer 108 is a cobalt silicide film 9 is a barrier film 109 is a silicon nitride film 10 and 110 are interlayer insulating films 12 is a contact plug 15 is an interlayer insulating film 115 is BPSG .

Claims (5)

A semiconductor substrate;
A plurality of gate electrodes formed on the semiconductor substrate via a gate insulating film, each having a metal semiconductor alloy layer formed thereon;
A barrier film made of a silicon nitride film that covers the semiconductor substrate between the plurality of adjacent gate electrodes and covers the side wall surfaces of the plurality of gate electrodes while exposing the upper surface and the side wall surfaces of the metal semiconductor alloy layer; ,
A nonvolatile semiconductor memory device comprising: an interlayer insulating film formed between the plurality of gate electrodes and on the plurality of gate electrodes.   2. The nonvolatile semiconductor memory device according to claim 1, wherein the interlayer insulating film is a BPSG film.   3. The nonvolatile semiconductor memory device according to claim 1, wherein the metal semiconductor alloy layer is one of cobalt silicide, nickel silicide, platinum silicide, titanium silicide, and tantalum silicide. Forming a first gate insulating film on the semiconductor substrate;
Forming a first semiconductor layer on the first insulating film;
Forming a second gate insulating film on the first semiconductor layer;
Forming a second semiconductor layer on the second insulating film;
A step of dividing the first and second semiconductor layers and the second gate insulating film into a plurality of portions to provide a divided region;
Forming a silicon nitride film so as to cover the first and second semiconductor layers and the first and second gate insulating films;
Forming a first interlayer insulating film made of a silicon oxide film on the silicon nitride film;
Removing the first interlayer insulating film and the silicon nitride film so that an upper surface and an upper sidewall of the second semiconductor layer are exposed;
Forming a metal semiconductor alloy layer on the exposed second semiconductor layer;
And a step of forming a second interlayer insulating film on the first interlayer insulating film and the metal semiconductor alloy layer. Forming a first gate insulating film on the semiconductor substrate;
Forming a first semiconductor layer on the first gate insulating film;
Forming a second gate insulating film on the first semiconductor layer;
Forming a second semiconductor layer on the second gate insulating film;
A step of dividing the first and second semiconductor layers and the second gate insulating film into a plurality of parts and arranging a gate electrode of a select gate transistor and a gate electrode of a memory cell transistor in parallel;
Forming a first interlayer insulating film made of a TEOS film so as to cover the first and second semiconductor layers and the first and second gate insulating films;
Removing the first interlayer insulating film between adjacent select gate electrodes;
Forming a barrier film made of a silicon nitride film on the first interlayer insulating film and along a side wall surface of the gate electrode of the select gate transistor;
Forming a second interlayer insulating film made of a BPSG film on the barrier film;
Removing the first and second interlayer insulating films and the silicon nitride film so as to expose an upper surface and an upper sidewall of the second semiconductor layer;
Forming a metal semiconductor alloy layer on top of the second semiconductor layer;
And a step of forming a third interlayer insulating film on the first and second interlayer insulating films and the metal semiconductor alloy layer.

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