JP4836892B2 - Digital frequency multiplier - Google Patents

Description

  The present invention relates to a digital frequency multiplying circuit that inputs a digital input signal having a frequency F and outputs a digital output signal having a frequency N times that of a frequency and a duty ratio of 50%.

  As shown in FIG. 10, for example, a conventional digital frequency multiplication circuit that doubles the frequency of a digital input signal having a duty ratio of 50% includes a delay element 101 that delays a digital input signal having a frequency F, and the delay element 101. And a circuit 100 having an exclusive OR circuit 102 to which the above-mentioned output and the previous digital input signal are input are used as a basic circuit, and this is cascaded in any number of stages (see Patent Document 1). In addition, as shown in FIG. 11, two signals that are 90 degrees out of phase with each other are generated by the hybrid circuit 111 from the input reference clock signal of the frequency F, and these two signals are input to the exclusive OR circuit 112. Thus, there is a digital frequency multiplication circuit 110 in which an output signal having a frequency twice that of the reference clock signal is output from the exclusive OR circuit 112 (see Patent Document 2).

JP-A-1-319321 JP-A-7-38391

  In a digital frequency multiplication circuit using a delay element as in Patent Document 1, each stage requires a delay element having a delay time of half that of the previous stage and a duty ratio of 50%. In this case, delay elements having different delay times must be prepared for each stage, and when the number of multiplications is large and the number of stages increases, the number of parts increases, and the man-hours for management and manufacturing costs increase. Further, in order to ensure the duty ratio of 50%, there is a problem that detailed design and adjustment of circuit constants including the delay time of the delay element and the threshold value of the logic circuit are required.

  In the circuit described in Patent Document 2, it is necessary to use a complicated hybrid circuit in order to obtain two signals that are 90 degrees out of phase with each other. When the multiplication number is large, the frequency multiplication circuit becomes large or the manufacturing cost increases. There was a problem such as soaring.

  In addition, when used in equipment that requires fail-safety, such as railway signal equipment, safety must be ensured even if a fixed failure occurs in the circuit. Therefore, it is required to ensure fail-safeness by preventing a situation in which an output signal is output during a period when there is no input signal and a relay that controls a traffic light, a switch, or the like malfunctions.

  The present invention has been made in view of the above points, and an object thereof is to provide a digital frequency multiplication circuit that does not require adjustment work, is easy to integrate, and ensures fail-safety even in the event of a failure. Yes.

  The gist of the present invention for achieving the object lies in the inventions of the following items.

[1] Input a digital input signal of frequency F with a duty ratio of about 50%, and output a digital output signal with a duty ratio of 50% when the frequency is N times the digital input signal (N is an even integer of 2 or more). In the digital frequency multiplier circuit
A change point detector for detecting change points of rising and falling edges of the digital input signal;
An N-stage shift register to which a clock signal having a frequency of 2 × N × F is input, and each time the change point is detected by the change point detection unit, N bits of 1 and 0 alternately arranged A frequency multiplier in which alternating data is loaded into the shift register;
Have
A digital frequency multiplication circuit that outputs the digital output signal from a serial output of the shift register.

  In the above invention, the change point detection unit detects a change point of a digital input signal with a frequency F and a duty ratio of 50%, and the frequency multiplication unit includes an N-stage shift register driven by a clock signal of frequency 2 × N × F. Each time a change point is detected, N-bit alternating data in which 1 (high level H) and 0 (low level L) are alternately arranged is loaded in parallel into the shift register. The alternating data loaded in parallel is shifted for each clock and serially output. At the timing when all the data is output, the changing point is detected again by the changing point detector, and the alternating data is loaded in parallel. By repeating this, a digital output signal having a frequency N times that of the digital input signal and a duty ratio of 50% is output as a serial output of the shift register in accordance with the input of the digital input signal. Since the change point detector detects the change point (rise and fall change points) of each half cycle of the digital input signal, the frequency multiplier has a shift register with the number of stages corresponding to the number of clocks corresponding to the half cycle of the digital input signal. Use it.

[2] The change point detection unit inverts the clock signal, a D flip-flop circuit cascaded in two stages, an exclusive OR circuit that takes an exclusive OR of outputs of these D flip-flop circuits, and With an inverter,
The clock signal is input to the clock terminal of one D flip-flop circuit, the output of the inverter is input to the clock terminal of the other D flip-flop circuit,
The digital frequency multiplication circuit according to [1], wherein an output of the exclusive OR circuit is output as a change point detection signal.

  According to the above invention, a change point detection signal having a pulse width of a half cycle of the clock signal is output at every change point (rising and falling) of the digital input signal having the frequency F and the duty ratio of 50%.

[3] The change point detection unit outputs a change point detection signal every time a change point is detected,
The frequency multiplier performs the load every time the change point detection signal is output,
A gate for preventing the clock signal from being input to the shift register while the change point detection signal is being output;
The digital frequency multiplication circuit according to claim 1 or 2, characterized in that

[4] Reduce the number of stages of the shift register by one stage,
The number of bits corresponding to the number of stages reduced by one stage and the alternate data in which the odd-numbered stage of the shift register is 1, is loaded in parallel and the serial input to the first stage is fixed at a low level, or the number of stages is reduced by one stage. [1] to [3], wherein alternating data having the number of bits corresponding to the number of stages and the even-numbered stage of the shift register being 1 is loaded in parallel and the serial input to the first stage is fixed at a high level. ] The digital frequency multiplier circuit described in any one of the above.

  In the above-described invention, the number of stages of shift registers constituting the frequency multiplier can be reduced by one.

[5] The digital frequency according to any one of [1] to [4], wherein the shift register is configured by cascading D flip-flop circuits having preset input and clear input functions. Multiplier circuit.

  In the above invention, the shift register is constituted by the cascade connection of the D flip-flop circuits. A preset input function and / or a clear input function is used for parallel loading of alternating data.

[6] The digital frequency multiplication circuit output from the digital frequency multiplication circuit according to any one of [1] to [5] is used as the digital input signal for the next stage, and the digital frequency multiplication circuit is connected in a plurality of stages. A digital frequency multiplication circuit characterized by that.

  In the above invention, the number of stages of shift registers (the number of D flip-flop circuits used) in the frequency multiplication section can be reduced by connecting in multiple stages.

  ADVANTAGE OF THE INVENTION According to this invention, the adjustment operation | work is unnecessary and integration is easy, and the digital frequency multiplication circuit which has fail safe property is provided.

  Hereinafter, various embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a digital frequency multiplication circuit 10 according to a first embodiment of the present invention. The digital frequency multiplication circuit 10 receives an input signal Si having a frequency of F hertz (Hz) and a duty ratio of 50% and a clock signal CLK having a frequency (2 × N × F), and the frequency is N × F. This circuit serves to generate and output an output signal So having a duty ratio of 50%. Here, N which is a multiplication number may be an arbitrary value as long as it is an even integer of 2 or more.

  The digital frequency multiplication circuit 10 has, as input / output terminals, an input terminal 11 to which an input signal Si having a frequency F and a duty ratio of 50% is input, and a clock terminal to which a clock signal CLK having a frequency (2 × N × F) is input. 12, a reset terminal 13 to which a reset signal POR is input, and an output terminal 14 to which an output signal So having a frequency (N × F) and a duty ratio of 50% is output. For example, a power-on reset signal of the digital frequency multiplier 10 is used as the reset signal POR, but a separate reset signal may be used.

  The digital frequency multiplication circuit 10 includes an input signal change detection unit 20 and a frequency multiplication unit 40 inside. The input signal change detector 20 receives the input signal Si, the clock signal CLK, and the reset signal POR. The input signal change detection unit 20 has a function of detecting each rising point and falling point of the input signal Si and outputting a change point detection signal PR / SH for each detection. Here, the change point detection signal PR / SH having a pulse width of one pulse of the clock signal CLK (half cycle of the clock signal CLK) is output in substantially the same phase as the clock signal CLK. The pulse width of the change point detection signal PR / SH may be arbitrary within a range shorter than one cycle of the clock signal CLK.

  The frequency multiplier 40 receives the change point detection signal PR / SH, the clock signal CLK, and the reset signal POR output from the input signal change detector 20. Every time one pulse of the change point detection signal PR / SH is input, the frequency multiplier 40 outputs an output signal So having a frequency N × F and a duty ratio of 50% for a period corresponding to a half cycle of the input signal of the frequency F. . Accordingly, when the change point detection signal PR / SH is continuously input to the frequency multiplier 40 as a pulse train having a frequency of 2 × F, an output signal So having a frequency N × F and a duty ratio of 50% is supplied to the frequency multiplier 40. Is output continuously.

  FIG. 2 shows a circuit example of the input signal change detection unit 20. The input signal change detection unit 20 includes D flip-flop circuits 21 and 22 having a preset / clear function, inverters 23 and 24, and a two-input exclusive OR (XOR) circuit 25.

  The input signal Si is input to the D terminal of the first stage D flip-flop circuit 21, and the output signal Sa output from the Q terminal of the first stage D flip-flop circuit 21 is the second stage D flip-flop circuit. 22 D terminals and one input terminal of the exclusive OR circuit 25. The output signal Sb output from the Q terminal of the second stage D flip-flop circuit 22 is input to the other input terminal of the exclusive OR circuit 25, and the output of the exclusive OR circuit 25 is the change point detection signal PR /. The signal is output to the subsequent frequency multiplier 40 as SH.

  A clock signal CLK is input to the clock terminal of the first stage D flip-flop circuit 21, and a signal obtained by inverting the clock signal CLK by the inverter 23 is input to the clock terminal of the second stage D flip-flop circuit 22. Yes. The preset terminals of the D flip-flop circuits 21 and 22 are fixed at a high level H (+5 V), and a signal obtained by inverting the reset signal POR by the inverter 24 is input to the clear terminal.

  FIG. 3 shows a circuit example of the frequency multiplier 40. FIG. 3 shows a circuit example when the frequency of the change point detection signal PR / SH is quadrupled (N = 4). The frequency multiplier 40 includes N flip-flop circuits 41, 42, 43, 44 with preset input and clear input functions, inverters 45, 46, and a 2-input logical product (AND) circuit 47 connected in cascade with N stages. And is configured. The D flip-flop circuits 41, 42, 43, and 44 with preset / clear functions connected in cascade in N stages each time the change point detection signal PR / SH is input (change point is detected) from the input signal change detection unit 20. In addition, it functions as a shift register in which N-bit alternating data in which 1 and 0 are alternately arranged is loaded in parallel.

  The change point detection signal PR / SH input from the input signal change detection unit 20 is input to the inverter 45, and the output signal Sd of the inverter 45 is preset to the D flip-flop circuits 41 and 43 in the first and third stages. Terminal and one input terminal of the AND circuit 47. A clock signal CLK having a frequency (2 × 4 × F) is input to the other input terminal of the AND circuit 47, and an output signal Se of the AND circuit 47 is output from each D flip-flop circuit 41, 42, 43, 44. Input to the clock terminal.

  The preset terminals of the second and fourth stage D flip-flop circuits 42 and 44 are fixed to high level H (+5 V), and the D terminal of the first stage D flip-flop circuit 41 is fixed to low level L (0 V). Has been. The output signal So is output from the Q terminal of the fourth-stage D flip-flop circuit 44. A signal obtained by inverting the reset signal POR by the inverter 46 is input to the clear terminals of the D flip-flop circuits 41, 42, 43, 44 of each stage.

  FIG. 3 illustrates the case where the multiplication number N = 4, but N may be any even integer of 2 or more. When the multiplication number is N, D flip-flop circuits are cascaded in N stages, and the output signal Sd (inverted change point detection signal PR / SH) Sd of the inverter 45 is sent to each odd-stage D flip-flop circuit. It is only necessary to input to the preset terminal, fix the even-numbered preset terminal to the high level, and fix the D terminal of the first-stage D flip-flop circuit to the low level L.

  FIG. 4 shows a truth table of the D flip-flop circuit and its input / output.

  Next, the operation of the digital frequency multiplier circuit 10 will be described.

  FIG. 5 is a timing chart showing signal waveforms of respective parts of the input signal change detection unit 20 shown in FIG. The input signal change detection unit 20 functions to output a change point detection signal PR / SH having a pulse width shorter than one cycle of a clock signal having a frequency of 2 × N × F every time a change point of the input signal Si is detected. .

  A reset signal POR is input to the input signal change detection unit 20 from the outside when power is supplied (time T1), the D flip-flop circuits 21 and 22 of the input signal change detection unit 20 are reset, and the D flip-flop circuit 21 is reset. , 22 and the change point detection signal PR / SH output from the exclusive OR circuit 25 are both at the low level L.

  Thereafter, when an input signal Si having a frequency F of 50% and a duty ratio of 50% is input under a state where the clock signal CLK is continuously input (time T2), the first stage D flip-flop circuit 21 rises the clock signal CLK. The output signal Sa obtained by sampling and holding the input signal Si at the edge is output, and the second stage D flip-flop circuit 22 samples and holds the output signal Sa of the first stage D flip-flop circuit 21 at the falling edge of the clock signal CLK. The output signal Sb is output.

  The output signal Sa is a signal having the same phase as the rising edge of the clock signal CLK and a frequency F and a duty ratio of 50%, and the output signal Sb is a signal having the same waveform as that of the output signal Sa and having a phase delayed by a half cycle of the clock signal CLK. It has become. Accordingly, when the exclusive OR circuit 25 obtains the exclusive OR of the output signal Sa and the output signal Sb, the clock signal is output at the rising (time T3) and falling (time T4) of the output signal Sa. A pulse signal having a pulse width corresponding to a half cycle of CLK is output from the exclusive OR circuit 25 as the change point detection signal PR / SH. The change point detection signal PR / SH is a signal having a frequency of 2 × F and a duty ratio of (1 / (2N)) × 100%. While the input signal Si is being input, the change point detection signal PR / SH having a frequency of 2 × F is continuously output. When the input signal Si is not input, the output of the exclusive OR circuit 25 is fixed at the low level L. Is done.

  FIG. 6 is a timing chart showing the input signal Si and signal waveforms of each part of the frequency multiplier 40 shown in FIG. When the reset signal POR is input at power-on, all the D flip-flop circuits 41, 42, 43, and 44 are cleared and the output of each Q terminal becomes a low level L. After that, when the clock signal CLK is input, the D flip-flop circuits 41, 42, 43, and 44 connected in cascade with N stages function as N-stage shift registers. Since the D terminal of the first-stage D flip-flop circuit 41 is fixed at the low level L, the outputs of the Q terminals of all the D flip-flop circuits 41, 42, 43, 44 are low even after the reset signal POR is released. Maintained at level L.

  When the pulse of the change point detection signal PR / SH is input from the input signal change detection unit 20 under the above-described state (time T11), the period during which the pulse is present (the change point detection signal PR / SH is at the high level) The odd-numbered stages of D flip-flop circuits 41 and 43 are preset (Q1 and Q3 are at a high level H). Therefore, the outputs Q1 to Q4 of the Q terminals of the D flip-flop circuits 41, 42, 43, and 44 connected in cascade in N stages are H (Q1), L (Q2), H (Q3), and L (Q4). In this state, the high level H and the low level L are alternately set. That is, a state in which alternating data of 1 (high level H) and 0 (low level L) is loaded in parallel into the N-stage shift register is formed at time T11.

  Since the pulse portion of the change point detection signal PR / SH is shorter than one clock of the clock signal CLK, when the next clock enters, it returns to the state where it has not been preset, and from the next clock, the alternating data loaded in parallel at the time of presetting is restored. A sequential shift operation is performed. Therefore, every time one pulse of the change point detection signal PR / SH is input, the output signal So having a frequency of half (N × F) of the clock signal CLK and a duty ratio of 50% is spread over N clocks. (Period corresponding to a half cycle of the input signal Si) is output.

  In the examples of FIGS. 3 and 6, since four stages are cascaded, the preset H and L alternating data are all serially output in four clocks. Then, when the pulse part of the change point detection signal PR / SH is input again and preset at the fifth clock (time T12), the alternating data of H and L are loaded in parallel as at time T11. Such an operation is repeated while the change point detection signal PR / SH having a frequency of 2 × F is input, so that the frequency of the final stage D flip-flop circuit 44 is half that of the clock signal CLK (N × F ), The output signal So having a duty ratio of 50% is continuously output.

  In the case of the frequency multiplier 40 of FIG. 3, an output signal So having a frequency of 4 × F and a duty ratio of 50% is output. In general, when the input signal Si is a signal of frequency F with a duty ratio of 50%, the frequency of the clock signal CLK is 2 × N × F, and the D flip-flop circuit is cascaded in N stages by the frequency multiplier 40, the frequency N × At F, an output signal So having a duty ratio of 50% is output from the digital frequency multiplication circuit 10.

  Next, the fail-safe property of the operation of the digital frequency multiplication circuit 10 when a single circuit element has a single fixed failure will be described.

 A. A case where a failure occurs in the input signal change detection unit 20 of FIG. 2 will be described.

  In the input signal change detector 20, when the input signal Si is not generated (input signal Si = continuous low level L) and the circuit is normal, the output signals Sa and output signals Sb of the D flip-flop circuits 21 and 22 are Both are at low level L. It is assumed that the following failure occurs from this state.

[A1] When a high-level fixed failure of the Q terminal of the first stage D flip-flop circuit 21 occurs In this case, the output signal Sa of the Q terminal of the first stage D flip-flop circuit 21 is at the high level H when the failure occurs. Thus, the output signal Sb at the Q terminal of the second stage D flip-flop circuit 22 is in the low level L, and both the output signal Sa and the output signal Sb are in the high level H within one clock. Therefore, a pulse within one clock time is output once from the exclusive OR circuit 25 as the change point detection signal PR / SH. When this one pulse is input to the frequency multiplier 40, the output signal So is output from the frequency multiplier 40 for the half cycle time of the input signal Si of frequency F.

  For example, when the output signal So is input to a transformer coupled rectification type or capacitor charge pump type drive circuit and the relay is driven by the output of this drive circuit, if the frequency F of the input signal Si is set to about 1 KHz (kilohertz), In order to operate the relay, it is usually necessary to output the output signal So for 10 cycles (10 milliseconds) of the input signal Si. Therefore, even if the output signal So is output for the half cycle time of the input signal Si, the relay does not malfunction.

[A2] When a low-level fixed failure of the Q terminal of the first stage D flip-flop circuit 21 occurs In this case, the output signals Sa and Sb of the D flip-flop circuits 21 and 22 are always low level L before and after the failure occurs. Therefore, the change point detection signal PR / SH remains at the low level L. Therefore, the output signal So is not output from the frequency multiplier 40.

[A3] When a high-level fixed failure occurs in the Q terminal of the second stage D flip-flop circuit 22 In this case, when the failure occurs, the output signal Sa of the Q terminal of the first stage D flip-flop circuit 21 is at the low level L. Thus, the output signal Sb at the Q terminal of the second-stage D flip-flop circuit 22 is in a high level H state, and both the output signal Sa and the output signal Sb are in a low level L state within one clock. Therefore, a pulse within one clock time is output once from the exclusive OR circuit 25 as the change point detection signal PR / SH. When this one pulse is input to the frequency multiplier 40, the output signal So is output from the frequency multiplier 40 for the half cycle time of the input signal Si of frequency F. However, as described above, no malfunction of the relay occurs.

[A4] When a low-level fixed failure occurs in the Q terminal of the second stage D flip-flop circuit 22 In this case, the output signals Sa and Sb of the D flip-flop circuits 21 and 22 are always at the low level L before and after the failure occurs. Therefore, the change point detection signal PR / SH remains at the low level L. Therefore, the output signal So is not output from the frequency multiplier 40.

[A5] When a high-level fixed failure occurs in the exclusive OR circuit 25 In this case, since the change point detection signal PR / SH, which is the output of the exclusive OR circuit 25 before the failure occurs, is at the low level L, a failure occurs. Sometimes the change point detection signal PR / SH changes from the low level L to the high level H, and thereafter is fixed to the high level H. However, when the change point detection signal PR / SH is fixed to the high level H, in the frequency multiplication unit 40 of FIG. 3, the input of the clock signal CLK to the D flip-flop circuits 41, 42, 43, 44 is input by the AND circuit 47. Since it is blocked, the output signal So is not output.

[A6] When a low-level fixed failure occurs in the exclusive OR circuit 25 In this case, the change point detection signal PR / SH output from the exclusive OR circuit 25 remains at the low level L before and after the occurrence of the failure. . Therefore, the output signal So is not output from the frequency multiplier 40.

  B. A case where a failure has occurred in the frequency multiplier 40 shown in FIG. 3 will be described.

  Assume that the following failure has occurred from a state where the change point detection signal PR / SH from the input signal change detection unit 20 is not generated (continuation state of low level L).

[B1] When a high-level fixed failure occurs in the Q terminal of the first stage D flip-flop circuit 41 In this case, before the failure occurs, each of the second to fourth stage D flip-flop circuits 42, 43, 44 Since the outputs Q2, Q3, and Q4 of the Q terminal are at the low level L, the output signal So changes to the high level H with a delay of 3 clocks from the occurrence of the failure, and is thereafter fixed to the high level H. Therefore, the output signal So of frequency (4 × F) is not generated.

  For example, when the output signal So is input to a transformer-coupled rectification type or capacitor charge pump type drive circuit and the relay is driven by the output of this drive circuit, the output signal So changes alternately between a high level H and a low level L. Otherwise, the output of the drive circuit cannot be obtained. Therefore, even if the output signal So changes from the low level L to the high level H and is fixed to the high level H, the relay or the like does not malfunction.

[B2] When a low-level fixed failure occurs in the Q terminal of the first stage D flip-flop circuit 41 In this case, before the failure occurs, each of the second to fourth stage D flip-flop circuits 42, 43, 44 Since the outputs Q2, Q3, and Q4 of the Q terminal are at the low level L, the output signal So remains at the low level L before and after the occurrence of the failure.

[B3] When a high-level fixed failure occurs in the Q terminal of the second-stage D flip-flop circuit 42 In this case, each Q terminal of the third-stage and fourth-stage D flip-flop circuits 43 and 44 before the failure occurs. Since the outputs Q3 and Q4 are at the low level L, the output signal So changes to the high level H with a delay of two clocks from the occurrence of the failure, and is thereafter fixed to the high level H. Therefore, the output signal So having the frequency (4 × F) is not generated, and the malfunction of the relay or the like does not occur as described in [B1].

[B4] When a low-level fixed failure occurs in the Q terminal of the second-stage D flip-flop circuit 42 In this case, each Q terminal of the third-stage and fourth-stage D flip-flop circuits 43 and 44 before the failure occurs. Since the outputs Q3 and Q4 are at the low level L, the output signal So remains at the low level L before and after the occurrence of the failure.

[B5] When a high-level fixed failure occurs in the Q terminal of the third stage D flip-flop circuit 43 In this case, the output Q4 of the Q terminal of the fourth stage D flip-flop circuit 44 is at the low level L before the failure occurs. Therefore, the output signal So changes to the high level H with a delay of one clock from the occurrence of the failure, and is thereafter fixed to the high level H. Therefore, the output signal So having the frequency (4 × F) is not generated, and the malfunction of the relay or the like does not occur as described in [B1].

[B6] When a low-level fixed failure of the Q terminal of the third stage D flip-flop circuit 43 occurs In this case, the output Q4 of the Q terminal of the fourth stage D flip-flop circuit 44 is at the low level L before the failure occurs. Therefore, the output signal So remains at the low level L before and after the occurrence of the failure.

[B7] When a high-level fixed failure occurs in the Q terminal of the fourth stage D flip-flop circuit 44 In this case, the output Q4 of the Q terminal of the fourth stage D flip-flop circuit 44 is low level L before the failure occurs. Therefore, when a failure occurs, the output signal So changes from the low level L to the high level H, and thereafter is fixed to the high level H. Therefore, the output signal So having the frequency (4 × F) is not generated, and the malfunction of the relay or the like does not occur as described in [B1].

[B8] When a low-level fixed failure occurs in the Q terminal of the fourth stage D flip-flop circuit 44 In this case, the output Q4 of the Q terminal of the fourth stage D flip-flop circuit 44 is at the low level L before the failure occurs. Therefore, the output signal So remains at the low level L before and after the occurrence of the failure.

[B9] When a high-level fixed failure occurs in the output of the inverter 45 In this case, before the failure occurs, the outputs Q1 of the Q terminals of the first to fourth D flip-flop circuits 41, 42, 43, and 44, Q2, Q3, and Q4 are at the low level L, and the low level L input to the D terminal of the first-stage D flip-flop circuit 41 is sequentially transferred according to the clock signal CLK, so that the fourth-stage D flip-flop Since the output signal So is output from the Q terminal of the output circuit 44, the output signal So remains at the low level L.

[B10] When a low-level fixed fault occurs in the output of the inverter 45 In this case, the output Q4 of the fourth stage D flip-flop circuit 44 is at the low level L before the fault occurs, and the first stage when the fault occurs. The third stage D flip-flop circuits 41 and 43 are preset, and their outputs Q1 and Q3 change to the high level H. However, when the output of the inverter 45 is at the low level, the input of the clock signal CLK to each D flip-flop circuit 41, 42, 43, 44 is blocked by the AND circuit 47, so the output signal So remains at the low level. It becomes.

[B11] When a high-level fixed failure occurs in the output of the AND circuit 47 In this case, the clock signal CLK is not input to each D flip-flop circuit 41, 42, 43, 44. The circuit 44 maintains the low level L that is the output value before the occurrence of the failure, and the output signal So remains at the low level L.

[B12] When a low-level fixed failure occurs in the output of the AND circuit 47 In this case, as in [B11], the clock signal CLK is not input to each D flip-flop circuit 41, 42, 43, 44. The four-stage D flip-flop circuit 44 maintains the low level L that is the output value before the occurrence of the failure, and the output signal So remains at the low level L.

[B13] When a high-level fixed failure occurs in the output of the inverter 46 Since each D flip-flop circuit 41, 42, 43, 44 is not reset when the power is turned on, each D flip-flop circuit 41, 42, 43, 44 The values Q1, Q2, Q3, and Q4 of the Q terminal are indeterminate. For example, immediately after the power is turned on, the outputs Q1 and Q3 of the Q terminals of the first and third stage D flip-flop circuits 41 and 43 are at the high level H, and the second and fourth stage D flip-flop circuits 42 and 44, respectively. When the outputs Q2 and Q4 of the Q terminal of the first and second terminals are at the low level L, the L, H, L, and H and the output signal So change over 4 clocks, and thereafter, the D flip-flop circuit 41 in the first stage. The low level L that is the input value of the D terminal is continuously output. Therefore, the output signal So having the frequency (4 × F) is output only for a half cycle of the input signal Si having the frequency F, and is thereafter fixed to the low level L.

  As described above in [A1], when the output signal So is input to a transformer coupled rectification type or capacitor charge pump type drive circuit and the relay is driven by the output of this drive circuit, one cycle time of the input signal Si Even if the output signal So is output for only 1 ms when the input signal Si is 1 kHz, the relay or the like does not malfunction.

[B14] When a low-level fixed failure occurs in the output of the inverter 46 In this case, since each D flip-flop circuit 41, 42, 43, 44 is cleared, for example, immediately before the first stage, the third stage, etc. The outputs Q1 and Q3 of the Q terminals of the D flip-flop circuits 41 and 43 become the high level H, and the outputs Q2 and Q4 of the Q terminals of the second and fourth D flip-flop circuits 42 and 44 become the low level L. If so, the output signal So remains at the low level L.

  As described above, even if any circuit element has a single fixed failure, the output signal So having a frequency of 4 × F is not output more than one cycle of the input signal Si. When the output signal So is input to the charge pump type drive circuit and the relay is driven by the output of the drive circuit, the relay will not malfunction even if any fixed failure occurs, and fail-safety is ensured. .

  That is, even when a fixed failure occurs in the input signal change detection unit 20 and the alternating data is not loaded into the shift register (D flip-flop circuit connected in cascade with N stages) or fixed in the load state. Since at least N clocks later, either the high level H or the low level L is fixedly output, the output signal So that alternately changes between the high level H and the low level L is not continuously output. The relay does not malfunction through a transformer-coupled rectifier type or capacitor charge pump type drive circuit, and fail-safety is ensured. Furthermore, even if a fixed failure occurs at an arbitrary stage of the shift register, fixed data is continuously output, so that fail-safeness is ensured as described above.

  In addition, an output signal So obtained by multiplying the frequency F of the input signal Si by N is generated by the digital frequency multiplying circuit 10, and this output signal So is input to a drive circuit of a transformer coupled rectification method or a capacitor charge pump method. Thus, a reduction in the size of the capacitor and a reduction in the capacitance of the capacitor can be realized, which can contribute to a reduction in size and cost of the drive circuit.

  For example, an input signal Si having a duty ratio of 50% and a frequency of 1 kHz is generated by a CPU (Central Processing Unit) as a relay control signal, and this is input to the digital frequency multiplication circuit 10 to increase the frequency by, for example, four times. By providing the drive circuit with a transformer coupled rectification method or a capacitor charge pump method, the output circuit So can be supplied to the drive circuit while reducing the processing load on the CPU, thereby reducing the size of the drive circuit.

  Further, since the digital frequency multiplication circuit 10 can be configured by a logic circuit such as a D flip-flop circuit without using a delay element or a hybrid circuit, the delay time and logic of the delay element can be secured in order to ensure a duty ratio of 50%. Detailed design and adjustment of circuit constants including circuit threshold values are not required, and manufacturing is facilitated. For example, by integrating the circuit 10 using a PDL (Programmable Logic Device) or the like, a small digital frequency multiplication circuit 10 having fail-safe properties can be realized.

  Next, a second embodiment of the present invention will be described.

  FIG. 7 shows a digital frequency multiplier 70 according to the second embodiment. The digital frequency multiplier 70 is configured by connecting the digital frequency multiplier 10 shown in the first embodiment in multiple stages (in this example, two stages).

  The first stage digital frequency multiplication circuit 10a is configured to multiply the frequency of the input signal Sia by N, and the second stage digital frequency multiplication circuit 10b is configured to multiply the frequency of the input signal Sib by M.

  The first input signal Sia (frequency = F, duty ratio 50%) is input to the input terminal 11a of the first stage digital frequency multiplication circuit 10a, and the first clock signal CLKa (frequency = 2 × N) is input to the clock terminal 12a. XF) is input. As a result, the first output signal Soa (frequency = N × F, duty ratio 50%) is output from the output terminal 14a of the first stage digital frequency multiplication circuit 10a.

  The output signal Soa output from the first stage digital frequency multiplier circuit 10a is input to the input terminal 11b of the second stage digital frequency multiplier circuit 10b, and the clock terminal 12b of the second stage digital frequency multiplier circuit 10b is input to the input terminal 11b. The second clock signal CLKb (frequency = 2 × M × N × F) is input. As a result, the second output signal Sob (frequency = M × N × F, duty ratio 50%) is output from the output terminal 14b of the second stage digital frequency multiplication circuit 10b.

  The reset signal POR is input to the reset terminals 13a and 13b of the digital frequency multipliers 10a and 10b when the power is turned on.

  By connecting the digital frequency multipliers 10a and 10b in multiple stages as described above, the number of D flip-flop circuits used in the frequency multiplier 40 (the number of shift register stages) is larger than that in the single-stage configuration when the number of multiplications is large. ) Can be reduced. For example, when multiplying by A, the number of uses in the one-stage configuration = A, but the number of uses in the two-stage configuration = (number of uses in the first stage = B) × (number of uses in the second stage = C) Become. That is, A = B × C, A = B + C, and B and C solve the simultaneous equations under even conditions, B = C = 2 and A = 4 are obtained, and the number of uses is the same with a multiplication factor of 4. With the multiplication number of 6 or more, the effect of reducing the number of uses due to the multistage configuration can be obtained.

  For example, when multiplying by 64, A = 64, but when B = C = 8, B + C = 16, and the number of D flip-flop circuits used in the frequency multiplying unit 40 can be reduced by 48. As the number of stages connected in multiple stages is increased, the number of D flip-flop circuits used can be reduced. The number of stages connected in multiple stages is not limited to two but can be set arbitrarily.

  Next, a third embodiment will be described.

  In the third embodiment, the number of D flip-flop circuits (the number of stages of shift registers) is reduced by one compared to the frequency multiplier 40 shown in the first embodiment. The reduction method includes a first case and a second case.

<First case>
When multiplying by N, (N-1) stages of D flip-flop circuits are connected in cascade to form a shift register of (N-1) stages, and each odd stage is at a high level when the change point detection signal PR / SH is input. The alternating data of (N-1) bits of high level H and low level L is parallel-loaded so as to become H, and the serial input at the first stage is fixed to low level L.

  FIG. 8 shows an example of the frequency multiplying unit 40a for quadruple multiplication in the first case.

In the frequency multiplier 40a, each odd-numbered stage is preset by the change point detection signal PR / SH, the preset terminal of the even-numbered stage is fixed to + 5V, and the D terminal of the first-stage D flip-flop circuit is set to the low level L. It is fixed to.

  Since the D terminal of the D flip-flop circuit 42 at the first stage is fixed at the low level L, the clock signal CLK is input for (N−1) clocks or more in the initial state, that is, the change point detection signal PR / SH is not input. In this state, the Q terminals of all the D flip-flop circuits 42, 43, 44 are at the low level L.

  In this state, when the change point detection signal PR / SH is input, the odd-numbered D flip-flop circuits 42 and 44 are preset, so that the D flip-flop circuits 42, 43, 44 have H, L, H Data (alternating data with odd-numbered stages being H) are loaded in parallel. Since the D terminal of the first-stage D flip-flop circuit 42 is fixed at the low level L, when data is shifted every clock, it becomes L, H, L after one clock, and L, L after two clocks. , H, and L, L, L after 3 clocks. That is, the output of the D flip-flop circuit 44 at the final stage changes to H, L, H, and L for 4 clocks including the preset, and the duty ratio 50 is obtained by multiplying the frequency of the change point detection signal PR / SH by 4. % Output signal So can be obtained. Also in the circuit of FIG. 8, the fail-safe property is ensured similarly to the frequency multiplication unit 40 of FIG.

<Second case>
When multiplying by N, D flip-flop circuits are cascaded to form (N-1) stages to form a (N-1) stage shift register, and each even stage is at a high level when the change point detection signal PR / SH is input. The high-level H and low-level L (N-1) bits of alternating data are loaded in parallel so as to become H, and the first-stage serial input is fixed to the high level H.

  FIG. 9 shows a frequency multiplication unit 40b for quadruple multiplication in the second case. In the frequency multiplier 40b, each odd stage is cleared by the change point detection signal PR / SH, the preset terminals of all stages are fixed to + 5V, and the D terminal of the first stage D flip-flop circuit is set to the high level H. It is fixed.

  Since the D terminal of the first-stage D flip-flop circuit 42 is fixed at the high level H, the clock signal CLK is input for not less than (N−1) clocks without inputting the change point detection signal PR / SH. In this state, the Q terminals of all the D flip-flop circuits 42, 43, 44 are at the high level H.

  In this state, when the change point detection signal PR / SH is input, the D flip-flop circuits 42 and 44 in the odd-numbered stages are cleared, so that the D flip-flop circuits 42, 43, and 44 are L, H, and L Data (alternate data with H in even-numbered stages) is loaded in parallel. Since the D terminal of the first stage D flip-flop circuit 42 is fixed at the high level H, when data is shifted every clock, it becomes H, L, H after one clock, and H, H after two clocks. , L, and H, H, H after 3 clocks. That is, the output of the D flip-flop circuit 44 at the final stage changes to L, H, L, and H during four clocks including clearing by the change point detection signal PR / SH, and the frequency multiplier 40 in FIG. The operation is similar, and an output signal So having a duty ratio of 50% obtained by multiplying the frequency of the change point detection signal PR / SH by 4 can be obtained. In the case of the circuit of FIG. 9 as well, the fail-safe property is ensured similarly to the frequency multiplier 40 of FIG.

  The embodiment of the present invention has been described with reference to the drawings. However, the specific configuration is not limited to that shown in the embodiment, and there are changes and additions within the scope of the present invention. Are also included in the present invention.

  For example, in each embodiment, the change point is detected both at the rising edge and the falling edge of the input signal Si, and the change point detection signal PR / SH twice the frequency of the input signal Si is generated. The signal change detection unit 20 detects a change point of either rising or falling of the input signal Si, and outputs a change point detection signal PR / SH having the same frequency as that of the input signal Si from the input signal change detection unit 20. A configuration in which the number of cascaded stages of D flip-flop circuits (the number of stages of the shift register) in the frequency multiplier 40 of the stage may be 2 × N stages. In this case, the duty ratio of the input signal Si may not be about 50% and may be arbitrary. In addition, the D flip-flop circuit (the number of stages of the shift register) may be reduced by one by using the method of the third embodiment to obtain (2N−1) stages. The circuit for detecting the rising or falling change point of the input signal Si may be constituted by any known edge detection circuit. For example, in the case of rising detection, the output of the exclusive OR circuit 25 in FIG. Is a circuit configuration that takes the logical product of the signal Sa (or signal Si), and a circuit configuration that takes the logical product of the output of the exclusive OR circuit 25 and the signal Sb (or the inverted signal of the signal Si) in the case of falling detection. But you can.

  In each embodiment, the reset signal POR is input when the power is turned on, but the input of the reset signal POR to the clear terminal of each D flip-flop circuit (shift register) of the frequency multiplier 40 and the inverter 46 are omitted. It may be configured to. In this case, the output value of each D flip-flop circuit at the time of power-on is uncertain, but the operation is the same as when the above-described failure [B13] occurs, and fail-safeness is ensured.

  Further, the AND circuit 47 may be omitted, and the clock signal CLK may be directly input to the clock terminals of the respective D flip-flop circuits 41, 42, 43, and 44 (shift registers). In this case, the AND circuit 47 does not prevent the clock even when a failure occurs in which the change point detection signal PR / SH is fixed at the high level H as shown in [A6]. However, since the state preset by the change point detection signal PR / SH (alternating data is parallel loaded) continues, for example, in the circuit of FIG. 3, the output of the third stage D flip-flop circuit 43 is fixed at a high level. After one clock, the output signal So is also fixed at the high level. Since this is a signal that does not change alternately between the high level H and the low level L, the relay does not malfunction through a drive circuit of a transformer coupled rectification type or a capacitor charge pump type.

  When the change point detection signal PR / SH is generated by detecting the change point of the rise and fall of the input signal Si, the duty ratio of the input signal Si is desirably 50%. It doesn't matter. In this case, nonuniformity of pulses occurs in the output signal So output from the frequency multiplier 40. However, if the nonuniformity is high enough to drive a drive circuit of a transformer coupled rectification method or a capacitor charge pump method, there is a problem. Does not occur.

  In the frequency multipliers 40 and 40a shown in FIGS. 3 and 8, the change point detection signal PR / SH is used as a preset for the D flip-flop circuit, and in the frequency multiplier 40b in FIG. Although the loaded state is formed, the change point detection signal PR / SH may be input to each stage alternately between preset and clear. For example, the change point detection signal PR / SH is input to the preset terminal of the odd-numbered stage D flip-flop circuit and the clear terminal of the even-numbered stage D flip-flop circuit, and the remaining preset terminal and clear terminal are pulled up to + 5V. May be configured.

  Further, in the frequency multipliers 40, 40a, and 40b shown in the embodiment, the configuration example in which the D flip-flop circuits are cascade-connected is shown, but instead of this, the function of parallel load and serial out (in the third embodiment) In the case of the frequency multipliers 40a and 40b, a shift register having a serial input function may be used.

    The use of the digital frequency N multiplier circuits 10 and 70 is not limited to the case where the output signal So is applied to a transformer coupled rectification type or capacitor charge pump type drive circuit. Further, fail-safety is ensured in a system that does not malfunction even when the output signal So is output for a period corresponding to the number of stages (or the number of stages-1) of the shift register.

1 is a block diagram showing a schematic configuration of a digital frequency multiplication circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of an input signal change detection part. It is a circuit diagram which shows the structure of a frequency multiplication part. It is explanatory drawing which shows the truth table of the input / output in D flip-flop circuit with a preset / clear function. FIG. 3 is a waveform diagram illustrating a timing chart illustrating signal waveforms of respective units of the input signal change detection unit illustrated in FIG. 2. FIG. 5 is a waveform diagram showing a timing chart showing an input signal Si and signal waveforms of each part of the frequency multiplication unit shown in FIG. 4. It is a block diagram which shows the structure of the digital frequency multiplication circuit (multistage connection) of 2nd Embodiment. It is a circuit diagram which shows the circuit example of the frequency multiplication part of a 1st case. It is a circuit diagram which shows the circuit example of the frequency multiplication part of a 2nd case. It is a circuit diagram which shows the conventional frequency multiplication circuit using a delay element. It is a circuit diagram which shows the conventional frequency multiplication circuit which uses a hybrid circuit.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10a, 10b ... Digital frequency multiplication circuit 11, 11a, 11b ... Input terminal 12, 12a, 12b ... Clock terminal 13, 13a, 13b ... Reset terminal 14, 14a, 14b ... Output terminal 20 ... Input signal change detection part 21 , 22 ... D flip-flop circuit 23, 24 ... Inverter 25 ... Exclusive OR circuit 40 ... Frequency multiplier 41, 42, 43, 44 ... D flip-flop circuit 45, 46 ... Inverter 47 ... AND circuit 70 ... Two stages Cascade-connected digital frequency multiplier CLK: clock signal POR reset signal PR / SH change point detection signal Sa ... output signal of first-stage digital frequency multiplier Sb output signal of second-stage digital frequency multiplier Sd ... output of inverter 45 Se ... output of AND circuit 47 Si ... input signal S o ... Output signal

Claims (6)

A digital frequency which inputs a digital input signal of frequency F with a duty ratio of about 50% and outputs a digital output signal with a duty ratio of 50% when the frequency is N times the digital input signal (N is an even integer of 2 or more). In the multiplier circuit,
A change point detector for detecting change points of rising and falling edges of the digital input signal;
An N-stage shift register to which a clock signal having a frequency of 2 × N × F is input, and each time the change point is detected by the change point detection unit, N bits of 1 and 0 alternately arranged A frequency multiplier in which alternating data is loaded into the shift register;
Have
A digital frequency multiplication circuit that outputs the digital output signal from a serial output of the shift register. The change point detection unit includes a D flip-flop circuit cascaded in two stages, an exclusive OR circuit that performs an exclusive OR of outputs from the D flip-flop circuit, and an inverter that inverts the clock signal. Prepared,
The clock signal is input to the clock terminal of one D flip-flop circuit, the output of the inverter is input to the clock terminal of the other D flip-flop circuit,
The digital frequency multiplication circuit according to claim 1, wherein an output of the exclusive OR circuit is output as a change point detection signal.   The change point detection unit outputs a change point detection signal every time a change point is detected,
  The frequency multiplier performs the load every time the change point detection signal is output,
  A gate for preventing the clock signal from being input to the shift register while the change point detection signal is being output;
  The digital frequency multiplication circuit according to claim 1 or 2, characterized in that Reduce the number of stages of the shift register by one stage,
The number of bits corresponding to the number of stages reduced by one stage and the alternate data in which the odd-numbered stage of the shift register is 1, is loaded in parallel and the serial input to the first stage is fixed at a low level, or the number of stages is reduced by one stage. 4. The number of bits corresponding to the number of stages and the alternating data in which the even-numbered stage of the shift register is 1, are loaded in parallel and the serial input to the first stage is fixed at a high level. The digital frequency multiplication circuit according to any one of the above. The digital frequency multiplication circuit according to any one of claims 1 to 4, wherein the shift register is configured by cascading D flip-flop circuits having preset input and clear input functions. A digital output signal comprising the digital output signal output from the digital frequency multiplier circuit according to any one of claims 1 to 5 as a digital input signal for the next stage, and a plurality of stages of the digital frequency multiplier circuits connected. Frequency multiplier circuit.

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