JP4836039B2 - Inspection device, method for inspecting conductor pattern of printed wiring board used therefor, and program therefor - Google Patents

Description

  The present invention relates to a method for inspecting a conductor pattern of a printed wiring board, and more particularly to a method for inspecting a conductor pattern disposed on a printed wiring board.

  In printed wiring boards, polygonal conductor patterns may be placed in the empty space where no components or patterns are mounted, in the discarded board, for the purpose of preventing board warpage, stabilizing the operation of the device, and improving the characteristics. It is increasing. In addition, in printed wiring boards, there is an increasing demand for strict compliance with UL (Underwriters Laboratories Inc.) standards, which are safety standards. Therefore, when arranging a polygonal conductor pattern, vias and hollows must be arranged at specific intervals.

  With the recent miniaturization and high density of LSI (Large Scale Integrated Circuit), FPGA (Field Programmable Gate Array), etc., the drive voltage has been lowered. For this reason, the current capacity is increased, and it is necessary to ensure the conductor pattern width. When the conductor pattern width cannot be secured with a single layer, the pattern width is secured in a plurality of layers. When wiring is divided into a plurality of layers, the operation is stabilized by mounting vias at specific intervals.

As a method for inspecting the above-mentioned conductor pattern, a circle whose diameter is the standard value of the maximum conductor diameter shown in the UL standard item is fine pitch in the conductor pattern information created by processing the design data of the printed wiring board. There is a method in which an assembly of arranged circles is applied to inspect for the presence or absence of an overlapping portion or contact portion between the outer periphery of the circle and the conductor pattern (see, for example, Patent Document 1). In this method, when it is determined that there is no overlapping portion or contact portion as a result, the inspection is rejected.
JP-A-2005-321846

  In the above-described conductor pattern inspection method related to the present invention, the above countermeasure must be visually checked by the designer of the printed wiring board, which results in check omissions and more time than necessary for the check. There is a problem.

  When checking the conductor area and via spacing in the conductor pattern, the printed wiring board pattern must be printed out as a drawing in units of layers and checked by human eyes.

  Further, in the method described in Patent Document 1, the determination is made based on the outer periphery of the circle and the overlapping portion of the conductor pattern. However, in order to process the overlapping in the circle with a program, complicated processing is required.

  Accordingly, an object of the present invention is to solve the above-mentioned problems, and an inspection apparatus capable of efficiently and reliably checking a conductor area and a via interval in a conductor pattern without requiring complicated processing, and to the same An object of the present invention is to provide a method for inspecting a conductive pattern of a printed wiring board to be used and a program therefor.

The inspection apparatus according to the present invention includes storage means for storing information on conductor patterns, vias, and terminals of inserted parts in printed wiring board data on mounting design CAD (Computer-Aided Design),
Processing means for meshing the conductor pattern based on information stored in the storage means, and confirming a conductor area and via spacing based on the meshed conductor pattern;
Display means for displaying the confirmation result of the processing means ,
The processing means confirms the presence of the maximum conductor diameter in the polygonal conductor pattern of the printed wiring board,
The processing means takes measures when the maximum conductor diameter exists in the conductor pattern.
The best position is detected, and the best position is displayed on the display means .

A printed wiring board conductor pattern inspection method according to the present invention is an inspection method for inspecting a printed wiring board conductor pattern on a mounting design CAD (Computer-Aided Design) by an inspection apparatus,
The inspection device is
A first process for storing information on conductor patterns, vias, and terminals of inserted parts in the printed wiring board data in the storage means;
A second process of meshing the conductor pattern based on the information stored in the storage means, and confirming a conductor area and via spacing based on the meshed conductor pattern;
Performing a third process of displaying a confirmation result of the second process on a display means ;
In the second process, the inspection device confirms the existence of the maximum conductor diameter in the polygonal conductor pattern of the printed wiring board,
In the second process, the inspection apparatus detects the best position for countermeasures when the maximum conductor diameter exists in the conductor pattern, and displays the best position on the display means .

A program according to the present invention is a program to be executed by a central processing unit in an inspection apparatus that inspects a conductor pattern of a printed wiring board on a mounting design CAD (Computer-Aided Design),
A first process for storing information on conductor patterns, vias, and terminals of inserted parts in the printed wiring board data in the storage means;
A second process of meshing the conductor pattern based on the information stored in the storage means, and confirming a conductor area and via spacing based on the meshed conductor pattern;
Look including a third process of displaying on the display means a confirmation result of said second processing,
In the second process, the polygonal conductor pattern of the printed wiring board is confirmed to have a maximum conductor diameter,
In the second process, when the maximum conductor diameter exists in the conductor pattern, the best position of the countermeasure is detected, and the best position is displayed on the display means .

  The present invention is configured and operated as described above, so that it is possible to efficiently and reliably check the conductor area and via spacing in the conductor pattern without requiring complicated processing. can get.

  Next, embodiments of the present invention will be described with reference to the drawings. First, a conductor pattern inspection apparatus for a printed wiring board according to the present invention will be described. FIG. 1 is a block diagram showing a configuration example of an inspection apparatus according to the present invention. In FIG. 1, the inspection apparatus 1 is comprised from the memory | storage part 1a, the process part 1b, and the display part 1c.

  The memory | storage part 1a memorize | stores the terminal of a conductor pattern, a via | veer, and an insertion component from the printed wiring board data 2 on mounting design CAD (Computer-Aided Design).

  The processing unit 1b meshes the conductor pattern based on the information stored in the storage unit 1a (conductor pattern meshing process 1b1), confirms the conductor area (conductor pattern maximum conductor diameter confirmation process 1b2), and the via interval. (Via interval mounting confirmation processing 1b3) is performed. The display unit 1c displays the result of the processing unit 1b.

  That is, the processing unit 1b confirms whether the maximum conductor diameter exists in the polygonal conductor pattern of the printed wiring board based on the meshed conductor pattern, and designates the via and the insertion component terminal in the polygonal conductor pattern. Check if it is implemented in the interval.

  When the maximum conductor diameter exists in the polygonal conductor pattern, the processing unit 1b detects the best countermeasure position (mesh position) and displays the mesh position on the display unit 1c as the countermeasure position. Further, the processing unit 1b detects the hole diameters of vias and insertion component terminals in a line, detects the best countermeasure position (mesh position) when not mounted at a specified interval, and uses the mesh position as the countermeasure position. It displays on the display part 1c.

  In a printed wiring board, polygonal conductor patterns are often arranged in empty spaces in which components and patterns are not mounted and discarded board portions. In this case, the wiring corresponding to the item regarding the maximum diameter conductor area without a through-hole is performed with the conductor pattern of UL (Underwriters Laboratories Inc.) standard which is a safety standard.

  In addition, when the conductor pattern is connected to the power supply and ground, and the pattern is arranged in multiple layers, wiring with vias (for connection between layers) arranged at specific intervals is performed for the purpose of stabilizing the operation. ing.

  In the present invention, these items are checked by a program for each conductor pattern, and when there is a portion that violates the conductor pattern, an alarm and a countermeasure position are displayed.

  By adopting such a configuration and operation, the present invention can efficiently and reliably check the conductor area and via spacing in the conductor pattern without requiring complicated processing. Further, in the present invention, since the polygon pattern is meshed (square rectangle) and then processed by the program, it is possible to inspect the conductor pattern of the printed wiring board with a process simpler than a circle. Become.

  FIG. 2 is a block diagram showing a configuration example of the inspection apparatus according to the first embodiment of the present invention. In FIG. 2, the inspection apparatus 1 according to the first embodiment of the present invention includes a storage unit 1a, a processing unit 1b, and a display unit 1c in the same manner as the inspection apparatus 1 according to the present invention shown in FIG. It is configured.

  The storage unit 1a stores a program 1a1 executed by the processing unit 1b, and stores a conductor pattern, a via, and a terminal (1a2) of an inserted component from the printed wiring board data 2 on a mounting design CAD (Computer-Aided Design). To do.

  The processing unit 1b includes, for example, a CPU (Central Processing Unit) and the like, and performs the following processing by executing the program 1a1 stored in the storage unit 1a. In other words, the processing unit 1b meshes the conductor pattern based on the information (1a2) stored in the storage unit 1a (conductor pattern meshing process 1b1), and confirms the conductor area (conductor pattern maximum conductor diameter confirmation process). 1b2) and via interval confirmation (via interval mounting confirmation processing 1b3) are performed. The display unit 1c displays the result of the processing unit 1b.

  That is, the processing unit 1b confirms whether the maximum conductor diameter exists in the polygonal conductor pattern of the printed wiring board based on the meshed conductor pattern, and designates the via and the insertion component terminal in the polygonal conductor pattern. Check if it is implemented in the interval.

  When the maximum conductor diameter exists in the polygonal conductor pattern, the processing unit 1b detects the best countermeasure position (mesh position) and displays the mesh position on the display unit 1c as the countermeasure position. Further, the processing unit 1b detects the hole diameters of vias and insertion component terminals in a line, detects the best countermeasure position (mesh position) when not mounted at a specified interval, and uses the mesh position as the countermeasure position. It displays on the display part 1c.

  FIG. 3 is a diagram showing printed wiring board data on the mounting design CAD used in the first embodiment of the present invention. In FIG. 3, in the printed wiring board on the mounting design CAD, the polygonal pattern 4 is mounted on the board outline data 3 and the hollow data 6 is included. The outline 5 is the outline of the polygon pattern 4, and the outline 7 is the outline of the hollow data 6.

  Vias 11 and 13 are mounted on the polygonal pattern 4. The outline 12 is an outline of the hole diameter of the via 11, and the outline 14 is an outline of the hole diameter of the via 13. In the hollow data 6, component terminals 31 to 34, wirings 41 to 44 having line widths, and vias 15, 17, and 19 are mounted. Outlines 16, 18, and 20 are outlines of hole diameters of vias 15, 17, and 19.

  4 to 8 are diagrams showing the inspection process of the conductor pattern of the printed wiring board according to the first embodiment of the present invention, and FIGS. 9 to 14 are the printed wiring boards according to the first embodiment of the present invention. It is a flowchart which shows the test | inspection process of this conductor pattern. With reference to FIGS. 2 to 14, the inspection process of the conductor pattern of the printed wiring board according to the first embodiment of the present invention will be described. The processing illustrated in FIGS. 9 to 14 is realized by the processing unit 1b executing the program 1a1 of the storage unit 1a.

  Hereinafter, the operation according to the present embodiment will be described for checking the maximum diameter conductor area with the printed wiring board shown in FIG.

  First, the mesh value and the diameter of the maximum circle of the conductor portion are input and set for the processing portion 1b (step S1 in FIG. 9). In the present embodiment, the accuracy can be changed by changing the mesh value.

  The processing unit 1b calculates the distance between the meshes from the mesh value and the diameter, and stores them in the memory (storage unit 1a) as the designated distance (step S2 in FIG. 9). Further, the processing unit 1b stores information on the printed wiring board on the mounting design CAD in the memory (storage unit 1a) (step S3 in FIG. 9). However, if part of the polygon patterns overlaps, the synthesis process is performed in advance.

  The processing unit 1b reads the polygon pattern in order from the memory (storage unit 1a), and performs processing with the polygon pattern alone (step S4 in FIG. 9). The processing unit 1b extracts the minimum and maximum coordinates of the X and Y axes from the coordinate data of the read polygon pattern, and stores them in the memory (storage unit 1a) (step S5 in FIG. 9).

  The processing unit 1b stores the extracted minimum coordinates of the X and Y axes in the memory (storage unit 1a) as the origin (step S6 in FIG. 9). The processing unit 1b meshes with a mesh value from the origin to a position including the maximum coordinates of the X and Y axes (step S7 in FIG. 9). Thus, in the present embodiment, the polygon pattern can be managed in units of meshes.

  A meshed state is shown in FIG. In FIG. 4, the origin is 51, the individual mesh is 52, and the mesh value is 53.

  The processing unit 1b converts the mesh units into a two-dimensional array and stores them in the memory (storage unit 1a) (step S8 in FIG. 9), and jumps to the processing shown in FIG.

  The processing unit 1b performs a loop process in units of meshes (steps S11 to S21 in FIG. 10). The processing unit 1b performs a calculation process to determine whether a polygon pattern exists in the mesh (step S12 in FIG. 10). When the polygon pattern does not exist (NO in step S12), the processing unit 1b sets the pattern flag to OFF and moves to the next mesh (step S20 in FIG. 10).

  When there is a polygon pattern (YES in step S12), the processing unit 1b adds a flag to the mesh (step S13 in FIG. 10). In this case, the flag attached to the mesh is ON, the pattern flag indicating the presence of the pattern in the mesh, OFF the outline flag indicating the presence of the outline in the mesh, OFF the hole flag indicating the presence of the hole in the mesh, The range flag indicating that it is within a specified distance from a mesh having an outline or a hole in the mesh is turned OFF.

  The processing unit 1b performs a calculation process to determine whether an outline exists in the mesh (step S14 in FIG. 10). When there is an outline (YES in step S14), the processing unit 1b turns on the outline flag and moves to the next mesh (step S15 in FIG. 10). When the outline does not exist (NO in step S14), the processing unit 1b performs a calculation process to determine whether a hollow is present in the mesh (step S16 in FIG. 10).

  If there is no hollow (NO in step S16), the processing unit 1b moves to the next mesh. When there is a hollow (YES in step S16), the processing unit 1b performs a calculation process to determine whether a hollow outline exists in the mesh (step S17 in FIG. 10).

  When there is a hollow outline (YES in step S17), the processing unit 1b turns on the outline flag and moves to the next mesh (step S18 in FIG. 10). If there is no hollow outline (NO in step S17), the processing unit 1b turns off the pattern flag and moves to the next mesh (step S19 in FIG. 10). When the processing of all meshes is completed, the processing unit 1b jumps to the processing illustrated in FIG.

  The processing unit 1b performs calculation processing of outlines of holes from vias and pins (terminals of insertion parts) (step S31 in FIG. 11), and performs loop processing in units of meshes (steps S32 to S36 in FIG. 11).

  When the pattern flag is ON and the outline flag is OFF (YES in step S33 in FIG. 11), the processing unit 1b performs a calculation process to determine whether a hole outline exists in the mesh (step S34 in FIG. 11). In other cases (NO in step S33), the processing unit 1b moves to the next mesh.

  When there is an outline (YES in step S34), the processing unit 1b turns on the hole flag (step S35 in FIG. 11), and moves to the next mesh. If there is no outline (NO in step S34), the processing unit 1b moves to the next mesh. When the processing of all the meshes is completed, the processing unit 1b jumps to the processing illustrated in FIG.

  The state up to the above processing is shown in FIG. In FIG. 5, a portion where X is marked on the mesh is a mesh whose pattern flag is ON and the outline flag is ON or the pattern flag is ON and the hole flag is ON. The difference between whether or not X is marked on the mesh indicates where 62 meshes are marked with X and where 61 meshes are where X is not marked.

  Subsequently, in the process illustrated in FIG. 12, the processing unit 1b performs a loop process in units of meshes (steps S41 to S48 in FIG. 12). If the pattern flag is ON (YES in step S42 in FIG. 12), the processing unit 1b moves to the process in step S43, and otherwise (NO in step S42 in FIG. 12) moves to the next mesh.

  If the outline flag is ON or the hole flag is ON (YES in step S43 in FIG. 12), the processing unit 1b proceeds to the process in step S44, and otherwise (NO in step S43 in FIG. 12) Move.

  The processing unit 1b stores the mesh information as a master mesh in the memory (storage unit 1a) (step S44 in FIG. 12). Subsequently, the processing unit 1b performs a loop process in units of meshes again (steps S45 to S47 in FIG. 12). The mesh in this case is referred to as a sleeve mesh.

  When the sleeve mesh pattern flag is ON (YES in step S46 in FIG. 12), the processing unit 1b jumps to the process in FIG. 13 and proceeds to the process in step S51. In other cases (NO in step S46 in FIG. 12), the processing unit 1b moves to the next sleeve mesh.

  When the sleeve mesh hole flag is OFF, the outline flag is OFF, and the range flag is OFF (YES in step S51 in FIG. 13), the processing unit 1b calculates the distance between the center position of the master mesh and the sleeve mesh. Then, the distance between meshes is stored in the memory (storage unit 1a) (step S52 in FIG. 13). In other cases (NO in step S51 in FIG. 13), the processing unit 1b jumps to the processing in FIG. 12 and moves to the next sleeve mesh.

  The processing unit 1b compares the set distance with the distance between meshes, and when the distance between meshes is short (YES in step S53 in FIG. 13), sets the range flag to ON (step S54 in FIG. 13), and jumps to the process in FIG. To the next sleeve mesh. In other cases (NO in step S53 in FIG. 13), the processing unit 1b jumps to the processing in FIG. 12 and moves to the next sleeve mesh.

  FIG. 6 shows a state in which the set distance and the mesh distance are compared. In FIG. 6, when the master mesh is 65 and the set distance is 68, the sleeve mesh 66 is shorter than the set distance by the distance 67, so the range flag is turned ON and indicated as X locations.

  Since the sleeve mesh 69 is longer than the set distance at the distance 70, the range flag is not turned ON. In FIG. 6, the mesh whose range flag is ON with respect to the master mesh 65 and the location where the outline flag is ON are shown as X marked locations.

  When the processing of all the sleeve meshes is completed, the processing unit 1b moves to the next mesh. Further, the processing unit 1b jumps to the processing of FIG. 14 when processing of all meshes is completed.

  The state up to the above processing is shown in FIG. In FIG. 7, the portion marked with X in the mesh is a mesh whose pattern flag is ON and the outline flag is ON, or whose pattern flag is ON and the hole flag is ON, or whose pattern flag is ON and the range flag is ON. A portion where the pattern flag is ON and X is not marked on the mesh is 71.

  The processing unit 1b performs a loop process in units of meshes (steps S61 to S65 in FIG. 14). If the pattern flag is ON (YES in step S62 in FIG. 14), the processing unit 1b proceeds to the process in step S63, and otherwise (NO in step S62 in FIG. 14) moves to the next mesh.

  When the hole flag is OFF, the outline flag is OFF, and the range flag is OFF (YES in step S63 in FIG. 14), the processing unit 1b proceeds to the process in step S64, and otherwise (NO in step S63 in FIG. 14). Move to the next mesh.

  The processing unit 1b stores the mesh information as NG information in the memory (storage unit 1a) (step S64 in FIG. 14), and moves to the next mesh. When the processing of all the meshes is completed, the processing unit 1b performs processing to determine whether NG information exists (step S65 in FIG. 14).

  When there is NG information (NO in step S66), the processing unit 1b performs NG display (alarm display), displays mesh position information as a countermeasure position (step S67 in FIG. 14), and completes the above processing. . When the NG information does not exist (YES in step S66), the processing unit 1b completes the above process.

  FIG. 8 shows a state where the maximum diameter conductor area is searched. In FIG. 8, a circle indicating the maximum diameter conductor area is overlapped around the mesh 71 of the alarm location. Therefore, in FIG. 8, the location of the circle 72 is the maximum diameter conductor area, and the position of the countermeasure is the mesh 71.

  Thus, in this embodiment, it can be seen that there is a portion with the maximum diameter conductor area without through holes in the polygonal pattern mounted on the printed wiring board, and the countermeasure is based on the mesh information (layer, coordinates). The position can be specified.

  In this embodiment, it is possible to identify the position where the most effective countermeasure can be taken at the time of countermeasures, and by programming this process, the conductor area in the conductor pattern and the via interval are checked efficiently and reliably. be able to. Therefore, in this embodiment, it is possible to efficiently and reliably check the conductor area and via spacing in the conductor pattern without requiring complicated processing.

  Although the present invention has been described with respect to the surface layer of the printed wiring board in the above embodiment, the same processing can be performed on the inner layer.

  Further, according to the present invention, by changing the determination processing shown in FIGS. 9 to 14, it is possible to check the arrangement state when the interval between the via and the pin is within a specified value. For example, (1) Check the surface layer of the polygonal pattern of the ground, (2) Check the inner layer of the polygonal pattern of the land, (3) Check the surface layer of the polygonal pattern of the power supply, (4) Polygon of the power supply The inner layer of the pattern can be checked.

  In this case, in the processes shown in FIGS. 9 to 14, by removing the outline flag item from the determination process, the interval between two or more vias and pins in the polygon pattern is arranged within the specified value. You can check whether or not. In the part where the outline flag item is deleted, the process at step S33 in FIG. 11 is determined only when the pattern plug is ON, the process at step S43 in FIG. 12 is determined only when the hole flag is ON, and the process at step S51 in FIG. This process can be realized by changing the processing to the determination that the hole flag is OFF & the range flag is OFF.

  FIG. 15 is a diagram showing component surface data of the printed wiring board on the mounting design CAD according to the second embodiment of the present invention. In FIG. 15, the component surface data according to the present embodiment indicates that the polygonal pattern 4 is mounted on the board outline data 3 and the hollow data 6 is included. In this case, the outline 5 represents the outline of the polygon pattern 4, and the outline 7 represents the outline of the hollow data 4.

  The signal name of the polygon pattern 4 is GND. Vias 11, 101 to 117 are mounted on the polygonal pattern 4. The signal names of the vias 11 and 101 to 117 are also set to GND. Therefore, the vias 11 and 101 to 117 are connected to the polygon pattern 4.

  In the hollow data 6, component terminals 31 to 34, wirings 41 to 44 having line widths, and vias 15, 17, and 19 are mounted. Signal names of the via 17, the wiring 44, and the component terminal 34 are GND.

  FIG. 16 is a diagram showing inner layer surface data of the printed wiring board shown in FIG. In FIG. 16, a polygonal pattern 201 is mounted on the board outline data 1. The signal name of the outline 202 of the polygon pattern 201 is GND. The vias 11, 17, and 101 to 117 are connected to the polygon pattern 201.

  Since the signal name of the via 15 is different from that of the polygon pattern 201, the via 15 is omitted in 203. Similarly, the via 19 is also omitted because it has a different signal name. Therefore, the portions other than the vias 15 and 19 are connected to the polygon pattern 201.

  17 and 18 are diagrams showing processing results according to the second embodiment of the present invention. FIGS. 17 and 18 show the results of the processing changed as described above in the processing of FIGS. 9 to 14.

  A portion where X is marked on the mesh indicates a mesh in which the pattern flag is ON and the hole flag is ON, or the pattern flag is ON and the range flag is ON. In FIG. 17, in the component surface data, the mesh surrounded by the polygon pattern 201 is an NG location. Reference numeral 202 denotes a circle in a specified range centering on an NG location.

  In this case, since there is no via in the circle of the specified range, it can be determined that the via is not mounted within the specified interval in this range. That is, it is shown that mounting the countermeasure via in the range surrounded by the polygon pattern 201 is the best countermeasure.

  In FIG. 18, the mesh surrounded by 203 in the inner layer surface data is an NG location. Reference numeral 204 denotes a circle in a specified range centering on the NG location. In this case, since there is no via in the circle of the specified range, it can be determined that the via is not mounted within the specified interval in this range.

It is a block diagram which shows the structural example of the test | inspection apparatus by this invention. It is a block diagram which shows the structural example of the test | inspection apparatus by the 1st Embodiment of this invention. It is a figure which shows the printed wiring board data on the mounting design CAD used in the 1st Embodiment of this invention. It is a figure which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a figure which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a figure which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a figure which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a figure which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a flowchart which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a flowchart which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a flowchart which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a flowchart which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a flowchart which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a flowchart which shows the inspection process of the conductor pattern of the printed wiring board by the 1st Embodiment of this invention. It is a figure which shows the component surface data of the printed wiring board on the mounting design CAD by the 2nd Embodiment of this invention. It is a figure which shows the inner layer surface data of the printed wiring board shown in FIG. It is a figure which shows the processing result by the 2nd Embodiment of this invention. It is a figure which shows the processing result by the 2nd Embodiment of this invention.

Explanation of symbols

1 Inspection device
1a storage unit
1a1 program
1a2 Conductor pattern, via, and terminal for inserted parts
1b Processing unit
1b1 Conductor pattern meshing
1b2 Calculation of conductor area
1b3 Calculation of via spacing
1c Display section
2 Printed wiring board data
3 Board outline data
4 Polygon patterns 5, 7, 12, 14,
16, 18, 20 outline
6 hollow data 11, 13, 15, 17,
19,101-118 via
31-34 Component terminal
41-44 wiring
51 Origin
52 mesh
53 mesh value
65 master mesh
66,69 Sleeve mesh
67,70 distance
68 Set distance
71 mesh
72 yen
201 Polygon pattern
202 Outline

Claims (11)

Storage means for storing information on conductor patterns, vias, and terminals of inserted parts in printed wiring board data on mounting design CAD (Computer-Aided Design);
Processing means for meshing the conductor pattern based on information stored in the storage means, and confirming a conductor area and via spacing based on the meshed conductor pattern;
Have a display means for displaying a confirmation result of said processing means,
The processing means confirms the presence of the maximum conductor diameter in the polygonal conductor pattern of the printed wiring board,
The processing means takes measures when the maximum conductor diameter exists in the conductor pattern.
An inspection apparatus for detecting a best position and displaying the best position on the display means . 2. The inspection apparatus according to claim 1 , wherein the processing means checks the via diameter and the hole diameter of the insertion component terminal in a line . The processing means adds the polygonal conductor pattern to the polygonal conductor pattern based on the lined hole diameter.
3. The inspection apparatus according to claim 2, wherein it is confirmed whether the via and the insertion component terminal are mounted at a specified interval . In the processing means, the via and the insertion component terminal are mounted at the specified interval.
4. The inspection apparatus according to claim 3 , wherein if there is not, the best position for countermeasure is detected and the best position is displayed on the display means . The inspection apparatus according to any one of claims 1 to 4, wherein the processing of the processing means can be applied to a polygonal conductor pattern of inner and outer layers . An inspection method for inspecting a conductor pattern of a printed wiring board on a mounting design CAD (Computer-Aided Design) with an inspection device,
The inspection device is
A first process for storing information on conductor patterns, vias, and terminals of inserted parts in the printed wiring board data in the storage means;
A second process of meshing the conductor pattern based on the information stored in the storage means, and confirming a conductor area and via spacing based on the meshed conductor pattern;
Performing a third process of displaying a confirmation result of the second process on a display means;
In the second process, the inspection device confirms the existence of the maximum conductor diameter in the polygonal conductor pattern of the printed wiring board,
In the second process, the inspection apparatus detects a best position for countermeasures when the maximum conductor diameter is present in the conductor pattern, and displays the best position on the display means. . The inspection method according to claim 6, wherein, in the second process, the inspection apparatus forms a hole diameter of the via and the insertion component terminal in a line. In the second process, the inspection device confirms whether the via and the insertion component terminal are mounted at a specified interval on a polygonal conductor pattern based on the lined hole diameter. The inspection method according to claim 7. In the second process, when the via and the insertion component terminal are not mounted at the specified interval, the inspection apparatus detects the best position for countermeasures and displays the best position on the display means. The inspection method according to claim 8, characterized in that: The inspection method according to any one of claims 6 to 9, wherein the processing by the inspection apparatus can be applied to a polygonal conductor pattern of inner and outer layers. A program to be executed by a central processing unit in an inspection apparatus for inspecting a conductor pattern of a printed wiring board on a mounting design CAD (Computer-Aided Design),
A first process for storing information on conductor patterns, vias, and terminals of inserted parts in the printed wiring board data in the storage means;
A second process of meshing the conductor pattern based on the information stored in the storage means, and confirming a conductor area and via spacing based on the meshed conductor pattern;
And a third process for displaying the confirmation result of the second process on the display means,
In the second process, the polygonal conductor pattern of the printed wiring board is confirmed to have a maximum conductor diameter,
In the second process, when the maximum conductor diameter exists in the conductor pattern, the best position for countermeasure is detected, and the best position is displayed on the display means.

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