JP4832034B2 - MOS image sensor - Google Patents

Description

  The present invention relates to a MOS image sensor, and more particularly to a MOS image sensor that can capture a high-quality image.

  FIG. 15A is a schematic view of a surface of a CMOS image sensor in which a plurality of photodiodes (photoelectric conversion elements) are arranged in a square lattice on a light receiving surface (Image Area) on the surface of a semiconductor substrate, and FIG. FIG. In the illustrated CMOS image sensor 1, a large number of unit pixels 3 are arrayed on a light receiving surface 2, and a control pulse generation circuit 4 and a vertical scanning circuit 5 are provided on the lower side of the light receiving surface 2 on the side of the light receiving surface 2. A noise suppression circuit 6 and a horizontal scanning circuit 7 are formed.

  R, G, and B added on each unit pixel 3 in FIG. 15A are a red filter (R), a green filter (G), and a blue filter (stacked on a photodiode constituting each unit pixel). B).

  The unit pixel 3 includes a photodiode 3a (see FIG. 15B) and a signal readout circuit that reads a signal detected by the photodiode 3a (FIG. 15B includes a known signal readout circuit having a four-transistor configuration. Is also shown in FIG.

  On the light receiving surface 2 of the CMOS image sensor 1, wirings 10 extending in the X direction (horizontal direction) and wirings 11 extending in the Y direction (vertical direction) are laid, and the wirings 10 are the control pulse generation circuit 4 and the vertical scanning circuit. 5, the wiring 11 is connected to the noise suppression circuit 6, the horizontal scanning circuit 7, and the power source.

  These wirings 10 and 11 laid on the light receiving surface 2 in the X direction or the Y direction are, for example, an internal wiring of a signal readout circuit, a control pulse generation circuit 4, a vertical scanning circuit 5, a noise suppression circuit 6, or the like. In order to distinguish from the internal wiring in the horizontal scanning circuit 7, it will be called “global wiring”. The global wiring includes a row selection line, a row reset line, a power supply line, and an output signal line, and is generally formed of a metal such as aluminum or copper.

  Since such a conventional CMOS image sensor 1 can be manufactured using a general-purpose CMOS process (DRAM process or the like), unlike a CCD image sensor using a dedicated manufacturing process, the manufacturing cost is lower than that of a CCD image sensor. It is said that it will be cheap.

  This is because the CMOS image sensor 1 uses a part of a MOS transistor (PN junction) manufactured in the same manner as other CMOS-LSIs as a photodiode 3a, and a signal readout circuit that reads a signal from the photodiode 3 This is because the structure is a combination of a plurality of MOS transistors.

  In addition, it is necessary to select a photodiode as a signal reading target from each photodiode 3a, and this selection is connected to a signal reading circuit of each photodiode as in the selection of a memory element such as a DRAM. This is made possible by the global wiring 10.

  FIG. 16A is a schematic perspective view of one unit pixel of the CMOS image sensor, and FIG. 16B is a schematic cross-sectional view thereof. For each unit pixel, visible light 15 enters from the outside through a microlens (top lens) 16 corresponding to the pixel, a color filter layer 17, and the like, and the light reaches the photodiode 3a.

  At this time, the global wirings 10 and 11 block part of incident light, and a metal thin film (see FIG. 16A) between the global wirings 10 and 11 or the signal readout circuit 18 (see FIG. 16A) other than the photodiode 3a is shielded. If a part of incident light is multiple-reflected between the light-shielding film (usually an aluminum thin film) 19 and this multiple-reflected light 20 leaks into the adjacent photodiode 3a, the image quality of the captured image is deteriorated. Occurs.

  The photodiode 3a formed on the semiconductor substrate is separated from a MOS transistor that constitutes a signal readout circuit that performs signal selection and signal amplification by the element isolation region 21. In the CMOS process, the gate electrode 22 constituting the MOS transistor is formed between the element isolation regions 21, the planarization protective film 23 is formed thereon, and then the first wiring layer is formed of a metal film such as aluminum. .

  If this first wiring layer is the global wiring 10 in the X direction, the global wiring 11 in the Y direction intersects with the global wiring 10 and is not electrically short-circuited further on the global wiring 10 in the X direction. It is necessary to form a flattened insulating film and form the global wiring 11 in the Y direction thereon.

  Usually, a flattening film is further formed thereon, a light shielding film 19 is laminated thereon, and a flattening film is further laminated thereon to form a color filter layer 17. Thus, in the CMOS process, the global wiring is generally formed with a multilayer structure.

  Conventionally, a low resistance metal material such as Al (aluminum) is used as a material for global wiring in order to guarantee high-speed operation of an integrated circuit (IC). It is difficult to avoid the multiple reflection problem.

  In the image sensor, in addition to an image sensor in which photodiodes are arranged in a square lattice pattern on a light receiving surface, for example, as described in Patent Document 1, an even number of photodiodes in odd rows of photodiodes provided in a matrix form is provided. Some of the photodiodes in a row are arranged with a ½ pitch shift. This so-called honeycomb arrangement is realized in the CCD image sensor, and a vertical transfer path provided between photodiodes adjacent in the horizontal direction (X direction) is formed to meander in the vertical direction (Y direction).

  Realization of a MOS image sensor in which photodiodes are arranged in a honeycomb is also desired, and those described in Patent Documents 2 and 3 below have been proposed. In this case, it is necessary to form the global wirings 10 and 11 in a meandering manner so as to avoid the photodiode, similarly to the vertical transfer path meandering of the CCD image sensor, and the wiring length becomes long and the wiring resistance increases. It is necessary to solve the above-described problem of image quality degradation due to multiple reflection.

JP-A-10-136391 Japanese Patent Publication No. 5-44642 Japanese Patent Publication No. 4-3231

  The MOS image sensor has a structure in which a multilayer wiring layer is formed on a semiconductor substrate on which a photodiode and a signal readout circuit are formed, and an optical layer such as a color filter or a microlens is stacked thereon. . Recent advances in microfabrication technology have led to an increase in the number of pixels (higher pixels) in image sensors, while the aperture size of one pixel has become smaller and the distance from adjacent pixels has become shorter. In each pixel, the light path from the incident light incident on the microlens to the photodiode in each pixel has become a narrow and narrow path. For this reason, with the increase in the number of pixels of the image sensor, the influence of multiple reflections cannot be ignored.

  When the photodiode array of a MOS image sensor is a honeycomb array, it is necessary to devise global wiring to prevent multiple reflections of incident light so that high-quality images can be captured. It must be ensured that there is no hindrance to reading and power supply.

  An object of the present invention is to provide a honeycomb array MOS image sensor capable of capturing a high-quality image by preventing multiple reflection of incident light by a global wiring, and a method for manufacturing the same.

In the MOS image sensor of the present invention, a plurality of photoelectric conversion elements are formed in a matrix on the light receiving surface of the surface of a semiconductor substrate , and the odd-numbered photoelectric conversion elements are ½ pitch from the even-numbered photoelectric conversion elements. In MOS image sensors arranged in stages,
A horizontal wiring and a vertical wiring that are connected to a signal readout circuit provided for each photoelectric conversion element and meander in the horizontal direction or the vertical direction so as to avoid the photoelectric conversion element across the light receiving surface. With directional wiring,
An output transistor and a row selection transistor constituting the signal readout circuit in a region along one side of each of the rectangular photoelectric conversion elements separated by the horizontal wiring and the vertical wiring formed between the photoelectric conversion elements And a reset transistor constituting the signal readout circuit is formed at a corner portion on the other side facing the one side of the rectangular shape,
The reset line and the row selection line constitute the horizontal wiring, the power line and the output signal line constitute the vertical wiring,
A gate of the output transistor is connected to the photoelectric conversion element, a drain of the reset transistor is connected to the photoelectric conversion element, a source of the output transistor and a source of the reset transistor are connected to the power supply line, and the output The drain of the row selection transistor having a source connected to the drain of the transistor is connected to the output signal line, the gate of the reset transistor is connected to the reset line, and the gate of the row selection transistor is connected to the row selection line. Connected,
Characterized in that said reset lines constituting the horizontal line and said row selection line is formed of a conductive polysilicon film.

The MOS image sensor of the present invention is characterized in that the horizontal wiring is formed on an element isolation region formed on the semiconductor substrate .

The vertical wiring of the MOS image sensor of the present invention is formed of a metal film .

In the MOS image sensor of the present invention, the horizontal wiring and the vertical wiring cross each other through a planarizing film .

The MOS image sensor of the present invention is characterized in that when a plurality of the horizontal wirings are formed adjacent to each other, the inter-wiring insulation is performed by an oxide film formed on the surface of the conductive polysilicon film.

  In the MOS image sensor according to the present invention, a plurality of wirings meandering in a horizontal direction or a vertical direction so as to avoid the photoelectric conversion element are connected to a required circuit provided in a peripheral portion of the light receiving surface. It is characterized in that it is formed at an equal pitch in the portion to be formed.

  The MOS image sensor of the present invention is characterized in that silicide or salicide is used instead of the conductive polysilicon.

The manufacturing method of the MOS image sensor according to the present invention includes forming the first layer of the conductive polysilicon film, patterning the conductive polysilicon film into a wiring shape, and patterning the conductive polysilicon film into the wiring shape. An insulating film is formed on the surface, a second layer of conductive polysilicon film is laminated on the insulating film, and the second layer of conductive polysilicon film is patterned into a wiring shape.

  The MOS image sensor manufacturing method of the present invention is characterized in that silicide or salicide is used in place of the conductive polysilicon.

  A digital camera according to the present invention includes any one of the above-described MOS image sensors.

  According to the present invention, the predetermined wiring is formed of conductive polysilicon (or silicide, salicide) having a lower reflectance than the metal film, so that multiple reflection of stray light in incident light can be suppressed, and high-quality images can be captured. In addition, since the pixel (photoelectric conversion element) is a so-called honeycomb arrangement, a pixel signal generated using two adjacent pixels in the horizontal direction is complemented as information on the intermediate position (referred to as honeycomb signal processing). It is possible to increase the resolution in the horizontal direction and bring the characteristics closer to human visibility. Furthermore, since the predetermined wiring can be formed directly on the insulating layer formed on the surface of the semiconductor substrate (without the planarization film), the thickness of the portion laminated on the surface of the semiconductor substrate can be reduced, and the microlens ( The distance between the top lens and the light receiving part can be shortened.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic view of the surface of a honeycomb array MOS image sensor mounted on a digital camera according to an embodiment of the present invention. In the illustrated CMOS image sensor 30, a large number of unit pixels 33 are formed in a matrix on a light receiving surface 32 of a semiconductor substrate 31. In the CMOS image sensor 30 of the present embodiment, the even-numbered unit pixels 33 are formed so as to be shifted by ½ pitch with respect to the odd-numbered unit pixels 33. A noise suppression circuit 34 and a horizontal scanning circuit 35 are provided on the lower side of the semiconductor substrate 31, and a control pulse generation circuit 36 and a vertical scanning circuit 37 are provided on the right side of the semiconductor substrate 31.

  Each unit pixel 33 includes a photodiode 33a (see FIG. 2) and a signal readout circuit that reads an optical signal detected by the photodiode 33a. A color filter is laminated on each photodiode 33a. In FIG. 1, a red filter is indicated by “R”, a green filter is indicated by “G”, and a blue filter is indicated by “B”.

  In this embodiment, the unit pixels 33 are arranged in a so-called honeycomb arrangement, so that the global wiring 41 in the horizontal direction (X direction) connected to the control pulse generation circuit 36 and the vertical scanning circuit 37 (only one is shown in FIG. 1). ) Is provided meandering in the horizontal direction so as to avoid the photodiodes on the light receiving surface 32, and similarly, the global wiring 42 in the vertical direction (Y direction) connected to the noise suppression circuit 34 and the horizontal scanning circuit 35 ( 1 is also provided to meander in the vertical direction.

  FIG. 2 is a circuit diagram of a signal readout circuit provided in the vicinity of the photodiode 33a for each unit pixel 33. FIG. 2A is a signal readout circuit diagram of a known three-transistor configuration, and FIG. FIG. 6 is a signal readout circuit diagram of a transistor configuration.

  In the case of a three-transistor configuration, a power supply terminal 44 a that supplies power Vcc, a reset terminal 45 a that applies a reset signal to the reset transistor 45, an output terminal 46 a that outputs a signal from the output transistor 46, and a row selection transistor 47 There is a row selection terminal 47a. In the case of the 4-transistor configuration, there is a row readout terminal 48a of the row readout transistor 48 in addition to the terminals 44a, 45a, 46a, 47a of the 3-transistor configuration.

  Global wirings 41 and 42 laid over the light receiving surface 32 are connected to the terminals 44a, 45a, 46a, 47a and 48a of the signal readout circuit. Accordingly, in FIG. 1, only one global wiring 41 in the horizontal direction and one global wiring 42 in the vertical direction are shown, but in reality, two or three global wirings are laid between the adjacent unit pixels 33. It will be.

  Of the global wiring, the power supply line connected to the power supply terminal 44a is preferably a low resistance wiring because a stable power supply Vcc is supplied to the signal readout circuit. Also, the output signal line connected to the output terminal 46a is preferably a low resistance wiring because an analog output signal passes therethrough.

  On the other hand, a control signal line connected to the gate electrode of the MOS transistor in each pixel, which is a reset line connected to the reset terminal 45a or a row selection line (ROW SELECT) connected to the row selection terminal 47a. The row readout line connected to the row readout terminal 48a only needs to be turned on / off by applying only an on / off signal (0, 1 signal), so that the switching speed of the transistor satisfying the requirements can be obtained. The electrical resistance of global wiring can be set.

  In a DRAM or the like, a low-resistance wiring is indispensable because the reading speed from the memory element is on the order of ns. be able to. Image sensor control signal lines such as reset lines, row selection lines, and row readout lines have a wider margin of specific resistance value per unit length than in the case of the DRAM, as in this embodiment. Even if the global wiring length is longer than that of the image sensor shown in FIG. 15A by meandering (approximately √2 times), there is no problem.

  Therefore, in the present embodiment, the control signal line is formed of conductive polysilicon instead of the metal wiring, and the power supply line and the output signal line are formed of a metal thin film such as aluminum or copper as in the conventional case.

3A is a schematic cross-sectional view of approximately two pixels of the MOS image sensor shown in FIG. 1, and FIG. 3B is a schematic cross-sectional view taken along the line IIIB-IIIB in FIG. In the MOS image sensor of this embodiment, the n region 51 is formed on the surface portion of the P-type semiconductor substrate 50, whereby the PN junction (photodiode) 33a is formed. A surface P ⁺ layer 52 effective to reduce so-called “white scratches” appearing on the imaging screen is formed on the surface portion of the n region 51, and an oxide film 53 is formed on the outermost surface.

  The oxide film 53 at the boundary between the photodiode 33a (51) and the signal readout circuit formation region is formed thick to form an element isolation region 54, and the source 55 and drain 56 of the MOS transistor are formed in the signal readout circuit formation region. Then, the gate electrode 57 is provided on the oxide film 53. The global wirings 60 and 61 are laid on the element isolation region 54 so that the potential fluctuation of the global wirings 60 and 61 does not reach the substrate 50. There are various methods for forming the element isolation region 54, and a method using LOCOS, recess LOCOS, trench isolation (STI), high-concentration boron ion implantation, or the like can be used.

  In the present embodiment, conductive polysilicon films 60 and 61 constituting two global wirings are laminated on the surface of the element isolation region 54. Each of the conductive polysilicon films 60 and 61 is used as, for example, a reset line and a row selection line in a three-transistor configuration (FIG. 2A).

  A gate electrode 57 and conductive polysilicon films 60 and 61 are formed on the oxide film 53 and the element isolation region 54, and an interlayer insulating film 62 is laminated thereon and planarized, and a metal such as aluminum is formed thereon. Global wirings 63 and 64 are formed by thin films. The metal wirings 63 and 64 are used as, for example, a power supply line and an output signal line having a three-transistor configuration.

  After the metal wirings 63 and 64 are formed, an interlayer insulating film 65 is laminated and planarized thereon, and a light shielding film 66 made of a metal film that shields the metal wirings 63 and 64 and the signal readout circuit is formed thereon. The interlayer insulating film 67 is stacked and planarized, the color filter layer 68 is stacked thereon, the interlayer insulating film 69 is stacked thereon, and the microlens 70 is stacked thereon. .

  When the configuration of the present embodiment is compared with the conventional configuration of FIG. 16B, the interlayer insulating film 23 and the metal layer 10 provided on the gate electrode 22 are not required, and the thickness h is correspondingly reduced.

  As described above, according to the present embodiment, since the conductive polysilicon film having a lower reflectance than the metal film is used as the global wiring, the number of the metal wirings that multiplexly reflect the stray light 71 in the incident light can be reduced. In addition, since the thickness h of the multilayer structure portion laminated on the semiconductor substrate 50 can be reduced, the color filter 68 and the microlens 70 can be brought close to the light receiving portion (photodiode). Focus control is also easy. Therefore, the MOS image sensor of this embodiment can capture a high-quality image.

  FIG. 4A is an enlarged view of the global wirings 60 and 61 formed of the low reflectivity conductive polysilicon shown in FIG. A gate oxide film 53 is formed on the outermost surface of the semiconductor substrate 50, and the element isolation region 54 is formed with a thick oxide film. Two global wirings 60 and 61 are formed on the element isolation region 54 in the illustrated example, and a planarizing film 62 is formed thereon.

  FIG. 4B is a diagram showing an example in which three global wirings 59, 60 and 61 are formed on the element isolation region 54. As described with reference to FIG. 2B, in the signal readout circuit having a four-transistor configuration, three control signal lines (reset signal line, row selection signal line, and row readout signal line) are required, and these three are used as elements. It will be formed on the isolation region 54. In this embodiment, since the global wiring 59, 60, 61 is formed using conductive polysilicon, three global wirings can be formed on the element isolation region 54 in a narrow range for the reason described later. It is.

FIG. 5A is a diagram showing an embodiment in which conductive polysilicon having a two-layer structure is applied to a MOS image sensor. A first low-reflectivity conductive polysilicon layer is formed, this polysilicon layer is patterned into a desired shape by a photolithography process to form a global wiring 60, and then the surface of the global wiring 60 is thermally oxidized and oxidized A film (SiO ₂ ) is formed, a second low-reflectivity conductive polysilicon layer is formed thereon, and this polysilicon layer is patterned into a desired shape by a photolithography process to form a global wiring 61.

  FIG. 5B is a diagram showing an example in which three global wirings 59, 60, 61 are formed of two layers of conductive polysilicon, and the global wiring is formed from the low-reflection conductive polysilicon film of the first layer. 59 and 61 are patterned, and the global wiring 60 is patterned from the second-layer low-reflectance conductive polysilicon film.

  6 (a) and 6 (b) are diagrams showing an improved embodiment of the global wiring shown in FIGS. 5 (a) and 5 (b). Of the global wirings shown in FIGS. 5A and 5B, the second-layer global wiring has an overlapped portion having a high height because the end portion overlaps the first-layer global wiring. Therefore, in the embodiment of FIG. 6, the overlapping portion of the global wiring in the second layer is flattened by a chemical mechanical polishing (CMP) method so that two or three global wirings are made into a single layer and then flattened. The film 62 is formed.

  This reduces the height (thickness) of the global wiring, enables the subsequent color filter layer and microlens layer to be formed with high accuracy, and allows the microlens to be close to the light receiving section. It becomes. Further, when forming the microlens, there is an advantage that the focal point of the microlens is easily controlled by the amount close to the light receiving unit.

  FIG. 7 is a diagram for explaining an advantage when the global wiring is formed of polysilicon as compared to the case where the global wiring is formed of a metal film. When three global wirings are formed on a narrow element isolation region 54 using a metal such as aluminum, the aluminum film is patterned into three global wirings by photolithography and subsequent etching.

  In this case, according to the manufacturing design rule, the line width L of the fine aluminum wire and the width S of the gap between the aluminum wires are the same. That is, L = S, and the total width of the three aluminum wires is 3L + 2S.

  On the other hand, when three global wirings are formed using conductive polysilicon, a highly insulating oxide obtained by thermally oxidizing the global wiring surface of the first layer as an insulating space between the global wirings. Since a film can be used, the space (gap) width can be 200 to 1500 angstroms.

  FIG. 8 is a schematic cross-sectional view of approximately two pixels of the MOS image sensor shown in FIG. 1, and only the cross-sectional position is different from FIG. 3 shows a cross section at a position where the gate electrode 57 and the global wiring of the MOS transistor are separated from each other, while FIG. 8 shows a cross section at a position where the gate electrode 57 and the global wiring are formed continuously (connected). .

  FIG. 9A is an enlarged view of a main part of FIG. 8 and shows a state where the global wiring 61 and the gate electrode 57 formed on the element isolation region 54 are continuously formed. Conventionally, as shown in FIG. 9B, the number of manufacturing steps has increased because it is necessary to connect the gate electrode 57 and the aluminum wiring 10 laid on the upper layer through the contact hole 10a. However, if the global wiring 61 is formed using a conductive polysilicon film as in the present embodiment, there is an advantage that the polysilicon film can be formed integrally with the gate electrode 57 to be connected. In addition, although the location where the contact hole 10a is provided cannot be a light receiving region, in this embodiment, the contact hole 10a is unnecessary, and thus the light receiving region can be widened.

  10 and 11 are wiring diagrams showing details of global wiring around four photodiodes (light receiving portions) in the MOS image sensor shown in FIG. 1, and FIG. 10 shows four photodiodes (PD). FIG. 11 shows global wirings 63 and 64 made of four photodiodes (PD) and upper metal lines. In FIG. 11, the illustration of the global wirings 60 and 61 in the lower layer is omitted, and therefore the illustration of the global wirings 60 and 61 in the lower layer is omitted.

  A diffusion region 77 is formed on the upper right side of each photodiode (PD51). An output transistor 46 and a row selection transistor 47 connected in series are formed in the diffusion region 77, and each photodiode (PD51) is formed. A reset transistor 45 is formed at the lower corner position.

  An element isolation region 54 is defined between the photodiodes (PD51) and between the photodiode (PD51) and the diffusion region 77. The element isolation regions meandering between the photodiodes (PD51) and extending in the horizontal direction. 54, a reset line 60 and a row selection line 61 made of conductive polysilicon are laid as global wiring.

  In addition, between the photodiodes (PD51) extending in the vertical direction orthogonal to the global wirings 60 and 61, as shown in FIG. 11, a power supply line 63 and an output signal line 64 made of metal wiring are connected to the reset line 60 and the output signal line 64, respectively. The row selection line 61 is laid with a planarizing film 62 (see FIG. 3) in between.

  12 is a schematic cross-sectional view taken along the line XII-XII of FIG. 11, and is a schematic cross-sectional view of the output transistor 46 portion formed in the region 77. The source terminal 55 of the output transistor 46 and the global wiring (power supply line) 63 in the upper layer are connected via a contact via 73a. FIG. 13 is a schematic cross-sectional view taken along the line XIII-XIII of FIG. 10, and is a schematic cross-sectional view of a connection portion between the gate terminal of the output transistor 46 and the photodiode (PD51). The gate terminal of the output transistor 46 and the photodiode (PD51) are connected through a conductive polysilicon wiring 74 and a contact via 73b.

  The source terminal of the reset transistor 45 shown in FIG. 11 and the power supply line 63 are connected via the contact via 73c as in FIG. 12, and the gate terminal of the reset transistor 45 is formed extending from the reset line 60. The conductive polysilicon terminal 60a (FIG. 10) is connected. The drain of the reset transistor 45 is continuously formed in the n region of the phototransistor (PD51).

  The gate terminal of the row selection transistor 47 whose source is connected to the drain of the output transistor 46 is connected to the conductive polysilicon terminal 61a formed extending from the row selection line 61. That drain, that is, FIG. The output terminal 46a shown is connected to the output signal line 64 shown in FIG. 11 via a contact via 73d.

  In the MOS image sensor 30 in which the global wirings 60, 61, 63 and 64 having such a configuration are laid, when a reset signal is output from the control pulse generation circuit 36 to the reset line 60, the reset signal is applied to the gate terminal of the reset transistor 45. Is applied to the row selection line 61 from the control pulse generation circuit 36, the row selection signal is applied to the gate terminal of the row selection transistor 47.

  Similarly, the power source voltage Vcc supplied from the power source (not shown) of the MOS image sensor 30 to the power source line 63 is supplied to each source terminal (power source terminal 44a: FIG. 2A) of the reset transistor 45 and output transistor 46 of each signal readout circuit. The output signal of the output transistor 46 is output to the output signal line 64.

  The two global wirings 63 and 64 in the vertical direction and the two global wirings 60 and 61 in the horizontal direction intersect with each other through the flattening film 62 at the intersection. In the present embodiment, for the adjacent pixels at the intersection. Similarly, since the horizontal global wirings 60 and 61 are adjacent to each other in the vertical direction global wirings 63 and 64, a total of eight global wirings intersect (see FIG. 14).

  On the other hand, in the square latticed MOS image sensor as shown in FIG. 15A, two global wires 11 in the vertical direction (only one is shown in the figure) and two global wires 10 in the horizontal direction (see FIG. 15). (Only one is shown in the figure) intersects with a total of four at the intersection.

  In the MOS image sensor, the smaller the global wiring laying area, the wider the light receiving area. Therefore, as the number of crossing lines at the intersection increases as in this embodiment, the area efficiency of the intersection increases accordingly, and the light receiving area increases. Therefore, a bright image can be taken.

  FIG. 10 shows the case where the signal readout circuit has a three-transistor configuration. However, in the case of a four-transistor configuration, a global wiring made of three conductive polysilicons including a reset line, a row selection line, and a row readout line. 10 is added to the configuration of FIG. 10 in which the row read lines and the gate terminals of the row read transistors 48 shown in FIG. 2B are connected by conductive polysilicon wiring. become.

  FIG. 14 is a schematic diagram of a connection point between the global wiring, the control pulse generation circuit 36 and the noise suppression circuit 34. When the global wiring is meandered between the photodiodes (pixels), a group of global wirings corresponding to adjacent pixels repeats approaching and separating, which causes a problem that the pitch is not constant in the layout of the global wiring. This causes a problem that the manufacturing of the connection portion connecting the global wiring to the peripheral circuit becomes troublesome.

  Therefore, in the present embodiment, as shown in FIG. 14, the pitch of the global wiring is changed to the same pitch in the connection regions 75 and 76 at the ends of the global wiring, and the circuit 34 and 36 are connected. This facilitates the connection between the global wiring and the peripheral circuit.

  In the embodiment shown in FIG. 3, the light shielding film 66 is provided in a flat plate shape below the color filter layer 68. However, the light shielding film 66 is provided so as to cover the metal wirings 63 and 64, and between the element isolation regions 54 sandwiching the MOS transistor. It is also possible to provide another light-shielding film covering the surface.

  In the above-described embodiment, the polysilicon film is used as the global wiring. However, silicide, salicide, or the like may be used instead of the polysilicon film.

As described above, according to the above-described embodiment, the following effects can be obtained.
(1) A honeycomb array CMOS image sensor can be easily formed.
(2) The signal processing circuit used in the honeycomb CCD can be applied.
(3) A part of incident light can be prevented from being reflected on the metal wiring layer and entering into adjacent pixels as stray light, and there is no deterioration of color mixing or color reproducibility, and high-quality imaging is possible.

(4) Since the microlens can be brought close to the photodiode portion, the image formation position by the microlens does not become the front pin even if the pixel is miniaturized.
(5) Since the global wiring in the lower layer is flattened, the patterning accuracy of signal lines, color filters, microlenses and the like laminated thereon is improved, yield is improved, and miniaturization is facilitated.
(6) Since the number of contacts in the unit pixel (pixel) is reduced, the area of the photodiode portion is not compressed, which is suitable for high sensitivity and pixel miniaturization.

  The MOS image sensor according to the present invention can be arranged in a honeycomb with a large light receiving area and can also suppress deterioration in image quality caused by incident light reflecting off a metal wiring. Therefore, a MOS image mounted on a digital camera that captures high-quality images. It is useful as a sensor.

It is a surface schematic diagram of the MOS image sensor of honeycomb arrangement concerning one embodiment of the present invention. FIG. 2 is a circuit diagram of a signal readout circuit provided in the vicinity of the photodiode shown in FIG. 1, (a) is a signal readout circuit diagram of a known 3-transistor configuration, and (b) is a signal readout circuit diagram of a known 4-transistor configuration. is there. It is a cross-sectional schematic diagram for about 2 pixels of the MOS image sensor shown in FIG. FIG. 4 is a schematic cross-sectional view of a global wiring made of low-reflectance conductive polysilicon formed on the element isolation region shown in FIG. 3, wherein (a) shows two global wirings and (b) shows three global wirings. Indicates. FIG. 4 is a schematic cross-sectional view of a global wiring made of a low-reflectance conductive polysilicon having a two-layer structure formed on the element isolation region shown in FIG. 3, wherein (a) shows two global wirings and (b) shows 3 The global wiring of the book is shown. It is a figure which shows the example which planarized each global wiring shown to Fig.5 (a) (b) by CMP. It is a figure explaining the advantage in the case of forming global wiring with conductive polysilicon, while forming global wiring with metal wiring. It is a cross-sectional schematic diagram in a position different from FIG. (A) is a principal part enlarged view of FIG. 8, (b) is the conventional cross-sectional schematic diagram compared with (a). FIG. 2 is a wiring diagram showing details of lower global wiring around four photodiodes (light receiving parts) in the MOS image sensor shown in FIG. 1. FIG. 2 is a wiring diagram showing details of upper global wiring around four photodiodes (light receiving portions) in the MOS image sensor shown in FIG. 1. FIG. 12 is a schematic cross-sectional view taken along line XII-XII in FIG. 11. FIG. 13 is a schematic cross-sectional view taken along line XIII-XIII in FIG. 12. It is a schematic diagram which shows the connection part of the edge part of the global wiring shown in FIG. 1, and a scanning circuit. (A) is a surface schematic diagram of a conventional square lattice MOSE image sensor, and (b) is a circuit diagram thereof. (A) is the principal part perspective view of 1 pixel shown in FIG. 15, (b) is the cross-sectional schematic diagram.

Explanation of symbols

30 MOS image sensors 31 and 50 in honeycomb arrangement, semiconductor substrate 32, light receiving area 33, unit pixel 33a, photodiode 34, noise suppression circuit 35, horizontal scanning circuit 36, control pulse generation circuit 37, vertical scanning circuit 41, horizontal global wiring 42, vertical global wiring 51 n region 53 gate insulating film 54 element isolation regions 55, 56 source, drain 57 gate electrodes 59, 60, 61 global wiring 62, 65, 67, 69 made of low reflectivity conductive polysilicon flattening film 63, 64 metal Global wiring composed of wiring 66 Light shielding film 68 Color filter layer 70 Micro lens

Claims (10)

A MOS image in which a plurality of photoelectric conversion elements are formed in a matrix on the light receiving surface of the surface of a semiconductor substrate , and the odd-numbered rows of photoelectric conversion elements are arranged with a ½ pitch shift from the even-numbered rows of photoelectric conversion elements. In the sensor
A horizontal wiring and a vertical wiring that are connected to a signal readout circuit provided for each photoelectric conversion element and meander in the horizontal direction or the vertical direction so as to avoid the photoelectric conversion element across the light receiving surface. With directional wiring,
An output transistor and a row selection transistor constituting the signal readout circuit in a region along one side of each of the rectangular photoelectric conversion elements separated by the horizontal wiring and the vertical wiring formed between the photoelectric conversion elements And a reset transistor constituting the signal readout circuit is formed at a corner portion on the other side facing the one side of the rectangular shape,
The reset line and the row selection line constitute the horizontal wiring, the power line and the output signal line constitute the vertical wiring,
A gate of the output transistor is connected to the photoelectric conversion element, a drain of the reset transistor is connected to the photoelectric conversion element, a source of the output transistor and a source of the reset transistor are connected to the power supply line, and the output The drain of the row selection transistor having a source connected to the drain of the transistor is connected to the output signal line, the gate of the reset transistor is connected to the reset line, and the gate of the row selection transistor is connected to the row selection line. Connected,
MOS image sensor, characterized in that said reset lines constituting the horizontal line and said row selection line is formed of a conductive polysilicon film. 2. The MOS image sensor according to claim 1, wherein the horizontal wiring is formed on an element isolation region formed on the semiconductor substrate . 3. The MOS image sensor according to claim 1, wherein the vertical wiring is formed of a metal film . 4. The MOS image sensor according to claim 1, wherein the horizontal wiring and the vertical wiring intersect with each other via a planarizing film . 5. 5. The MOS image sensor according to claim 1, wherein when a plurality of the horizontal wirings are formed adjacent to each other, an inter-wiring insulation is formed on the surface of the conductive polysilicon film. 6. M OS image sensor characterized in that it is configured to perform oxide film. 6. The MOS image sensor according to claim 1, wherein a required circuit is provided in a peripheral portion of the light receiving surface between the wirings of the horizontal wirings and between the wirings of the vertical wirings. 7. A MOS image sensor characterized in that the MOS image sensor is formed at an equal pitch at a portion connected to the . 7. The MOS image sensor according to claim 1, wherein silicide or salicide is used in place of the conductive polysilicon . 2. The method of manufacturing a MOS image sensor according to claim 1, wherein the conductive polysilicon film of the first layer is formed, the conductive polysilicon film is patterned into a wiring shape, and the conductive material patterned into the wiring shape is formed. Forming an insulating film on the surface of the conductive polysilicon film, laminating a second layer of conductive polysilicon film on the insulating film, and patterning the second layer of conductive polysilicon film into a wiring shape. A method of manufacturing a MOS image sensor . 9. The method of manufacturing a MOS image sensor according to claim 8, wherein silicide or salicide is used in place of the conductive polysilicon. A digital camera comprising the MOS image sensor according to any one of claims 1 to 7 .

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